Re: Fix PCI in Holly device tree
Signed-off-by: David Gibson [EMAIL PROTECTED] Acked-by: Josh Boyer [EMAIL PROTECTED] Paul, I can include this in my 'next' branch if you aren't opposed. I'll have another set of patches going in there today/tomorrow. Er... on second thought, this actually fixes a regression on Holly. So I'll amend my offer to put it in my 'next' branch to be contingent on you not wanting to get it into 2.6.27 this late. I've picked it up, I need to check a thing or two and I'll send patches for .27 to Linus tomorrow (Paulus is on vacation for a week). With a bit of luck he won't have closed .27 before that :-) Cheers Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: Fix PCI in Holly device tree
On Thu, 25 Sep 2008 12:39:04 +1000 David Gibson [EMAIL PROTECTED] wrote: The PCI bridge on the Holly board is current incorrectly represented in the device tree. The current device tree node for the PCI bridge sits under the tsi-bridge node. That's not obviously wrong, but the PCI bridge translated some PCI spaces into CPU address ranges which were not translated by the tsi-bridge node. We used to get away with this problem because the PCI bridge discovery code was also buggy, assuming incorrectly that PCI host bridge nodes were always directly under the root bus and treating the translated addresses as raw CPU addresses, rather than parent bus addresses. This has since been fixed, breaking Holly. This could be fixed by adding extra translations to the tsi-bridge node, but this patch instead moves the Holly PCI bridge out of the tsi-bridge node to the root bus. This makes the tsi-bridge node represent only the built-in IO devices in the bridge, with a more-or-less contiguous address range. This is the same convention used on Freescale SoC chips, where the soc node represents only the IMMR region, and the PCI and other bus bridges are separate nodes under the root bus. Signed-off-by: David Gibson [EMAIL PROTECTED] Acked-by: Josh Boyer [EMAIL PROTECTED] Paul, I can include this in my 'next' branch if you aren't opposed. I'll have another set of patches going in there today/tomorrow. josh ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: Fix PCI in Holly device tree
On Thu, Sep 25, 2008 at 08:11:29AM -0400, Josh Boyer wrote: On Thu, 25 Sep 2008 12:39:04 +1000 David Gibson [EMAIL PROTECTED] wrote: The PCI bridge on the Holly board is current incorrectly represented in the device tree. The current device tree node for the PCI bridge sits under the tsi-bridge node. That's not obviously wrong, but the PCI bridge translated some PCI spaces into CPU address ranges which were not translated by the tsi-bridge node. We used to get away with this problem because the PCI bridge discovery code was also buggy, assuming incorrectly that PCI host bridge nodes were always directly under the root bus and treating the translated addresses as raw CPU addresses, rather than parent bus addresses. This has since been fixed, breaking Holly. This could be fixed by adding extra translations to the tsi-bridge node, but this patch instead moves the Holly PCI bridge out of the tsi-bridge node to the root bus. This makes the tsi-bridge node represent only the built-in IO devices in the bridge, with a more-or-less contiguous address range. This is the same convention used on Freescale SoC chips, where the soc node represents only the IMMR region, and the PCI and other bus bridges are separate nodes under the root bus. Signed-off-by: David Gibson [EMAIL PROTECTED] Acked-by: Josh Boyer [EMAIL PROTECTED] Paul, I can include this in my 'next' branch if you aren't opposed. I'll have another set of patches going in there today/tomorrow. Er... on second thought, this actually fixes a regression on Holly. So I'll amend my offer to put it in my 'next' branch to be contingent on you not wanting to get it into 2.6.27 this late. josh ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Fix PCI in Holly device tree
The PCI bridge on the Holly board is current incorrectly represented
in the device tree. The current device tree node for the PCI bridge
sits under the tsi-bridge node. That's not obviously wrong, but the
PCI bridge translated some PCI spaces into CPU address ranges which
were not translated by the tsi-bridge node.
We used to get away with this problem because the PCI bridge discovery
code was also buggy, assuming incorrectly that PCI host bridge nodes
were always directly under the root bus and treating the translated
addresses as raw CPU addresses, rather than parent bus addresses.
This has since been fixed, breaking Holly.
This could be fixed by adding extra translations to the tsi-bridge
node, but this patch instead moves the Holly PCI bridge out of the
tsi-bridge node to the root bus. This makes the tsi-bridge node
represent only the built-in IO devices in the bridge, with a
more-or-less contiguous address range. This is the same convention
used on Freescale SoC chips, where the soc node represents only the
IMMR region, and the PCI and other bus bridges are separate nodes
under the root bus.
Signed-off-by: David Gibson [EMAIL PROTECTED]
Index: working-2.6/arch/powerpc/boot/dts/holly.dts
===
--- working-2.6.orig/arch/powerpc/boot/dts/holly.dts2008-09-02
11:50:12.0 +1000
+++ working-2.6/arch/powerpc/boot/dts/holly.dts 2008-09-17 11:50:23.0
+1000
@@ -133,61 +133,61 @@
reg = 0x7400 0x0400;
big-endian;
};
+ };
- [EMAIL PROTECTED] {
- device_type = pci;
- compatible = tsi109-pci, tsi108-pci;
- #interrupt-cells = 1;
- #size-cells = 2;
- #address-cells = 3;
- reg = 0x1000 0x1000;
- bus-range = 0x0 0x0;
- /*+
- | PCI memory range.
- | 01 denotes I/O space
- | 02 denotes 32-bit memory space
- +*/
- ranges = 0x0200 0x 0x4000 0x4000
0x 0x1000
- 0x0100 0x 0x 0x7e00
0x 0x0001;
- clock-frequency = 13332;
- interrupt-parent = MPIC;
+ [EMAIL PROTECTED] {
+ device_type = pci;
+ compatible = tsi109-pci, tsi108-pci;
+ #interrupt-cells = 1;
+ #size-cells = 2;
+ #address-cells = 3;
+ reg = 0xc0001000 0x1000;
+ bus-range = 0x0 0x0;
+ /*+
+ | PCI memory range.
+ | 01 denotes I/O space
+ | 02 denotes 32-bit memory space
+ +*/
+ ranges = 0x0200 0x 0x4000 0x4000
0x 0x1000
+ 0x0100 0x 0x 0x7e00
0x 0x0001;
+ clock-frequency = 13332;
+ interrupt-parent = MPIC;
+ interrupts = 0x17 0x2;
+ interrupt-map-mask = 0xf800 0x0 0x0 0x7;
+ /*+
+ | The INTA, INTB, INTC, INTD are shared.
+ +*/
+ interrupt-map =
+ 0x800 0x0 0x0 0x1 RT0 0x24 0x0
+ 0x800 0x0 0x0 0x2 RT0 0x25 0x0
+ 0x800 0x0 0x0 0x3 RT0 0x26 0x0
+ 0x800 0x0 0x0 0x4 RT0 0x27 0x0
+
+ 0x1000 0x0 0x0 0x1 RT0 0x25 0x0
+ 0x1000 0x0 0x0 0x2 RT0 0x26 0x0
+ 0x1000 0x0 0x0 0x3 RT0 0x27 0x0
+ 0x1000 0x0 0x0 0x4 RT0 0x24 0x0
+
+ 0x1800 0x0 0x0 0x1 RT0 0x26 0x0
+ 0x1800 0x0 0x0 0x2 RT0 0x27 0x0
+ 0x1800 0x0 0x0 0x3 RT0 0x24 0x0
+ 0x1800 0x0 0x0 0x4 RT0 0x25 0x0
+
+ 0x2000 0x0 0x0 0x1 RT0 0x27 0x0
+ 0x2000 0x0 0x0 0x2 RT0 0x24 0x0
+ 0x2000 0x0 0x0 0x3 RT0 0x25 0x0
+ 0x2000 0x0 0x0 0x4 RT0 0x26 0x0
+ ;
+
+ RT0: [EMAIL PROTECTED] {
+ device_type = pic-router;
+ interrupt-controller;
+ big-endian;
+ clock-frequency = 0;
+ #address-cells = 0;
+ #interrupt-cells = 2;
