The specific mpt2sas problem is that if we write a 64 bit register non
atomically, we can't allow any interleaving writes for any other
region
on the chip, otherwise the HW will take the write as complete in the
64
bit register and latch the wrong value. The only way to achieve that
given the semantics of writeq is a global static spinlock.
That sounds like very specific and slightly dodgy hardware.
You don't say what the scope of 'region on the chip' is, but
it looks like you need to disable ALL writes to the memory
area between the first and second writes of the 64bit value
and not just those coming from writeq().
I don't see how this can possibly be done by normal mutexing
around the writeq() sequence, surely you need to lock the bus
between the two transfers.
Even dma writes would be a problem.
The only way I can think to stop other cpus doing writes
is to use IPIs for force them into a busy wait loop.
All rather reminds me of a PCI slave that got things
horribly wrong when a read was done while a write was
still 'posted', or a 2nd master did a cycle did a read
while a read rerun sequence was still in progress.
(required a mutex and dummy cycles).
At least than one wqs confined to one driver.
David
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