Re: RFC [PATCH] fsl pci quirk to __devinit Re: PCIe end-point on FPGA doesn't show up on PCI bus when configured

2012-06-29 Thread Kumar Gala

On Sep 19, 2011, at 10:35 AM, Matias Garcia wrote:

 
 Here's the patch against 2.6.37:
 
 Change quirk_fsl_pcie_header from __init to __devinit.
 
 Signed-off-by: Matias Garcia mgar...@rossvideo.com

applied

- k
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RFC [PATCH] fsl pci quirk to __devinit Re: PCIe end-point on FPGA doesn't show up on PCI bus when configured

2011-09-19 Thread Matias Garcia
On Fri, 2011-01-28 at 21:06 +0100, Elie De Brauwer wrote:
 On 01/28/11 19:37, Matias Garcia wrote:
  I'm running a vanilla linux 2.6.37 kernel on a Freescale P2020 dual-core
  processor, and have the following conundrum: I configure the FPGA which
  brings up a PCIe interface to the processor. I scan both PCI buses on
  the system (I believe the second bus is behind the Freescale integrated
  bridge on the first), and it doesn't show up. I initiate a reset on the
  processor, and both U-boot and Linux now see the FPGA PCI device at
  :01:00.00. I've noticed some of the memory mappings in the PCI
  bridge windows are different between the two boot sequences. I've tried
  all manner of pci calls (including the pcibios_fixup routines) on the
  bridge device (including removing and re-scanning it), and on bus 1,
  which is otherwise empty, to no avail. Following are some debug listings
  from dmesg; any help/ideas in tracking down the problem (hardware or
  software) is greatly appreciated.
 
  #Boot without FPGA configured:
  snip
  Found FSL PCI host bridge at 0x0008ff70a000. Firmware bus number:
  0-255
  PCI host bridge /pcie@8ff70a000 ranges:
  MEM 0x00088000..0x00088fff - 0x8000
  IO 0x0008a000..0x0008a000 - 0x
  /pcie@8ff70a000: PCICSRBAR @ 0xfff0
  /pcie@8ff70a000: WARNING: Outbound window cfg leaves gaps in memory map.
  Adjusting the memory map could reduce unnecessary bounce buffering.
  /pcie@8ff70a000: DMA window size is 0x8000
  MPC85xx RDB board from Freescale Semiconductor
  ...
  PCI: Probing PCI hardware
  pci :00:00.0: [1957:0070] type 1 class 0x000b20
  pci :00:00.0: ignoring class b20 (doesn't match header type 01)
  pci :00:00.0: supports D1 D2
  pci :00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
  pci :00:00.0: PME# disabled
  pci :00:00.0: PCI bridge to [bus 01-ff]
  pci :00:00.0: bridge window [io 0x-0x] (disabled)
  pci :00:00.0: bridge window [mem 0x-0x000f] (disabled)
  pci :00:00.0: bridge window [mem 0x-0x000f pref] (disabled)
  PCI :00 Cannot reserve Legacy IO [io 0xffbed000-0xffbedfff]
  pci :00:00.0: PCI bridge to [bus 01-01]
  pci :00:00.0: bridge window [io 0xffbed000-0xffbfcfff]
  pci :00:00.0: bridge window [mem 0x88000-0x88fff]
  pci :00:00.0: bridge window [mem pref disabled]
  pci :00:00.0: enabling device (0106 - 0107)
  pci_bus :00: resource 0 [io 0xffbed000-0xffbfcfff]
  pci_bus :00: resource 1 [mem 0x88000-0x88fff]
  pci_bus :01: resource 0 [io 0xffbed000-0xffbfcfff]
  pci_bus :01: resource 1 [mem 0x88000-0x88fff]
 
  #Reset with FPGA configured:
  snip
  Found FSL PCI host bridge at 0x0008ff70a000. Firmware bus number:
  0-255
  PCI host bridge /pcie@8ff70a000 ranges:
  MEM 0x00088000..0x00088fff - 0x8000
  IO 0x0008a000..0x0008a000 - 0x
  /pcie@8ff70a000: PCICSRBAR @ 0xfff0
  /pcie@8ff70a000: WARNING: Outbound window cfg leaves gaps in memory map.
  Adjusting the memory map could reduce unnecessary bounce buffering.
  /pcie@8ff70a000: DMA window size is 0x8000
  MPC85xx RDB board from Freescale Semiconductor
  ...
  PCI: Probing PCI hardware
  pci :00:00.0: [1957:0070] type 1 class 0x000b20
  pci :00:00.0: ignoring class b20 (doesn't match header type 01)
  pci :00:00.0: supports D1 D2
  pci :00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
  pci :00:00.0: PME# disabled
  pci :01:00.0: [1172:0004] type 0 class 0x001000
  pci :01:00.0: reg 10: [mem 0x8000-0x80ff]
  pci :01:00.0: reg 14: [mem 0x8100-0x81ff]
  pci :01:00.0: reg 18: [mem 0x8200-0x82ff]
  pci :00:00.0: PCI bridge to [bus 01-ff]
  pci :00:00.0: bridge window [io 0x-0x] (disabled)
  pci :00:00.0: bridge window [mem 0x8000-0x82ff]
  pci :00:00.0: bridge window [mem 0x1000-0x000f pref] (disabled)
  irq: irq 0 on host /soc@8ff70/pic@4 mapped to virtual irq 16
  PCI :00 Cannot reserve Legacy IO [io 0xffbed000-0xffbedfff]
  pci :00:00.0: PCI bridge to [bus 01-01]
  pci :00:00.0: bridge window [io 0xffbed000-0xffbfcfff]
  pci :00:00.0: bridge window [mem 0x88000-0x88fff]
  pci :00:00.0: bridge window [mem pref disabled]
  pci :00:00.0: enabling device (0106 - 0107)
  pci_bus :00: resource 0 [io 0xffbed000-0xffbfcfff]
  pci_bus :00: resource 1 [mem 0x88000-0x88fff]
  pci_bus :01: resource 0 [io 0xffbed000-0xffbfcfff]
  pci_bus :01: resource 1 [mem 0x88000-0x88fff]
 
 
 Hi Mattias,
 
 I'm doing the same on a similar setup, also a P2020 but a 2.6.36 and 
 with me it works just fine. However I encountered one problem. I 
 understand it as follows, if there is no physical PCIe link then 
 somewhere a flag PPC_INDIRECT_TYPE_NO_PCIE_LINK gets set. This has as