On Tue, 2017-06-20 at 08:37:28 UTC, Alistair Popple wrote: > NPU2 requires an extra explicit flush to an active GPU PID when sending > address translation shoot downs (ATSDs) to reliably flush the GPU TLB. This > patch adds just such a flush at the end of each sequence of ATSDs. > > We can safely use PID 0 which is always reserved and active on the GPU. PID > 0 is only used for init_mm which will never be a user mm on the GPU. To > enforce this we add a check in pnv_npu2_init_context() just in case someone > tries to use PID 0 on the GPU. > > Signed-off-by: Alistair Popple <alist...@popple.id.au>
Applied to powerpc fixes, thanks. https://git.kernel.org/powerpc/c/bbd5ff50afffcf4a01d05367524736 cheers