Problem booting Linux on MPC8260ADS board
hello, I am facing a problem in booting the Linux on MPC8260ADS board. Linux version : 2.4.17 (MontaVista) I have added the patches required to MPC8260ADS board like setting up the memory map and BATs. Control enters "start_here" subroutine (linux2.4.17_mvl121/arch/ppc/kernel). But it hangs before calling "load_mmu" subroutine. --- Code begins --- /* * Go back to running unmapped so we can load up new values * for SDR1 (hash table pointer) and the segment registers * and change to using our exception vectors. */ lis r4,2f at h ori r4,r4,2f at l tophys(r4,r4) li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) FIX_SRR1(r3,r5) mtspr SRR0,r4 mtspr SRR1,r3 SYNC RFI( <= After this, MPC8260 hangs ) /* Load up the kernel context */ 2: --- Code ends --- Is there any reason for this to happen??? And any solutions to get the linux going... Am i using the wrong file in compilation, by any chance? Any help is appreciated. Thanks and regards, kamal ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
NFS and ram filesystems
On Thu, 2003-02-20 at 19:19, Ing.Gianfranco Morandi wrote: > The question is: > How can I boot the board by using PPCboot, mount initially the NFS > filesystem, load a new big ramdisk image and finally remount root on > ramdisk? ??? say what ?? You just have to explain this a bit more what are you really trying to do? if you have nfsroot why switch over to a ramdisk. If you want to test the system you have in a ramdisk there is much easier ways. -- Kenneth Johansson Ericsson AB Tel: +46 8 719 70 20 Tellusborgsv?gen 94 Fax: +46 8 719 29 45 126 25 Stockholm ken at switchboard.ericsson.se ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
NFS and ram filesystems
Dear friends, We are finalizing our project on a custom 8260 board and as suggested in many "Linux HOWTO" we are trying to move from NFS to ram filesystem. Actually we have burned the flash with both kernel and ramdisk images and modified the initial bootargs variable to indicate where to find the two images. At this point all is working, but the ramdisk image is obviously too small to support the whole application (Flash size cannot be larger than 2Mbytes). The question is: How can I boot the board by using PPCboot, mount initially the NFS filesystem, load a new big ramdisk image and finally remount root on ramdisk? Any help would be appreciated. many thanks Gianfranco ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
How to start a Master DMA transfer on the MPC8245 ?
Hello, I didn't find a clear example of the start of a master DMA write to an external device or the hardware specific DMA code for the MPC 8245. Can someone explain me how I must do this, or say me where I can find an example of such a thing. Thanks -- Benoit Callebaut Software Development Engineer Barco | Control Rooms Noordlaan 5, 8520 Kuurne, Belgium Tel +32(0)56 36 84 28 Fax +32(0)56 36 86 05 mailto:benoit.callebaut at barco.com http://www.barcocontrolrooms.com ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
boot up the linux kernel using vxworks boot ROM(split the elf )
hello, all: I am having trouble loading the image section of the elf file into ram (vmlinux) with the VxWorks bootloader. The vxworks bootloader could handle this by the bootloadmodule function(the vxworks lib function) using ftp to load the image and boot up the kernel.But now we want to copy the image section of the elf instead of using the function metioned above. Does someone have a idea on how to handle this ? un your_book at sina.com ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
FW: PowerMac vs. Intel for PowerPC Development Host
On Fri, Feb 21, 2003 at 10:05:10AM +1100, Paul Mackerras wrote: > OK, the hard disk on the G4 is an 80GB Seagate ST380021A, while the > hard disk on the P4 (which is not a laptop) is a 40GB Seagate > ST340016A, so they should be pretty similar. On a `hdparm -tT' > test, the G4 gets 39.75 MB/s from disk whereas the P4 gets 31.98 > MB/s. In any case, after the first compilation, it hardly hits the > disk at all on either machine. I can't see any reasonable machine hitting the disk hard, pretty much any files required during compilation should buffer/page cache. When I compile here, the disk is almost completely inactive except for the odd shirt burst of dirty pages being flushed every 5s or so. --cw ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
Bringing up Motorola MGT5100
On Thu, Feb 20, 2003 at 12:55:23PM -0700, Tom Rini wrote: > > On Thu, Feb 20, 2003 at 02:48:12PM -0500, Kent Borg wrote: > > [snip] > > [TARGET] > > CPUTYPE 5100;the CPU type > > Are you sure you want this? Maybe it should be '603'.. I certainly am not sure, but as the file from Abatron has "5100" as part of its name, I think they know of this beast. > > > ;MMU XLAT ;translate effective to physical address > > PTBASE 0x00f0 ;here is the pointer to the page table pointers > > Keep the MMU line, YES! Looky: Breakpoint 1, 0xc00037a0 in start_here () 3: x/5i $pc 0xc00037a0 : lis r2,-16368 0xc00037a4 :ori r2,r2,42032 0xc00037a8 :addis r4,r2,16384 0xc00037ac : addir4,r4,624 0xc00037b0 : mtsprg 3,r4 (gdb) > comment out the PTBASE maybe? But I want that hint to work once I get that far...and I can read those high values without changing it, so I'm leaving it alone for now. Thanks a bunch, -kb ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
Bringing up Motorola MGT5100
On Thu, Feb 20, 2003 at 12:36:11PM -0700, Tom Rini wrote: > Bad config. Can you post it please? If you could spot any obvious errors in here, I would love that. Thanks, -kb ; bdiGDB configuration file for the MGT5100 evaluation board ; -- ; [INIT] ; init core register WREGMSR 0x1002 ;MSR : ME,RI WM320x8000 0x0001e000 ;MBAR : internal registers at 0xf000 WSPR279 0xf000 ;SPRG7: save internal register offset ; ; init memory controller ;WM320x8004 0x0001ffe0 ;CS0STR: start = 0xfff0 ;WM320x8008 0x0001ffef ;CS0STP: stop = 0xfff7 ;WM320x8300 0x00047800 ;CS0CR: ctrl ;WM320x8054 0x0041 ;ADREN: enable CS0, disable CSBOOT ; WM320xf04c 0x0001ff00 ;BOOTSTR: start = 0xff80 WM320xf050 0x0001 ;BOOTSTP: stop = 0x WM320xf300 0x00043801 ;CS0CR: ; WM320xf034 0x ;SDRAMSTR: Start = 0x WM320xf038 0x07ff ;SDRAMSTP: Stop = 0x03ff WM320xf054 0x0240 ;ADREN: SDRAM enable WM320xf108 0xc600 ;SDRAM Config 1 WM320xf10c 0x88b70004 ;SDRAM Config 2 WM320xf110 0x0300 ;SDRAM Adrsel WM320xf104 0xd14f ;SDRAM Control WM320xf104 0xd14f0002 ;SDRAM Control WM320xf104 0xd14f0004 ;SDRAM Control WM320xf100 0x008d ;SDRAM Mode WM320xf104 0x514f ;SDRAM Control ; define maximal transfer size TSZ40xFF80 0x ;ROM space TSZ40xF000 0xF0003FFF ;internal registers ; define the valie memory map MMAP0x 0x03FF ;Memory range for SDRAM MMAP0xF000 0xF0003FFF ;Memory map for Internal Register MMAP0xF004 0xF0005FFF ;Memory map for On-chip SRAM ; Setup MMU info WM320x00f0 0x ;invalidate page table pointer pointer [TARGET] CPUTYPE 5100;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock WORKSPACE 0x0200 ;workspace for fast download and cache flush BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT) ;STARTUP STOP 5000 WAKEUP 1000;give reset time to complete BREAKMODE HARD;SOFT or HARD, HARD uses PPC hardware breakpoint ;MMU XLAT ;translate effective to physical address PTBASE 0x00f0 ;here is the pointer to the page table pointers DCACHE NOFLUSH ;VECTOR CATCH ;catch unhandled exceptions ;MEMDELAY2000;additional memory access delay ;PARITY ON ;enable data parity generation [HOST] ; in the copy in your /tftpboot directory, uncomment the line that is yours IP 199.10.246.44 ; rome ;IP 199.10.246.18 ; vienna ;FILEE:\cygwin\home\bdidemo\mpc4200\fibo.exe ;FILEE:\cygwin\home\bdidemo\mpc4200\eppc_c_isr.elf ;FILEvmlinux FILElinux.bin FORMAT BIN ;FORMAT ELF ;LOADMANUAL ;load code MANUAL or AUTO after reset [FLASH] [REGS] DMM10xF000 ;dBug remaps IPIB to 0xF000 FILEreg5100.def ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
Bringing up Motorola MGT5100
I am working on bringing up Linux on a Motorola MGT5100 board. It's core is roughly a 603e, with lots of other devices on the chip. I am using an Abatron and have a question about really early boot. When the MMU is first turned and we are executing at 0xC-bazillion the Abatron can't read the contents of those addresses. Is this a dark time when the Abatron isn't expected to be able to read that memory, or do I have the MMU or Abatron set up wrong? (I can single step and put hardware breakpoints up there.) Thanks, -kb ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
Bringing up Motorola MGT5100
On Thu, Feb 20, 2003 at 02:48:12PM -0500, Kent Borg wrote: [snip] > [TARGET] > CPUTYPE 5100;the CPU type Are you sure you want this? Maybe it should be '603'.. > ;MMU XLAT ;translate effective to physical address > PTBASE 0x00f0 ;here is the pointer to the page table pointers Keep the MMU line, comment out the PTBASE maybe? I'm not sure 'tho.. -- Tom Rini http://gate.crashing.org/~trini/ ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
PowerMac vs. Intel for PowerPC Development Host
Ah, if that's the case, another data point. The 2.8 GHz dual P4, with hyperthreading on (very important) and make -j 8 gives me a 1m 45s _devel tree build for the ebony. If the cache is warm it's faster but that's with a cold buffer cache. } I wasn't trying to compare fairly, mostly get the lowest possible } compile time. } } } On Wed, Feb 19, 2003 at 09:10:48PM -0800, Eugene Surovegin wrote: } } > I tried to compile the _same_ PPC kernel for one of boards (440GP } > based). } } > Cross compiling on PIII 755Mhz running SuSE- 16 min } > Cross compiling on G4 PowerBook 1Ghz running YDL - 6 min } } I don't have a PPC host to reasonably compare with, but a 440GP kernel } (linuxppc_2_4_devel) for me builds in 3 minutes 29s (with gcc-2.95). } } } }--cw } ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
PowerMac vs. Intel for PowerPC Development Host
A $600 Dell 1.8GHz builds the 2_4_devel 440 kernel in 2m 45s. That's just great for our users. The x86's are getting cheaper and faster, too. However, we do use the native builds for some whacky packages (like X) that are never going to cross-build properly. } As an actual data point: my measurements show that a dual 1GHz G4 } powermac is more than twice as fast at compiling PPC kernels as a } 1.7GHz P4 (single cpu). } } You can't fairly compare compiling a PPC kernel on a PPC box with } compiling an x86 kernel on an x86 box. GCC does more work compiling } for PPC than for x86. } } Paul. } ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
Bringing up Motorola MGT5100
On Thu, Feb 20, 2003 at 02:27:03PM -0500, Kent Borg wrote: > I am working on bringing up Linux on a Motorola MGT5100 board. It's > core is roughly a 603e, with lots of other devices on the chip. > > I am using an Abatron and have a question about really early boot. > When the MMU is first turned and we are executing at 0xC-bazillion the > Abatron can't read the contents of those addresses. Is this a dark > time when the Abatron isn't expected to be able to read that memory, > or do I have the MMU or Abatron set up wrong? (I can single step and > put hardware breakpoints up there.) Bad config. Can you post it please? -- Tom Rini http://gate.crashing.org/~trini/ ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
PowerMac vs. Intel for PowerPC Development Host
Chris Wedgwood writes: > > On Wed, Feb 19, 2003 at 01:52:58PM -0800, brian.auld at adic.com wrote: > > > In the Intel vs. Mac debate for a linux development host for > > embedded ppc development, if money was not an issue, would I get > > more PowerMac recommendations?? > > Despire what Apple and a few other people claim, Intel solutions are > faster in terms of compile times, and if money was no barrier, then > Intel solutions are potentially *much* faster. As an actual data point: my measurements show that a dual 1GHz G4 powermac is more than twice as fast at compiling PPC kernels as a 1.7GHz P4 (single cpu). You can't fairly compare compiling a PPC kernel on a PPC box with compiling an x86 kernel on an x86 box. GCC does more work compiling for PPC than for x86. Paul. ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
FW: PowerMac vs. Intel for PowerPC Development Host
-Original Message- From: Wells, Charles Sent: Thursday, February 20, 2003 9:48 AM To: 'Chris Wedgwood' Subject: RE: PowerMac vs. Intel for PowerPC Development Host While I don't want to get into the Mac vs. Intel debate, I have an observations about Paul's numbers. Building kernels requires a lot of disk accesses. The Toshiba/Hitachi/IBM style hard disks that are used in most modern laptops (Mac or Intel) are notoriously slow compared to full-sized desktop hard drives (particularly the high performance SCSI drives). It wouldn't be meaningful to compare two systems without describing the access time performance of the hard disks. While I don't have the numbers in front of me, I believe the the fastest machine I have access to for building kernels is my trusty old 450 MHz. desktop G3 at home. It has 3 very fast IBM SCSI drives. In my book, how fast a kernel compiles is as much a matter of how much you're willing to spend on hard drives as it is CPU architectural considerations. Leave the "CPU clock speed comparisons" to the marketing guys. -Original Message- From: Chris Wedgwood [mailto:[EMAIL PROTECTED] Sent: Thursday, February 20, 2003 12:46 AM To: Paul Mackerras; Eugene Surovegin Cc: brian.auld at adic.com; linuxppc-embedded at lists.linuxppc.org Subject: Re: PowerMac vs. Intel for PowerPC Development Host On Thu, Feb 20, 2003 at 12:22:52PM +1100, Paul Mackerras wrote: > As an actual data point: my measurements show that a dual 1GHz G4 > powermac is more than twice as fast at compiling PPC kernels as a > 1.7GHz P4 (single cpu). Wow... that's *much* better that I would have guessed. Is the compiler the same for each? > You can't fairly compare compiling a PPC kernel on a PPC box with > compiling an x86 kernel on an x86 box. GCC does more work compiling > for PPC than for x86. I wasn't trying to compare fairly, mostly get the lowest possible compile time. On Wed, Feb 19, 2003 at 09:10:48PM -0800, Eugene Surovegin wrote: > I tried to compile the _same_ PPC kernel for one of boards (440GP > based). > Cross compiling on PIII 755Mhz running SuSE- 16 min > Cross compiling on G4 PowerBook 1Ghz running YDL - 6 min I don't have a PPC host to reasonably compare with, but a 440GP kernel (linuxppc_2_4_devel) for me builds in 3 minutes 29s (with gcc-2.95). ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
PPC405 UART
Hi guys, I'm currently working on a IBM ppc405 core based STBx25 board, and I'm trying to hack its UARTs. For those of you who are not familiar with these boards, the UARTs are "almost" standard ones. Their only difference with the typical 16550 ones is that they use 2 divisors instead of just (DLL+DLH) to fix the baud rate. I'm tweaking the serial.c driver in order to use both divisors, but with no success so far. So my questions to you would be : - Are some of you working on the same core/boards (i.e. IBM STBx25 set top boxes) ? - If yes, have you ever tried to use the 2 available divisors on the UARTs? - If no, then do you know of some other mailing list, IRC channel, news group or web site where I could find any kind of help related to my problem ? Any suggestions, remarks, hints are greatly appreciated. Thanks in advance for your help. Cheers, Samuel. ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
PowerMac vs. Intel for PowerPC Development Host
Brian, I think one advantage of using a mac with linuxppc as host (I use that @ home) is that you can use newer compiler/library versions a little bit more easy. I wasn't able yet to cross compile gcc-3.x for ppc on Solaris host, it worked however on the mac. Jaap-Jan brian.auld at adic.com wrote: > > A while back I wrote an email to this list regarding development kit > suggestions. Based mainly on feedback from this email, I am currently moving > in the Intel/ELDK direction. > > Out of all the feedback I received, only one person suggested developing on > a PowerMac based Linux box, thus eliminating the need for cross-compiling. I > have become more interested in this option as some people in our company > have noted that cross-compiling embedded linux presented problems on past > projects when it came to building certain 3rd party applications. > > In the Intel vs. Mac debate for a linux development host for embedded ppc > development, if money was not an issue, would I get more PowerMac > recommendations?? > > Thanks, > > -- Brian > -- J.G.J. Boor Room: BE-525 Lucent Technologies Nederland b.v. Phone: +31 35 687 4721 Optical Networking Group TMS DataFax: +31 35 687 5976 P.O. Box 1168, 1200 BD, Hilversum, The Netherlands mailto:jjboor at lucent.com ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
about filesize when copy from flash to ram
You are copying flash over top of your interrupt vectors, overwriting active code and crashing your system. Don't do that. Getting a load into the bottom of RAM (e.g. loading linux) is a delicate dance that u-boot does well, so use that function. You are not going to be able to do it with the "cp" command. Read the README file for a lot more information. gvb >From: okisoftxman [mailto:okisoftxman at hotmail.com] >Sent: Wednesday, February 19, 2003 6:04 PM >To: linux-emb >Subject: about filesize when copy from flash to ram > > > >First thank you for your help. > >Useing my MBX860 board's u-boot,I try to copy some files from flash to >ram.The files in this address "fe60" in the flash. >I find a problem when I use this command"cp.b fe00 filesize",if >the filesize<=900sbit(hex),the >file can copy from flash to ram.but if the filesize>=900sbit(hex),the system >will reset.e.g."cp.b fe00 1000"will reset the system and fail >to copy to ram,why? > >The critical value of filesize is between 900~1000,about 2Kbytes,why? > >Thank you > > ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
Support for MPC8265 PCI Bridge
Does Linux have support for the MPC8265 PCI Bridge? If so, how is it configured? What does the bootloader have to do? I am using U-Boot. Thanks, Don ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
Romdisk
Hello, I have created a romfs image using the Genromfs . DO i need to cat this image with the kernel image (Vmlinux.gz) ? I had created a single image using the command ./mkimage -A ppc -O Linux -T multi -C gzip \ -n 'Linux-2.4.4 Multiboot-Image' -e 0 -a 0 \ -d vmlinux.gz:romfs.img Romimage I have given the Bootargs as "root=/dev/mtdblock0" I have enabled the romfs file system option as well as MTd block device option in the kernel. Wheni download this multiimage kernel i get the error like VFS: Mounted root (romfs filesystem) readonly. Kernel panic: I have no root and I want to scream please tell me how does the kernel recognise the start of the romfs.and where should the romfs be loaded ? Yahoo! Tax Center - forms, calculators, tips, more http://taxes.yahoo.com/ ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
