Timer modification
Hi all, Can any one know how the "timer_adj" calculation is working in timer.c in linuxkernle2.6.12.5 If we change the HZ value to more than 1000. What hapens to the wall clock. And i have seen different "time_adj" calculations for HZ 100 and 1000. How to change this calculation for new HZ value. Thanks, Cjag
[RFC] MPC5200 BestComm microcode [en]/[de]coding draft
Hello Sylvain, This a draft of Documentation/powerpc/bestcomm.txt, it was born since I couldn't find DRD/LCD description and "... graphical task builder are currently in development" (quotation from AN2604) :(, so I try write doco by myself. Here result of my reverse engineering. If you or somebody have more information or found some bugs, please, fix/expand my text, especially places marked by "?". -- Regards Andrey Volkov -- next part -- An embedded and charset-unspecified text was scrubbed... Name: bestcomm.diff Url: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20050818/0cdd94b9/attachment.txt
[PATCH] ppc32: ppc_sys SOC identification additions
Here's the same but without strcmp(). Signed-off-by: Vitaly Bordug -- Sincerely, Vitaly -- next part -- A non-text attachment was scrubbed... Name: ppc_sys_add.patch Type: text/x-patch Size: 2491 bytes Desc: not available Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20050818/6c96e248/attachment.bin
How to implementing CLI using bison and FLEX
HI, I am currenly working on mpc850 processor.I wanted to implement a Command Line interface. I like implement it using bison and flex tool. If anyone is familar or already implemented plz help me -- With Regards, Sanjeevi G
Regarding Keyboard events mapping in different consoles
Hi, I am currently working on Powerpc405 Processor. Here I have two interfaces like serial Interface and IR Interface. When I boot the kernel using the Serial console what ever i type from the keyboard(on a PC) using minicom the serial data transfer takes place in kernel , the kernel decodes the key events of serial console( serial interface). Now, I have built the IR Driver which access the handle_scancode function in the kernel (keyboard.c) by passing the required scan codes and status of the keys. The problem here is What ever i type using IR Keyboard appears on my VC (virtual console or Frame buffer Device) . How do I make IR key events(handle_scancode) to be handled by the Serial console's keyboard part. Please do guide me how to proceed. -- Thanks and Regards, Vijesh V H -- next part -- An HTML attachment was scrubbed... URL: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20050818/b5e3c9c1/attachment.htm
jffs2 image upgrade on running root
Hi Guys, I have a running embedded 2.6.11 distro with a busybox type jffs2 rfs. Not I am trying to upgrade that jffs2 imaged and tried something like to following. Have a temp ext2 ramdisk mounted in /mnt pivot_root . oldroot exec chroot . /linuxrc dev/console 2>&1 or exec chroot . /sbin/init dev/console 2>&1 all "seem" to work bit init is still running I think on the /oldroot/ as well so when I try to umount /oldroot is just get device or resource busy. Any ideas? Tony Hardie B.Sc SHOUTIP Software Architect Net.com 6900 Paseo Padre Parkway Fremont CA, 94555 Ph: 510-574-2386 Mob: 510-449-4339
segmentaion fault with array[4096]
Hi! On Thu, Aug 18, 2005 at 11:45:04AM +0200, Studencki Pawel wrote: > hello, > > because I want to do some tests with fusion/RTAI on my mpc852, > I had to downgrade my system to kernel 2.6.10 Downgrade from what? > And I get a strange problem: if I start application with char array size > 4096 (or even smaller 2600) I get "segmentation fault". > > Could someone gives me a hint? Is this kernel configuration problem? > Where can I start looking for a reason? Have you tried to debug the application with gdb to spot more precisely what is it doing that makes it receive a segfault? Most likely its doing an invalid memory access.
[PATCH] PPC: Don't sleep in flush_dcache_icache_page()
Hi Roland,
On Tue, Aug 16, 2005 at 01:56:49PM -0700, Roland Dreier wrote:
> flush_dcache_icache_page() will be called on an instruction page
> fault. We can't sleep in the fault handler, so use kmap_atomic()
> instead of just kmap() for the Book-E case.
>
> Signed-off-by: Roland Dreier
Why do you need to disable interrupts during the kmap_atomic/flush_dcache_icache
operation ?
I fail to see how an interrupt could have any reference to the data
being dealt with here (the user page).
> diff --git a/arch/ppc/mm/init.c b/arch/ppc/mm/init.c
> --- a/arch/ppc/mm/init.c
> +++ b/arch/ppc/mm/init.c
> @@ -560,8 +560,16 @@ void flush_dcache_page(struct page *page
> void flush_dcache_icache_page(struct page *page)
> {
> #ifdef CONFIG_BOOKE
> - __flush_dcache_icache(kmap(page));
> - kunmap(page);
> + unsigned long flags;
> + void *start;
> +
> + local_irq_save(flags);
> +
> + start = kmap_atomic(page, KM_PPC_SYNC_PAGE);
> + __flush_dcache_icache(start);
> + kunmap_atomic(start, KM_PPC_SYNC_PAGE);
> +
> + local_irq_restore(flags);
> #elif CONFIG_8xx
> /* On 8xx there is no need to kmap since highmem is not supported */
> __flush_dcache_icache(page_address(page));
[PATCH] Fix for TLB errata on early Xilinx Virtex-II Pro silicon
Grant Likely wrote: > Early versions of the Xilinx Virtex-II Pro have a TLB errata where > only even numbered TLB entries work correctly. Occurs on chips where > PVR == 0x20010820 || 0x20010860 > > See Record #14052, solution #12 in the Xilinx answers database > http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=14052 > > This patch adds a config option to use only even TLB entries on the V2Pro > It also makes a trivial change to the Kconfig so that Xilinx options depend > on VIRTEX_II_PRO instead of XILINX_ML300 > > Signed-off-by: Grant Likely > --- > > arch/ppc/kernel/head_4xx.S | 11 +++ > arch/ppc/platforms/4xx/Kconfig | 28 ++-- > 2 files changed, 33 insertions(+), 6 deletions(-) > > 322a82cd190a777e4ebe728cad2a2a3759039260 > diff --git a/arch/ppc/kernel/head_4xx.S b/arch/ppc/kernel/head_4xx.S > --- a/arch/ppc/kernel/head_4xx.S > +++ b/arch/ppc/kernel/head_4xx.S > @@ -769,7 +769,11 @@ finish_tlb_load: > /* load the next available TLB index. > */ > lwz r9, tlb_4xx_index at l(0) > +#if defined(CONFIG_VIRTEX_II_PRO_TLB_FIX) > + addir9, r9, 2 > +#else > addir9, r9, 1 > +#endif > andi. r9, r9, (PPC4XX_TLB_SIZE-1) > stw r9, tlb_4xx_index at l(0) I would also fix the comment in this file (it has nothing to do with the TLB fix but...): @@ -915,10 +919,10 @@ initial_mmu: mtspr SPRN_PID,r0 sync - /* Configure and load two entries into TLB slots 62 and 63. -* In case we are pinning TLBs, these are reserved in by the + /* Configure and load an entry into TLB slot 63. +* In case we are pinning TLBs, it is reserved in by the * other TLB functions. If not reserving, then it doesn't -* matter where they are loaded. +* matter where it is loaded. */ clrrwi r4,r4,10/* Mask off the real page number */ ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ > @@ -926,7 +930,14 @@ initial_mmu: > clrrwi r3,r3,10/* Mask off the effective page number > */ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M)) > > +#if defined(CONFIG_VIRTEX_II_PRO_TLB_FIX) > + /* Odd numbered TLB slots are broken on Xilinx V2Pro processors > +* where PVR = 20010820 | 20010860 > +*/ > +li r0,62/* TLB slot 62 */ > +#else > li r0,63/* TLB slot 63 */ > +#endif > > tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry > */tlbwe r3,r0,TLB_TAG /* Load the tag portion of the > entry */ > diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig > --- a/arch/ppc/platforms/4xx/Kconfig > +++ b/arch/ppc/platforms/4xx/Kconfig > @@ -161,11 +161,6 @@ config IBM_OCP > depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || > LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT > default y > > -config XILINX_OCP > - bool > - depends on XILINX_ML300 > - default y > - > config IBM_EMAC4 > bool > depends on 440GX || 440SP > @@ -201,6 +196,27 @@ config VIRTEX_II_PRO > depends on XILINX_ML300 > default y > > +config VIRTEX_II_PRO_TLB_FIX > + bool "Virtex-II Pro TLB bugfix" > + depends on VIRTEX_II_PRO > + default n > + help > + Early versions of the Xilinx Virtex-II Pro have a TLB errata where > + only even numbered TLB entries work correctly. Say Y here if > + PVR == 0x20010820 || 0x20010860, or if your board crashes early > + after enabling the MMU > + > + See Record #14052, solution #12 in the Xilinx answers database > + http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=14052 > + > + It is safe to say Y here, but there is a performance impact. > + Say N if unsure. > + > +config XILINX_OCP > + bool > + depends on VIRTEX_II_PRO > + default y > + > config STB03xxx > bool > depends on REDWOOD_5 || REDWOOD_6 > @@ -208,7 +224,7 @@ config STB03xxx > > config EMBEDDEDBOOT > bool > - depends on EP405 || XILINX_ML300 > + depends on EP405 || VIRTEX_II_PRO > default y > > config IBM_OPENBIOS I would drop the last chunk. I agree that VIRTEX_II_PRO_TLB_FIX and XILINX_OCP should depend on the chip (VIRTEX_II_PRO), but using EMBEDDEDBOOT or, say, U-Boot is at least board specific. Well, even the same board can use different bootloaders, but tying together EMBEDDEDBOOT and VIRTEX_II_PRO is even worse IMO. Otherwise the patch looks OK. These changes to head_4xx.S were tested OK on ML300: in both cases (odd numbered TLB slots used or not) there were no problems. (For some unknown reason my ML300 doesn't need this workaround though 'cat /proc/cpuinfo' gets "revision: 8.32 (pvr 2001 0
[PATCH] Fix for TLB errata on early Xilinx Virtex-II Pro silicon
[PATCH] Early versions of the Xilinx Virtex-II Pro have a TLB errata where only even numbered TLB entries work correctly. Occurs on chips where PVR == 0x20010820 || 0x20010860 See Record #14052, solution #12 in the Xilinx answers database http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=14052 This patch adds a config option to use only even TLB entries on the V2Pro It also makes a trivial change to the Kconfig so that Xilinx options depend on VIRTEX_II_PRO instead of XILINX_ML300. Also fixes incorrect comment Signed-off-by: Grant Likely --- arch/ppc/kernel/head_4xx.S | 18 ++ arch/ppc/platforms/4xx/Kconfig | 26 +- 2 files changed, 35 insertions(+), 9 deletions(-) b9dd781e27bc3ddce51141b3d9844ebec1e424f2 diff --git a/arch/ppc/kernel/head_4xx.S b/arch/ppc/kernel/head_4xx.S --- a/arch/ppc/kernel/head_4xx.S +++ b/arch/ppc/kernel/head_4xx.S @@ -769,7 +769,11 @@ finish_tlb_load: /* load the next available TLB index. */ lwz r9, tlb_4xx_index at l(0) +#if defined(CONFIG_VIRTEX_II_PRO_TLB_FIX) + addir9, r9, 2 +#else addir9, r9, 1 +#endif andi. r9, r9, (PPC4XX_TLB_SIZE-1) stw r9, tlb_4xx_index at l(0) @@ -915,10 +919,9 @@ initial_mmu: mtspr SPRN_PID,r0 sync - /* Configure and load two entries into TLB slots 62 and 63. -* In case we are pinning TLBs, these are reserved in by the -* other TLB functions. If not reserving, then it doesn't -* matter where they are loaded. + /* Configure and load a temporary TLB entry into slot 63 (or 62 when +* CONFIG_VIRTEX_II_PRO_TLB_FIX is enabled). This entry is +* invalidated once the page tables are set up. */ clrrwi r4,r4,10/* Mask off the real page number */ ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ @@ -926,7 +929,14 @@ initial_mmu: clrrwi r3,r3,10/* Mask off the effective page number */ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M)) +#if defined(CONFIG_VIRTEX_II_PRO_TLB_FIX) + /* Odd numbered TLB slots are broken on Xilinx V2Pro processors +* where PVR = 20010820 | 20010860 +*/ +li r0,62/* TLB slot 62 */ +#else li r0,63/* TLB slot 63 */ +#endif tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */ diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig --- a/arch/ppc/platforms/4xx/Kconfig +++ b/arch/ppc/platforms/4xx/Kconfig @@ -161,11 +161,6 @@ config IBM_OCP depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT default y -config XILINX_OCP - bool - depends on XILINX_ML300 - default y - config IBM_EMAC4 bool depends on 440GX || 440SP @@ -201,6 +196,27 @@ config VIRTEX_II_PRO depends on XILINX_ML300 default y +config VIRTEX_II_PRO_TLB_FIX + bool "Virtex-II Pro TLB bugfix" + depends on VIRTEX_II_PRO + default n + help + Early versions of the Xilinx Virtex-II Pro have a TLB errata where + only even numbered TLB entries work correctly. Say Y here if + PVR == 0x20010820 || 0x20010860, or if your board crashes early + after enabling the MMU + + See Record #14052, solution #12 in the Xilinx answers database + http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=14052 + + It is safe to say Y here, but there is a performance impact. + Say N if unsure. + +config XILINX_OCP + bool + depends on VIRTEX_II_PRO + default y + config STB03xxx bool depends on REDWOOD_5 || REDWOOD_6
segmentaion fault with array[4096]
hello, because I want to do some tests with fusion/RTAI on my mpc852, I had to downgrade my system to kernel 2.6.10 And I get a strange problem: if I start application with char array size 4096 (or even smaller 2600) I get "segmentation fault". Could someone gives me a hint? Is this kernel configuration problem? Where can I start looking for a reason? thanks Pawel
Best kernel for Xilinx VirtexII Pro/PPC405 ?
Hi Peter - Well, the good news is that it works, and works well. In my humble opinion, supporting it would be pretty simple, but I completely understand why RHEL is the supported distribution. I would much rather see effort put into polishing up EDK under Linux than in supporting every Linux distro out there. For me, the bottom line was this: do I want to migrate all of other development activities from FC4 to RHEL for the sake of EDK, or try to run EDK under FC4? I tried the latter approach, and now that the Jungo WinDriver v7.1 is out, parallel port debugging works by simply using WinDriver 7.1 and patching the Xilinx XPC4 parport driver. I now have the kernel booting on a Memec 2VP50 eval board using U-Boot as the bootloader. I used the linuxppc-2.4 kernel rsynced from MontaVista. That particular kernel did not have support for U-Boot but it did support the ML300 and a Memec 2VP40/2VP70 board. I had to modify the kernel to accept a board description structure from U-Boot and I added a new board type for my custom hardware. The approach I took was definitely the "roll your own approach", but then again I've done this (Linux board ports) a couple times and I know U-Boot well. Keith Peter Ryser wrote on 08/18/2005 07:39:21 AM: > > > I am running all of my development tools (EDK, ISE, ELDK, etc...) under > >Fedora Core 4, so I am looking for a publicly accessible kernel source > >tree that best supports the PPC405 in the Virtex II Pro. > > > Keep in mind that EDK and ISE are not "officially" supported on FC4. > Anyway, with EDK, ISE, and ELDK you seem to have all that is needed to > get started with Linux on Virtex-II Pro and Virtex-4. > > - Peter > >
[PATCH] PPC: Don't sleep in flush_dcache_icache_page()
On Thu, Aug 18, 2005 at 02:56:42PM -0300, Marcelo Tosatti wrote: > > Hi Roland, > > On Tue, Aug 16, 2005 at 01:56:49PM -0700, Roland Dreier wrote: > > flush_dcache_icache_page() will be called on an instruction page > > fault. We can't sleep in the fault handler, so use kmap_atomic() > > instead of just kmap() for the Book-E case. > > > > Signed-off-by: Roland Dreier > > Why do you need to disable interrupts during the > kmap_atomic/flush_dcache_icache > operation ? > > I fail to see how an interrupt could have any reference to the data > being dealt with here (the user page). We just took care of this offline. The original patch is sharing a kmap slot with another kmap_atomic user I put in before...the sync page user. If an interrupt came in causing the DMA API to be used, we would have a problem. The clean solution was to use a different kmap slot. -Matt
How to implementing CLI using bison and FLEX
On Thu, Aug 18, 2005 at 05:16:19PM +0530, Sanjeevi Gopal wrote: > HI, > > > I am currenly working on mpc850 processor.I wanted to > implement a Command Line interface. I like implement it using bison > and flex tool. If anyone is familar or already implemented plz help me See the Lex and YACC HOWTO[1] on tldp.org for a gentle introduction, and the flex[2] and bison[3] manuals on gnu.org for the gory details: [1] http://tldp.org/HOWTO/Lex-YACC-HOWTO.html [2] http://www.gnu.org/software/flex/manual/ [3] http://www.gnu.org/software/bison/manual/
Multiple I2C busses on PPC405
I've not received any reply to my inquiry. Since it was last Friday afternoon it might have been missed. I really do appreciate if someone would suggest a bitbang I2C interface driver generic enough to modify. I only need /dev/i2c? support from the driver. Tolunay Tolunay Orkun wrote: > I have a working embedded linux on Cogent CSB472 board (PPC405GP) > currently based on off 2.4.31. We are already using the I2C bus on > PowerPC using hardware I2C driver (IBM IIC I2C Interface) at Fast > (400khz) mode. > > We need to add support for yet another (slow) I2C bus with PPC405 being > the master and I'm looking at implementing bit bang interface using GPIO > pins. > > What is the best way to get this going? I am looking at modifying the > bit bang driver (PPC_405_I2C_Algorithm?) for the I/O pins I'll use. > Anyone has done something similar. I appreciate all the advice I can get. > > Best Regards, > Tolunay > > >
linux2.6 crosscompiler setup
On Thursday 18 August 2005 08:54, somshekar chandrashekar kadam wrote: > ?HI , hey, there's no need to ask twice if you did not get an answer within 4 minutes! > need to set the cross compiler for Linux 2.6 PPC from scratch on X86 host, is > there any howto or anyother document , > i saw only denx eldk supporting it . guess you didn't search carefully enough ;) > wanted to build entire cross compiler from scratch , please direct me to any > good link if it is there , > tried to open the link given on Embedded PowerPC linux howto , that page > doesnt exist anymore ,please suggest guys which one is better he, what about google? http://www.google.de/search?hl=de&ie=ISO-8859-1&q=cross%2Bcompiler%2Bscratch%2Blinux%2Bppc&btnG=Google-Suche&meta= Anyway, try: http://www.kegel.com/crosstool/ Ciao, Gerhard -- Gerhard Jaeger SYSGO AG Embedded and Real-Time Software www.sysgo.com | www.elinos.com | www.pikeos.com | www.osek.de
[PATCH] Fix for TLB errata on early Xilinx Virtex-II Pro silicon
On Wed, Aug 17, 2005 at 02:05:47PM -0600, Grant Likely wrote: > config EMBEDDEDBOOT > bool > - depends on EP405 || XILINX_ML300 > + depends on EP405 || VIRTEX_II_PRO > default y > Grant, Can you post another patch without this hunk?..as Andrei pointed out, it's a board specific feature. Otherwise, looks good to go upstream. -Matt
Best kernel for Xilinx VirtexII Pro/PPC405 ?
> I am running all of my development tools (EDK, ISE, ELDK, etc...) under >Fedora Core 4, so I am looking for a publicly accessible kernel source >tree that best supports the PPC405 in the Virtex II Pro. > Keep in mind that EDK and ISE are not "officially" supported on FC4. Anyway, with EDK, ISE, and ELDK you seem to have all that is needed to get started with Linux on Virtex-II Pro and Virtex-4. - Peter
[PATCH] Fix for TLB errata on early Xilinx Virtex-II Pro silicon
None of the ML300 will need this workaround as the core voltage is slightly higher than recommended in the data sheet of Virtex-II Pro. An increased core voltage is one way to fix the TLB problem in early parts but it is not the right way as it can have a negative impact on other V2P features. Since the ML300 configuration is used as the base for other boards the patch is still useful. However, all Virtex-II Pro FPGAs that are shipping today are based on newer core versions and do not show the TLB problem. - Peter Andrei Konovalov wrote: > Grant Likely wrote: > >> Early versions of the Xilinx Virtex-II Pro have a TLB errata where >> only even numbered TLB entries work correctly. Occurs on chips where >> PVR == 0x20010820 || 0x20010860 >> >> See Record #14052, solution #12 in the Xilinx answers database >> http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=14052 >> >> This patch adds a config option to use only even TLB entries on the >> V2Pro >> It also makes a trivial change to the Kconfig so that Xilinx options >> depend >> on VIRTEX_II_PRO instead of XILINX_ML300 >> >> Signed-off-by: Grant Likely >> --- >> >> arch/ppc/kernel/head_4xx.S | 11 +++ >> arch/ppc/platforms/4xx/Kconfig | 28 ++-- >> 2 files changed, 33 insertions(+), 6 deletions(-) >> >> 322a82cd190a777e4ebe728cad2a2a3759039260 >> diff --git a/arch/ppc/kernel/head_4xx.S b/arch/ppc/kernel/head_4xx.S >> --- a/arch/ppc/kernel/head_4xx.S >> +++ b/arch/ppc/kernel/head_4xx.S >> @@ -769,7 +769,11 @@ finish_tlb_load: >> /* load the next available TLB index. >> */ >> lwz r9, tlb_4xx_index at l(0) >> +#if defined(CONFIG_VIRTEX_II_PRO_TLB_FIX) >> + addir9, r9, 2 >> +#else >> addir9, r9, 1 >> +#endif >> andi. r9, r9, (PPC4XX_TLB_SIZE-1) >> stw r9, tlb_4xx_index at l(0) > > > I would also fix the comment in this file > (it has nothing to do with the TLB fix but...): > > @@ -915,10 +919,10 @@ initial_mmu: > mtsprSPRN_PID,r0 > sync > > -/* Configure and load two entries into TLB slots 62 and 63. > - * In case we are pinning TLBs, these are reserved in by the > +/* Configure and load an entry into TLB slot 63. > + * In case we are pinning TLBs, it is reserved in by the > * other TLB functions. If not reserving, then it doesn't > - * matter where they are loaded. > + * matter where it is loaded. > */ > clrrwir4,r4,10/* Mask off the real page number */ > orir4,r4,(TLB_WR | TLB_EX)/* Set the write and execute > bits */ > >> @@ -926,7 +930,14 @@ initial_mmu: >> clrrwi r3,r3,10/* Mask off the effective >> page number */ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M)) >> >> +#if defined(CONFIG_VIRTEX_II_PRO_TLB_FIX) >> + /* Odd numbered TLB slots are broken on Xilinx V2Pro processors >> +* where PVR = 20010820 | 20010860 >> +*/ >> +li r0,62/* TLB slot 62 */ >> +#else >> li r0,63/* TLB slot 63 */ >> +#endif >> >> tlbwe r4,r0,TLB_DATA /* Load the data portion of >> the entry */tlbwe r3,r0,TLB_TAG /* Load the tag >> portion of the entry */ >> diff --git a/arch/ppc/platforms/4xx/Kconfig >> b/arch/ppc/platforms/4xx/Kconfig >> --- a/arch/ppc/platforms/4xx/Kconfig >> +++ b/arch/ppc/platforms/4xx/Kconfig >> @@ -161,11 +161,6 @@ config IBM_OCP >> depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || >> EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT >> default y >> >> -config XILINX_OCP >> - bool >> - depends on XILINX_ML300 >> - default y >> - >> config IBM_EMAC4 >> bool >> depends on 440GX || 440SP >> @@ -201,6 +196,27 @@ config VIRTEX_II_PRO >> depends on XILINX_ML300 >> default y >> >> +config VIRTEX_II_PRO_TLB_FIX >> + bool "Virtex-II Pro TLB bugfix" >> + depends on VIRTEX_II_PRO >> + default n >> + help >> + Early versions of the Xilinx Virtex-II Pro have a TLB >> errata where >> + only even numbered TLB entries work correctly. Say Y here if >> + PVR == 0x20010820 || 0x20010860, or if your board crashes >> early >> + after enabling the MMU >> + >> + See Record #14052, solution #12 in the Xilinx answers database >> + >> http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=14052 >> + >> + It is safe to say Y here, but there is a performance impact. >> + Say N if unsure. >> + >> +config XILINX_OCP >> + bool >> + depends on VIRTEX_II_PRO >> + default y >> + >> config STB03xxx >> bool >> depends on REDWOOD_5 || REDWOOD_6 >> @@ -208,7 +224,7 @@ config STB03xxx >> >> config EMBEDDEDBOOT >> bool >> - depends on EP405 || XILINX_ML300 >> + depends on EP405 ||
linux2.6 crosscompiler setup
?HI , need to set the cross compiler for Linux 2.6 PPC from scratch on X86 host , is there any howto or anyother document , i saw only denx eldk supporting it . wanted to build entire cross compiler from scratch , please direct me to any good link if it is there , tried to open the link given on Embedded PowerPC linux howto , that page doesnt exist anymore ,please suggest guys which one is better Thanks In Advance Neelu -- next part -- An HTML attachment was scrubbed... URL: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20050818/273a3a5c/attachment.htm
linux2.6 crosscompiler setup
?HI , need to set the cross compiler for Linux 2.6 PPC from scratch on X86 host , is there any howto or anyother document , i saw only denx eldk supporting it . wanted to build entire cross compiler from scratch , please direct me to any good link if it is there , tried to open the link given on Embedded PowerPC linux howto , that page doesnt exist anymore ,please suggest guys which one is better Thanks In Advance Neelu -- next part -- An HTML attachment was scrubbed... URL: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20050818/e1d4cfce/attachment.htm
