atomic operations in user space
-Original Message- From: Brent Cook [mailto:bcook at bpointsys.com] Sent: Thursday, August 24, 2006 10:18 PM To: linuxppc-embedded at ozlabs.org Cc: Li Yang-r58472; Terry Liang Subject: Re: atomic operations in user space On Thursday 24 August 2006 05:39, Li Yang-r58472 wrote: Why do you need atomic operations in user land? IPC will be sufficient to deal with race conditions between processes. Best Regards, Leo What about multiple threads within a process updating a counter? Is there anything preventing semaphore to be used in threads? Of course, if you look at these functions in the kernel header, they're just 2 or 3 inline assembly calls - you could easily rewrite them. Google for 'PowerPC atomic increment' and grab one of the unencumbered implementations if you need to use it in a non-GPL program. On the other hand, I see no license at the top of my /usr/include/asm-i386/atomic.h file at all, same for PowerPC - are Linux header files actually GPL or are they more like the glibc headers, with exceptions made for userspace programs? The atomic operations on x86 were accidentally exported early on, so they have to hang around apparently for compatibility (there are some mailing list threads out there to this effect.) Currently, you just have to assume in Linux that if you include something from /usr/include/linux or asm that it will not necessarily be cross-version or cross-architecture compatible. Not every arch in Linux even has atomic operations of this nature, which I guess is the main reason why they are not exported in general. - Brent
Cache coherency question
Tim I'm using an MVME6100 with Linux 2.6.14 and experiencing what Tim I think is a cache coherency problem. An external PCIX Tim master performs a DMA transfer of a well known data pattern Tim into SDRAM, but when the device driver goes to look at the Tim data it is mostly okay, but occasionally has garbage. If the hardware is reliable, I think you are right. The cache coherency problem. Tim I'm allocating the memory using alloc_skb, then giving a PCI Tim translated pointer to the PCIX master. Since I think it is a Tim cache coherency problem, I tried to use the dma_cache_inv Tim macro to invalidate the cache before looking at the data, but Tim realized that for this board, that function does nothing Tim since CONFIG_NOT_COHERENT_CACHE is undefined. So Tim questions: If the CONFIG_NOT_COHERENT_CACHE is not set. You are assuming and using the hardware cache coherency mechanism. Tim 1) Should the processor bus cache snooping actually work on Tim an MVME6100? Tim E.g. is it correct that CONFIG_NOT_COHERENT_CACHE is undefined? Yes, you can undefine the CONFIG_NOT_COHERENT_CACHE, but you must make sure the host bridge did the snooping setup for PCI inbound transaction. If you setup the snooping window, I think the host bridge will assert /GLB signal to processor. The processor will snoop the 60x/MPX bus to keep cache coherence. Also, you can define the CONFIG_NOT_COHERENT_CACHE, then you are assuming The system has not hardware coherency. You need use the software to keep the cache coherency. Tim 1a) Does this type of bus snooping work when a bus master Tim physically external to the PowerPC chip is doing the transfer? As above, you must tell the bridge what address need snoop. If you did, The proceesor will do snooping. Tim 2) If this really is a cache coherency problem, are there Tim other cache management functions available in ppc linux Tim besides the dma_cache_inv, dma_cache_wback, Tim dma_cache_wback_inv macros I should be looking at? I think it is a cache coherency problem, if you define the CONFIG_NOT_COHERENT_CACHE You can get these functions, dma_map_single -Dave
Problems with uaccsess.h
Hi when I compile my program i got this message bash-2.05b# make gcc -O2 -DMODULE -D__KERNEL__ -W -Wall -Wstrict-prototypes -Wmissing-prototypes -isystem /lib/modules/`uname -r`/build/include -c -o hello.o hello.c hello.c:5:25: linux/version: No such file or directory In file included from hello.c:9: /usr/include/asm/uaccess.h: In function `verify_area': /usr/include/asm/uaccess.h:37: error: `CONFIG_TASK_SIZE' undeclared (first use in this function) /usr/include/asm/uaccess.h:37: error: (Each undeclared identifier is reported only once /usr/include/asm/uaccess.h:37: error: for each function it appears in.) /usr/include/asm/uaccess.h: In function `copy_from_user': /usr/include/asm/uaccess.h:280: error: `CONFIG_TASK_SIZE' undeclared (first use in this function) /usr/include/asm/uaccess.h: In function `copy_to_user': /usr/include/asm/uaccess.h:294: error: `CONFIG_TASK_SIZE' undeclared (first use in this function) /usr/include/asm/uaccess.h: In function `clear_user': /usr/include/asm/uaccess.h:313: error: `CONFIG_TASK_SIZE' undeclared (first use in this function) /usr/include/asm/uaccess.h: In function `strncpy_from_user': /usr/include/asm/uaccess.h:327: error: `CONFIG_TASK_SIZE' undeclared (first use in this function) /usr/include/asm/uaccess.h: In function `strnlen_user': /usr/include/asm/uaccess.h:350: error: `CONFIG_TASK_SIZE' undeclared (first use in this function) These Header files I have include #include linux/module.h /* Needed by all modules */ #include linux/kernel.h /* Needed for KERN_ALERT */ #include linux/slab.h #include linux/delay.h #include linux/version #include linux/init.h #include linux/fs.h #include asm/types.h #include asm/mpc8260.h #include asm/cpm_8260.h #include asm/page.h #include asm/uaccess.h My linux is 2.4.25 Need I a patch to correct this ?? I need the funktion copy_to_user. Regards Fred -- Der GMX SmartSurfer hilft bis zu 70% Ihrer Onlinekosten zu sparen! Ideal f?r Modem und ISDN: http://www.gmx.net/de/go/smartsurfer
ip= command line strangeness...
Hi, please provide the ip-commandline in the full-size format ip=my ip:server ip:host ip:net mask:hostname:which ethernet port, e.g. eth0 I assume, that this will fix your problem -- Mit freundlichen Gruessen / Best regards Claus Gindhart SW RD Kontron Modular Computers phone :++49 (0)8341-803-374 mailto:claus.gindhart at kontron-modular.com http://www.kontron.com -BEGIN GEEK CODE BLOCK- Version: 3.1 GU d- s++:++:+ a+ C++$ !U !P L++$ E-- W+(-) N- o? K? w !O !M V !PS PE- Y+ PGP+ t 5? X R* tv- b+ DI+++ D-- G e++ h--- !r x+++ --END GEEK CODE BLOCK-- -Original Message- From: [EMAIL PROTECTED] [mailto:linuxppc-embedded-bounces+claus.gindhart=kontron.com at ozlabs.org] On Behalf Of T Ziomek Sent: Freitag, 25. August 2006 01:39 To: linuxppc-embedded Cc: tomz Subject: ip= command line strangeness... On my previous project, a 2.4 kernel on PPC, I frequently used ip=w.x.y.z on the kernel command line to specify a static IP address for my target board (when booting with a flash- or RAM-based root filesystem). Similarly, when using an NFS-mounted root fs, I would use ip=w.x.y.z:a.b.c.d, along with the appropriate nfsroot=... setting, with my NFS server having IP a.b.c.d . Now I am working with a 2.6.10-based kernel on ARM. Using an NFS root fs works fine when I use the expected ip=w.x.y.z:a.b.c.d. And booting off with root=/dev/hda1 works fine with ip=dhcp. I'd expect to be able to use root=/dev/hda1 ip=w.x.y.z if I want the target using a static IP address. But this fails, and in a VERY weird way: (1) It tries doing DHCP, which it shouldn't, and (2) the DHCP fails, which it shouldn't because it works when I want DHCP to be used. Here's a snippet of console output: . . . NET: Registered protocol family 2 IP: routing cache hash table of 512 buckets, 4Kbytes TCP: Hash tables configured (established 8192 bind 16384) NET: Registered protocol family 1 NET: Registered protocol family 17 Sending DHCP requests .. timed out! EMAC: TX Complete: Starting queue IP-Config: Reopening network devices... Sending DHCP requests ... Okay, that's two weird things. There is a third -- this problem goes a- way if I change the command line to something like root=/dev/hda1 ip=w.x.y.z:a.b.c.d. The only change is adding an NFS server IP address to the ip= command, which should have no effect be- cause NFS is not being used. Yet when I do that the board boots as ex- pected -- it does not try to do DHCP, it does use /dev/hda1 for its root fs, and it does take the specified IP address. In fact, it works even if I use a command line with, literally, root=/dev/hda1 ip=199.5.233.72:gobbledygook: . . . NET: Registered protocol family 2 IP: routing cache hash table of 512 buckets, 4Kbytes TCP: Hash tables configured (established 8192 bind 16384) NET: Registered protocol family 1 NET: Registered protocol family 17 IP-Config: Guessing netmask 255.255.255.0 IP-Config: Complete: device=eth0, addr=199.5.233.72, mask=255.255.255.0, gw=255.255.255.255, host=199.5.233.72, domain=, nis-domain=(none), bootserver=232.0.0.0, rootserver=232.0.0.0, rootpath= . . . This isn't a big problem, but can anybody explain what the heck is going on? Thanks, Tom -- /\ ASCII Ribbon Campaign | \ / | Email to user 'CTZ001' XAgainst HTML | at 'email.mot.com' / \ in e-mail news | ___ Linuxppc-embedded mailing list Linuxppc-embedded at ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Problems with uaccsess.h
Hi, Seems your makefile does not include all the kernel header ... Please try to add this ' -I(linux kernel source path)/include ' to your makefile as CFLAGS. Best regards, Lo Chun Chung -Original Message- From: linuxppc-embedded-bounces+cclo=astri.org at ozlabs.org [mailto:[EMAIL PROTECTED] On Behalf Of Keinen Namen Sent: Friday, 25 August, 2006 1:29 PM To: linuxppc-embedded at ozlabs.org Subject: Problems with uaccsess.h Hi when I compile my program i got this message bash-2.05b# make gcc -O2 -DMODULE -D__KERNEL__ -W -Wall -Wstrict-prototypes -Wmissing-prototypes -isystem /lib/modules/`uname -r`/build/include -c -o hello.o hello.c hello.c:5:25: linux/version: No such file or directory In file included from hello.c:9: /usr/include/asm/uaccess.h: In function `verify_area': /usr/include/asm/uaccess.h:37: error: `CONFIG_TASK_SIZE' undeclared (first use in this function) /usr/include/asm/uaccess.h:37: error: (Each undeclared identifier is reported only once /usr/include/asm/uaccess.h:37: error: for each function it appears in.) /usr/include/asm/uaccess.h: In function `copy_from_user': /usr/include/asm/uaccess.h:280: error: `CONFIG_TASK_SIZE' undeclared (first use in this function) /usr/include/asm/uaccess.h: In function `copy_to_user': /usr/include/asm/uaccess.h:294: error: `CONFIG_TASK_SIZE' undeclared (first use in this function) /usr/include/asm/uaccess.h: In function `clear_user': /usr/include/asm/uaccess.h:313: error: `CONFIG_TASK_SIZE' undeclared (first use in this function) /usr/include/asm/uaccess.h: In function `strncpy_from_user': /usr/include/asm/uaccess.h:327: error: `CONFIG_TASK_SIZE' undeclared (first use in this function) /usr/include/asm/uaccess.h: In function `strnlen_user': /usr/include/asm/uaccess.h:350: error: `CONFIG_TASK_SIZE' undeclared (first use in this function) These Header files I have include #include linux/module.h /* Needed by all modules */ #include linux/kernel.h /* Needed for KERN_ALERT */ #include linux/slab.h #include linux/delay.h #include linux/version #include linux/init.h #include linux/fs.h #include asm/types.h #include asm/mpc8260.h #include asm/cpm_8260.h #include asm/page.h #include asm/uaccess.h My linux is 2.4.25 Need I a patch to correct this ?? I need the funktion copy_to_user. Regards Fred -- Der GMX SmartSurfer hilft bis zu 70% Ihrer Onlinekosten zu sparen! Ideal f?r Modem und ISDN: http://www.gmx.net/de/go/smartsurfer ___ Linuxppc-embedded mailing list Linuxppc-embedded at ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded This message (including any attachments) is for the named addressee(s)'s use only. It may contain sensitive, confidential, private proprietary or legally privileged information intended for a specific individual and purpose, and is protected by law. If you are not the intended recipient, please immediately delete it and all copies of it from your system, destroy any hard copies of it and notify the sender. Any use, disclosure, copying, or distribution of this message and/or any attachments is strictly prohibited.
Toolchain for ppc405
Hi, I'm current running 2.4.18 kernel from montavista for my pp405(redwood6) platform. I wish to upgrade to 2.6 kernel. Is is possible ? How should I proceed in this direction. Has anybody earlier ported ppc405(redwood6) for 2.6 kernel Thanx in advance. Regards, Akhilesh -- next part -- An HTML attachment was scrubbed... URL: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20060825/8022f384/attachment.htm
Toolchain for ppc405
Hi, For quick reference, ELDK (Embedded Linux Development Kit) may be suitable for you. http://www.denx.de/en/News/PressReleaseELDK40 or http://www.denx.de/wiki/DULG/ELDK The latest version is 4.0, which support linux kernel 2.6. Thanks. Best regards, Lo Chun Chung -Original Message- From: [EMAIL PROTECTED] [mailto:linuxppc-embedded-bounces+cclo=astri.org at ozlabs.org] On Behalf Of Akhilesh Soni Sent: Friday, 25 August, 2006 2:01 PM To: linuxppc-embedded at ozlabs.org Subject: Toolchain for ppc405 Hi, I'm current running 2.4.18 kernel from montavista for my pp405(redwood6) platform. I wish to upgrade to 2.6 kernel. Is is possible ? How should I proceed in this direction. Has anybody earlier ported ppc405(redwood6) for 2.6 kernel Thanx in advance. Regards, Akhilesh This message (including any attachments) is for the named addressee(s)'s use only. It may contain sensitive, confidential, private proprietary or legally privileged information intended for a specific individual and purpose, and is protected by law. If you are not the intended recipient, please immediately delete it and all copies of it from your system, destroy any hard copies of it and notify the sender. Any use, disclosure, copying, or distribution of this message and/or any attachments is strictly prohibited.
communication with i2c client
I think you should check the i2c drivers first. Only the i2c drivers support the slave mode, the user space application can access the i2c device. The i2c drivers should modify the mode register of i2c controller to switch the mode. -- next part -- An HTML attachment was scrubbed... URL: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20060825/c12b4abd/attachment.htm
pci_id_table and mid_idsel?
Hi, Can someone please explain me pci_irq_table and how to select the value of min_idsel , max_idsel for my 85xx boards? I am facing issues in registering the interrupt handler. On what basis we have to select the min_idsel and max_idsel value?? Currently common_swizzle function retuns slot number 11, if I hard-code the value of 11 in the min_idsel and max_idsel because I have only one slot, I am able to register the interrupt handler. PCI_SLOT in common_swizzle returns 11 because device function number (devfn) has value of 88 ( I am wondering why 88 instead of from 0-7). (( 88 8) 0x1f) = 11 Since max functions we can have 8. (0-7). Why OS assign the value of 88 inside? Configuration transaction uses only 3 bits of function number in the CONFIG_ADDRESS as per PCI local bus specification 2.2. Regards, Parav Pandit - All-new Yahoo! Mail - Fire up a more powerful email and get things done faster. -- next part -- An HTML attachment was scrubbed... URL: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20060825/960c07b4/attachment.htm
pci_id_table and mid_idsel?
Parav, Please self study the existing source code. It can help you. -DAve From: linuxppc-embedded-bounces+daveliu=freescale.com at ozlabs.org [mailto:linuxppc-embedded-bounces+daveliu=freescale.com at ozlabs.org] On Behalf Of Parav Pandit Sent: Friday, August 25, 2006 4:57 PM To: linuxppc-embedded at ozlabs.org Subject: pci_id_table and mid_idsel? Hi, Can someone please explain me pci_irq_table and how to select the value of min_idsel , max_idsel for my 85xx boards? I am facing issues in registering the interrupt handler. On what basis we have to select the min_idsel and max_idsel value?? Currently common_swizzle function retuns slot number 11, if I hard-code the value of 11 in the min_idsel and max_idsel because I have only one slot, I am able to register the interrupt handler. PCI_SLOT in common_swizzle returns 11 because device function number (devfn) has value of 88 ( I am wondering why 88 instead of from 0-7). (( 88 8) 0x1f) = 11 Since max functions we can have 8. (0-7). Why OS assign the value of 88 inside? Configuration transaction uses only 3 bits of function number in the CONFIG_ADDRESS as per PCI local bus specification 2.2. Regards, Parav Pandit All-new Yahoo! Mail http://us.rd.yahoo.com/evt=43256/*http://advision.webevents.yahoo.com/m ailbeta - Fire up a more powerful email and get things done faster. -- next part -- An HTML attachment was scrubbed... URL: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20060825/fec60cfd/attachment.htm
m8260_cpm_dpalloc - m8260_cpm_dpfree ?
Hi Simple Question, I allocate Memory for my BDs with m8260_cpm_dpalloc, but there are no dpfree in Linux 2.4.25. In Linux 2.6 are a funktion to free dp memory. Are there no funktion in Linux 2.4 ? Regards Fred -- Der GMX SmartSurfer hilft bis zu 70% Ihrer Onlinekosten zu sparen! Ideal f?r Modem und ISDN: http://www.gmx.net/de/go/smartsurfer
How to boot powerPC linux-2.6.10 from diifferent address other than 0x0000
Hi, We are working on MPC 8540, Linux kernel version is 2.6.10 from Montavista. The bootloader used in Uboot and currently it loads the uImage at physical memory address 0x0 and transfers control to it. We want to load the kernel at a different address say 0x8000 and for this we made the following changes. 1) Altered the Makefile to linked the kernel at virtual address 0xc0008000 ( the default was 0xc000:) 2) Modified Uboot to load kernel at 0x8000 instead of 0x0 The kernel space still starts from 0xc000: When we transferred control to the kernel (loaded at 0x8000) we found that the execution proceeds only till the mapping and invalidation on TLBs. We do not know where the control goes after this as the further instructions does not seems to get executed. Currently we do not have the provision to connect a debugger and hence we are unable to make out what is happening. Can some one give us any clue as to what we might have done wrong? This is our first experience on PowerPC. Thanksregards Suneel -- next part -- An HTML attachment was scrubbed... URL: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20060825/270ea0ac/attachment.htm
GPIO Control Driver
I am working on a PowerQuickIII processor that has a GPIO port, port C. Connect to this port are buffer enables for various devices on the product. I am trying to write a driver to control certain GPIO lines. Any suggestions on the best way to implement this? Currently I have created a module that creates character devices but I am now feeling it would have been better to create sysfs entries. Looking at the structs from the Linux device model bus_type, device_driver, and device I am having troubles determining what needs to be declared? What I think I would like to create in sysfs is: /sys/module/MODULE NAME/rtm_enable /rtm_reset /clk1a_enable /clk1b_enable /clk2a_enable /clk2b_enable
m8260_cpm_dpalloc - m8260_cpm_dpfree ?
Keinen Namen wrote: Hi Simple Question, I allocate Memory for my BDs with m8260_cpm_dpalloc, but there are no dpfree in Linux 2.4.25. In Linux 2.6 are a funktion to free dp memory. Are there no funktion in Linux 2.4 ? I've implemented the free function for my own benefit. See attached patch which should work against ELDK 3.1 Alex -- next part -- An embedded and charset-unspecified text was scrubbed... Name: patch-2006-08-25-m8260_cpm_dpfree Url: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20060825/a6da508d/attachment.txt
Cache coherency question
Tim I'm using an MVME6100 with Linux 2.6.14 and experiencing what I Tim think is a cache coherency problem. An external PCIX master Tim performs a DMA transfer of a well known data pattern into SDRAM, Tim but when the device driver goes to look at the data it is mostly Tim okay, but occasionally has garbage. If the hardware is reliable, I think you are right. The cache coherency problem. The hardware is reliable. Tim 1) Should the processor bus cache snooping actually work on an Tim MVME6100? Tim E.g. is it correct that CONFIG_NOT_COHERENT_CACHE is undefined? Yes, you can undefine the CONFIG_NOT_COHERENT_CACHE, but you must make sure the host bridge did the snooping setup for PCI inbound transaction. If you setup the snooping window, I think the host bridge will assert /GLB signal to processor. The processor will snoop the 60x/MPX bus to keep cache coherence. Ah. This must be the problem. I have a few PCI devices, and on one of them it looked like snooping was working. I just assumed the other device was setup correctly. Also, you can define the CONFIG_NOT_COHERENT_CACHE, then you are assuming The system has not hardware coherency. You need use the software to keep the cache coherency. I tried this, and got compiler errors. Tim 2) If this really is a cache coherency problem, are there other Tim cache management functions available in ppc linux besides the Tim dma_cache_inv, dma_cache_wback, dma_cache_wback_inv macros I should Tim be looking at? I think it is a cache coherency problem, if you define the CONFIG_NOT_COHERENT_CACHE You can get these functions, dma_map_single I added some inline assembly dcbi/dcbf (invalidate/flush) instructions to the particular code in question, and the problems went away. So definitely a cache problem. As I said above, defining CONFIG_NOT_COHERENT_CACHE causes compiler errors, so I'm going to look into this more. I suppose whatever file implements the include/linux/dma-mapping.h stuff isn't BSP specific, so its probably just not being compiled in? Will look into it. Thanks for you help, Tim
MPC8555 PCI interrupts are not coming
On Aug 24, 2006, at 07:52, Parav Pandit wrote: Hi, Can someone give light on PCI interrupts routing to the OS from the openPIC? The routing depends on your board. On the CDS board, PCI interrupts are mapped to ext[0-3]. On the ADS, they are mapped to ext[1-4]. There are four PCI interrupts (A,B,C,D), and they are usually swizzled so that different slots have a different mapping (this way, two cards in different slots which use interrupt A don't conflict). Basically I am able to talk to PCI end device connected on MPC8555 board in 2.6.13 but not getting interrupts reported by my device. When I read the INTERRUPT_LINE byte, it comes as 0. pdev-irq is also reporting 0. Due to that request_irq() fails. But now I request for IRQ line 8 + openPIC offset. Handler gets registered but still not getting the interrupts. (PCI interrupt line is 8,9 in case of MPC8555). When are you trying to read the interrupt_line byte? In 2.6.13, you need to have an IRQ mapping function, which takes the idsel reported by the slot, and converts it to the interrupt number for the PIC. That code also writes the INTERRUPT_LINE byte. Can anyone please guide me, what are the different things need be configure in the platform code to receive the PCI interrupts in the driver? I don't understand the pci_irq_table, and what it should represent? Currrently no one is writing the INTERRUPT LINE value in the config space. In which function I should configure that value? pcibios_fixup?? Regards, Parav Pandit Do you Yahoo!? Get on board. You're invited to try the new Yahoo! Mail. ___ Linuxppc-embedded mailing list Linuxppc-embedded at ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
m8260_cpm_dpalloc - m8260_cpm_dpfree ?
Alex Zeffertt wrote: Keinen Namen wrote: Hi Simple Question, I allocate Memory for my BDs with m8260_cpm_dpalloc, but there are no dpfree in Linux 2.4.25. In Linux 2.6 are a funktion to free dp memory. Are there no funktion in Linux 2.4 ? I've implemented the free function for my own benefit. See attached patch which should work against ELDK 3.1 On the other hand I may have just ported it from somewhere else. I can't remember now, but anyway it works for me. Alex
CompactFlash on PQII Pro
On Aug 24, 2006, at 1:35 PM, Ben Warren wrote: Kumar, On Thu, 2006-08-24 at 13:25 -0500, Kumar Gala wrote: The only code in u-boot was the UPM setup code, I'm happy to send that to you. If it's no trouble, that would be great. My HW guy is calculating the settings, but this stuff can be frustrating to debug. BTW - was the system bus speed for your CPU 33 or 66 MHz? We're targeting for a 400MHz 8349 which has a 33MHz system bus. I think we were running @ 66Mhz, but I've run the FSL ref board @ 33MHZ. - k
