Re: Memory Corruption in Linux kernel MPC8347 revision 3

[Bhupender Saharan]

Hi Boris,

When you are running the memory test make sure Data cahe and Instruction
caches are enabled.

Also check your BAT setting, there also Cache enable BIT shall be set.

As the burst transcation will happen only when cache is enabled.

How abt ECC...?

Bhupi



On 7/17/07, Boris Shteinbock <[EMAIL PROTECTED]> wrote:


 Hi Everyone.
I am working on the Linux port for MPC8347 revision 3 custom build board
with DDR2 memory.

I've successfully ported U-boot (latest git) and the kernel itself,
however during kernel boot I am encountering serious memory corruption
errors. The log for one of the examples is at the bottom of this
message.

Basically, the corruption is always happening somewhere at memory
management intensive tasks such as networking, JFFS2 mounting etc.

As far as I can see, it is not related to some specific driver, because
even it happens even at kernel configured at absolute minimum, ( console
serial driver only and even without it)
The place of the corruption depends on kernel configuration.

The DDR2 memory controller is configured correctly as far as I can tell,
since :
1. DDR2 controller register values are taken from VxWorks bootrom
that works on this board without any problems.
2. u-boot mtest passes successfully
3. u-boot alternative mtest passes successfully
4. My own custom mem tests in u-boot pass successfully
5. If I manage two boot the board into shell prompt (with absolute
minimum configuration) memtester application is also successful.

The minimum configuration that is one I am able to boot into shell is a
kernel configured with serial console and small busybox JFFS2 file
system in the flash. In this configuration, the boot fails the first
time JFFS2 root FS is mounted. However it does boot after reset.

I've tried different kernels with the same results  starting from, I
think, 2.6.16  up to 2.6.22
I tried the kernel that is provided by Freescale for 834x reference
boards. ( with my board support of course)

I tried booting both OF flat trees (powerpc) and bd_t based builds (ppc)

I've also tried all memory management options :
SLAB, SLOB and SLUB (in the latest kernel). They all failed at some
point of time, so the assumption is that the problem is not in the
memory management facilities.

The board manufacturer swears that DDR2 memory controller values are
correct and should work perfectly.

So now I almost out of options and I am seeking your help.
Any type of input on this issue would be greatly appreciated.

Thanks,
Boris

PS. Note that an below example represents failure during DHCP
autoconfiguration. However the similar error happens even when
networking is disabled completely. just in a different place.

=> bootm
## Booting image at 0040 ...
   Image Name:   Linux-.6.21.5
   Created:  2007-07-10  14:20:19 UTC
   Image Type:   PowerPC Linux Kernel Image (gzip compressed)
   Data Size:898361 Bytes = 877.3 kB
   Load Address: 
   Entry Point:  
   Verifying Checksum ... OK
   Uncompressing Kernel Image ... OK
## Current stack ends at 0x07FA3CF8 => set upper limit to 0x0080
## cmdline at 0x007FFF00 ... 0x007FFF41
bd address  = 0x07FA3FBC
memstart= 0x
memsize = 0x0800
flashstart  = 0xFE00
flashsize   = 0x0200
flashoffset = 0x00033000
sramstart   = 0x
sramsize= 0x
bootflags   = 0x0001
intfreq =528 MHz
busfreq =264 MHz
ethaddr = 00:04:9F:EF:23:35
eth1addr= 00:E0:0C:00:7E:25
IP addr = 10.2.222.20
baudrate= 115200 bps
No initrd
## Transferring control to Linux (at address ) ...
 of_flat_tree = 
Booting without OF Flat tree
Linux version .6.21.5 ([EMAIL PROTECTED]) (gcc version
4.0.0 (DENX ELDK 4.1 4.0.0)) #24 Tue Jul 10 17:20:09 IDT 2007
Zone PFN ranges:
  DMA 0 ->32768
  Normal  32768 ->32768
early_node_map[1] active PFN ranges
0:0 ->32768
Built 1 zonelists.  Total pages: 32512
Kernel command line: console=ttyS0,115200 root=/dev/mtdblock1
rootfstype=jffs2 ip=dhcp
IPIC (128 IRQ sources, 8 External IRQs) at fe000700
PID hash table entries: 512 (order: 9, 2048 bytes)
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Memory: 127744k available (1584k kernel code, 444k data, 84k init, 0k
highmem)
Mount-cache hash table entries: 512
NET: Registered protocol family 16
Setup MTD partitions
Generic PHY: Registered new driver
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 4096 (order: 3, 32768 bytes)
TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
TCP reno registered
JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc.
io scheduler noop registered
io scheduler anticipatory registered (default)
io scheduler deadline registered
io scheduler cfq registered
Serial: 8250/16550 drive

Re: PageFault when I write in the Serial registers, MMU ?

[Bhupender Saharan]

Hi,

You could call *io_block_mapping* function from your setup.c file that will
add the entry into MMU.

regards
Bhupi





On 7/11/07, Nicolas Mederle <[EMAIL PROTECTED]> wrote:


Hi,

   I am porting linux on a custom board equipped with a PPC750, and I
will like to have some advices on the MMU. I used the powerpc arch, and
I built my device tree.
   I will like to know in which files we can configure the
authorizations access for the I/O registers. When I use the function
md_ppc.progress, I have a data access fault. I modified the head. S
files, for add the BAT config. But I think that it is not correct, and
that it is possible to do it elsewhere (platform_init?). Moreover the
kernel modify the MMU config, it removes the BATs, and configures the
Registers Segments. So, must I remake the configuration? Or is it
possible to indicate, at the beginning, which space is reserved for I/O?
   I studied several patch (sandpoint, PrPMC2800) but none configures
really the MMU for I/O registers. In the same way, I read several books,
but I am not able to have information that I seek, therefore I am really
blocked. I warmly thank you for the assistance which you will be able to
bring to me.

   Mapping : 0x ->  0x0FFF    :   RAM
0x2000    ->   0x201F    :   ASIC (
UART, DMA, GPIO, PIC...)
0x8000    ->   0x8FFF    :   PCI
0xF000    ->   0x    :   Flash
   The kernel is load at 0x0, an the system is a Run In Memory.
Currently, I don't use the flash.


Best regards,
Nicolas MEDERLE

--
Cordialement,

Nicolas MEDERLE.

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Re: ARCH=ppc or ARCH=powerpc

[Bhupender Saharan]

Hi,

All the new development is happening in arch/powerpc  architecure. So it is
good to use this architecure if you are upgrading the kernel. But it might
not work with kernel 1.1.2, As arch/powerpc need a structure like open
firmware for the parameters.


If you want to stick to 1.1.2 u-boot version then you shall use arch/ppc
architecure.

Regards
Bhupi


On 6/27/07, Bizhan Gholikhamseh (bgholikh) <[EMAIL PROTECTED]> wrote:


 Hi All,
Sorry for asking this question again, I am still not clear on some of the
issues.
Background:
We have developed a custom board based on Freescale reference board:
MPC8555_CDS with MPC8541E processor running Linux 2.6.11 and uboot 1.1.2version.

I would like to update the Linux kernel to the latest available kernel
2.6.21.
Here are my questions:
1- Should I use ARCH=ppc or ARCH=powerpc to build the kernel?
2- I have seen similar filenames under arch/ppc and arch/powerpc, which
one applies to MPC8541E?
3- Once I build the kernel, could I load the kernel with uboot version
1.1.2 or not? if not what I should do?

Many thanks in advance,
Bizhan


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Re: ML403 gigabit ethernet bandwidth - 2.6 kernel

[Bhupender Saharan]

Hi,

We need to findout where is the bottlenect.

1. Run vmstat on the ML403 board and find out the percentage CPU is busy
when you are transferring the file. That will show if cpu is busy or not.
2. Run oprofile and find out which are the routines eating away the cpu
time.

Once we have data from both the above routines, we can find out the
bottlenecks.


Regards
Bhupi


On 6/23/07, Mohammad Sadegh Sadri <[EMAIL PROTECTED]> wrote:



Dear all,

Recently we did a set of tests on performance of virtex 4FX hard TEMAC
module using ML403

we studied all of the posts here carefully: these are the system
characteristics;

Board : ML403
EDK: EDK9.1SP2
Hard TEMAC version and PLTEMAC version are both 3.0.a
PPC clock frequency :  300MHz
Kernel : 2.6.21-rc7 , downloaded from grant's git tree some thing near one
week ago
DMA type: 3 (sg dma)
DRE : enabled for TX and RX, (2)
CSUM offload is enabled for both of TX and RX
tx and rx fifo sizes : 131072 bits

the board comes up over NFS root file system completely and without any
problems.

PC system used for these tests is : CPU P4 Dual Core, 3.4GHz , 2Gigabytes
memory, Dual gigabit ethernet port, running linux 2.6.21.3
We have tested the PC system band width and it can easily reach 966mbits/s
when connected to the same PC. ( using the same cross cable used for ml403
test)

Netperf is compiled with TCP SEND FILE enabled, ( -DHAVE_SENDFILE)

(from board to PC)
netperf -t TCP_SENDFILE -H 10.10.10.250 -F /boot/zImage.elf -- -m 16384 -s
87380 -S 87380

the measured bandwidth for this test was just 40.66Mbits.
It is also true for netperf from PC to board.

we do not have any more idea about what we should do to improve the
bandwidth.
any help or ideas is appreciated...

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Re: Regarding MPC8540 IRQ Issue

[Bhupender Saharan]

Hi Sudhir,

You got a try all the interrupt vecrots corressponding to INTA, INTB, INTC
and INTD, Not the free interrupts.

Bhupi


On 6/18/07, sudheer <[EMAIL PROTECTED]> wrote:


 Hi Bhupi
Thanks for the response.
I tried with all the free irqs as per  /proc/interrupts  in request_irq
function one in each trial.  But in none of them it jumped to interrupt
handler.
Please let me know whether this is the one you said to try or anything
else. ?

Thanks
Sudheer

Bhupender Saharan wrote:

Hi Sudhir,

>From the PCI dump it looks like IRQ PIN register is 0. During enumeration
when BIOS sees that IRQ PIN register is 0, it would not allocate any
interrupt for this card and that's why you are seeing IRQ Line register also
as 0 value.

We need to do some work around for this.

 IN the driver you need to register for all the pci vectors( INTA,B,C and
D). You would be called for any interrupt happening on the bus. you have to
check if the interrupt is for you and then claim it otherwise return that
interrupt is not for you.


Regards
Bhupi


On 6/16/07, sudheer <[EMAIL PROTECTED]> wrote:
>
> Hello All
>
> I am working on MPC8540 board placing it in the PCI slot of the x86
> system.
> After system bootup , i could see the powerpc board detected and pci
> config space configured.
> But i could not find any IRQ assigned for it.
>
> SetUp:
> Host: x86 System- Linux-2.6.9
> HOST PCI Slot is 64-bit, 66MHz
> Agent: MPC8540 Board.
>
> Here is dump of "lspci -vx " for this device.
>
> 04:03.0 Power PC: Motorola MPC8540 (rev 20) (prog-if 01)
> Flags: bus master, 66Mhz, fast devsel, latency 64
> Memory at dee0 (32-bit, non-prefetchable) [size=1M]
> Capabilities: [60] #00 []
> 00: 57 10 08 00 46 01 b0 00 20 01 20 0b 00 40 00 00
> 10: 00 00 e0 de 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 60 00 00 00 00 00 00 00 00 00 00 00
>
> >From the above dump - IRQ Pin & Line of config space shows zeroes.
>
> I tried writing a small module and probing for IRQ generating a message
> interrupt. Though i could see in the 8540 message status register that
> interrupt is generated, i could not get any IRQ when i do the probe. For
>
> this trial,  i have configured the PIC message enable register, message
> vector/priority and destination registers, processor current task
> priority register (CPTR).
>
> Can anyone give me some suggestions to try out.
>
> Thanks
> Sudheer
>
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Re: Regarding MPC8540 IRQ Issue

[Bhupender Saharan]

Hi Sudhir,


From the PCI dump it looks like IRQ PIN register is 0. During enumeration

when BIOS sees that IRQ PIN register is 0, it would not allocate any
interrupt for this card and that's why you are seeing IRQ Line register also
as 0 value.

We need to do some work around for this.

IN the driver you need to register for all the pci vectors( INTA,B,C and
D). You would be called for any interrupt happening on the bus. you have to
check if the interrupt is for you and then claim it otherwise return that
interrupt is not for you.


Regards
Bhupi


On 6/16/07, sudheer <[EMAIL PROTECTED]> wrote:


Hello All

I am working on MPC8540 board placing it in the PCI slot of the x86
system.
After system bootup , i could see the powerpc board detected and pci
config space configured.
But i could not find any IRQ assigned for it.

SetUp:
Host: x86 System- Linux-2.6.9
HOST PCI Slot is 64-bit, 66MHz
Agent: MPC8540 Board.

Here is dump of "lspci -vx " for this device.

04:03.0 Power PC: Motorola MPC8540 (rev 20) (prog-if 01)
Flags: bus master, 66Mhz, fast devsel, latency 64
Memory at dee0 (32-bit, non-prefetchable) [size=1M]
Capabilities: [60] #00 []
00: 57 10 08 00 46 01 b0 00 20 01 20 0b 00 40 00 00
10: 00 00 e0 de 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 60 00 00 00 00 00 00 00 00 00 00 00

From the above dump - IRQ Pin & Line of config space shows zeroes.

I tried writing a small module and probing for IRQ generating a message
interrupt. Though i could see in the 8540 message status register that
interrupt is generated, i could not get any IRQ when i do the probe. For
this trial,  i have configured the PIC message enable register, message
vector/priority and destination registers, processor current task
priority register (CPTR).

Can anyone give me some suggestions to try out.

Thanks
Sudheer

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Re: Problems with access to PCI on MVME3100

[Bhupender Saharan]

Hi Johan,


From the pci log it looks like that BAR registers are not mapped properly by

the BIOS/U-boot. Looks like you have 3 BARS which are asking for memory, But
that are not spaced apart propoerly. Mean physical address difference
between BAR0 and BAR2 shall be 512 Megabyte, but that is not what it is
programmed.

Need to fix up the memory allocation first. then we need to see if the DMA
descriptor are defimed propoerly. As you are saying you are porting the
driver from X-86 to PPC. SO endian coversion is required.

Regards
Bhupi









On 5/22/07, Johan Borkhuis <[EMAIL PROTECTED]> wrote:


Hello,

I am working on porting a PCI driver from I386-Linux to PPC (MVME-3100).
The device is a Reflective Memory card (VMIC 5565), and we use a driver
based on the standard Linux driver, provided by the supplier.

I try to start a DMA transfer (using the DMA engine on the PCI card)
from user space, but then I get a PCI Error. The following data is
displayed:
PCI Error!
PCI ERROR DETECT REG 0x0042
PCI ERROR ADDRESS REG 0x00fffa00
PCI ERROR EXT ADDRESS REG 0x
PCI ERROR ATTRIBUTES REG 0xc001
PCI ERROR DATA HIGH REG 0x60010004
PCI ERROR DATA LOW REG 0x10060020
PCI STATUS REG 0x
PCI GASKET TIMER REG 0x3fff
PCI PCIX TIMER REG 0x01ff

Access to the registers from kernel mode is no problem. I did an mmap to
map the registers into user space, and then access the registers as an
array of chars or ints. Is there a limitation in access to PCI registers
from user space on PPC?

When I try to do this in kernel mode I don't get any errors, but the
transfer is not started. I am not sure if this is a SW problem, or that
it might be caused by the PCI-PCI bridge.

The code runs perfectly on a I386 platform, and I use read[bwl] and
write[bwl] to access the registers, so this should fix the endianess
problems that exist.

Below is the PCI information from the card:
01:00.0 Network controller: VMIC: Unknown device 5565 (rev 01)
   Subsystem: PLX Technology, Inc.: Unknown device 9656
   Flags: 66Mhz, medium devsel, IRQ 52
   Memory at dfeffe00 (32-bit, non-prefetchable) [size=512]
   I/O ports at e000 [size=256]
   Memory at dfeffdc0 (32-bit, non-prefetchable) [size=64]
   Memory at d800 (32-bit, non-prefetchable) [size=64M]
   Capabilities: [40] Power Management version 2
   Capabilities: [48] #00 [0080]

Kind regards,
Johan Borkhuis

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Re: Down when i get date from rtc by "hwclock --hctosys"

[Bhupender Saharan]

Hi Leo,

Looks like your system is unstable when the cache is enabed. It might have
nothing to do with generic RTC driver.

Can you run cachebench or another memory benchmarks tools on the system and
see if memory sub system is OK.

Regards
Bhupi


On 5/17/07, liChunlin <[EMAIL PROTECTED]> wrote:


The system is Embeded Linux with kernel 2.6.14. And the CPU is MPC8270 of
freescale. The rtc module is "Generic /dev/rtc emulation" and "Extended RTC
operation". And the chip of rtc is ds1338 with the interface of i2c. The
module of i2c has been included.
When i enable the dcache of mpc8270 and use "hwclock --hctosys" or
"hwclock --show", the system will down. But if i disable dcache, it is ok.
I found that when it call schedule_work(&genrtc_task) in the function
"static inline int gen_set_rtc_irq_bit(unsigned char bit)" in file
genrtc.c it will down.
Can you help me?
Thanks.
Leo


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