bootstrap of virtex-ii pro eval board ML300
> As Scott describes correctly the preferred method of booting ML300 is through > System ACE CF. System ACE CF reads ACE files and programs the FPGA and the > PowerPC processor through the JTAG chain. System ACE CF reads one of the .ace files (at most 8) from the first partition of FAT16/FAT12 fs. > On power-up or reset System ACE CF reads the ACE file from the MicroDrive or > CompactFlash card and in a first step programs the FPGA. Then, in a second > step, from the same ACE file, it programs the processor, i.e. similar to an > external debugger it loads code and data contained in the ELF file into the > processor memories, sets the PC to the start address, and starts executing the > program. > what is this "it"? Is it System ACE CF or other small executive edited by developper? -hyding best regards ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
bootstrap of virtex-ii pro eval board ML300
System ACE CF. - Peter NARI_DHY wrote: > > As Scott describes correctly the preferred method of booting ML300 is > > through > > System ACE CF. System ACE CF reads ACE files and programs the FPGA and the > > PowerPC processor through the JTAG chain. > System ACE CF reads one of the .ace files (at most 8) from the first > partition of FAT16/FAT12 fs. > > > On power-up or reset System ACE CF reads the ACE file from the MicroDrive or > > CompactFlash card and in a first step programs the FPGA. Then, in a second > > step, from the same ACE file, it programs the processor, i.e. similar to an > > external debugger it loads code and data contained in the ELF file into the > > processor memories, sets the PC to the start address, and starts executing > > the > > program. > > > what is this "it"? Is it System ACE CF or other small executive edited by > developper? > > -hyding > > best regards > ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
bootstrap of virtex-ii pro eval board ML300
As Scott describes correctly the preferred method of booting ML300 is through System ACE CF. System ACE CF reads ACE files and programs the FPGA and the PowerPC processor through the JTAG chain. The ACE file is a concatenation of zero or one bitstream with zero to n ELF files. Typically, it is one bitstream and one ELF file. On power-up or reset System ACE CF reads the ACE file from the MicroDrive or CompactFlash card and in a first step programs the FPGA. Then, in a second step, from the same ACE file, it programs the processor, i.e. similar to an external debugger it loads code and data contained in the ELF file into the processor memories, sets the PC to the start address, and starts executing the program. For Linux, you will use the Linux kernel as the ELF file. You can generate ACE files easily by using EDK by running the command $ xmd genace.tcl implementation/system.bit arch/ppc/boot/images/zImage.embedded top.ace in your hardware project directory. - Peter - Some useful links: System ACE CF: (http://www.xilinx.com/isp/systemace/systemacecf.htm EDK: http://www.xilinx.com/edk ML300: http://www.xilinx.com/ml300 Scott Anderson wrote: > On Monday, June 2, 2003, at 01:48 PM, Kerl, John wrote: > > You're saying that the entire zvmlinux.initrd file > > (2-3 MB, say) is contained in the FPGA bitstream?? > > I am saying that the entire zImage.embedded (without > an initrd) is in the FPGA bitstream. Its root partition > is an ext2 partition on the IBM MicroDrive. > >Scott > ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
bootstrap of virtex-ii pro eval board ML300
On Monday, June 2, 2003, at 01:48 PM, Kerl, John wrote: > You're saying that the entire zvmlinux.initrd file > (2-3 MB, say) is contained in the FPGA bitstream?? I am saying that the entire zImage.embedded (without an initrd) is in the FPGA bitstream. Its root partition is an ext2 partition on the IBM MicroDrive. Scott ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
bootstrap of virtex-ii pro eval board ML300
News to me. Thanks. -Original Message- From: Scott Anderson [mailto:[EMAIL PROTECTED] Sent: Monday, June 02, 2003 1:53 PM To: Kerl, John Cc: ???; linuxppc-embedded at lists.linuxppc.org Subject: Re: bootstrap of virtex-ii pro eval board ML300 On Monday, June 2, 2003, at 01:48 PM, Kerl, John wrote: > You're saying that the entire zvmlinux.initrd file > (2-3 MB, say) is contained in the FPGA bitstream?? I am saying that the entire zImage.embedded (without an initrd) is in the FPGA bitstream. Its root partition is an ext2 partition on the IBM MicroDrive. Scott ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
bootstrap of virtex-ii pro eval board ML300
On Monday, June 2, 2003, at 01:41 PM, Kerl, John wrote: > (2) Whether the bit file is obtained via System ACE or JTAG, > the FPGA is initialized. This includes populating the > block RAM. > > Note that your block RAM will almost certainly not be > big enough to contain your Linux kernel. Sizes vary but > in my experience they are measured in kilobytes -- e.g. > 4KB to 64KB. For this reason, it is preferable to have > the ELF file that is contained in your bitstream be a *small* > executable that can fit in the block RAM. This small > executable can *find* a larger executable (e.g. the Linux > kernel image), from a flash device, compact flash, TFTP, > etc., then load and run it. > Um, since he was asking about the ML300 specifically, my experience on it is that the memory controller got initialized along with everything else so that the ELF did not have to fit in block RAM; rather the ELF got slammed right into the 128MB of DDR SDRAM. Scott ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
bootstrap of virtex-ii pro eval board ML300
You're saying that the entire zvmlinux.initrd file (2-3 MB, say) is contained in the FPGA bitstream?? I find that hard to believe ... -Original Message- From: Scott Anderson [mailto:[EMAIL PROTECTED] Sent: Monday, June 02, 2003 1:49 PM To: Kerl, John Cc: ???; linuxppc-embedded at lists.linuxppc.org Subject: Re: bootstrap of virtex-ii pro eval board ML300 On Monday, June 2, 2003, at 01:41 PM, Kerl, John wrote: > (2) Whether the bit file is obtained via System ACE or JTAG, > the FPGA is initialized. This includes populating the > block RAM. > > Note that your block RAM will almost certainly not be > big enough to contain your Linux kernel. Sizes vary but > in my experience they are measured in kilobytes -- e.g. > 4KB to 64KB. For this reason, it is preferable to have > the ELF file that is contained in your bitstream be a *small* > executable that can fit in the block RAM. This small > executable can *find* a larger executable (e.g. the Linux > kernel image), from a flash device, compact flash, TFTP, > etc., then load and run it. > Um, since he was asking about the ML300 specifically, my experience on it is that the memory controller got initialized along with everything else so that the ELF did not have to fit in block RAM; rather the ELF got slammed right into the 128MB of DDR SDRAM. Scott ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
bootstrap of virtex-ii pro eval board ML300
There are two details here, one of them important. (1) The System ACE is one configuration option; you can also download a new bit file via the JTAG cable. (2) Whether the bit file is obtained via System ACE or JTAG, the FPGA is initialized. This includes populating the block RAM. Note that your block RAM will almost certainly not be big enough to contain your Linux kernel. Sizes vary but in my experience they are measured in kilobytes -- e.g. 4KB to 64KB. For this reason, it is preferable to have the ELF file that is contained in your bitstream be a *small* executable that can fit in the block RAM. This small executable can *find* a larger executable (e.g. the Linux kernel image), from a flash device, compact flash, TFTP, etc., then load and run it. -Original Message- From: Scott Anderson [mailto:[EMAIL PROTECTED] Sent: Monday, June 02, 2003 1:36 PM To: ??? Cc: linuxppc-embedded at lists.linuxppc.org Subject: Re: bootstrap of virtex-ii pro eval board ML300 On Saturday, May 31, 2003, at 06:14 PM, ??? wrote: ?We have subscribe the ML300 demo board from xilinx,but it needs several > months to arrive. I remember someone has done some work in virtex II > pro demo boards.Will someone tell me some details about the bootstrap's > procedure of such systems. A quick high level description from my understanding: There is a piece of Xilinx hardware called System ACE which reads a rotary switch to determine which of eight possible files it should load from the first partition (which must be a FAT partition) of the IBM MicroDrive. System ACE initializes the FPGA, processor and memory by using the contents of this file to manipulate the JTAG chain. Xilinx provides tools so that you can combine an ELF image (e.g. a Linux kernel) with an FPGA bitstream so that when the processor comes out of reset, your image is already loaded into memory ready to go. For your development, I would suggest using a JTAG debugger (specifically, the Abatron BDI2000) to load your kernel into memory so that you don't have to keep mucking with the MicroDrive. Having the BDI2000 also gives you a good tool for debugging the kernel and drivers. Scott ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
bootstrap of virtex-ii pro eval board ML300
On Saturday, May 31, 2003, at 06:14 PM, ??? wrote: \We have subscribe the ML300 demo board from xilinx,but it needs several > months to arrive. I remember someone has done some work in virtex II > pro demo boards.Will someone tell me some details about the bootstrap's > procedure of such systems. A quick high level description from my understanding: There is a piece of Xilinx hardware called System ACE which reads a rotary switch to determine which of eight possible files it should load from the first partition (which must be a FAT partition) of the IBM MicroDrive. System ACE initializes the FPGA, processor and memory by using the contents of this file to manipulate the JTAG chain. Xilinx provides tools so that you can combine an ELF image (e.g. a Linux kernel) with an FPGA bitstream so that when the processor comes out of reset, your image is already loaded into memory ready to go. For your development, I would suggest using a JTAG debugger (specifically, the Abatron BDI2000) to load your kernel into memory so that you don't have to keep mucking with the MicroDrive. Having the BDI2000 also gives you a good tool for debugging the kernel and drivers. Scott ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
bootstrap of virtex-ii pro eval board ML300
Dear all, We have subscribe the ML300 demo board from xilinx,but it needs several months to arrive. I remember someone has done some work in virtex II pro demo boards.Will someone tell me some details about the bootstrap's procedure of such systems. thanks in advance ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
