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Subject: Added Digiteq Automotive MGB4 driver documentation
Author: Martin Tůma
Date:Mon Sep 25 16:36:05 2023 +0200
The "admin-guide" documentation for the Digiteq Automotive MGB4 driver.
Signed-off-by: Martin Tůma
Signed-off-by: Hans Verkuil
Documentation/admin-guide/media/mgb4.rst | 374 +++
Documentation/admin-guide/media/pci-cardlist.rst | 1 +
Documentation/admin-guide/media/v4l-drivers.rst | 1 +
3 files changed, 376 insertions(+)
---
diff --git a/Documentation/admin-guide/media/mgb4.rst
b/Documentation/admin-guide/media/mgb4.rst
new file mode 100644
index ..2977f74d7e26
--- /dev/null
+++ b/Documentation/admin-guide/media/mgb4.rst
@@ -0,0 +1,374 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+
+mgb4 sysfs interface
+
+
+The mgb4 driver provides a sysfs interface, that is used to configure video
+stream related parameters (some of them must be set properly before the v4l2
+device can be opened) and obtain the video device/stream status.
+
+There are two types of parameters - global / PCI card related, found under
+``/sys/class/video4linux/videoX/device`` and module specific found under
+``/sys/class/video4linux/videoX``.
+
+
+Global (PCI card) parameters
+
+
+**module_type** (R):
+Module type.
+
+| 0 - No module present
+| 1 - FPDL3
+| 2 - GMSL
+
+**module_version** (R):
+Module version number. Zero in case of a missing module.
+
+**fw_type** (R):
+Firmware type.
+
+| 1 - FPDL3
+| 2 - GMSL
+
+**fw_version** (R):
+Firmware version number.
+
+**serial_number** (R):
+Card serial number. The format is::
+
+PRODUCT-REVISION-SERIES-SERIAL
+
+where each component is a 8b number.
+
+
+Common FPDL3/GMSL input parameters
+==
+
+**input_id** (R):
+Input number ID, zero based.
+
+**oldi_lane_width** (RW):
+Number of deserializer output lanes.
+
+| 0 - single
+| 1 - dual (default)
+
+**color_mapping** (RW):
+Mapping of the incoming bits in the signal to the colour bits of the
pixels.
+
+| 0 - OLDI/JEIDA
+| 1 - SPWG/VESA (default)
+
+**link_status** (R):
+Video link status. If the link is locked, chips are properly connected and
+communicating at the same speed and protocol. The link can be locked
without
+an active video stream.
+
+A value of 0 is equivalent to the V4L2_IN_ST_NO_SYNC flag of the V4L2
+VIDIOC_ENUMINPUT status bits.
+
+| 0 - unlocked
+| 1 - locked
+
+**stream_status** (R):
+Video stream status. A stream is detected if the link is locked, the input
+pixel clock is running and the DE signal is moving.
+
+A value of 0 is equivalent to the V4L2_IN_ST_NO_SIGNAL flag of the V4L2
+VIDIOC_ENUMINPUT status bits.
+
+| 0 - not detected
+| 1 - detected
+
+**video_width** (R):
+Video stream width. This is the actual width as detected by the HW.
+
+The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the width
+field of the v4l2_bt_timings struct.
+
+**video_height** (R):
+Video stream height. This is the actual height as detected by the HW.
+
+The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in the
height
+field of the v4l2_bt_timings struct.
+
+**vsync_status** (R):
+The type of VSYNC pulses as detected by the video format detector.
+
+The value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in
+the polarities field of the v4l2_bt_timings struct.
+
+| 0 - active low
+| 1 - active high
+| 2 - not available
+
+**hsync_status** (R):
+The type of HSYNC pulses as detected by the video format detector.
+
+The value is equivalent to the flags returned by VIDIOC_QUERY_DV_TIMINGS in
+the polarities field of the v4l2_bt_timings struct.
+
+| 0 - active low
+| 1 - active high
+| 2 - not available
+
+**vsync_gap_length** (RW):
+If the incoming video signal does not contain synchronization VSYNC and
+HSYNC pulses, these must be generated internally in the FPGA to achieve
+the correct frame ordering. This value indicates, how many "empty" pixels
+(pixels with deasserted Data Enable signal) are necessary to generate the
+internal VSYNC pulse.
+
+**hsync_gap_length** (RW):
+If the incoming video signal does not contain synchronization VSYNC and
+HSYNC pulses, these must be generated internally in the FPGA to achieve
+the correct frame ordering. This value indicates, how many "empty" pixels
+(pixels with deasserted Data Enable signal) are necessary to generate the
+internal HSYNC pulse. The value must be greater than 1 and smaller than
+vsync_gap_length.
+
+**pclk_frequency** (R):
+Input pixel clock frequency in kHz.
+
+The value is identical to what VIDIOC_QUERY_DV_TIMINGS returns in
+
