[Lldb-commits] [mlir] [llvm] [libc] [clang] [libcxx] [lldb] [clang-tools-extra] [compiler-rt] [flang] intrinsic to generate a bfi instruction (PR #79672)
https://github.com/inclyc edited https://github.com/llvm/llvm-project/pull/79672 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [libc] [libcxx] [lldb] [clang] [compiler-rt] [clang-tools-extra] [mlir] [flang] [llvm] intrinsic to generate a bfi instruction (PR #79672)
https://github.com/inclyc commented: Also I kindly wonder if this intrinsic is necessary for optimization/codegen. Why not prefer inline assembly? https://github.com/llvm/llvm-project/pull/79672 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [compiler-rt] [clang] [llvm] [mlir] [flang] [libc] [lldb] [clang-tools-extra] [libcxx] intrinsic to generate a bfi instruction (PR #79672)
@@ -2558,6 +2558,14 @@ def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)), def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)), (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>; +def SDT_AArch64BFI_32bit : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, +SDTCisVT<2, i32>]>; +def SDT_AArch64BFI_64bit : SDTypeProfile<1, 2, [SDTCisVT<0, i64>, SDTCisVT<1, i64>, +SDTCisVT<2, i64>]>; + +def aarch64_bfiw : SDNode<"AArch64::BFMWri", SDT_AArch64BFI_32bit>; inclyc wrote: (question) could you explain why creating a new SDNode? Is this necessary? https://github.com/llvm/llvm-project/pull/79672 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [compiler-rt] [clang] [llvm] [mlir] [flang] [libc] [lldb] [clang-tools-extra] [libcxx] [AArch64] add intrinsic to generate a bfi instruction (PR #79672)
https://github.com/inclyc edited https://github.com/llvm/llvm-project/pull/79672 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [libc] [clang-tools-extra] [lldb] [flang] [mlir] [llvm] [clang] [compiler-rt] [libcxx] [AArch64] add intrinsic to generate a bfi instruction (PR #79672)
davemgreen wrote: Hello. Can you explain why this is needed, as opposed to using the equivalent shift/and/ors? https://github.com/llvm/llvm-project/pull/79672 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [libcxx] [lld] [clang] [libc] [compiler-rt] [flang] [lldb] [clang-tools-extra] [llvm] [VPlan] Implement cloning of VPlans. (PR #73158)
Enna1 wrote: Hi @fhahn I think this change introduce a memory leak in `VPlan::duplicate()`, see https://lab.llvm.org/buildbot/#/builders/168/builds/18308/steps/10/logs/stdio Can you take a look? https://github.com/llvm/llvm-project/pull/73158 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [clang] [llvm] [clang-tools-extra] [compiler-rt] [mlir] [libc] [flang] [OpenMP] atomic compare weak : Parser & AST support (PR #79475)
https://github.com/SunilKuravinakop updated
https://github.com/llvm/llvm-project/pull/79475
>From 6614e517cf0888b4502efc0af974d1612fa7a822 Mon Sep 17 00:00:00 2001
From: Sunil Kuravinakop
Date: Thu, 25 Jan 2024 10:37:20 -0600
Subject: [PATCH 1/2] Changes to Support Parsing & Sema of atomic compare weak.
Changes to be committed:
modified: clang/include/clang/AST/OpenMPClause.h
modified: clang/include/clang/AST/RecursiveASTVisitor.h
modified: clang/include/clang/Basic/DiagnosticSemaKinds.td
modified: clang/include/clang/Sema/Sema.h
modified: clang/lib/AST/OpenMPClause.cpp
modified: clang/lib/AST/StmtProfile.cpp
modified: clang/lib/CodeGen/CGStmtOpenMP.cpp
modified: clang/lib/Parse/ParseOpenMP.cpp
modified: clang/lib/Sema/SemaOpenMP.cpp
modified: clang/lib/Sema/TreeTransform.h
modified: clang/lib/Serialization/ASTReader.cpp
modified: clang/lib/Serialization/ASTWriter.cpp
modified: clang/test/OpenMP/atomic_ast_print.cpp
modified: clang/test/OpenMP/atomic_messages.cpp
modified: clang/tools/libclang/CIndex.cpp
modified: llvm/include/llvm/Frontend/OpenMP/OMP.td
---
clang/include/clang/AST/OpenMPClause.h| 40 +++
clang/include/clang/AST/RecursiveASTVisitor.h | 5 +++
.../clang/Basic/DiagnosticSemaKinds.td| 3 +-
clang/include/clang/Sema/Sema.h | 3 ++
clang/lib/AST/OpenMPClause.cpp| 2 +
clang/lib/AST/StmtProfile.cpp | 2 +
clang/lib/CodeGen/CGStmtOpenMP.cpp| 3 ++
clang/lib/Parse/ParseOpenMP.cpp | 1 +
clang/lib/Sema/SemaOpenMP.cpp | 35 +++-
clang/lib/Sema/TreeTransform.h| 6 +++
clang/lib/Serialization/ASTReader.cpp | 5 +++
clang/lib/Serialization/ASTWriter.cpp | 2 +
clang/test/OpenMP/atomic_ast_print.cpp| 8
clang/test/OpenMP/atomic_messages.cpp | 11 +
clang/tools/libclang/CIndex.cpp | 2 +
llvm/include/llvm/Frontend/OpenMP/OMP.td | 4 +-
16 files changed, 129 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/AST/OpenMPClause.h
b/clang/include/clang/AST/OpenMPClause.h
index 924ca189381ba8..325a1baa446142 100644
--- a/clang/include/clang/AST/OpenMPClause.h
+++ b/clang/include/clang/AST/OpenMPClause.h
@@ -2513,6 +2513,46 @@ class OMPRelaxedClause final : public OMPClause {
}
};
+/// This represents 'weak' clause in the '#pragma omp atomic'
+/// directives.
+///
+/// \code
+/// #pragma omp atomic compare weak
+/// \endcode
+/// In this example directive '#pragma omp atomic' has 'weak' clause.
+class OMPWeakClause final : public OMPClause {
+public:
+ /// Build 'weak' clause.
+ ///
+ /// \param StartLoc Starting location of the clause.
+ /// \param EndLoc Ending location of the clause.
+ OMPWeakClause(SourceLocation StartLoc, SourceLocation EndLoc)
+ : OMPClause(llvm::omp::OMPC_weak, StartLoc, EndLoc) {}
+
+ /// Build an empty clause.
+ OMPWeakClause()
+ : OMPClause(llvm::omp::OMPC_weak, SourceLocation(), SourceLocation()) {}
+
+ child_range children() {
+return child_range(child_iterator(), child_iterator());
+ }
+
+ const_child_range children() const {
+return const_child_range(const_child_iterator(), const_child_iterator());
+ }
+
+ child_range used_children() {
+return child_range(child_iterator(), child_iterator());
+ }
+ const_child_range used_children() const {
+return const_child_range(const_child_iterator(), const_child_iterator());
+ }
+
+ static bool classof(const OMPClause *T) {
+return T->getClauseKind() == llvm::omp::OMPC_weak;
+ }
+};
+
/// This represents 'fail' clause in the '#pragma omp atomic'
/// directive.
///
diff --git a/clang/include/clang/AST/RecursiveASTVisitor.h
b/clang/include/clang/AST/RecursiveASTVisitor.h
index 8f2714e142bbe3..0fbf3e30e2d8d6 100644
--- a/clang/include/clang/AST/RecursiveASTVisitor.h
+++ b/clang/include/clang/AST/RecursiveASTVisitor.h
@@ -3423,6 +3423,11 @@ bool
RecursiveASTVisitor::VisitOMPRelaxedClause(OMPRelaxedClause *) {
return true;
}
+template
+bool RecursiveASTVisitor::VisitOMPWeakClause(OMPWeakClause *) {
+ return true;
+}
+
template
bool RecursiveASTVisitor::VisitOMPThreadsClause(OMPThreadsClause *) {
return true;
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index a97182cad5d513..42fa19e0424fbb 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -10996,7 +10996,8 @@ def note_omp_atomic_compare: Note<
"expect lvalue for result value|expect scalar value|expect integer
value|unexpected 'else' statement|expect '==' operator|expect an assignment
statement 'v = x'|"
"expect a 'if' statement|expect no more than two statements|expect a
compound statemen
[Lldb-commits] [libcxx] [flang] [libc] [clang-tools-extra] [clang] [llvm] [compiler-rt] [libunwind] [lld] [lldb] [X86] Use RORX over SHR imm (PR #77964)
@@ -4216,6 +4217,95 @@ MachineSDNode *X86DAGToDAGISel::emitPCMPESTR(unsigned
ROpc, unsigned MOpc,
return CNode;
}
+// When the consumer of a right shift (arithmetic or logical) wouldn't notice
+// the difference if the instruction was a rotate right instead (because the
+// bits shifted in are truncated away), the shift can be replaced by the RORX
+// instruction from BMI2. This doesn't set flags and can output to a different
+// register. However, this increases code size in most cases, and doesn't leave
+// the high bits in a useful state. There may be other situations where this
+// transformation is profitable given those conditions, but currently the
+// transformation is only made when it likely avoids spilling flags.
+bool X86DAGToDAGISel::rightShiftUnclobberFlags(SDNode *N) {
+ EVT VT = N->getValueType(0);
+
+ // Target has to have BMI2 for RORX
+ if (!Subtarget->hasBMI2())
+return false;
+
+ // Only handle scalar shifts.
+ if (VT.isVector())
+return false;
+
+ unsigned OpSize;
+ if (VT == MVT::i64)
+OpSize = 64;
+ else if (VT == MVT::i32)
+OpSize = 32;
+ else if (VT == MVT::i16)
+OpSize = 16;
+ else if (VT == MVT::i8)
+return false; // i8 shift can't be truncated.
+ else
+llvm_unreachable("Unexpected shift size");
+
+ unsigned TruncateSize = 0;
+ // This only works when the result is truncated.
+ for (const SDNode *User : N->uses()) {
+if (!User->isMachineOpcode() ||
+User->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
+ return false;
+EVT TuncateType = User->getValueType(0);
+if (TuncateType == MVT::i32)
+ TruncateSize = std::max(TruncateSize, 32U);
+else if (TuncateType == MVT::i16)
+ TruncateSize = std::max(TruncateSize, 16U);
+else if (TuncateType == MVT::i8)
+ TruncateSize = std::max(TruncateSize, 8U);
+else
+ return false;
+ }
+ if (TruncateSize >= OpSize)
+return false;
+
+ // The shift must be by an immediate that wouldn't expose the zero or sign
+ // extended result.
+ auto *ShiftAmount = dyn_cast(N->getOperand(1));
+ if (!ShiftAmount || ShiftAmount->getZExtValue() > OpSize - TruncateSize)
+return false;
+
+ // If the shift argument has non-dead EFLAGS, then this shift probably
+ // clobbers those flags making the transformation to RORX useful. This may
+ // have false negatives or positives so ideally this transformation is made
+ // later on.
+ bool ArgProducesFlags = false;
+ SDNode *Input = N->getOperand(0).getNode();
+ for (auto Use : Input->uses()) {
+if (Use->getOpcode() == ISD::CopyToReg) {
+ auto *RegisterNode =
+ dyn_cast(Use->getOperand(1).getNode());
RKSimon wrote:
```dyn_cast(Use->getOperand(1))```
https://github.com/llvm/llvm-project/pull/77964
___
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[Lldb-commits] [flang] [compiler-rt] [clang-tools-extra] [clang] [llvm] [libc] [lldb] [mlir] [libcxx] [AArch64] add intrinsic to generate a bfi instruction (PR #79672)
RamaMalladiAWS wrote: > Hello. Can you explain why this is needed, as opposed to using the equivalent > shift/and/ors? Hi @davemgreen, one of AWS customers requested for such an intrinsic to be made available so that they could consume it their IR directly. The reasoning they had was to use 1 instruction such `bfi` instead of a combination of `shift`, `and`, `or`. https://github.com/llvm/llvm-project/pull/79672 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [libc] [clang-tools-extra] [mlir] [lldb] [flang] [compiler-rt] [libcxx] [llvm] [libunwind] [clang] [lld] Reland: [libc++][format] P2637R3: Member visit (std::basic_format_arg) #76449 (P
mordante wrote: > @mordante I guess the PR missed LLVM18 release. I'll update the release notes > accordingly. Is that OK? Yes. It would have been nice to get this in LLVM 18, but I don't feel it's critical to backport it. (Especially since it's a C++26 only feature and I expect very few people are already using it.) https://github.com/llvm/llvm-project/pull/79032 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [libc] [clang-tools-extra] [lldb] [flang] [compiler-rt] [libcxx] [llvm] [libunwind] [clang] [lld] [X86] Use RORX over SHR imm (PR #77964)
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 01/16] [X86] Use RORX over SHR imm
---
llvm/lib/Target/X86/X86InstrShiftRotate.td | 78 ++
llvm/test/CodeGen/X86/atomic-unordered.ll | 3 +-
llvm/test/CodeGen/X86/bmi2.ll | 6 +-
llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll | 3 +-
llvm/test/CodeGen/X86/pr35636.ll | 4 +-
llvm/test/CodeGen/X86/vector-trunc-ssat.ll | 116 ++---
6 files changed, 143 insertions(+), 67 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrShiftRotate.td
b/llvm/lib/Target/X86/X86InstrShiftRotate.td
index f951894db1890c..238e8e9b6e97f3 100644
--- a/llvm/lib/Target/X86/X86InstrShiftRotate.td
+++ b/llvm/lib/Target/X86/X86InstrShiftRotate.td
@@ -879,6 +879,26 @@ let Predicates = [HasBMI2, HasEGPR, In64BitMode] in {
defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem, "_EVEX">, T8, PD, REX_W,
EVEX;
}
+
+def immle16_8 : ImmLeaf;
+def immle32_8 : ImmLeaf;
+def immle64_8 : ImmLeaf;
+def immle32_16 : ImmLeaf;
+def immle64_16 : ImmLeaf;
+def immle64_32 : ImmLeaf;
+
let Predicates = [HasBMI2] in {
// Prefer RORX which is non-destructive and doesn't update EFLAGS.
let AddedComplexity = 10 in {
@@ -891,6 +911,64 @@ let Predicates = [HasBMI2] in {
(RORX32ri GR32:$src, (ROT32L2R_imm8 imm:$shamt))>;
def : Pat<(rotl GR64:$src, (i8 imm:$shamt)),
(RORX64ri GR64:$src, (ROT64L2R_imm8 imm:$shamt))>;
+
+// A right shift by less than a smaller register size that is then
+// truncated to that register size can be replaced by RORX to
+// preserve flags with the same execution cost
+
+def : Pat<(i8 (trunc (srl GR16:$src, (i8 immle16_8:$shamt,
+ (EXTRACT_SUBREG (RORX32ri (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
GR16:$src, sub_16bit), imm:$shamt), sub_8bit)>;
+def : Pat<(i8 (trunc (sra GR16:$src, (i8 immle16_8:$shamt,
+ (EXTRACT_SUBREG (RORX32ri (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
GR16:$src, sub_16bit), imm:$shamt), sub_8bit)>;
+def : Pat<(i8 (trunc (srl GR32:$src, (i8 immle32_8:$shamt,
+ (EXTRACT_SUBREG (RORX32ri GR32:$src, imm:$shamt), sub_8bit)>;
+def : Pat<(i8 (trunc (sra GR32:$src, (i8 immle32_8:$shamt,
+ (EXTRACT_SUBREG (RORX32ri GR32:$src, imm:$shamt), sub_8bit)>;
+def : Pat<(i8 (trunc (srl GR64:$src, (i8 immle64_8:$shamt,
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_8bit)>;
+def : Pat<(i8 (trunc (sra GR64:$src, (i8 immle64_8:$shamt,
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_8bit)>;
+
+
+def : Pat<(i16 (trunc (srl GR32:$src, (i8 immle32_16:$shamt,
+ (EXTRACT_SUBREG (RORX32ri GR32:$src, imm:$shamt), sub_16bit)>;
+def : Pat<(i16 (trunc (sra GR32:$src, (i8 immle32_16:$shamt,
+ (EXTRACT_SUBREG (RORX32ri GR32:$src, imm:$shamt), sub_16bit)>;
+def : Pat<(i16 (trunc (srl GR64:$src, (i8 immle64_16:$shamt,
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_16bit)>;
+def : Pat<(i16 (trunc (sra GR64:$src, (i8 immle64_16:$shamt,
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_16bit)>;
+
+def : Pat<(i32 (trunc (srl GR64:$src, (i8 immle64_32:$shamt,
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_32bit)>;
+def : Pat<(i32 (trunc (sra GR64:$src, (i8 immle64_32:$shamt,
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_32bit)>;
+
+
+// Can't expand the load
+def : Pat<(i8 (trunc (srl (loadi32 addr:$src), (i8 immle32_8:$shamt,
+ (EXTRACT_SUBREG (RORX32mi addr:$src, imm:$shamt), sub_8bit)>;
+def : Pat<(i8 (trunc (sra (loadi32 addr:$src), (i8 immle32_8:$shamt,
+ (EXTRACT_SUBREG (RORX32mi addr:$src, imm:$shamt), sub_8bit)>;
+def : Pat<(i8 (trunc (srl (loadi64 addr:$src), (i8 immle64_8:$shamt,
+ (EXTRACT_SUBREG (RORX64mi addr:$src, imm:$shamt), sub_8bit)>;
+def : Pat<(i8 (trunc (sra (loadi64 addr:$src), (i8 immle64_8:$shamt,
+ (EXTRACT_SUBREG (RORX64mi addr:$src, imm:$shamt), sub_8bit)>;
+
+
+def : Pat<(i16 (trunc (srl (loadi32 addr:$src), (i8 immle32_16:$shamt,
+ (EXTRACT_SUBREG (RORX32mi addr:$src, imm:$shamt), sub_16bit)>;
+def : Pat<(i16 (trunc (sra (loadi32 addr:$src), (i8 immle32_16:$shamt,
+ (EXTRACT_SUBREG (RORX32mi addr:$src, imm:$shamt), sub_16bit)>;
+def : Pat<(i16 (trunc (srl (loadi64 addr:$src), (i8 immle64_16:$shamt,
+ (EXTRACT_SUBREG (RORX64mi addr:$src, imm:$shamt), sub_16bit)>;
+def : Pat<(i16 (trunc (sra (loadi64 addr:$src), (i8 immle64_16:$shamt,
+ (EXTRACT_SUBREG (RORX64mi addr:$src, imm:$shamt), sub_16bit)>;
+
+def : Pat<(i32 (trunc (sr
[Lldb-commits] [libc] [clang-tools-extra] [lldb] [flang] [compiler-rt] [libcxx] [llvm] [libunwind] [clang] [lld] [X86] Use RORX over SHR imm (PR #77964)
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 01/16] [X86] Use RORX over SHR imm
---
llvm/lib/Target/X86/X86InstrShiftRotate.td | 78 ++
llvm/test/CodeGen/X86/atomic-unordered.ll | 3 +-
llvm/test/CodeGen/X86/bmi2.ll | 6 +-
llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll | 3 +-
llvm/test/CodeGen/X86/pr35636.ll | 4 +-
llvm/test/CodeGen/X86/vector-trunc-ssat.ll | 116 ++---
6 files changed, 143 insertions(+), 67 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrShiftRotate.td
b/llvm/lib/Target/X86/X86InstrShiftRotate.td
index f951894db1890cd..238e8e9b6e97f30 100644
--- a/llvm/lib/Target/X86/X86InstrShiftRotate.td
+++ b/llvm/lib/Target/X86/X86InstrShiftRotate.td
@@ -879,6 +879,26 @@ let Predicates = [HasBMI2, HasEGPR, In64BitMode] in {
defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem, "_EVEX">, T8, PD, REX_W,
EVEX;
}
+
+def immle16_8 : ImmLeaf;
+def immle32_8 : ImmLeaf;
+def immle64_8 : ImmLeaf;
+def immle32_16 : ImmLeaf;
+def immle64_16 : ImmLeaf;
+def immle64_32 : ImmLeaf;
+
let Predicates = [HasBMI2] in {
// Prefer RORX which is non-destructive and doesn't update EFLAGS.
let AddedComplexity = 10 in {
@@ -891,6 +911,64 @@ let Predicates = [HasBMI2] in {
(RORX32ri GR32:$src, (ROT32L2R_imm8 imm:$shamt))>;
def : Pat<(rotl GR64:$src, (i8 imm:$shamt)),
(RORX64ri GR64:$src, (ROT64L2R_imm8 imm:$shamt))>;
+
+// A right shift by less than a smaller register size that is then
+// truncated to that register size can be replaced by RORX to
+// preserve flags with the same execution cost
+
+def : Pat<(i8 (trunc (srl GR16:$src, (i8 immle16_8:$shamt,
+ (EXTRACT_SUBREG (RORX32ri (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
GR16:$src, sub_16bit), imm:$shamt), sub_8bit)>;
+def : Pat<(i8 (trunc (sra GR16:$src, (i8 immle16_8:$shamt,
+ (EXTRACT_SUBREG (RORX32ri (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
GR16:$src, sub_16bit), imm:$shamt), sub_8bit)>;
+def : Pat<(i8 (trunc (srl GR32:$src, (i8 immle32_8:$shamt,
+ (EXTRACT_SUBREG (RORX32ri GR32:$src, imm:$shamt), sub_8bit)>;
+def : Pat<(i8 (trunc (sra GR32:$src, (i8 immle32_8:$shamt,
+ (EXTRACT_SUBREG (RORX32ri GR32:$src, imm:$shamt), sub_8bit)>;
+def : Pat<(i8 (trunc (srl GR64:$src, (i8 immle64_8:$shamt,
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_8bit)>;
+def : Pat<(i8 (trunc (sra GR64:$src, (i8 immle64_8:$shamt,
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_8bit)>;
+
+
+def : Pat<(i16 (trunc (srl GR32:$src, (i8 immle32_16:$shamt,
+ (EXTRACT_SUBREG (RORX32ri GR32:$src, imm:$shamt), sub_16bit)>;
+def : Pat<(i16 (trunc (sra GR32:$src, (i8 immle32_16:$shamt,
+ (EXTRACT_SUBREG (RORX32ri GR32:$src, imm:$shamt), sub_16bit)>;
+def : Pat<(i16 (trunc (srl GR64:$src, (i8 immle64_16:$shamt,
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_16bit)>;
+def : Pat<(i16 (trunc (sra GR64:$src, (i8 immle64_16:$shamt,
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_16bit)>;
+
+def : Pat<(i32 (trunc (srl GR64:$src, (i8 immle64_32:$shamt,
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_32bit)>;
+def : Pat<(i32 (trunc (sra GR64:$src, (i8 immle64_32:$shamt,
+ (EXTRACT_SUBREG (RORX64ri GR64:$src, imm:$shamt), sub_32bit)>;
+
+
+// Can't expand the load
+def : Pat<(i8 (trunc (srl (loadi32 addr:$src), (i8 immle32_8:$shamt,
+ (EXTRACT_SUBREG (RORX32mi addr:$src, imm:$shamt), sub_8bit)>;
+def : Pat<(i8 (trunc (sra (loadi32 addr:$src), (i8 immle32_8:$shamt,
+ (EXTRACT_SUBREG (RORX32mi addr:$src, imm:$shamt), sub_8bit)>;
+def : Pat<(i8 (trunc (srl (loadi64 addr:$src), (i8 immle64_8:$shamt,
+ (EXTRACT_SUBREG (RORX64mi addr:$src, imm:$shamt), sub_8bit)>;
+def : Pat<(i8 (trunc (sra (loadi64 addr:$src), (i8 immle64_8:$shamt,
+ (EXTRACT_SUBREG (RORX64mi addr:$src, imm:$shamt), sub_8bit)>;
+
+
+def : Pat<(i16 (trunc (srl (loadi32 addr:$src), (i8 immle32_16:$shamt,
+ (EXTRACT_SUBREG (RORX32mi addr:$src, imm:$shamt), sub_16bit)>;
+def : Pat<(i16 (trunc (sra (loadi32 addr:$src), (i8 immle32_16:$shamt,
+ (EXTRACT_SUBREG (RORX32mi addr:$src, imm:$shamt), sub_16bit)>;
+def : Pat<(i16 (trunc (srl (loadi64 addr:$src), (i8 immle64_16:$shamt,
+ (EXTRACT_SUBREG (RORX64mi addr:$src, imm:$shamt), sub_16bit)>;
+def : Pat<(i16 (trunc (sra (loadi64 addr:$src), (i8 immle64_16:$shamt,
+ (EXTRACT_SUBREG (RORX64mi addr:$src, imm:$shamt), sub_16bit)>;
+
+def : Pat<(i32 (trunc (
[Lldb-commits] [llvm] [libcxx] [lldb] [compiler-rt] [flang] [libc] [clang] [lld] [clang-tools-extra] [VPlan] Implement cloning of VPlans. (PR #73158)
fhahn wrote: @Enna1 thanks, should be fixed by 1b37e8087e1e1ecf5aadd8da536ee17dc21832e2. Bot should be back to green https://github.com/llvm/llvm-project/pull/73158 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [flang] [mlir] [lldb] [libcxxabi] [llvm] [clang-tools-extra] [libcxx] [libc] [clang] [lld] [compiler-rt] [mlir][complex] Prevent underflow in complex.abs (PR #76316)
Lewuathe wrote: @joker-eph Oh, sorry for bothering you. I'll check what's going on. https://github.com/llvm/llvm-project/pull/76316 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb] Implement WebAssembly debugging (PR #77949)
xujuntwt95329 wrote: > > Hi @mh4ck-Thales this is caused by [#77949 > > (comment)](https://github.com/llvm/llvm-project/pull/77949#discussion_r1463458728), > > currently we need to modify it manually. > > Thanks! That did the trick for the breakpoint and disassembly problems. When > using `read register` I can only see `pc` and nothing else though. I'm not > sure assimilating Wasm variables to registers is the good way to go anyway, > because the number of Wasm variables is not fixed in advance, and subject to > the context of execution (with local variables). This is not the case at all > for classic CPU registers, and I'm not sure the generic code managing > registers in lldb will support that. Using a solution like @jimingham > proposed with subcommands of `language wasm` may be a easier, less bug prone > way to implement this. Yes, the `virtual register` concepts is just used internally to allow us to process wasm locals/globals/operand stack values in a plugin without a huge modification to LLDB core part. This allows users to debug their source code, but doesn't support reading specific local/global values. Currently lldb doesn't have an exist model for representing wasm's local/global/operand stack values, I think encoding them as virtual registers is an easy approach for enabling WebAssembly debugging and without a huge modification to LLDB core part. On the other hand, as a managed language, I think most people won't need to read specific local/global of an instance, just like most of the JavaScript developer won't care about the value of a register in V8 during debugging, they just care about the value of their variables. So I think the virtual register approach should be okay for the developer usage, with small engineering effort and limited quality influence to LLDB. https://github.com/llvm/llvm-project/pull/77949 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
