[Lldb-commits] [clang] [lldb] Use CLANG_RESOURCE_DIR more consistently (PR #103388)
https://github.com/MaskRay approved this pull request. clangDriver changes look reasonable. https://github.com/llvm/llvm-project/pull/103388 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [LLDB] Improve ObjectFileELF files ability to load from memory. (PR #100900)
MaskRay wrote: > I like this idea a lot, but I have some reservations about the implementation. > > For one, I think this patch is too big. I once heard someone say "if you have > bullet points in your patch description, then the patch is doing too much". > While I don't think we should go as far as to create a separate PR for each > of your bullet points, I do believe that splitting it up into a couple of > pieces would go along way towards making it easier to review. > > I also see that some of the functionality is guarded by `IsInMemory()`, which > doesn't sounds like the right thing to do, as the we should in principle be > able to use the same code for parsing parsing section-header-less object > files on disk. These aren't exactly common, but like @MaskRay said, section > headers aren't strictly needed for linked object files, and it's much easier > to make test using these. > > Finally, I think that structuring some of this code as "fallback" is not > ideal, as it can cause some data can be parsed twice (I think it happens at > least with ELF notes in this patch). Even if that's innocuous , I don't think > it's right because the two mechanisms (program and section headers) are just > different ways of finding the same data. I think it'd be cleaner if this was > implemented as a two-step process: > > 1. find the data (e.g., notes): This will look into section and program > headers to find the appropriate bytes (I might even argue it should look at > program headers first, as that's what the operating system will use) > 2. use the data (regardless of where it comes from) > > I realise this feedback isn't very specific, but that's because I found it > very hard to follow everything that's going on in this patch. I'm sure I'll > be able to be more specific on the partial patches (and maybe some of my > assumptions will turn out to be incorrect). As a first patch in the series, > I'd recommend teaching lldb to parse section-header-less object files. Right > now, if I run lldb on such a file, it will tell me that it's empty (has zero > sections). Making the program headers visible would lay the foundation for > other changes, and it would also be the smallest testable piece of > functionality (by dumping the section list). > > @MaskRay can you recommend a good to create these kinds of files? I was > thinking of a combination `yaml2obj` + `llvm-objcopy --strip-sections` > (because IIRC yaml2obj always inserts some sections into the output), but > maybe there's something better (?) yaml2obj omits the section header table when `NoHeaders: true` is specified. ``` - Type: SectionHeaderTable NoHeaders: true ``` However, obj2yaml doesn't create `NoHeaders: true` yet. If the test utilizes `ld.lld`, `llvm-objcopy --strip-sections` will be needed. GNU ld 2.41 supports `-z nosectionheader`, which lld doesn't support yet (if there is enough interest I can add it). https://github.com/llvm/llvm-project/pull/100900 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [LLDB] Improve ObjectFileELF files ability to load from memory. (PR #100900)
MaskRay wrote: I'm not familiar with lldb, but I can make some comments as @tschuett invited me:) Parsing PT_NOTE is a great step, as program headers are sufficient for executables, shared objects, and core dumps. The section header table isn't needed and the relevant code could be dropped (unless relocatable file debugging is required). Has the code been updated to handle p_align=8 PT_LOAD correctly? https://reviews.llvm.org/D150022 might be a related change from LLVMObject. https://github.com/llvm/llvm-project/pull/100900 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [lldb] [llvm] Remove some `try_compile` CMake checks for compiler flags (PR #92953)
MaskRay wrote: > Hi @Endilll > > I did a git bisect that pointed to this change as the one blocking my > compilation on an Ubuntu docker image with clang 14.0 > > The error I see: > > ``` > CMake Error at > /test_radsan/llvm-project/compiler-rt/cmake/Modules/CheckSectionExists.cmake:72 > (message): > cc: error: unrecognized command-line option > '-Wcovered-switch-default'; did you mean > '-Wno-switch-default'? > > cc: error: unrecognized command-line option > '-Wstring-conversion'; did you mean > '-Wsign-conversion'? > > Call Stack (most recent call first): > /test_radsan/llvm-project/compiler-rt/lib/builtins/CMakeLists.txt:923 > (check_section_exists) > ``` > > My compiler info, printed from CMake: > > ``` > CMAKE_CXX_COMPILER_VERSION: 14.0.0 > CMAKE_CXX_COMPILER_ID: Clang > ``` > > More info from the command line: > > ``` > $ clang --version > Ubuntu clang version 14.0.0-1ubuntu1.1 > Target: aarch64-unknown-linux-gnu > Thread model: posix > InstalledDir: /usr/bin > $ uname -a > Linux 18728bf50582 6.5.11-linuxkit #1 SMP PREEMPT Mon Dec 4 11:30:00 UTC > 2023 aarch64 aarch64 aarch64 GNU/Linux > $ cmake --version > cmake version 3.22.1 > ``` > > Let me know what other information may be helpful, or if this is user error. > It seems from your godbolt links above, clang 5.0 and higher should work, so > I'm surprised that 14.0 is dying in this environment `unrecognized command-line option` is from GCC. Your build environment might conflate GCC with Clang (`CMAKE_CXX_COMPILER_ID: Clang`). ``` % gcc -Wx -c a.c gcc: error: unrecognized command-line option ‘-Wx’ % clang -Wx -c a.c warning: unknown warning option '-Wx' [-Wunknown-warning-option] 1 warning generated. ``` https://github.com/llvm/llvm-project/pull/92953 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [compiler-rt] [lldb] [llvm] Reapply "[Support] Remove terminfo dependency (#92865)" (PR #93889)
https://github.com/MaskRay approved this pull request. https://github.com/llvm/llvm-project/pull/93889 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [compiler-rt] [lldb] [llvm] Reapply "[Support] Remove terminfo dependency (#92865)" (PR #93889)
MaskRay wrote: Consider copying the original description to ensure that the linked issues will be properly closed. https://github.com/llvm/llvm-project/pull/93889 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [compiler-rt] [lldb] [llvm] [Support] Remove terminfo dependency (PR #92865)
https://github.com/MaskRay approved this pull request. https://github.com/llvm/llvm-project/pull/92865 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [compiler-rt] [libc] [libclc] [libcxxabi] [lld] [lldb] [llvm] [mlir] Add clarifying parenthesis around non-trivial conditions in ternary expressions. (PR #90391)
@@ -801,7 +801,7 @@ static OutputDesc *addInputSec(StringMap> &map, auto *firstIsec = cast( cast(sec->commands[0])->sectionBases[0]); OutputSection *firstIsecOut = - firstIsec->flags & SHF_LINK_ORDER MaskRay wrote: A CppCheck issue may or may not be useful for the project. Projects have different code styles. Applying a random static analyzer report may not be useful. https://github.com/llvm/llvm-project/pull/90391 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [lldb] [llvm] Remove some `try_compile` CMake checks for compiler flags (PR #92953)
https://github.com/MaskRay approved this pull request. Great 👍 https://github.com/llvm/llvm-project/pull/92953 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb] Use operator==(StringRef, StringRef) instead of StringRef::equals (NFC) (PR #92476)
https://github.com/MaskRay approved this pull request. https://github.com/llvm/llvm-project/pull/92476 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] Read and store gnu build id from loaded core file (PR #92078)
@@ -983,6 +999,40 @@ llvm::Error
ProcessElfCore::ParseThreadContextsFromNoteSegment(
}
}
+bool ProcessElfCore::IsElf(const NT_FILE_Entry entry) {
+ size_t size = strlen(llvm::ELF::ElfMagic);
+ uint8_t buf[size];
MaskRay wrote:
We can allocate a buffer of 4 and read it.
Can ELFHeader::MagicBytesMatch be used here?
https://github.com/llvm/llvm-project/pull/92078
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[Lldb-commits] [lldb] Read and store gnu build id from loaded core file (PR #92078)
@@ -983,6 +999,40 @@ llvm::Error
ProcessElfCore::ParseThreadContextsFromNoteSegment(
}
}
+bool ProcessElfCore::IsElf(const NT_FILE_Entry entry) {
+ size_t size = strlen(llvm::ELF::ElfMagic);
+ uint8_t buf[size];
MaskRay wrote:
```
15: error: variable length arrays in C++ are a Clang extension
[-Werror,-Wvla-cxx-extension]
1004 | uint8_t buf[size];
```
https://github.com/llvm/llvm-project/pull/92078
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[Lldb-commits] [clang] [compiler-rt] [libc] [libclc] [libcxxabi] [lld] [lldb] [llvm] [mlir] Add clarifying parenthesis around non-trivial conditions in ternary expressions. (PR #90391)
@@ -801,7 +801,7 @@ static OutputDesc *addInputSec(StringMap> &map, auto *firstIsec = cast( cast(sec->commands[0])->sectionBases[0]); OutputSection *firstIsecOut = - firstIsec->flags & SHF_LINK_ORDER MaskRay wrote: Why is random change made to lld/ELF? `[-+*%] \w+ \?'` is extensively used and I don't see we add `)` https://github.com/llvm/llvm-project/pull/90391 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [compiler-rt] [libc] [libclc] [libcxxabi] [lld] [lldb] [llvm] [mlir] Add clarifying parenthesis around non-trivial conditions in ternary expressions. (PR #90391)
@@ -3802,7 +3802,7 @@ bool X86AsmParser::validateInstruction(MCInst &Inst,
const OperandVector &Ops) {
//VFMULCPHZrr Dest, Src1, Src2
//VFMULCPHZrrk Dest, Dest, Mask, Src1, Src2
//VFMULCPHZrrkz Dest, Mask, Src1, Src2
-for (unsigned i = TSFlags & X86II::EVEX_K ? 2 : 1;
MaskRay wrote:
I know it's subjective, but the new code with two levels of parens decreases
readability.
https://github.com/llvm/llvm-project/pull/90391
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[Lldb-commits] [clang] [clang-tools-extra] [compiler-rt] [flang] [lldb] [llvm] [mlir] [openmp] [pstl] Finally formalise our defacto line-ending policy (PR #86318)
@@ -1,3 +1,10 @@ +# Checkout as native, commit as LF except in specific circumstances +* text=auto +*.bat text eol=crlf +*.rc text eol=crlf +*.sln text eol=crlf MaskRay wrote: Do we need `.sln`? There is only one file in `clang/tools/clang-format-vs`. There are a few other text files in this directory, so perhaps a gitattributes in that directory is better? https://github.com/llvm/llvm-project/pull/86318 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [clang-tools-extra] [compiler-rt] [flang] [lldb] [llvm] [mlir] [openmp] [pstl] Finally formalise our defacto line-ending policy (PR #86318)
https://github.com/MaskRay approved this pull request. https://github.com/llvm/llvm-project/pull/86318 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [clang-tools-extra] [compiler-rt] [flang] [lld] [lldb] [llvm] [mlir] [openmp] [pstl] Finally formalise our defacto line-ending policy (PR #86318)
@@ -0,0 +1 @@ +dos-style-eol.txt MaskRay wrote: missing text=auto eol=crlf ? https://github.com/llvm/llvm-project/pull/86318 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] 5a12f28 - LLVM_FALLTHROUGH => [[fallthrough]]. NFC
Author: Fangrui Song
Date: 2024-04-25T17:50:59-07:00
New Revision: 5a12f2867a167bbe11099150f3cb6b6cb77d767c
URL:
https://github.com/llvm/llvm-project/commit/5a12f2867a167bbe11099150f3cb6b6cb77d767c
DIFF:
https://github.com/llvm/llvm-project/commit/5a12f2867a167bbe11099150f3cb6b6cb77d767c.diff
LOG: LLVM_FALLTHROUGH => [[fallthrough]]. NFC
Added:
Modified:
clang-tools-extra/clangd/CodeCompletionStrings.cpp
lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
llvm/include/llvm/IR/GenericConvergenceVerifierImpl.h
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/lib/Support/regcomp.c
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/utils/TableGen/DXILEmitter.cpp
Removed:
diff --git a/clang-tools-extra/clangd/CodeCompletionStrings.cpp
b/clang-tools-extra/clangd/CodeCompletionStrings.cpp
index 2075e5965f181e..9b4442b0bb76fd 100644
--- a/clang-tools-extra/clangd/CodeCompletionStrings.cpp
+++ b/clang-tools-extra/clangd/CodeCompletionStrings.cpp
@@ -253,7 +253,7 @@ void getSignature(const CodeCompletionString &CCS,
std::string *Signature,
if (!IncludeFunctionArguments &&
ResultKind == CodeCompletionResult::RK_Declaration)
TruncateSnippetAt.emplace(Snippet->size());
- LLVM_FALLTHROUGH;
+ [[fallthrough]];
case CodeCompletionString::CK_RightParen:
case CodeCompletionString::CK_LeftBracket:
case CodeCompletionString::CK_RightBracket:
diff --git
a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
index d3fc487aed4333..9409497f1c81ba 100644
---
a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
+++
b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
@@ -1869,15 +1869,15 @@
AppleObjCRuntimeV2::DynamicClassInfoExtractor::ComputeHelper(
if (loader->IsFullyInitialized()) {
switch (exe_ctx.GetTargetRef().GetDynamicClassInfoHelper()) {
case eDynamicClassInfoHelperAuto:
- LLVM_FALLTHROUGH;
+ [[fallthrough]];
case eDynamicClassInfoHelperGetRealizedClassList:
if (m_runtime.m_has_objc_getRealizedClassList_trylock)
return
DynamicClassInfoExtractor::objc_getRealizedClassList_trylock;
- LLVM_FALLTHROUGH;
+ [[fallthrough]];
case eDynamicClassInfoHelperCopyRealizedClassList:
if (m_runtime.m_has_objc_copyRealizedClassList)
return DynamicClassInfoExtractor::objc_copyRealizedClassList;
- LLVM_FALLTHROUGH;
+ [[fallthrough]];
case eDynamicClassInfoHelperRealizedClassesStruct:
return DynamicClassInfoExtractor::gdb_objc_realized_classes;
}
diff --git a/llvm/include/llvm/IR/GenericConvergenceVerifierImpl.h
b/llvm/include/llvm/IR/GenericConvergenceVerifierImpl.h
index a3ebde709ae6e1..7525c9eb758bef 100644
--- a/llvm/include/llvm/IR/GenericConvergenceVerifierImpl.h
+++ b/llvm/include/llvm/IR/GenericConvergenceVerifierImpl.h
@@ -76,7 +76,7 @@ void GenericConvergenceVerifier::visit(const
InstructionT &I) {
"Entry intrinsic cannot be preceded by a convergent operation in the
"
"same basic block.",
{Context.print(&I)});
-LLVM_FALLTHROUGH;
+[[fallthrough]];
case CONV_ANCHOR:
Check(!TokenDef,
"Entry or anchor intrinsic cannot have a convergencectrl token "
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 8cf392ab0567e5..d7b0c9aa166735 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -2223,7 +2223,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst
&CI, Intrinsic::ID ID,
// addresses. We can treat it like a normal dbg_value intrinsic here; to
// benefit from the full analysis of stack/SSA locations, GlobalISel would
// need to register for and use the AssignmentTrackingAnalysis pass.
-LLVM_FALLTHROUGH;
+[[fallthrough]];
case Intrinsic::dbg_value: {
// This form of DBG_VALUE is target-independent.
const DbgValueInst &DI = cast(CI);
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index aefedd060f897d..ef9f7833551905 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1424,7 +1424,7 @@ bool FastISel::selectIntrinsicCall(const IntrinsicInst
*II) {
// happened (such as an optimised fun
[Lldb-commits] [lldb] [lldb/test] Add basic ld.lld --debug-names tests (PR #88335)
https://github.com/MaskRay closed https://github.com/llvm/llvm-project/pull/88335 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb/test] Add basic ld.lld --debug-names tests (PR #88335)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/88335 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb/test] Add basic ld.lld --debug-names tests (PR #88335)
https://github.com/MaskRay ready_for_review https://github.com/llvm/llvm-project/pull/88335 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb/test] Add basic ld.lld --debug-names tests (PR #88335)
https://github.com/MaskRay updated https://github.com/llvm/llvm-project/pull/88335 >From 210b1e85f2d827a7c57f3b1106d876d2e0f18511 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Wed, 10 Apr 2024 18:03:57 -0700 Subject: [PATCH] [lldb/test] Add basic ld.lld --debug-names tests Test that ld.lld --debug-names (#86508) built per-module index can be consumed by lldb. This has uncovered a bug during the development of the lld feature. --- lldb/test/Shell/SymbolFile/DWARF/x86/find-basic-function.cpp | 5 + lldb/test/Shell/SymbolFile/DWARF/x86/find-basic-variable.cpp | 5 + 2 files changed, 10 insertions(+) diff --git a/lldb/test/Shell/SymbolFile/DWARF/x86/find-basic-function.cpp b/lldb/test/Shell/SymbolFile/DWARF/x86/find-basic-function.cpp index 30143a41d5e734..b9a63525d0711d 100644 --- a/lldb/test/Shell/SymbolFile/DWARF/x86/find-basic-function.cpp +++ b/lldb/test/Shell/SymbolFile/DWARF/x86/find-basic-function.cpp @@ -59,6 +59,11 @@ // RUN: lldb-test symbols --name=not_there --find=function %t | \ // RUN: FileCheck --check-prefix=EMPTY %s +/// Test a per-module index built by lld. +// RUN: ld.lld --debug-names %t.o -o %t +// RUN: lldb-test symbols --name=foo --find=function --function-flags=base %t | \ +// RUN: FileCheck --check-prefix=BASE %s + // NAMES: Name: .debug_names // BASE: Found 4 functions: diff --git a/lldb/test/Shell/SymbolFile/DWARF/x86/find-basic-variable.cpp b/lldb/test/Shell/SymbolFile/DWARF/x86/find-basic-variable.cpp index 98b4097cdda01f..e46fa14489d32d 100644 --- a/lldb/test/Shell/SymbolFile/DWARF/x86/find-basic-variable.cpp +++ b/lldb/test/Shell/SymbolFile/DWARF/x86/find-basic-variable.cpp @@ -33,6 +33,11 @@ // RUN: lldb-test symbols --name=not_there --find=variable %t | \ // RUN: FileCheck --check-prefix=EMPTY %s +/// Test a per-module index built by lld. +// RUN: ld.lld --debug-names %t.o -o %t +// RUN: lldb-test symbols --name=foo --find=variable --context=context %t | \ +// RUN: FileCheck --check-prefix=CONTEXT %s + // NAMES: Name: .debug_names // EMPTY: Found 0 variables: ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lld] [lldb] [lldb/test] Add basic ld.lld --debug-names tests (PR #88335)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/88335 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lld] [lldb] [lldb/test] Add basic ld.lld --debug-names tests (PR #88335)
MaskRay wrote: This is not for review yet. When ld.lld --debug-names is added, this PR will be changed to add a few lines to `lldb/test/Shell/SymbolFile/DWARF/x86` tests. https://github.com/llvm/llvm-project/pull/88335 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lld] [lldb] [llvm] [mlir] Rename ThreadPool->DefaultThreadPool and ThreadPoolInterface->ThreadPool (NFC) (PR #83702)
https://github.com/MaskRay approved this pull request. https://github.com/llvm/llvm-project/pull/83702 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] ebaf26d - [lldb] Fix -Wformat after #83602
Author: Fangrui Song
Date: 2024-03-01T12:09:32-08:00
New Revision: ebaf26dabec00c32177cd4fa47f3bf5902b194b7
URL:
https://github.com/llvm/llvm-project/commit/ebaf26dabec00c32177cd4fa47f3bf5902b194b7
DIFF:
https://github.com/llvm/llvm-project/commit/ebaf26dabec00c32177cd4fa47f3bf5902b194b7.diff
LOG: [lldb] Fix -Wformat after #83602
Added:
Modified:
lldb/source/Commands/CommandObjectThread.cpp
Removed:
diff --git a/lldb/source/Commands/CommandObjectThread.cpp
b/lldb/source/Commands/CommandObjectThread.cpp
index 6d84315a471d95..cf4f8ccaa0c4aa 100644
--- a/lldb/source/Commands/CommandObjectThread.cpp
+++ b/lldb/source/Commands/CommandObjectThread.cpp
@@ -280,7 +280,7 @@ class ThreadStepScopeOptionGroup : public OptionGroup {
if (!success)
error.SetErrorStringWithFormat(
"invalid boolean value for option '%c': %s", short_option,
-option_arg);
+option_arg.data());
else {
m_step_in_avoid_no_debug = avoid_no_debug ? eLazyBoolYes : eLazyBoolNo;
}
@@ -293,7 +293,7 @@ class ThreadStepScopeOptionGroup : public OptionGroup {
if (!success)
error.SetErrorStringWithFormat(
"invalid boolean value for option '%c': %s", short_option,
-option_arg);
+option_arg.data());
else {
m_step_out_avoid_no_debug = avoid_no_debug ? eLazyBoolYes :
eLazyBoolNo;
}
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[Lldb-commits] [libc] [clang-tools-extra] [openmp] [libcxx] [compiler-rt] [lldb] [mlir] [llvm] [lld] [flang] [clang] [Driver] Report invalid target triple versions for all environment types. (PR #7865
MaskRay wrote: > > There's apparently also wasm32-wasi-preview2 and wasm32-wasi-pthread, which > > I suppose are equally broken by this change. > > Yes, I think so. I think adding these environment types in wasi-libc repo > could help fix those errors. If wasm can arbitrary environment types, it seems that we can opt out the check for `isWasm()`. We define new environment types when they affect the compiler behavior. If wasm arbitrary sets the environment, we should not define a type for each one. https://github.com/llvm/llvm-project/pull/78655 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [libcxx] [clang] [libc] [libcxxabi] [flang] [llvm] [lld] [msan] Unpoison indirect outputs for userspace using memset for large operands (PR #79924)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79924 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [libcxx] [clang] [libc] [libcxxabi] [flang] [llvm] [lld] [msan] Unpoison indirect outputs for userspace using memset for large operands (PR #79924)
@@ -4552,16 +4552,22 @@ struct MemorySanitizerVisitor : public
InstVisitor {
}
if (!ElemTy->isSized())
return;
-Value *SizeVal =
- IRB.CreateTypeSize(MS.IntptrTy, DL.getTypeStoreSize(ElemTy));
+auto Size = DL.getTypeStoreSize(ElemTy);
+Value *SizeVal = IRB.CreateTypeSize(MS.IntptrTy, Size);
if (MS.CompileKernel) {
IRB.CreateCall(MS.MsanInstrumentAsmStoreFn, {Operand, SizeVal});
} else {
// ElemTy, derived from elementtype(), does not encode the alignment of
// the pointer. Conservatively assume that the shadow memory is
unaligned.
+ // When Size is large, avoid StoreInst as it would expand to many
+ // instructions.
auto [ShadowPtr, _] =
getShadowOriginPtrUserspace(Operand, IRB, IRB.getInt8Ty(), Align(1));
- IRB.CreateAlignedStore(getCleanShadow(ElemTy), ShadowPtr, Align(1));
+ if (Size <= 32)
MaskRay wrote:
Thanks for your previous comment about the interceptor. The committed patch
does contain this description:
"The intrinsic, if lowered to libcall, will use the msan interceptor."
Inline asm isn't commonly used:) This patch is for `=m` in extended asm, which
I believe is typically used with small objects. I guess 32 and 64 won't make a
difference.
https://github.com/llvm/llvm-project/pull/79924
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[Lldb-commits] [llvm] [lldb] [lld] [openmp] [compiler-rt] [mlir] [libc] [clang-tools-extra] [clang] [libcxx] [flang] Make clang report invalid target versions for all environment types. (PR #78655)
@@ -1219,8 +1222,25 @@ VersionTuple Triple::getEnvironmentVersion() const {
StringRef Triple::getEnvironmentVersionString() const {
StringRef EnvironmentName = getEnvironmentName();
+
+ // none is a valid environment type - it basically amounts to a freestanding
+ // environment.
+ if (EnvironmentName == "none")
+return "";
+
StringRef EnvironmentTypeName = getEnvironmentTypeName(getEnvironment());
EnvironmentName.consume_front(EnvironmentTypeName);
+
+ if (EnvironmentName.contains("-")) {
+// -obj is the suffix
+if (getObjectFormat() != Triple::UnknownObjectFormat) {
+ StringRef ObjectFormatTypeName =
+ getObjectFormatTypeName(getObjectFormat());
+ const std::string &tmp = (Twine("-") + ObjectFormatTypeName).str();
MaskRay wrote:
Just use `const std::string`. The lifetime extension due to `const &` is subtle
and fragile, and does not give any benefit here.
https://en.cppreference.com/w/cpp/language/reference_initialization#Lifetime_of_a_temporary
https://abseil.io/tips/107
Then `EnvironmentName.consume_back(tmp);`
Avoid the used-once `StringRef Suffix = tmp;`
https://github.com/llvm/llvm-project/pull/78655
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[Lldb-commits] [flang] [clang-tools-extra] [openmp] [compiler-rt] [lld] [libc] [mlir] [lldb] [clang] [llvm] [libcxx] Make clang report invalid target versions for all environment types. (PR #78655)
https://github.com/MaskRay approved this pull request. A better title may be: [Driver] Report invalid target triple versions for all environment types. "Driver" is better than "clang" as it is specific about where the error arises. https://github.com/llvm/llvm-project/pull/78655 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [openmp] [llvm] [lld] [flang] [clang] [compiler-rt] [libcxx] [clang-tools-extra] [mlir] [libc] Make clang report invalid target versions for all environment types. (PR #78655)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/78655 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lld] [clang-tools-extra] [flang] [llvm] [libcxx] [libc] [clang] [lldb] [AArch64] Support optional constant offset for constraint "S" (PR #80255)
https://github.com/MaskRay closed https://github.com/llvm/llvm-project/pull/80255 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [libc] [clang-tools-extra] [lld] [lldb] [clang] [libcxx] [flang] [llvm] [AArch64] Support optional constant offset for constraint "S" (PR #80255)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/80255
>From 8ce25b59ac48e3b0a69c28e8af3abe6d7cbf0c42 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Wed, 31 Jan 2024 23:25:23 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
clang/test/Sema/inline-asm-validate-aarch64.c | 17 ++---
llvm/docs/LangRef.rst | 2 ++
.../Target/AArch64/AArch64ISelLowering.cpp| 19 ++-
.../CodeGen/AArch64/inlineasm-S-constraint.ll | 4
.../CodeGen/RISCV/inline-asm-S-constraint.ll | 1 +
5 files changed, 27 insertions(+), 16 deletions(-)
diff --git a/clang/test/Sema/inline-asm-validate-aarch64.c
b/clang/test/Sema/inline-asm-validate-aarch64.c
index 014767d5a3923..1e753d40d8ca0 100644
--- a/clang/test/Sema/inline-asm-validate-aarch64.c
+++ b/clang/test/Sema/inline-asm-validate-aarch64.c
@@ -1,14 +1,24 @@
+// RUN: %clang_cc1 -triple aarch64 -fsyntax-only -verify -DVERIFY %s
// RUN: %clang_cc1 -triple arm64-apple-darwin -fsyntax-only
-fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s
typedef unsigned char uint8_t;
+#ifdef VERIFY
+void test_s(int i) {
+ asm("" :: "s"(i)); // expected-error{{invalid input constraint 's' in asm}}
+
+ /// Codegen error
+ asm("" :: "S"(i));
+ asm("" :: "S"(test_s(i))); // expected-error{{invalid type 'void' in asm
input for constraint 'S'}}
+}
+#else
uint8_t constraint_r(uint8_t *addr) {
uint8_t byte;
__asm__ volatile("ldrb %0, [%1]" : "=r" (byte) : "r" (addr) : "memory");
// CHECK: warning: value size does not match register size specified by the
constraint and modifier
// CHECK: note: use constraint modifier "w"
-// CHECK: fix-it:{{.*}}:{8:26-8:28}:"%w0"
+// CHECK: fix-it:{{.*}}:{[[#@LINE-3]]:26-[[#@LINE-3]]:28}:"%w0"
return byte;
}
@@ -19,7 +29,7 @@ uint8_t constraint_r_symbolic(uint8_t *addr) {
__asm__ volatile("ldrb %[s0], [%[s1]]" : [s0] "=r" (byte) : [s1] "r" (addr)
: "memory");
// CHECK: warning: value size does not match register size specified by the
constraint and modifier
// CHECK: note: use constraint modifier "w"
-// CHECK: fix-it:{{.*}}:{19:26-19:31}:"%w[s0]"
+// CHECK: fix-it:{{.*}}:{[[#@LINE-3]]:26-[[#@LINE-3]]:31}:"%w[s0]"
return byte;
}
@@ -40,11 +50,11 @@ uint8_t constraint_r_symbolic_macro(uint8_t *addr) {
// CHECK: warning: value size does not match register size specified by the
constraint and modifier
// CHECK: asm ("%w0 %w1 %2" : "+r" (one) : "r" (wide_two));
// CHECK: note: use constraint modifier "w"
-// CHECK: fix-it:{{.*}}:{47:17-47:19}:"%w2"
void read_write_modifier0(int one, int two) {
long wide_two = two;
asm ("%w0 %w1 %2" : "+r" (one) : "r" (wide_two));
+// CHECK: fix-it:{{.*}}:{[[#@LINE-1]]:17-[[#@LINE-1]]:19}:"%w2"
}
// CHECK-NOT: warning:
@@ -52,3 +62,4 @@ void read_write_modifier1(int one, int two) {
long wide_two = two;
asm ("%w0 %1" : "+r" (one), "+r" (wide_two));
}
+#endif
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index 7a7ddc59ba985..b13f8c7811d16 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -5107,6 +5107,8 @@ AArch64:
offsets). (However, LLVM currently does this for the ``m`` constraint as
well.)
- ``r``: A 32 or 64-bit integer register (W* or X*).
+- ``S``: A symbol or label reference with a constant offset. The generic ``s``
+ is not supported.
- ``Uci``: Like r, but restricted to registers 8 to 11 inclusive.
- ``Ucj``: Like r, but restricted to registers 12 to 15 inclusive.
- ``w``: A 32, 64, or 128-bit floating-point, SIMD or SVE vector register.
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index bb19aef978b94..62f160c1c33fc 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -10618,7 +10618,7 @@ AArch64TargetLowering::getConstraintType(StringRef
Constraint) const {
case 'Z':
return C_Immediate;
case 'z':
-case 'S': // A symbolic address
+case 'S': // A symbol or label reference with a constant offset
return C_Other;
}
} else if (parsePredicateConstraint(Constraint))
@@ -10801,19 +10801,12 @@ void
AArch64TargetLowering::LowerAsmOperandForConstraint(
Result = DAG.getRegister(AArch64::WZR, MVT::i32);
break;
}
- case 'S': {
-// An absolute symbolic address or label reference.
-if (const GlobalAddressSDNode *GA = dyn_cast(Op)) {
- Result = DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op),
- GA->getValueType(0));
-} else if (const BlockAddressSDNode *BA =
- dyn_cast(Op)) {
- Result =
- DAG.getTargetBlockAddress(BA->getBlockAddress(),
BA->getValueType(0));
-} else
- return;
+ case '
[Lldb-commits] [lld] [libcxxabi] [clang] [libc] [flang] [libcxx] [lldb] [llvm] [msan] Unpoison indirect outputs for userspace using memset for large operands (PR #79924)
@@ -4552,16 +4552,22 @@ struct MemorySanitizerVisitor : public
InstVisitor {
}
if (!ElemTy->isSized())
return;
-Value *SizeVal =
- IRB.CreateTypeSize(MS.IntptrTy, DL.getTypeStoreSize(ElemTy));
+auto Size = DL.getTypeStoreSize(ElemTy);
+Value *SizeVal = IRB.CreateTypeSize(MS.IntptrTy, Size);
if (MS.CompileKernel) {
IRB.CreateCall(MS.MsanInstrumentAsmStoreFn, {Operand, SizeVal});
} else {
// ElemTy, derived from elementtype(), does not encode the alignment of
// the pointer. Conservatively assume that the shadow memory is
unaligned.
+ // When Size is large, avoid StoreInst as it would expand to many
+ // instructions.
auto [ShadowPtr, _] =
getShadowOriginPtrUserspace(Operand, IRB, IRB.getInt8Ty(), Align(1));
- IRB.CreateAlignedStore(getCleanShadow(ElemTy), ShadowPtr, Align(1));
+ if (Size <= 32)
MaskRay wrote:
This is a bit arbitrary. Perhaps
`// The size threshold matches shouldUseBZeroPlusStoresToInitialize for
-ftrivial-auto-var-init=zero`?
https://github.com/llvm/llvm-project/pull/79924
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[Lldb-commits] [clang] [lld] [libc] [libcxx] [compiler-rt] [llvm] [lldb] [flang] [clang-tools-extra] Make clang report invalid target versions for all environment types. (PR #78655)
MaskRay wrote:
If I remove `OpenCL`, `clang/test/CodeGenOpenCL/amdgpu-alignment.cl` won't
fail. It seems that OpenCL is a not a necessary change in this PR.
```
--- i/llvm/lib/TargetParser/Triple.cpp
+++ w/llvm/lib/TargetParser/Triple.cpp
@@ -325,4 +325,2 @@ StringRef Triple::getEnvironmentTypeName(EnvironmentType
Kind) {
case Amplification: return "amplification";
- case OpenCL:
-return "opencl";
case OpenHOS: return "ohos";
@@ -696,3 +694,2 @@ static Triple::EnvironmentType parseEnvironment(StringRef
EnvironmentName) {
.StartsWith("amplification", Triple::Amplification)
- .StartsWith("opencl", Triple::OpenCL)
.StartsWith("ohos", Triple::OpenHOS)
```
https://github.com/llvm/llvm-project/pull/78655
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[Lldb-commits] [lldb] [clang-tools-extra] [libcxx] [lld] [clang] [libc] [llvm] [compiler-rt] [flang] Make clang report invalid target versions for all environment types. (PR #78655)
@@ -400,12 +400,12 @@ // LONG-CALLS-DEF-NOT: "long-calls" // // -mbranch-likely -// RUN: %clang -target -mips-mti-linux-gnu -### -c %s -mbranch-likely 2>&1 \ +// RUN: %clang -target mips-mti-linux-gnu -### -c %s -mbranch-likely 2>&1 \ MaskRay wrote: while updating, switching to `--target=`. `-target ` has been deprecated since Clang 3.4 https://github.com/llvm/llvm-project/pull/78655 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [clang-tools-extra] [libcxx] [lld] [clang] [libc] [llvm] [compiler-rt] [flang] Make clang report invalid target versions for all environment types. (PR #78655)
@@ -1219,8 +1222,24 @@ VersionTuple Triple::getEnvironmentVersion() const {
StringRef Triple::getEnvironmentVersionString() const {
StringRef EnvironmentName = getEnvironmentName();
+
+ // none is a valid environment type - it basically amounts to a freestanding
+ // environment.
+ if (EnvironmentName == "none")
+return "";
+
StringRef EnvironmentTypeName = getEnvironmentTypeName(getEnvironment());
EnvironmentName.consume_front(EnvironmentTypeName);
+
+ if (EnvironmentName.contains("-")) {
+// -obj is the suffix
+if (getObjectFormat() != Triple::UnknownObjectFormat) {
+ StringRef ObjectFormatTypeName =
+ getObjectFormatTypeName(getObjectFormat());
+ StringRef Suffix = (Twine("-") + ObjectFormatTypeName).str();
MaskRay wrote:
This creates a temporary `std::string` and binds it on a StringRef. The
temporary `std::string` is then destroyed, leading to a dangling reference,
which Clang helpfully warns -Wdangling-gsl
https://github.com/llvm/llvm-project/pull/78655
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[Lldb-commits] [libc] [llvm] [libcxx] [clang-tools-extra] [clang] [flang] [lldb] [RISCV] Support constraint "s" (PR #80201)
https://github.com/MaskRay closed https://github.com/llvm/llvm-project/pull/80201 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [llvm] [libc] [clang-tools-extra] [libcxx] [lldb] [flang] [RISCV] Support constraint "s" (PR #80201)
@@ -0,0 +1,76 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -relocation-model=static < %s | FileCheck %s
--check-prefix=RV32
+; RUN: llc -mtriple=riscv64 -relocation-model=pic < %s | FileCheck %s
--check-prefix=RV64
+
+@var = external dso_local global i32, align 4
+@a = external global [2 x [2 x i32]], align 4
+
+define dso_local void @test() {
+; CHECK-LABEL: test:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:#APP
+; CHECK-NEXT:# var a+12 test
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:ret{{[l|q]}}
MaskRay wrote:
Thanks for catching this. Removed
https://github.com/llvm/llvm-project/pull/80201
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[Lldb-commits] [clang] [llvm] [libc] [clang-tools-extra] [libcxx] [lldb] [flang] [RISCV] Support constraint "s" (PR #80201)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/80201
>From 7e9a74f18904f689d76bb2ea06ddf5f30d651b5e Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Wed, 31 Jan 2024 13:39:13 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
clang/lib/Basic/Targets/RISCV.cpp | 3 +-
clang/test/CodeGen/RISCV/riscv-inline-asm.c | 16 +++-
clang/test/Sema/inline-asm-validate-riscv.c | 8 ++
llvm/docs/LangRef.rst | 3 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 9 +--
.../CodeGen/RISCV/inline-asm-S-constraint.ll | 54 -
.../RISCV/inline-asm-s-constraint-error.ll| 14
.../CodeGen/RISCV/inline-asm-s-constraint.ll | 76 +++
8 files changed, 116 insertions(+), 67 deletions(-)
delete mode 100644 llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll
create mode 100644 llvm/test/CodeGen/RISCV/inline-asm-s-constraint-error.ll
create mode 100644 llvm/test/CodeGen/RISCV/inline-asm-s-constraint.ll
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index c71b2e9eeb6c1..837a6e799e3a9 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -96,7 +96,8 @@ bool RISCVTargetInfo::validateAsmConstraint(
// An address that is held in a general-purpose register.
Info.setAllowsMemory();
return true;
- case 'S': // A symbolic address
+ case 's':
+ case 'S': // A symbol or label reference with a constant offset
Info.setAllowsRegister();
return true;
case 'v':
diff --git a/clang/test/CodeGen/RISCV/riscv-inline-asm.c
b/clang/test/CodeGen/RISCV/riscv-inline-asm.c
index 48de5ba3a27e3..3565705dea713 100644
--- a/clang/test/CodeGen/RISCV/riscv-inline-asm.c
+++ b/clang/test/CodeGen/RISCV/riscv-inline-asm.c
@@ -45,8 +45,16 @@ void test_A(int *p) {
asm volatile("" :: "A"(*p));
}
-void test_S(void) {
-// CHECK-LABEL: define{{.*}} void @test_S()
-// CHECK: call void asm sideeffect "", "S"(ptr nonnull @f)
- asm volatile("" :: "S"(&f));
+extern int var, arr[2][2];
+struct Pair { int a, b; } pair;
+
+// CHECK-LABEL: test_s(
+// CHECK: call void asm sideeffect "// $0 $1 $2", "s,s,s"(ptr nonnull
@var, ptr nonnull getelementptr inbounds ([2 x [2 x i32]], ptr @arr, {{.*}}),
ptr nonnull @test_s)
+// CHECK: call void asm sideeffect "// $0", "s"(ptr nonnull
getelementptr inbounds (%struct.Pair, ptr @pair, {{.*}}))
+// CHECK: call void asm sideeffect "// $0 $1 $2", "S,S,S"(ptr nonnull
@var, ptr nonnull getelementptr inbounds ([2 x [2 x i32]], ptr @arr, {{.*}}),
ptr nonnull @test_s)
+void test_s(void) {
+ asm("// %0 %1 %2" :: "s"(&var), "s"(&arr[1][1]), "s"(test_s));
+ asm("// %0" :: "s"(&pair.b));
+
+ asm("// %0 %1 %2" :: "S"(&var), "S"(&arr[1][1]), "S"(test_s));
}
diff --git a/clang/test/Sema/inline-asm-validate-riscv.c
b/clang/test/Sema/inline-asm-validate-riscv.c
index 43a5378bc3f25..806ef60dacbec 100644
--- a/clang/test/Sema/inline-asm-validate-riscv.c
+++ b/clang/test/Sema/inline-asm-validate-riscv.c
@@ -22,6 +22,14 @@ void K(int k) {
asm volatile ("" :: "K"(AboveMax)); // expected-error{{value '32' out of
range for constraint 'K'}}
}
+void test_s(int i) {
+ asm("" :: "s"(test_s(0))); // expected-error{{invalid type 'void' in asm
input for constraint 's'}}
+ /// Codegen error
+ asm("" :: "s"(i));
+
+ asm("" :: "S"(test_s(0))); // expected-error{{invalid type 'void' in asm
input for constraint 'S'}}
+}
+
void test_clobber_conflict(void) {
register long x10 asm("x10");
asm volatile("" :: "r"(x10) : "x10"); // expected-error {{conflicts with asm
clobber list}}
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index 7a7ddc59ba985..3648ea2611dd4 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -5075,7 +5075,7 @@ Some constraint codes are typically supported by all
targets:
- ``i``: An integer constant (of target-specific width). Allows either a simple
immediate, or a relocatable value.
- ``n``: An integer constant -- *not* including relocatable values.
-- ``s``: An integer constant, but allowing *only* relocatable values.
+- ``s``: A symbol or label reference with a constant offset.
- ``X``: Allows an operand of any kind, no constraint whatsoever. Typically
useful to pass a label for an asm branch or call.
@@ -5283,6 +5283,7 @@ RISC-V:
- ``f``: A 32- or 64-bit floating-point register (requires F or D extension).
- ``r``: A 32- or 64-bit general-purpose register (depending on the platform
``XLEN``).
+- ``S``: Alias for ``s``.
- ``vr``: A vector register. (requires V extension).
- ``vm``: A vector register for masking operand. (requires V extension).
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b8994e7b7bdb2
[Lldb-commits] [lldb] [llvm] [libcxxabi] [libcxx] [libc] [lld] [clang] [flang] [msan] Unpoison indirect outputs for userspace using memset for large operands (PR #79924)
https://github.com/MaskRay closed https://github.com/llvm/llvm-project/pull/79924 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [flang] [libcxx] [clang] [llvm] [lld] [libcxxabi] [lldb] [libc] [msan] Unpoison indirect outputs for userspace using llvm.memset.* (PR #79924)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79924
>From 07043d27155ffd89e23b64c77a99880b2fa57e57 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Mon, 29 Jan 2024 17:02:18 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
.../Instrumentation/MemorySanitizer.cpp | 5 -
.../MemorySanitizer/msan_asm_conservative.ll | 16
2 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index 2b697557d8a9..0806d7a5b145 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -4559,9 +4559,12 @@ struct MemorySanitizerVisitor : public
InstVisitor {
} else {
// ElemTy, derived from elementtype(), does not encode the alignment of
// the pointer. Conservatively assume that the shadow memory is
unaligned.
+ // Avoid StoreInst as SizeVal may be large, expanding to many
+ // instructions.
auto [ShadowPtr, _] =
getShadowOriginPtrUserspace(Operand, IRB, IRB.getInt8Ty(), Align(1));
- IRB.CreateAlignedStore(getCleanShadow(ElemTy), ShadowPtr, Align(1));
+ IRB.CreateMemSet(ShadowPtr, ConstantInt::getNullValue(IRB.getInt8Ty()),
+ SizeVal, Align(1));
}
}
diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_asm_conservative.ll
b/llvm/test/Instrumentation/MemorySanitizer/msan_asm_conservative.ll
index 894f76b9b8d3..86ca697ed9a4 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/msan_asm_conservative.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/msan_asm_conservative.ll
@@ -177,8 +177,8 @@ entry:
}
; CHECK-LABEL: @f_2i_2o_mem
-; USER-CONS: store i32 0, ptr inttoptr (i64 xor (i64 ptrtoint (ptr @id1 to
i64), i64 87960930222080) to ptr), align 1
-; USER-CONS: store i32 0, ptr inttoptr (i64 xor (i64 ptrtoint (ptr @id2 to
i64), i64 87960930222080) to ptr), align 1
+; USER-CONS: call void @llvm.memset.p0.i64(ptr align 1 inttoptr (i64 xor (i64
ptrtoint (ptr @id1 to i64), i64 87960930222080) to ptr), i8 0, i64 4, i1 false)
+; USER-CONS: call void @llvm.memset.p0.i64(ptr align 1 inttoptr (i64 xor (i64
ptrtoint (ptr @id2 to i64), i64 87960930222080) to ptr), i8 0, i64 4, i1 false)
; CHECK-CONS: call void @__msan_instrument_asm_store({{.*}}@id1{{.*}}, i64 4)
; CHECK-CONS: call void @__msan_instrument_asm_store({{.*}}@id2{{.*}}, i64 4)
; CHECK: call void asm "", "=*m,=*m,*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr
elementtype(i32) @id1, ptr elementtype(i32) @id2, ptr elementtype(i32) @is1,
ptr elementtype(i32) @is2)
@@ -196,7 +196,7 @@ entry:
; CHECK-LABEL: @f_1i_1o_memreg
; CHECK: [[IS1_F7:%.*]] = load i32, ptr @is1, align 4
-; USER-CONS: store i32 0, ptr inttoptr (i64 xor (i64 ptrtoint (ptr @id1 to
i64), i64 87960930222080) to ptr), align 1
+; USER-CONS: call void @llvm.memset.p0.i64(ptr align 1 inttoptr (i64 xor (i64
ptrtoint (ptr @id1 to i64), i64 87960930222080) to ptr), i8 0, i64 4, i1 false)
; CHECK-CONS: call void @__msan_instrument_asm_store({{.*}}@id1{{.*}}, i64 4)
; CHECK: call void @__msan_warning
; CHECK: call i32 asm "", "=r,=*m,r,*m,~{dirflag},~{fpsr},~{flags}"(ptr
elementtype(i32) @id1, i32 [[IS1_F7]], ptr elementtype(i32) @is1)
@@ -215,7 +215,7 @@ entry:
}
; CHECK-LABEL: @f_3o_reg_mem_reg
-; USER-CONS: store i32 0, ptr inttoptr (i64 xor (i64 ptrtoint (ptr @id2 to
i64), i64 87960930222080) to ptr), align 1
+; USER-CONS: call void @llvm.memset.p0.i64(ptr align 1 inttoptr (i64 xor (i64
ptrtoint (ptr @id2 to i64), i64 87960930222080) to ptr), i8 0, i64 4, i1 false)
; CHECK-CONS: call void @__msan_instrument_asm_store(ptr @id2, i64 4)
; CHECK: call { i32, i32 } asm "", "=r,=*m,=r,~{dirflag},~{fpsr},~{flags}"(ptr
elementtype(i32) @id2)
@@ -240,7 +240,7 @@ entry:
; CHECK: [[PAIR1_F9:%.*]] = load {{.*}} @pair1
; CHECK: [[C1_F9:%.*]] = load {{.*}} @c1
; CHECK: [[MEMCPY_S1_F9:%.*]] = load {{.*}} @memcpy_s1
-; USER-CONS: store { i32, i32 } zeroinitializer, ptr inttoptr (i64 xor (i64
ptrtoint (ptr @pair2 to i64), i64 87960930222080) to ptr), align 1
+; USER-CONS: call void @llvm.memset.p0.i64(ptr align 1 inttoptr (i64 xor (i64
ptrtoint (ptr @pair2 to i64), i64 87960930222080) to ptr), i8 0, i64 8, i1
false)
; CHECK-CONS: call void @__msan_instrument_asm_store({{.*}}@pair2{{.*}}, i64 8)
; CHECK: call void @__msan_warning
; KMSAN: call void @__msan_warning
@@ -257,9 +257,9 @@ entry:
}
; CHECK-LABEL: @f_3i_3o_complex_mem
-; USER-CONS: store { i32, i32 } zeroinitializer, ptr inttoptr (i64 xor
(i64 ptrtoint (ptr @pair2 to i64), i64 87960930222080) to ptr), align 1
-; USER-CONS-NEXT: store i8 0, ptr inttoptr (i64 xor (i64 ptrtoint (ptr @c2
[Lldb-commits] [flang] [libcxx] [clang] [llvm] [lld] [libcxxabi] [lldb] [libc] [msan] Unpoison indirect outputs for userspace using llvm.memset.* (PR #79924)
MaskRay wrote: > LGTM in general. > > But the downside here is that the compiler won't be able to optimize away > repeated stores if they are transformed to memset calls. Maybe introduce some > threshold and only memset() sizes greater than, say, 64? (IIRC that's what > `-ftrivial-auto-var-init` does) TIL. Changed to keep using StoreInst when size <= 32, similar to `shouldUseBZeroPlusStoresToInitialize` `-ftrivial-auto-var-init`) https://github.com/llvm/llvm-project/pull/79924 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [flang] [libcxx] [clang] [llvm] [lld] [libcxxabi] [lldb] [libc] [msan] Unpoison indirect outputs for userspace using llvm.memset.* (PR #79924)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79924
>From 07043d27155ffd89e23b64c77a99880b2fa57e57 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Mon, 29 Jan 2024 17:02:18 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
.../Instrumentation/MemorySanitizer.cpp | 5 -
.../MemorySanitizer/msan_asm_conservative.ll | 16
2 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index 2b697557d8a92..0806d7a5b1452 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -4559,9 +4559,12 @@ struct MemorySanitizerVisitor : public
InstVisitor {
} else {
// ElemTy, derived from elementtype(), does not encode the alignment of
// the pointer. Conservatively assume that the shadow memory is
unaligned.
+ // Avoid StoreInst as SizeVal may be large, expanding to many
+ // instructions.
auto [ShadowPtr, _] =
getShadowOriginPtrUserspace(Operand, IRB, IRB.getInt8Ty(), Align(1));
- IRB.CreateAlignedStore(getCleanShadow(ElemTy), ShadowPtr, Align(1));
+ IRB.CreateMemSet(ShadowPtr, ConstantInt::getNullValue(IRB.getInt8Ty()),
+ SizeVal, Align(1));
}
}
diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_asm_conservative.ll
b/llvm/test/Instrumentation/MemorySanitizer/msan_asm_conservative.ll
index 894f76b9b8d32..86ca697ed9a4c 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/msan_asm_conservative.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/msan_asm_conservative.ll
@@ -177,8 +177,8 @@ entry:
}
; CHECK-LABEL: @f_2i_2o_mem
-; USER-CONS: store i32 0, ptr inttoptr (i64 xor (i64 ptrtoint (ptr @id1 to
i64), i64 87960930222080) to ptr), align 1
-; USER-CONS: store i32 0, ptr inttoptr (i64 xor (i64 ptrtoint (ptr @id2 to
i64), i64 87960930222080) to ptr), align 1
+; USER-CONS: call void @llvm.memset.p0.i64(ptr align 1 inttoptr (i64 xor (i64
ptrtoint (ptr @id1 to i64), i64 87960930222080) to ptr), i8 0, i64 4, i1 false)
+; USER-CONS: call void @llvm.memset.p0.i64(ptr align 1 inttoptr (i64 xor (i64
ptrtoint (ptr @id2 to i64), i64 87960930222080) to ptr), i8 0, i64 4, i1 false)
; CHECK-CONS: call void @__msan_instrument_asm_store({{.*}}@id1{{.*}}, i64 4)
; CHECK-CONS: call void @__msan_instrument_asm_store({{.*}}@id2{{.*}}, i64 4)
; CHECK: call void asm "", "=*m,=*m,*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr
elementtype(i32) @id1, ptr elementtype(i32) @id2, ptr elementtype(i32) @is1,
ptr elementtype(i32) @is2)
@@ -196,7 +196,7 @@ entry:
; CHECK-LABEL: @f_1i_1o_memreg
; CHECK: [[IS1_F7:%.*]] = load i32, ptr @is1, align 4
-; USER-CONS: store i32 0, ptr inttoptr (i64 xor (i64 ptrtoint (ptr @id1 to
i64), i64 87960930222080) to ptr), align 1
+; USER-CONS: call void @llvm.memset.p0.i64(ptr align 1 inttoptr (i64 xor (i64
ptrtoint (ptr @id1 to i64), i64 87960930222080) to ptr), i8 0, i64 4, i1 false)
; CHECK-CONS: call void @__msan_instrument_asm_store({{.*}}@id1{{.*}}, i64 4)
; CHECK: call void @__msan_warning
; CHECK: call i32 asm "", "=r,=*m,r,*m,~{dirflag},~{fpsr},~{flags}"(ptr
elementtype(i32) @id1, i32 [[IS1_F7]], ptr elementtype(i32) @is1)
@@ -215,7 +215,7 @@ entry:
}
; CHECK-LABEL: @f_3o_reg_mem_reg
-; USER-CONS: store i32 0, ptr inttoptr (i64 xor (i64 ptrtoint (ptr @id2 to
i64), i64 87960930222080) to ptr), align 1
+; USER-CONS: call void @llvm.memset.p0.i64(ptr align 1 inttoptr (i64 xor (i64
ptrtoint (ptr @id2 to i64), i64 87960930222080) to ptr), i8 0, i64 4, i1 false)
; CHECK-CONS: call void @__msan_instrument_asm_store(ptr @id2, i64 4)
; CHECK: call { i32, i32 } asm "", "=r,=*m,=r,~{dirflag},~{fpsr},~{flags}"(ptr
elementtype(i32) @id2)
@@ -240,7 +240,7 @@ entry:
; CHECK: [[PAIR1_F9:%.*]] = load {{.*}} @pair1
; CHECK: [[C1_F9:%.*]] = load {{.*}} @c1
; CHECK: [[MEMCPY_S1_F9:%.*]] = load {{.*}} @memcpy_s1
-; USER-CONS: store { i32, i32 } zeroinitializer, ptr inttoptr (i64 xor (i64
ptrtoint (ptr @pair2 to i64), i64 87960930222080) to ptr), align 1
+; USER-CONS: call void @llvm.memset.p0.i64(ptr align 1 inttoptr (i64 xor (i64
ptrtoint (ptr @pair2 to i64), i64 87960930222080) to ptr), i8 0, i64 8, i1
false)
; CHECK-CONS: call void @__msan_instrument_asm_store({{.*}}@pair2{{.*}}, i64 8)
; CHECK: call void @__msan_warning
; KMSAN: call void @__msan_warning
@@ -257,9 +257,9 @@ entry:
}
; CHECK-LABEL: @f_3i_3o_complex_mem
-; USER-CONS: store { i32, i32 } zeroinitializer, ptr inttoptr (i64 xor
(i64 ptrtoint (ptr @pair2 to i64), i64 87960930222080) to ptr), align 1
-; USER-CONS-NEXT: store i8 0, ptr inttoptr (i64 xor (i64 ptrtoint (ptr @c2
[Lldb-commits] [libc] [lldb] [libcxxabi] [llvm] [lld] [libcxx] [clang] [flang] [msan] Unpoison indirect outputs for userspace using llvm.memset.* (PR #79924)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79924 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [libcxx] [lldb] [flang] [clang] [clang-tools-extra] [libc] [llvm] [compiler-rt] [llvm-cov] Simplify and optimize MC/DC computation (PR #79727)
https://github.com/MaskRay closed https://github.com/llvm/llvm-project/pull/79727 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [clang] [compiler-rt] [libc] [libcxx] [flang] [clang-tools-extra] [llvm] [llvm-cov] Simplify and optimize MC/DC computation (PR #79727)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79727 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [clang] [compiler-rt] [libc] [libcxx] [flang] [clang-tools-extra] [llvm] [llvm-cov] Simplify and optimize MC/DC computation (PR #79727)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79727 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [clang] [compiler-rt] [libc] [libcxx] [flang] [clang-tools-extra] [llvm] [llvm-cov] Simplify and optimize MC/DC computation (PR #79727)
@@ -353,71 +331,30 @@ class MCDCRecordProcessor {
}
}
- /// For a given condition and two executed Test Vectors, A and B, see if the
- /// two test vectors match forming an Independence Pair for the condition.
- /// For two test vectors to match, the following must be satisfied:
- /// - The condition's value in each test vector must be opposite.
- /// - The result's value in each test vector must be opposite.
- /// - All other conditions' values must be equal or marked as "don't care".
- bool matchTestVectors(unsigned Aidx, unsigned Bidx, unsigned ConditionIdx) {
-const MCDCRecord::TestVector &A = ExecVectors[Aidx];
-const MCDCRecord::TestVector &B = ExecVectors[Bidx];
-
-// If condition values in both A and B aren't opposites, no match.
-// Because a value can be 0 (false), 1 (true), or -1 (DontCare), a check
-// that "XOR != 1" will ensure that the values are opposites and that
-// neither of them is a DontCare.
-// 1 XOR 0 == 1 | 0 XOR 0 == 0 | -1 XOR 0 == -1
-// 1 XOR 1 == 0 | 0 XOR 1 == 1 | -1 XOR 1 == -2
-// 1 XOR -1 == -2 | 0 XOR -1 == -1 | -1 XOR -1 == 0
-if ((A[ConditionIdx] ^ B[ConditionIdx]) != 1)
- return false;
-
-// If the results of both A and B aren't opposites, no match.
-if ((A[NumConditions] ^ B[NumConditions]) != 1)
- return false;
-
-for (unsigned Idx = 0; Idx < NumConditions; ++Idx) {
- // Look for other conditions that don't match. Skip over the given
- // Condition as well as any conditions marked as "don't care".
- const auto ARecordTyForCond = A[Idx];
- const auto BRecordTyForCond = B[Idx];
- if (Idx == ConditionIdx ||
- ARecordTyForCond == MCDCRecord::MCDC_DontCare ||
- BRecordTyForCond == MCDCRecord::MCDC_DontCare)
-continue;
-
- // If there is a condition mismatch with any of the other conditions,
- // there is no match for the test vectors.
- if (ARecordTyForCond != BRecordTyForCond)
-return false;
-}
-
-// Otherwise, match.
-return true;
- }
-
- /// Find all possible Independence Pairs for a boolean expression given its
- /// executed Test Vectors. This process involves looking at each condition
- /// and attempting to find two Test Vectors that "match", giving us a pair.
+ // Find an independence pair for each condition.
void findIndependencePairs() {
unsigned NumTVs = ExecVectors.size();
-
-// For each condition.
-for (unsigned C = 0; C < NumConditions; ++C) {
- bool PairFound = false;
-
- // For each executed test vector.
- for (unsigned I = 0; !PairFound && I < NumTVs; ++I) {
-// Compared to every other executed test vector.
-for (unsigned J = 0; !PairFound && J < NumTVs; ++J) {
- if (I == J)
+for (unsigned I = 1; I < NumTVs; ++I) {
+ const MCDCRecord::TestVector &A = ExecVectors[I];
+ for (unsigned J = 0; J < I; ++J) {
+const MCDCRecord::TestVector &B = ExecVectors[J];
+// Enumerate two execution vectors whose outcomes are different.
+if (A[NumConditions] == B[NumConditions])
+ continue;
+unsigned Flip = NumConditions, Idx;
+for (Idx = 0; Idx < NumConditions; ++Idx) {
+ MCDCRecord::CondState ACond = A[Idx], BCond = B[Idx];
+ if (ACond == BCond || ACond == MCDCRecord::MCDC_DontCare ||
+ BCond == MCDCRecord::MCDC_DontCare)
continue;
-
- // If a matching pair of vectors is found, record them.
- if ((PairFound = matchTestVectors(I, J, C)))
-IndependencePairs[C] = std::make_pair(I + 1, J + 1);
+ if (Flip != NumConditions)
+break;
+ Flip = Idx;
}
MaskRay wrote:
I left some notes on
https://maskray.me/blog/2024-01-28-mc-dc-and-compiler-implementations
GCC has a pending patch implementing MC/DC as well and they apply an algorithm
described by _Efficient Test Coverage Measurement for MC/DC_, which is linear
in terms of the number of conditions.
https://github.com/llvm/llvm-project/pull/79727
___
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lldb-commits@lists.llvm.org
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[Lldb-commits] [lldb] [clang] [compiler-rt] [libc] [libcxx] [flang] [clang-tools-extra] [llvm] [llvm-cov] Simplify and optimize MC/DC computation (PR #79727)
@@ -458,7 +395,7 @@ class MCDCRecordProcessor {
MCDCRecord::TestVector TV(NumConditions, MCDCRecord::MCDC_DontCare);
// Use the base test vector to build the list of all possible test vectors.
-buildTestVector(TV);
+buildTestVector(TV, 1, 0);
MaskRay wrote:
Thanks for the suggestion. Added
https://github.com/llvm/llvm-project/pull/79727
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [clang] [compiler-rt] [libc] [libcxx] [flang] [clang-tools-extra] [llvm] [llvm-cov] Simplify and optimize MC/DC computation (PR #79727)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79727
>From 1d2470c2d67673f9ef9ea504e0abb3e964d43ebb Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Sat, 27 Jan 2024 22:24:39 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
.../ProfileData/Coverage/CoverageMapping.cpp | 133 +-
1 file changed, 35 insertions(+), 98 deletions(-)
diff --git a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
index da8e1d87319dded..16a45d1788236a0 100644
--- a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
+++ b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
@@ -286,17 +286,8 @@ class MCDCRecordProcessor {
TestVectors((size_t)1 << NumConditions) {}
private:
- void recordTestVector(MCDCRecord::TestVector &TV,
+ void recordTestVector(MCDCRecord::TestVector &TV, unsigned Index,
MCDCRecord::CondState Result) {
-// Calculate an index that is used to identify the test vector in a vector
-// of test vectors. This index also corresponds to the index values of an
-// MCDC Region's bitmap (see findExecutedTestVectors()).
-unsigned Index = 0;
-for (auto Cond = std::rbegin(TV); Cond != std::rend(TV); ++Cond) {
- Index <<= 1;
- Index |= (*Cond == MCDCRecord::MCDC_True) ? 0x1 : 0x0;
-}
-
// Copy the completed test vector to the vector of testvectors.
TestVectors[Index] = TV;
@@ -305,38 +296,25 @@ class MCDCRecordProcessor {
TestVectors[Index].push_back(Result);
}
- void shouldCopyOffTestVectorForTruePath(MCDCRecord::TestVector &TV,
- unsigned ID) {
-// Branch regions are hashed based on an ID.
-const CounterMappingRegion *Branch = Map[ID];
-
-TV[ID - 1] = MCDCRecord::MCDC_True;
-if (Branch->MCDCParams.TrueID > 0)
- buildTestVector(TV, Branch->MCDCParams.TrueID);
-else
- recordTestVector(TV, MCDCRecord::MCDC_True);
- }
-
- void shouldCopyOffTestVectorForFalsePath(MCDCRecord::TestVector &TV,
- unsigned ID) {
-// Branch regions are hashed based on an ID.
+ // Walk the binary decision tree and try assigning both false and true to
each
+ // node. When a terminal node (ID == 0) is reached, fill in the value in the
+ // truth table.
+ void buildTestVector(MCDCRecord::TestVector &TV, unsigned ID,
+ unsigned Index) {
const CounterMappingRegion *Branch = Map[ID];
TV[ID - 1] = MCDCRecord::MCDC_False;
if (Branch->MCDCParams.FalseID > 0)
- buildTestVector(TV, Branch->MCDCParams.FalseID);
+ buildTestVector(TV, Branch->MCDCParams.FalseID, Index);
else
- recordTestVector(TV, MCDCRecord::MCDC_False);
- }
+ recordTestVector(TV, Index, MCDCRecord::MCDC_False);
- /// Starting with the base test vector, build a comprehensive list of
- /// possible test vectors by recursively walking the branch condition IDs
- /// provided. Once an end node is reached, record the test vector in a vector
- /// of test vectors that can be matched against during MC/DC analysis, and
- /// then reset the positions to 'DontCare'.
- void buildTestVector(MCDCRecord::TestVector &TV, unsigned ID = 1) {
-shouldCopyOffTestVectorForTruePath(TV, ID);
-shouldCopyOffTestVectorForFalsePath(TV, ID);
+Index |= 1 << (ID - 1);
+TV[ID - 1] = MCDCRecord::MCDC_True;
+if (Branch->MCDCParams.TrueID > 0)
+ buildTestVector(TV, Branch->MCDCParams.TrueID, Index);
+else
+ recordTestVector(TV, Index, MCDCRecord::MCDC_True);
// Reset back to DontCare.
TV[ID - 1] = MCDCRecord::MCDC_DontCare;
@@ -353,71 +331,30 @@ class MCDCRecordProcessor {
}
}
- /// For a given condition and two executed Test Vectors, A and B, see if the
- /// two test vectors match forming an Independence Pair for the condition.
- /// For two test vectors to match, the following must be satisfied:
- /// - The condition's value in each test vector must be opposite.
- /// - The result's value in each test vector must be opposite.
- /// - All other conditions' values must be equal or marked as "don't care".
- bool matchTestVectors(unsigned Aidx, unsigned Bidx, unsigned ConditionIdx) {
-const MCDCRecord::TestVector &A = ExecVectors[Aidx];
-const MCDCRecord::TestVector &B = ExecVectors[Bidx];
-
-// If condition values in both A and B aren't opposites, no match.
-// Because a value can be 0 (false), 1 (true), or -1 (DontCare), a check
-// that "XOR != 1" will ensure that the values are opposites and that
-// neither of them is a DontCare.
-// 1 XOR 0 == 1 | 0 XOR 0 == 0 | -1 XOR 0 == -1
-// 1 XOR 1 == 0 | 0 XOR 1 == 1 | -1 XOR 1 == -2
-// 1 XOR -1 == -2 | 0 XOR -1 =
[Lldb-commits] [compiler-rt] [flang] [clang] [lldb] [clang-tools-extra] [llvm] [libcxx] [libc] [llvm-cov] Simplify and optimize MC/DC computation (PR #79727)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79727 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [compiler-rt] [lldb] [clang] [mlir] [libcxx] [clang-tools-extra] [libc] [lld] [libunwind] [flang] [llvm] [Driver, CodeGen] Support -mtls-dialect= (PR #79256)
https://github.com/MaskRay closed https://github.com/llvm/llvm-project/pull/79256 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang-tools-extra] [llvm] [libc] [clang] [libcxx] [lldb] [lld] [libunwind] [flang] [mlir] [compiler-rt] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay closed https://github.com/llvm/llvm-project/pull/79239 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [flang] [clang] [libunwind] [libc] [mlir] [compiler-rt] [lld] [clang-tools-extra] [llvm] [lldb] [libcxx] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
MaskRay wrote: """ This branch is out-of-date with the base branch Merge the latest changes from main into this branch. This merge commit will be associated with ... """ Hmm. rebase + `spr diff` cannot fix it. I'll merge this manually. https://github.com/llvm/llvm-project/pull/79239 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [flang] [clang] [libunwind] [libc] [mlir] [compiler-rt] [lld] [clang-tools-extra] [llvm] [lldb] [libcxx] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79239
>From 3725fa4eac3d3d946289d7eb7213f3a1751a2770 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:58:07 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp| 158 +
lld/ELF/Relocations.cpp | 25 ++--
lld/test/ELF/riscv-tlsdesc-gd-mixed.s | 26
lld/test/ELF/riscv-tlsdesc-relax.s| 125 +
lld/test/ELF/riscv-tlsdesc.s | 192 ++
5 files changed, 492 insertions(+), 34 deletions(-)
create mode 100644 lld/test/ELF/riscv-tlsdesc-gd-mixed.s
create mode 100644 lld/test/ELF/riscv-tlsdesc-relax.s
create mode 100644 lld/test/ELF/riscv-tlsdesc.s
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index d7d3d3e47814971..67d7e2562e9b178 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -61,6 +61,7 @@ enum Op {
AUIPC = 0x17,
JALR = 0x67,
LD = 0x3003,
+ LUI = 0x37,
LW = 0x2003,
SRLI = 0x5013,
SUB = 0x4033,
@@ -73,6 +74,7 @@ enum Reg {
X_T0 = 5,
X_T1 = 6,
X_T2 = 7,
+ X_A0 = 10,
X_T3 = 28,
};
@@ -102,6 +104,26 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
(extractBits(imm, 4, 0) << 7);
}
+namespace {
+struct SymbolAnchor {
+ uint64_t offset;
+ Defined *d;
+ bool end; // true for the anchor of st_value+st_size
+};
+} // namespace
+
+struct elf::RISCVRelaxAux {
+ // This records symbol start and end offsets which will be adjusted according
+ // to the nearest relocDeltas element.
+ SmallVector anchors;
+ // For relocations[i], the actual offset is r_offset - (i ? relocDeltas[i-1]
:
+ // 0).
+ std::unique_ptr relocDeltas;
+ // For relocations[i], the actual type is relocTypes[i].
+ std::unique_ptr relocTypes;
+ SmallVector writes;
+};
+
RISCV::RISCV() {
copyRel = R_RISCV_COPY;
pltRel = R_RISCV_JUMP_SLOT;
@@ -119,6 +141,7 @@ RISCV::RISCV() {
tlsGotRel = R_RISCV_TLS_TPREL32;
}
gotRel = symbolicRel;
+ tlsDescRel = R_RISCV_TLSDESC;
// .got[0] = _DYNAMIC
gotHeaderEntriesNum = 1;
@@ -187,6 +210,8 @@ int64_t RISCV::getImplicitAddend(const uint8_t *buf,
RelType type) const {
case R_RISCV_JUMP_SLOT:
// These relocations are defined as not having an implicit addend.
return 0;
+ case R_RISCV_TLSDESC:
+return config->is64 ? read64le(buf + 8) : read32le(buf + 4);
}
}
@@ -295,6 +320,12 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol
&s,
case R_RISCV_PCREL_LO12_I:
case R_RISCV_PCREL_LO12_S:
return R_RISCV_PC_INDIRECT;
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
+return R_TLSDESC_PC;
+ case R_RISCV_TLSDESC_CALL:
+return R_TLSDESC_CALL;
case R_RISCV_TLS_GD_HI20:
return R_TLSGD_PC;
case R_RISCV_TLS_GOT_HI20:
@@ -419,6 +450,7 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
case R_RISCV_GOT_HI20:
case R_RISCV_PCREL_HI20:
+ case R_RISCV_TLSDESC_HI20:
case R_RISCV_TLS_GD_HI20:
case R_RISCV_TLS_GOT_HI20:
case R_RISCV_TPREL_HI20:
@@ -430,6 +462,8 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
}
case R_RISCV_PCREL_LO12_I:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
case R_RISCV_TPREL_LO12_I:
case R_RISCV_LO12_I: {
uint64_t hi = (val + 0x800) >> 12;
@@ -513,29 +547,113 @@ void RISCV::relocate(uint8_t *loc, const Relocation
&rel, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE relaxation");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC
[Lldb-commits] [clang] [clang-tools-extra] [lldb] [libc] [libcxx] [lld] [llvm] [flang] [compiler-rt] Make clang report invalid target versions for all environment types. (PR #78655)
@@ -276,7 +276,7 @@ class Triple {
Callable,
Mesh,
Amplification,
-
+OpenCL,
MaskRay wrote:
I wonder why we need this addition. This is not mentioned in the description.
https://github.com/llvm/llvm-project/pull/78655
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [libc] [lld] [flang] [libcxx] [clang] [clang-tools-extra] [compiler-rt] [llvm] [lldb] Make clang report invalid target versions for all environment types. (PR #78655)
@@ -255,7 +255,7 @@ class Triple {
Cygnus,
CoreCLR,
Simulator, // Simulator variants of other systems, e.g., Apple's iOS
-MacABI, // Mac Catalyst variant of Apple's iOS deployment target.
+MacABI,// Mac Catalyst variant of Apple's iOS deployment target.
MaskRay wrote:
Revert this difference? You can ignore clang-format reports.
https://github.com/llvm/llvm-project/pull/78655
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [lld] [llvm] [libc] [flang] [libcxx] [compiler-rt] [clang-tools-extra] [lldb] Make clang report invalid target versions for all environment types. (PR #78655)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/78655 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [lld] [llvm] [libc] [flang] [libcxx] [compiler-rt] [clang-tools-extra] [lldb] Make clang report invalid target versions for all environment types. (PR #78655)
@@ -1443,15 +1443,17 @@ Compilation *Driver::BuildCompilation(ArrayRef ArgList) {
const ToolChain &TC = getToolChain(
*UArgs, computeTargetTriple(*this, TargetTriple, *UArgs));
- if (TC.getTriple().isAndroid()) {
-llvm::Triple Triple = TC.getTriple();
-StringRef TripleVersionName = Triple.getEnvironmentVersionString();
-
-if (Triple.getEnvironmentVersion().empty() && TripleVersionName != "") {
- Diags.Report(diag::err_drv_triple_version_invalid)
- << TripleVersionName << TC.getTripleString();
- ContainsError = true;
-}
+ // Check if the environment version is valid.
+ llvm::Triple Triple = TC.getTriple();
+ StringRef TripleVersionName = Triple.getEnvironmentVersionString();
+ StringRef TripleObjectFormat =
+ Triple.getObjectFormatTypeName(Triple.getObjectFormat());
+
MaskRay wrote:
(the prevailing code style does not insert a blank line in this case. )
https://github.com/llvm/llvm-project/pull/78655
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
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[Lldb-commits] [lldb] [mlir] [libcxx] [lld] [flang] [libc] [clang] [llvm] [libunwind] [clang-tools-extra] [compiler-rt] [Driver, CodeGen] Support -mtls-dialect= (PR #79256)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79256
>From be08e64c2c1f433b017185ce78525ad097e609be Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 21:37:04 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
clang/include/clang/Basic/CodeGenOptions.def | 3 +++
clang/include/clang/Driver/Options.td| 5 +
clang/lib/CodeGen/BackendUtil.cpp| 1 +
clang/lib/Driver/ToolChains/Clang.cpp| 23
clang/test/CodeGen/RISCV/tls-dialect.c | 13 +++
clang/test/Driver/tls-dialect.c | 19
6 files changed, 64 insertions(+)
create mode 100644 clang/test/CodeGen/RISCV/tls-dialect.c
create mode 100644 clang/test/Driver/tls-dialect.c
diff --git a/clang/include/clang/Basic/CodeGenOptions.def
b/clang/include/clang/Basic/CodeGenOptions.def
index 2f2e45d5cf63df..7c0bfe32849614 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -369,6 +369,9 @@ ENUM_CODEGENOPT(VecLib, llvm::driver::VectorLibrary, 3,
llvm::driver::VectorLibr
/// The default TLS model to use.
ENUM_CODEGENOPT(DefaultTLSModel, TLSModel, 2, GeneralDynamicTLSModel)
+/// Whether to enable TLSDESC. AArch64 enables TLSDESC regardless of this
value.
+CODEGENOPT(EnableTLSDESC, 1, 0)
+
/// Bit size of immediate TLS offsets (0 == use the default).
VALUE_CODEGENOPT(TLSSize, 8, 0)
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 7f4fa33748faca..773bc1dcda01d5 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4419,6 +4419,8 @@ def mtls_size_EQ : Joined<["-"], "mtls-size=">,
Group,
HelpText<"Specify bit size of immediate TLS offsets (AArch64 ELF only): "
"12 (for 4KB) | 24 (for 16MB, default) | 32 (for 4GB) | 48 (for
256TB, needs -mcmodel=large)">,
MarshallingInfoInt>;
+def mtls_dialect_EQ : Joined<["-"], "mtls-dialect=">, Group,
+ Flags<[TargetSpecific]>, HelpText<"Which thread-local storage dialect to use
for dynamic accesses of TLS variables">;
def mimplicit_it_EQ : Joined<["-"], "mimplicit-it=">, Group;
def mdefault_build_attributes : Joined<["-"], "mdefault-build-attributes">,
Group;
def mno_default_build_attributes : Joined<["-"],
"mno-default-build-attributes">, Group;
@@ -7066,6 +7068,9 @@ def fexperimental_assignment_tracking_EQ : Joined<["-"],
"fexperimental-assignme
Values<"disabled,enabled,forced">,
NormalizedValues<["Disabled","Enabled","Forced"]>,
MarshallingInfoEnum, "Enabled">;
+def enable_tlsdesc : Flag<["-"], "enable-tlsdesc">,
+ MarshallingInfoFlag>;
+
} // let Visibility = [CC1Option]
//===--===//
diff --git a/clang/lib/CodeGen/BackendUtil.cpp
b/clang/lib/CodeGen/BackendUtil.cpp
index ec203f6f28bc17..7877e20d77f772 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -401,6 +401,7 @@ static bool initTargetOptions(DiagnosticsEngine &Diags,
Options.UniqueBasicBlockSectionNames =
CodeGenOpts.UniqueBasicBlockSectionNames;
Options.TLSSize = CodeGenOpts.TLSSize;
+ Options.EnableTLSDESC = CodeGenOpts.EnableTLSDESC;
Options.EmulatedTLS = CodeGenOpts.EmulatedTLS;
Options.DebuggerTuning = CodeGenOpts.getDebuggerTuning();
Options.EmitStackSizeSection = CodeGenOpts.StackSizeSection;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index 5dc614e11aab59..93fd579eb92ba5 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -5822,6 +5822,29 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
Args.AddLastArg(CmdArgs, options::OPT_mtls_size_EQ);
}
+ if (Arg *A = Args.getLastArg(options::OPT_mtls_dialect_EQ)) {
+StringRef V = A->getValue();
+bool SupportedArgument = false, EnableTLSDESC = false;
+bool Unsupported = !Triple.isOSBinFormatELF();
+if (Triple.isRISCV()) {
+ SupportedArgument = V == "desc" || V == "trad";
+ EnableTLSDESC = V == "desc";
+} else if (Triple.isX86()) {
+ SupportedArgument = V == "gnu";
+} else {
+ Unsupported = true;
+}
+if (Unsupported) {
+ D.Diag(diag::err_drv_unsupported_opt_for_target)
+ << A->getSpelling() << TripleStr;
+} else if (!SupportedArgument) {
+ D.Diag(diag::err_drv_unsupported_option_argument_for_target)
+ << A->getSpelling() << V << TripleStr;
+} else if (EnableTLSDESC) {
+ CmdArgs.push_back("-enable-tlsdesc");
+}
+ }
+
// Add the target cpu
std::string CPU = getCPUName(D, Args, Triple, /*FromAs*/ false);
if (!CPU.empty()) {
diff --git a/clang/test/CodeGen/RISCV
[Lldb-commits] [compiler-rt] [flang] [libcxx] [libunwind] [clang] [llvm] [clang-tools-extra] [lldb] [mlir] [libc] [lld] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79239
>From 3725fa4eac3d3d946289d7eb7213f3a1751a2770 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:58:07 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp| 158 +
lld/ELF/Relocations.cpp | 25 ++--
lld/test/ELF/riscv-tlsdesc-gd-mixed.s | 26
lld/test/ELF/riscv-tlsdesc-relax.s| 125 +
lld/test/ELF/riscv-tlsdesc.s | 192 ++
5 files changed, 492 insertions(+), 34 deletions(-)
create mode 100644 lld/test/ELF/riscv-tlsdesc-gd-mixed.s
create mode 100644 lld/test/ELF/riscv-tlsdesc-relax.s
create mode 100644 lld/test/ELF/riscv-tlsdesc.s
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index d7d3d3e4781497..67d7e2562e9b17 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -61,6 +61,7 @@ enum Op {
AUIPC = 0x17,
JALR = 0x67,
LD = 0x3003,
+ LUI = 0x37,
LW = 0x2003,
SRLI = 0x5013,
SUB = 0x4033,
@@ -73,6 +74,7 @@ enum Reg {
X_T0 = 5,
X_T1 = 6,
X_T2 = 7,
+ X_A0 = 10,
X_T3 = 28,
};
@@ -102,6 +104,26 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
(extractBits(imm, 4, 0) << 7);
}
+namespace {
+struct SymbolAnchor {
+ uint64_t offset;
+ Defined *d;
+ bool end; // true for the anchor of st_value+st_size
+};
+} // namespace
+
+struct elf::RISCVRelaxAux {
+ // This records symbol start and end offsets which will be adjusted according
+ // to the nearest relocDeltas element.
+ SmallVector anchors;
+ // For relocations[i], the actual offset is r_offset - (i ? relocDeltas[i-1]
:
+ // 0).
+ std::unique_ptr relocDeltas;
+ // For relocations[i], the actual type is relocTypes[i].
+ std::unique_ptr relocTypes;
+ SmallVector writes;
+};
+
RISCV::RISCV() {
copyRel = R_RISCV_COPY;
pltRel = R_RISCV_JUMP_SLOT;
@@ -119,6 +141,7 @@ RISCV::RISCV() {
tlsGotRel = R_RISCV_TLS_TPREL32;
}
gotRel = symbolicRel;
+ tlsDescRel = R_RISCV_TLSDESC;
// .got[0] = _DYNAMIC
gotHeaderEntriesNum = 1;
@@ -187,6 +210,8 @@ int64_t RISCV::getImplicitAddend(const uint8_t *buf,
RelType type) const {
case R_RISCV_JUMP_SLOT:
// These relocations are defined as not having an implicit addend.
return 0;
+ case R_RISCV_TLSDESC:
+return config->is64 ? read64le(buf + 8) : read32le(buf + 4);
}
}
@@ -295,6 +320,12 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol
&s,
case R_RISCV_PCREL_LO12_I:
case R_RISCV_PCREL_LO12_S:
return R_RISCV_PC_INDIRECT;
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
+return R_TLSDESC_PC;
+ case R_RISCV_TLSDESC_CALL:
+return R_TLSDESC_CALL;
case R_RISCV_TLS_GD_HI20:
return R_TLSGD_PC;
case R_RISCV_TLS_GOT_HI20:
@@ -419,6 +450,7 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
case R_RISCV_GOT_HI20:
case R_RISCV_PCREL_HI20:
+ case R_RISCV_TLSDESC_HI20:
case R_RISCV_TLS_GD_HI20:
case R_RISCV_TLS_GOT_HI20:
case R_RISCV_TPREL_HI20:
@@ -430,6 +462,8 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
}
case R_RISCV_PCREL_LO12_I:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
case R_RISCV_TPREL_LO12_I:
case R_RISCV_LO12_I: {
uint64_t hi = (val + 0x800) >> 12;
@@ -513,29 +547,113 @@ void RISCV::relocate(uint8_t *loc, const Relocation
&rel, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE relaxation");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_A
[Lldb-commits] [compiler-rt] [flang] [libcxx] [libunwind] [clang] [llvm] [clang-tools-extra] [lldb] [mlir] [libc] [lld] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
@@ -513,29 +547,125 @@ void RISCV::relocate(uint8_t *loc, const Relocation
&rel, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+break;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+break;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+break;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+if (isInt<12>(val))
+ write32le(loc, 0x0013); // nop
+else
+ write32le(loc, utype(LUI, X_A0, hi20(val))); // lui a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (isInt<12>(val))
+ write32le(loc, itype(ADDI, X_A0, 0, val)); // addi a0,zero,
+else
+ write32le(loc, itype(ADDI, X_A0, X_A0, lo12(val))); // addi a0,a0,
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to LE");
+ }
+}
+
void RISCV::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
uint64_t secAddr = sec.getOutputSection()->addr;
if (auto *s = dyn_cast(&sec))
secAddr += s->outSecOff;
else if (auto *ehIn = dyn_cast(&sec))
secAddr += ehIn->getParent()->outSecOff;
- for (size_t i = 0, size = sec.relocs().size(); i != size; ++i) {
-const Relocation &rel = sec.relocs()[i];
+ uint64_t tlsdescVal = 0;
+ bool isToLe = false;
+ const ArrayRef relocs = sec.relocs();
+ for (size_t i = 0, size = relocs.size(); i != size; ++i) {
+const Relocation &rel = relocs[i];
uint8_t *loc = buf + rel.offset;
-const uint64_t val =
+uint64_t val =
sec.getRelocTargetVA(sec.file, rel.type, rel.addend,
secAddr + rel.offset, *rel.sym, rel.expr);
switch (rel.expr) {
case R_RELAX_HINT:
+ continue;
+case R_TLSDESC_PC:
+ // For R_RISCV_TLSDESC_HI20, store &got(sym)-PC to be used by the
+ // following two instructions L[DW] and ADDI.
+ if (rel.type == R_RISCV_TLSDESC_HI20)
+tlsdescVal = val;
+ else
+val = tlsdescVal;
break;
+case R_RELAX_TLS_GD_TO_IE:
+ // Only R_RISCV_TLSDESC_HI20 reaches here. tlsdescVal will be finalized
+ // after we see R_RISCV_TLSDESC_ADD_LO12 in the R_RELAX_TLS_GD_TO_LE
case.
+ // The net effect is that tlsdescVal will be smaller than `val` to take
+ // into account of NOP instructions (in the absence of R_RISCV_RELAX)
+ // before AUIPC.
+ tlsdescVal = val + rel.offset;
+ isToLe = false;
+ if (!(i + 1 != relocs.size() && relocs[i + 1].type == R_RISCV_RELAX))
+tlsdescToIe(loc, rel, val);
+ continue;
+case R_RELAX_TLS_GD_TO_LE:
+ // See the comment in handleTlsRelocation. For TLSDESC=>IE,
+ // R_RISCV_TLSDESC_{LOAD_LO12,ADD_LO12,CALL} also reach here. If isToIe
is
+ // true, this is actually TLSDESC=>IE optimization.
+ if (rel.type == R_RISCV_TLSDESC_HI20) {
+tlsdescVal = val;
+isToLe = true;
+ } else {
+if (!isToLe && rel.type == R_RISCV_TLSDESC_ADD_LO12)
+ tlsdescVal -= rel.offset;
+val = tlsdescVal;
+ }
+ // When NOP conversion is eligible and R_RISCV_RELAX is present, don't
+ // write a NOP in case an unrelated instruction follows the current
+ // instruction.
+ if ((rel.type == R_RISCV_TLSDESC_HI20 ||
+ rel.type == R_RISCV_TLSDESC_LOAD_LO12 ||
+ (rel.type == R_RISCV_TLSDESC_ADD_LO12 && isToLe && !hi20(val))) &&
+ i + 1 != relocs.size() && relocs[i + 1].type == R_RISCV_RELAX)
MaskRay wrote:
> That sounds like a nice approach.
Thanks. Adopted this approach:)
> Noted. Should we bring this up with the psABI?
Filed https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/421
https://github.com/llvm/llvm-project/pull/79239
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [compiler-rt] [flang] [libcxx] [libunwind] [clang] [llvm] [clang-tools-extra] [lldb] [mlir] [libc] [lld] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79239
>From 3725fa4eac3d3d946289d7eb7213f3a1751a2770 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:58:07 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp| 158 +
lld/ELF/Relocations.cpp | 25 ++--
lld/test/ELF/riscv-tlsdesc-gd-mixed.s | 26
lld/test/ELF/riscv-tlsdesc-relax.s| 125 +
lld/test/ELF/riscv-tlsdesc.s | 192 ++
5 files changed, 492 insertions(+), 34 deletions(-)
create mode 100644 lld/test/ELF/riscv-tlsdesc-gd-mixed.s
create mode 100644 lld/test/ELF/riscv-tlsdesc-relax.s
create mode 100644 lld/test/ELF/riscv-tlsdesc.s
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index d7d3d3e47814971..67d7e2562e9b178 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -61,6 +61,7 @@ enum Op {
AUIPC = 0x17,
JALR = 0x67,
LD = 0x3003,
+ LUI = 0x37,
LW = 0x2003,
SRLI = 0x5013,
SUB = 0x4033,
@@ -73,6 +74,7 @@ enum Reg {
X_T0 = 5,
X_T1 = 6,
X_T2 = 7,
+ X_A0 = 10,
X_T3 = 28,
};
@@ -102,6 +104,26 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
(extractBits(imm, 4, 0) << 7);
}
+namespace {
+struct SymbolAnchor {
+ uint64_t offset;
+ Defined *d;
+ bool end; // true for the anchor of st_value+st_size
+};
+} // namespace
+
+struct elf::RISCVRelaxAux {
+ // This records symbol start and end offsets which will be adjusted according
+ // to the nearest relocDeltas element.
+ SmallVector anchors;
+ // For relocations[i], the actual offset is r_offset - (i ? relocDeltas[i-1]
:
+ // 0).
+ std::unique_ptr relocDeltas;
+ // For relocations[i], the actual type is relocTypes[i].
+ std::unique_ptr relocTypes;
+ SmallVector writes;
+};
+
RISCV::RISCV() {
copyRel = R_RISCV_COPY;
pltRel = R_RISCV_JUMP_SLOT;
@@ -119,6 +141,7 @@ RISCV::RISCV() {
tlsGotRel = R_RISCV_TLS_TPREL32;
}
gotRel = symbolicRel;
+ tlsDescRel = R_RISCV_TLSDESC;
// .got[0] = _DYNAMIC
gotHeaderEntriesNum = 1;
@@ -187,6 +210,8 @@ int64_t RISCV::getImplicitAddend(const uint8_t *buf,
RelType type) const {
case R_RISCV_JUMP_SLOT:
// These relocations are defined as not having an implicit addend.
return 0;
+ case R_RISCV_TLSDESC:
+return config->is64 ? read64le(buf + 8) : read32le(buf + 4);
}
}
@@ -295,6 +320,12 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol
&s,
case R_RISCV_PCREL_LO12_I:
case R_RISCV_PCREL_LO12_S:
return R_RISCV_PC_INDIRECT;
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
+return R_TLSDESC_PC;
+ case R_RISCV_TLSDESC_CALL:
+return R_TLSDESC_CALL;
case R_RISCV_TLS_GD_HI20:
return R_TLSGD_PC;
case R_RISCV_TLS_GOT_HI20:
@@ -419,6 +450,7 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
case R_RISCV_GOT_HI20:
case R_RISCV_PCREL_HI20:
+ case R_RISCV_TLSDESC_HI20:
case R_RISCV_TLS_GD_HI20:
case R_RISCV_TLS_GOT_HI20:
case R_RISCV_TPREL_HI20:
@@ -430,6 +462,8 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
}
case R_RISCV_PCREL_LO12_I:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
case R_RISCV_TPREL_LO12_I:
case R_RISCV_LO12_I: {
uint64_t hi = (val + 0x800) >> 12;
@@ -513,29 +547,113 @@ void RISCV::relocate(uint8_t *loc, const Relocation
&rel, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE relaxation");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC
[Lldb-commits] [compiler-rt] [flang] [libcxx] [libunwind] [clang] [llvm] [clang-tools-extra] [lldb] [mlir] [libc] [lld] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79239
>From 3725fa4eac3d3d946289d7eb7213f3a1751a2770 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:58:07 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp| 158 +
lld/ELF/Relocations.cpp | 25 ++--
lld/test/ELF/riscv-tlsdesc-gd-mixed.s | 26
lld/test/ELF/riscv-tlsdesc-relax.s| 125 +
lld/test/ELF/riscv-tlsdesc.s | 192 ++
5 files changed, 492 insertions(+), 34 deletions(-)
create mode 100644 lld/test/ELF/riscv-tlsdesc-gd-mixed.s
create mode 100644 lld/test/ELF/riscv-tlsdesc-relax.s
create mode 100644 lld/test/ELF/riscv-tlsdesc.s
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index d7d3d3e47814971..67d7e2562e9b178 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -61,6 +61,7 @@ enum Op {
AUIPC = 0x17,
JALR = 0x67,
LD = 0x3003,
+ LUI = 0x37,
LW = 0x2003,
SRLI = 0x5013,
SUB = 0x4033,
@@ -73,6 +74,7 @@ enum Reg {
X_T0 = 5,
X_T1 = 6,
X_T2 = 7,
+ X_A0 = 10,
X_T3 = 28,
};
@@ -102,6 +104,26 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
(extractBits(imm, 4, 0) << 7);
}
+namespace {
+struct SymbolAnchor {
+ uint64_t offset;
+ Defined *d;
+ bool end; // true for the anchor of st_value+st_size
+};
+} // namespace
+
+struct elf::RISCVRelaxAux {
+ // This records symbol start and end offsets which will be adjusted according
+ // to the nearest relocDeltas element.
+ SmallVector anchors;
+ // For relocations[i], the actual offset is r_offset - (i ? relocDeltas[i-1]
:
+ // 0).
+ std::unique_ptr relocDeltas;
+ // For relocations[i], the actual type is relocTypes[i].
+ std::unique_ptr relocTypes;
+ SmallVector writes;
+};
+
RISCV::RISCV() {
copyRel = R_RISCV_COPY;
pltRel = R_RISCV_JUMP_SLOT;
@@ -119,6 +141,7 @@ RISCV::RISCV() {
tlsGotRel = R_RISCV_TLS_TPREL32;
}
gotRel = symbolicRel;
+ tlsDescRel = R_RISCV_TLSDESC;
// .got[0] = _DYNAMIC
gotHeaderEntriesNum = 1;
@@ -187,6 +210,8 @@ int64_t RISCV::getImplicitAddend(const uint8_t *buf,
RelType type) const {
case R_RISCV_JUMP_SLOT:
// These relocations are defined as not having an implicit addend.
return 0;
+ case R_RISCV_TLSDESC:
+return config->is64 ? read64le(buf + 8) : read32le(buf + 4);
}
}
@@ -295,6 +320,12 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol
&s,
case R_RISCV_PCREL_LO12_I:
case R_RISCV_PCREL_LO12_S:
return R_RISCV_PC_INDIRECT;
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
+return R_TLSDESC_PC;
+ case R_RISCV_TLSDESC_CALL:
+return R_TLSDESC_CALL;
case R_RISCV_TLS_GD_HI20:
return R_TLSGD_PC;
case R_RISCV_TLS_GOT_HI20:
@@ -419,6 +450,7 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
case R_RISCV_GOT_HI20:
case R_RISCV_PCREL_HI20:
+ case R_RISCV_TLSDESC_HI20:
case R_RISCV_TLS_GD_HI20:
case R_RISCV_TLS_GOT_HI20:
case R_RISCV_TPREL_HI20:
@@ -430,6 +462,8 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
}
case R_RISCV_PCREL_LO12_I:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
case R_RISCV_TPREL_LO12_I:
case R_RISCV_LO12_I: {
uint64_t hi = (val + 0x800) >> 12;
@@ -513,29 +547,113 @@ void RISCV::relocate(uint8_t *loc, const Relocation
&rel, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE relaxation");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD
[Lldb-commits] [lld] [clang] [clang-tools-extra] [libunwind] [compiler-rt] [libc] [lldb] [llvm] [libcxx] [mlir] [flang] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79239 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [lldb] [libunwind] [libcxx] [compiler-rt] [libc] [flang] [lld] [llvm] [clang-tools-extra] [mlir] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
@@ -513,29 +547,125 @@ void RISCV::relocate(uint8_t *loc, const Relocation
&rel, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+break;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+break;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+break;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+if (isInt<12>(val))
+ write32le(loc, 0x0013); // nop
+else
+ write32le(loc, utype(LUI, X_A0, hi20(val))); // lui a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (isInt<12>(val))
+ write32le(loc, itype(ADDI, X_A0, 0, val)); // addi a0,zero,
+else
+ write32le(loc, itype(ADDI, X_A0, X_A0, lo12(val))); // addi a0,a0,
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to LE");
+ }
+}
+
void RISCV::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
uint64_t secAddr = sec.getOutputSection()->addr;
if (auto *s = dyn_cast(&sec))
secAddr += s->outSecOff;
else if (auto *ehIn = dyn_cast(&sec))
secAddr += ehIn->getParent()->outSecOff;
- for (size_t i = 0, size = sec.relocs().size(); i != size; ++i) {
-const Relocation &rel = sec.relocs()[i];
+ uint64_t tlsdescVal = 0;
+ bool isToLe = false;
+ const ArrayRef relocs = sec.relocs();
+ for (size_t i = 0, size = relocs.size(); i != size; ++i) {
+const Relocation &rel = relocs[i];
uint8_t *loc = buf + rel.offset;
-const uint64_t val =
+uint64_t val =
sec.getRelocTargetVA(sec.file, rel.type, rel.addend,
secAddr + rel.offset, *rel.sym, rel.expr);
switch (rel.expr) {
case R_RELAX_HINT:
+ continue;
+case R_TLSDESC_PC:
+ // For R_RISCV_TLSDESC_HI20, store &got(sym)-PC to be used by the
+ // following two instructions L[DW] and ADDI.
+ if (rel.type == R_RISCV_TLSDESC_HI20)
+tlsdescVal = val;
+ else
+val = tlsdescVal;
break;
+case R_RELAX_TLS_GD_TO_IE:
+ // Only R_RISCV_TLSDESC_HI20 reaches here. tlsdescVal will be finalized
+ // after we see R_RISCV_TLSDESC_ADD_LO12 in the R_RELAX_TLS_GD_TO_LE
case.
+ // The net effect is that tlsdescVal will be smaller than `val` to take
+ // into account of NOP instructions (in the absence of R_RISCV_RELAX)
+ // before AUIPC.
+ tlsdescVal = val + rel.offset;
+ isToLe = false;
+ if (!(i + 1 != relocs.size() && relocs[i + 1].type == R_RISCV_RELAX))
+tlsdescToIe(loc, rel, val);
+ continue;
+case R_RELAX_TLS_GD_TO_LE:
+ // See the comment in handleTlsRelocation. For TLSDESC=>IE,
+ // R_RISCV_TLSDESC_{LOAD_LO12,ADD_LO12,CALL} also reach here. If isToIe
is
+ // true, this is actually TLSDESC=>IE optimization.
+ if (rel.type == R_RISCV_TLSDESC_HI20) {
+tlsdescVal = val;
+isToLe = true;
+ } else {
+if (!isToLe && rel.type == R_RISCV_TLSDESC_ADD_LO12)
+ tlsdescVal -= rel.offset;
+val = tlsdescVal;
+ }
+ // When NOP conversion is eligible and R_RISCV_RELAX is present, don't
+ // write a NOP in case an unrelated instruction follows the current
+ // instruction.
+ if ((rel.type == R_RISCV_TLSDESC_HI20 ||
+ rel.type == R_RISCV_TLSDESC_LOAD_LO12 ||
+ (rel.type == R_RISCV_TLSDESC_ADD_LO12 && isToLe && !hi20(val))) &&
+ i + 1 != relocs.size() && relocs[i + 1].type == R_RISCV_RELAX)
MaskRay wrote:
I am thinking of a simplification where I only check whether
R_RISCV_TLSDESC_HI20 has an associated R_RISCV_RELAX. If yes, apply relaxation
whether or not the following 3 instructions has an associated R_RISCV_RELAX.
Then, I just use another variable to hold "whether there is R_RISCV_RELAX" and
arguably the straight line code will be more readable than introducing a
function call.
On the LLVM side, relaxation can be enabled by adding R_RISCV_RELAX to just the
first instruction, decreasing the size bloat (sizeof(Elf6
[Lldb-commits] [mlir] [libunwind] [lld] [flang] [clang-tools-extra] [libc] [libcxx] [llvm] [clang] [compiler-rt] [lldb] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79239 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [mlir] [libunwind] [lld] [flang] [clang-tools-extra] [libc] [libcxx] [llvm] [clang] [compiler-rt] [lldb] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79239
>From 3725fa4eac3d3d946289d7eb7213f3a1751a2770 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:58:07 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp| 158 +
lld/ELF/Relocations.cpp | 25 ++--
lld/test/ELF/riscv-tlsdesc-gd-mixed.s | 26
lld/test/ELF/riscv-tlsdesc-relax.s| 125 +
lld/test/ELF/riscv-tlsdesc.s | 192 ++
5 files changed, 492 insertions(+), 34 deletions(-)
create mode 100644 lld/test/ELF/riscv-tlsdesc-gd-mixed.s
create mode 100644 lld/test/ELF/riscv-tlsdesc-relax.s
create mode 100644 lld/test/ELF/riscv-tlsdesc.s
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index d7d3d3e47814971..67d7e2562e9b178 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -61,6 +61,7 @@ enum Op {
AUIPC = 0x17,
JALR = 0x67,
LD = 0x3003,
+ LUI = 0x37,
LW = 0x2003,
SRLI = 0x5013,
SUB = 0x4033,
@@ -73,6 +74,7 @@ enum Reg {
X_T0 = 5,
X_T1 = 6,
X_T2 = 7,
+ X_A0 = 10,
X_T3 = 28,
};
@@ -102,6 +104,26 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
(extractBits(imm, 4, 0) << 7);
}
+namespace {
+struct SymbolAnchor {
+ uint64_t offset;
+ Defined *d;
+ bool end; // true for the anchor of st_value+st_size
+};
+} // namespace
+
+struct elf::RISCVRelaxAux {
+ // This records symbol start and end offsets which will be adjusted according
+ // to the nearest relocDeltas element.
+ SmallVector anchors;
+ // For relocations[i], the actual offset is r_offset - (i ? relocDeltas[i-1]
:
+ // 0).
+ std::unique_ptr relocDeltas;
+ // For relocations[i], the actual type is relocTypes[i].
+ std::unique_ptr relocTypes;
+ SmallVector writes;
+};
+
RISCV::RISCV() {
copyRel = R_RISCV_COPY;
pltRel = R_RISCV_JUMP_SLOT;
@@ -119,6 +141,7 @@ RISCV::RISCV() {
tlsGotRel = R_RISCV_TLS_TPREL32;
}
gotRel = symbolicRel;
+ tlsDescRel = R_RISCV_TLSDESC;
// .got[0] = _DYNAMIC
gotHeaderEntriesNum = 1;
@@ -187,6 +210,8 @@ int64_t RISCV::getImplicitAddend(const uint8_t *buf,
RelType type) const {
case R_RISCV_JUMP_SLOT:
// These relocations are defined as not having an implicit addend.
return 0;
+ case R_RISCV_TLSDESC:
+return config->is64 ? read64le(buf + 8) : read32le(buf + 4);
}
}
@@ -295,6 +320,12 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol
&s,
case R_RISCV_PCREL_LO12_I:
case R_RISCV_PCREL_LO12_S:
return R_RISCV_PC_INDIRECT;
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
+return R_TLSDESC_PC;
+ case R_RISCV_TLSDESC_CALL:
+return R_TLSDESC_CALL;
case R_RISCV_TLS_GD_HI20:
return R_TLSGD_PC;
case R_RISCV_TLS_GOT_HI20:
@@ -419,6 +450,7 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
case R_RISCV_GOT_HI20:
case R_RISCV_PCREL_HI20:
+ case R_RISCV_TLSDESC_HI20:
case R_RISCV_TLS_GD_HI20:
case R_RISCV_TLS_GOT_HI20:
case R_RISCV_TPREL_HI20:
@@ -430,6 +462,8 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
}
case R_RISCV_PCREL_LO12_I:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
case R_RISCV_TPREL_LO12_I:
case R_RISCV_LO12_I: {
uint64_t hi = (val + 0x800) >> 12;
@@ -513,29 +547,113 @@ void RISCV::relocate(uint8_t *loc, const Relocation
&rel, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE relaxation");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD
[Lldb-commits] [mlir] [libunwind] [lld] [flang] [clang-tools-extra] [libc] [libcxx] [llvm] [clang] [compiler-rt] [lldb] [Driver, CodeGen] Support -mtls-dialect= (PR #79256)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79256
>From be08e64c2c1f433b017185ce78525ad097e609be Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 21:37:04 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
clang/include/clang/Basic/CodeGenOptions.def | 3 +++
clang/include/clang/Driver/Options.td| 5 +
clang/lib/CodeGen/BackendUtil.cpp| 1 +
clang/lib/Driver/ToolChains/Clang.cpp| 23
clang/test/CodeGen/RISCV/tls-dialect.c | 13 +++
clang/test/Driver/tls-dialect.c | 19
6 files changed, 64 insertions(+)
create mode 100644 clang/test/CodeGen/RISCV/tls-dialect.c
create mode 100644 clang/test/Driver/tls-dialect.c
diff --git a/clang/include/clang/Basic/CodeGenOptions.def
b/clang/include/clang/Basic/CodeGenOptions.def
index 2f2e45d5cf63df..7c0bfe32849614 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -369,6 +369,9 @@ ENUM_CODEGENOPT(VecLib, llvm::driver::VectorLibrary, 3,
llvm::driver::VectorLibr
/// The default TLS model to use.
ENUM_CODEGENOPT(DefaultTLSModel, TLSModel, 2, GeneralDynamicTLSModel)
+/// Whether to enable TLSDESC. AArch64 enables TLSDESC regardless of this
value.
+CODEGENOPT(EnableTLSDESC, 1, 0)
+
/// Bit size of immediate TLS offsets (0 == use the default).
VALUE_CODEGENOPT(TLSSize, 8, 0)
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 7f4fa33748faca..773bc1dcda01d5 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4419,6 +4419,8 @@ def mtls_size_EQ : Joined<["-"], "mtls-size=">,
Group,
HelpText<"Specify bit size of immediate TLS offsets (AArch64 ELF only): "
"12 (for 4KB) | 24 (for 16MB, default) | 32 (for 4GB) | 48 (for
256TB, needs -mcmodel=large)">,
MarshallingInfoInt>;
+def mtls_dialect_EQ : Joined<["-"], "mtls-dialect=">, Group,
+ Flags<[TargetSpecific]>, HelpText<"Which thread-local storage dialect to use
for dynamic accesses of TLS variables">;
def mimplicit_it_EQ : Joined<["-"], "mimplicit-it=">, Group;
def mdefault_build_attributes : Joined<["-"], "mdefault-build-attributes">,
Group;
def mno_default_build_attributes : Joined<["-"],
"mno-default-build-attributes">, Group;
@@ -7066,6 +7068,9 @@ def fexperimental_assignment_tracking_EQ : Joined<["-"],
"fexperimental-assignme
Values<"disabled,enabled,forced">,
NormalizedValues<["Disabled","Enabled","Forced"]>,
MarshallingInfoEnum, "Enabled">;
+def enable_tlsdesc : Flag<["-"], "enable-tlsdesc">,
+ MarshallingInfoFlag>;
+
} // let Visibility = [CC1Option]
//===--===//
diff --git a/clang/lib/CodeGen/BackendUtil.cpp
b/clang/lib/CodeGen/BackendUtil.cpp
index ec203f6f28bc17..7877e20d77f772 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -401,6 +401,7 @@ static bool initTargetOptions(DiagnosticsEngine &Diags,
Options.UniqueBasicBlockSectionNames =
CodeGenOpts.UniqueBasicBlockSectionNames;
Options.TLSSize = CodeGenOpts.TLSSize;
+ Options.EnableTLSDESC = CodeGenOpts.EnableTLSDESC;
Options.EmulatedTLS = CodeGenOpts.EmulatedTLS;
Options.DebuggerTuning = CodeGenOpts.getDebuggerTuning();
Options.EmitStackSizeSection = CodeGenOpts.StackSizeSection;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index 5dc614e11aab59..93fd579eb92ba5 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -5822,6 +5822,29 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
Args.AddLastArg(CmdArgs, options::OPT_mtls_size_EQ);
}
+ if (Arg *A = Args.getLastArg(options::OPT_mtls_dialect_EQ)) {
+StringRef V = A->getValue();
+bool SupportedArgument = false, EnableTLSDESC = false;
+bool Unsupported = !Triple.isOSBinFormatELF();
+if (Triple.isRISCV()) {
+ SupportedArgument = V == "desc" || V == "trad";
+ EnableTLSDESC = V == "desc";
+} else if (Triple.isX86()) {
+ SupportedArgument = V == "gnu";
+} else {
+ Unsupported = true;
+}
+if (Unsupported) {
+ D.Diag(diag::err_drv_unsupported_opt_for_target)
+ << A->getSpelling() << TripleStr;
+} else if (!SupportedArgument) {
+ D.Diag(diag::err_drv_unsupported_option_argument_for_target)
+ << A->getSpelling() << V << TripleStr;
+} else if (EnableTLSDESC) {
+ CmdArgs.push_back("-enable-tlsdesc");
+}
+ }
+
// Add the target cpu
std::string CPU = getCPUName(D, Args, Triple, /*FromAs*/ false);
if (!CPU.empty()) {
diff --git a/clang/test/CodeGen/RISCV
[Lldb-commits] [libc] [lldb] [libunwind] [clang] [compiler-rt] [mlir] [llvm] [lld] [flang] [libcxx] [clang-tools-extra] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
@@ -513,29 +547,113 @@ void RISCV::relocate(uint8_t *loc, const Relocation
&rel, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE relaxation");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation &rel, uint64_t val) {
MaskRay wrote:
Thanks for catching this. Implemented the short form.
https://github.com/llvm/llvm-project/pull/79239
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [libc] [lldb] [libunwind] [clang] [compiler-rt] [mlir] [llvm] [lld] [flang] [libcxx] [clang-tools-extra] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79239 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [flang] [libc] [clang] [lld] [clang-tools-extra] [libcxx] [compiler-rt] [libunwind] [llvm] [mlir] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79239
>From 3725fa4eac3d3d946289d7eb7213f3a1751a2770 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:58:07 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp| 158 +
lld/ELF/Relocations.cpp | 25 ++--
lld/test/ELF/riscv-tlsdesc-gd-mixed.s | 26
lld/test/ELF/riscv-tlsdesc-relax.s| 125 +
lld/test/ELF/riscv-tlsdesc.s | 192 ++
5 files changed, 492 insertions(+), 34 deletions(-)
create mode 100644 lld/test/ELF/riscv-tlsdesc-gd-mixed.s
create mode 100644 lld/test/ELF/riscv-tlsdesc-relax.s
create mode 100644 lld/test/ELF/riscv-tlsdesc.s
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index d7d3d3e47814971..67d7e2562e9b178 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -61,6 +61,7 @@ enum Op {
AUIPC = 0x17,
JALR = 0x67,
LD = 0x3003,
+ LUI = 0x37,
LW = 0x2003,
SRLI = 0x5013,
SUB = 0x4033,
@@ -73,6 +74,7 @@ enum Reg {
X_T0 = 5,
X_T1 = 6,
X_T2 = 7,
+ X_A0 = 10,
X_T3 = 28,
};
@@ -102,6 +104,26 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
(extractBits(imm, 4, 0) << 7);
}
+namespace {
+struct SymbolAnchor {
+ uint64_t offset;
+ Defined *d;
+ bool end; // true for the anchor of st_value+st_size
+};
+} // namespace
+
+struct elf::RISCVRelaxAux {
+ // This records symbol start and end offsets which will be adjusted according
+ // to the nearest relocDeltas element.
+ SmallVector anchors;
+ // For relocations[i], the actual offset is r_offset - (i ? relocDeltas[i-1]
:
+ // 0).
+ std::unique_ptr relocDeltas;
+ // For relocations[i], the actual type is relocTypes[i].
+ std::unique_ptr relocTypes;
+ SmallVector writes;
+};
+
RISCV::RISCV() {
copyRel = R_RISCV_COPY;
pltRel = R_RISCV_JUMP_SLOT;
@@ -119,6 +141,7 @@ RISCV::RISCV() {
tlsGotRel = R_RISCV_TLS_TPREL32;
}
gotRel = symbolicRel;
+ tlsDescRel = R_RISCV_TLSDESC;
// .got[0] = _DYNAMIC
gotHeaderEntriesNum = 1;
@@ -187,6 +210,8 @@ int64_t RISCV::getImplicitAddend(const uint8_t *buf,
RelType type) const {
case R_RISCV_JUMP_SLOT:
// These relocations are defined as not having an implicit addend.
return 0;
+ case R_RISCV_TLSDESC:
+return config->is64 ? read64le(buf + 8) : read32le(buf + 4);
}
}
@@ -295,6 +320,12 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol
&s,
case R_RISCV_PCREL_LO12_I:
case R_RISCV_PCREL_LO12_S:
return R_RISCV_PC_INDIRECT;
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
+return R_TLSDESC_PC;
+ case R_RISCV_TLSDESC_CALL:
+return R_TLSDESC_CALL;
case R_RISCV_TLS_GD_HI20:
return R_TLSGD_PC;
case R_RISCV_TLS_GOT_HI20:
@@ -419,6 +450,7 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
case R_RISCV_GOT_HI20:
case R_RISCV_PCREL_HI20:
+ case R_RISCV_TLSDESC_HI20:
case R_RISCV_TLS_GD_HI20:
case R_RISCV_TLS_GOT_HI20:
case R_RISCV_TPREL_HI20:
@@ -430,6 +462,8 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
}
case R_RISCV_PCREL_LO12_I:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
case R_RISCV_TPREL_LO12_I:
case R_RISCV_LO12_I: {
uint64_t hi = (val + 0x800) >> 12;
@@ -513,29 +547,113 @@ void RISCV::relocate(uint8_t *loc, const Relocation
&rel, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE relaxation");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD
[Lldb-commits] [flang] [libunwind] [llvm] [clang] [lldb] [libc] [clang-tools-extra] [compiler-rt] [libcxx] [lld] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79239 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [flang] [libunwind] [llvm] [clang] [lldb] [libc] [clang-tools-extra] [compiler-rt] [libcxx] [lld] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
@@ -0,0 +1,125 @@
+# REQUIRES: riscv
+# RUN: rm -rf %t && split-file %s %t && cd %t
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax a.s -o a.64.o
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax c.s -o c.64.o
+# RUN: ld.lld -shared -soname=c.64.so c.64.o -o c.64.so
+
+# RUN: ld.lld -shared -z now a.64.o c.64.o -o a.64.so -z separate-code
+# RUN: llvm-objdump --no-show-raw-insn -M no-aliases -h -d a.64.so | FileCheck
%s --check-prefix=GD64
+
+# RUN: ld.lld -e 0 -z now a.64.o c.64.o -o a.64.le -z separate-code
+# RUN: llvm-objdump --no-show-raw-insn -M no-aliases -h -d a.64.le | FileCheck
%s --check-prefix=LE64
+
+# RUN: ld.lld -e 0 -z now a.64.o c.64.so -o a.64.ie -z separate-code
+# RUN: llvm-objdump --no-show-raw-insn -M no-aliases -h -d a.64.ie | FileCheck
%s --check-prefix=IE64
+
+# GD64: .got 0018 20c0
+# GD64-LABEL: <_start>:
+# GD64-NEXT: jal {{.*}}
+# GD64-LABEL: :
+## &.got[c]-. = 0x20c0+8 - 0x1004 = 0x10c4
+# GD64:1004: auipc a2, 0x1
+# GD64-NEXT: ld a3, 0xc4(a2)
+# GD64-NEXT: addia0, a2, 0xc4
+# GD64-NEXT: jalrt0, 0x0(a3)
+# GD64-NEXT: c.add a0, tp
+# GD64-NEXT: jal {{.*}}
+# GD64-NEXT: auipc a4, 0x1
+# GD64-NEXT: ld a5, 0xae(a4)
+# GD64-NEXT: addia0, a4, 0xae
+# GD64-NEXT: jalrt0, 0x0(a5)
+# GD64-NEXT: c.add a0, tp
+
+# LE64-LABEL: <_start>:
+# LE64-NEXT: jal {{.*}}
+# LE64-LABEL: :
+# LE64-NEXT: 11004: lui a0, 0x0
+# LE64-NEXT: addia0, zero, 0xc
+# LE64-NEXT: c.add a0, tp
+# LE64-NEXT: jal {{.*}}
+# LE64-NEXT: addizero, zero, 0x0
+# LE64-NEXT: lui a0, 0x0
+# LE64-NEXT: addia0, zero, 0xc
+# LE64-NEXT: c.add a0, tp
+# LE64-NEXT: addizero, zero, 0x0
+# LE64-NEXT: lui a0, 0x0
+# LE64-NEXT: addia0, zero, 0xc
+# LE64-NEXT: c.add a0, tp
+
+# IE64: .got 0010 000120e0
+# IE64-LABEL: <_start>:
+# IE64-NEXT: jal {{.*}}
+# IE64-LABEL: :
+## &.got[c]-. = 0x120e0+8 - 0x11004 = 0x10e4
+# IE64-NEXT: 11004: auipc a0, 0x1
+# IE64-NEXT: ld a0, 0xe4(a0)
+# IE64-NEXT: c.add a0, tp
+# IE64-NEXT: jal {{.*}}
+# IE64-NEXT: addizero, zero, 0x0
+## &.got[c]-. = 0x120e0+8 - 0x11016 = 0x10d2
+# IE64-NEXT: 11016: auipc a0, 0x1
+# IE64-NEXT: ld a0, 0xd2(a0)
+# IE64-NEXT: c.add a0, tp
+# IE64-NEXT: addizero, zero, 0x0
+## &.got[c]-. = 0x120e0+8 - 0x11024 = 0x10c4
+# IE64-NEXT: 11024: auipc a0, 0x1
+# IE64-NEXT: ld a0, 0xc4(a0)
+# IE64-NEXT: c.add a0, tp
+
+#--- a.s
+.globl _start
+_start:
+.balign 16
+ call foo
+
+foo:
+.Ltlsdesc_hi0:
+.option norelax
+## All 4 instructions have an R_RISCV_RELAX.
+ auipc a2, %tlsdesc_hi(c)
+ .reloc .-4, R_RISCV_RELAX, 0
+ lda3, %tlsdesc_load_lo(.Ltlsdesc_hi0)(a2)
+ .reloc .-4, R_RISCV_RELAX, 0
+ addi a0, a2, %tlsdesc_add_lo(.Ltlsdesc_hi0)
+ .reloc .-4, R_RISCV_RELAX, 0
+ jalr t0, 0(a3), %tlsdesc_call(.Ltlsdesc_hi0)
+ .reloc .-4, R_RISCV_RELAX, 0
+ add a0, a0, tp
MaskRay wrote:
Thanks for noticing this. `i386-tlsdesc-gd.s` has `movl %edx, %ebx # GCC -O0
may add an extra insn in between.` that I forgot to copy here. Done.
This requires the following code to handle it.
```
+ // For HI20/LOAD_LO12, disable NOP conversion in the presence of
+ // R_RISCV_RELAX, in case an unrelated instruction follows the current
+ // instruction.
+ if ((rel.type == R_RISCV_TLSDESC_HI20 ||
+ rel.type == R_RISCV_TLSDESC_LOAD_LO12) &&
+ i + 1 != relocs.size() && relocs[i + 1].type == R_RISCV_RELAX)
+continue;
```
https://github.com/llvm/llvm-project/pull/79239
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [llvm] [compiler-rt] [flang] [clang] [clang-tools-extra] [libunwind] [lld] [libc] [libcxx] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79239
>From 3725fa4eac3d3d946289d7eb7213f3a1751a2770 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:58:07 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp| 158 +
lld/ELF/Relocations.cpp | 25 ++--
lld/test/ELF/riscv-tlsdesc-gd-mixed.s | 26
lld/test/ELF/riscv-tlsdesc-relax.s| 125 +
lld/test/ELF/riscv-tlsdesc.s | 192 ++
5 files changed, 492 insertions(+), 34 deletions(-)
create mode 100644 lld/test/ELF/riscv-tlsdesc-gd-mixed.s
create mode 100644 lld/test/ELF/riscv-tlsdesc-relax.s
create mode 100644 lld/test/ELF/riscv-tlsdesc.s
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index d7d3d3e4781497..67d7e2562e9b17 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -61,6 +61,7 @@ enum Op {
AUIPC = 0x17,
JALR = 0x67,
LD = 0x3003,
+ LUI = 0x37,
LW = 0x2003,
SRLI = 0x5013,
SUB = 0x4033,
@@ -73,6 +74,7 @@ enum Reg {
X_T0 = 5,
X_T1 = 6,
X_T2 = 7,
+ X_A0 = 10,
X_T3 = 28,
};
@@ -102,6 +104,26 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
(extractBits(imm, 4, 0) << 7);
}
+namespace {
+struct SymbolAnchor {
+ uint64_t offset;
+ Defined *d;
+ bool end; // true for the anchor of st_value+st_size
+};
+} // namespace
+
+struct elf::RISCVRelaxAux {
+ // This records symbol start and end offsets which will be adjusted according
+ // to the nearest relocDeltas element.
+ SmallVector anchors;
+ // For relocations[i], the actual offset is r_offset - (i ? relocDeltas[i-1]
:
+ // 0).
+ std::unique_ptr relocDeltas;
+ // For relocations[i], the actual type is relocTypes[i].
+ std::unique_ptr relocTypes;
+ SmallVector writes;
+};
+
RISCV::RISCV() {
copyRel = R_RISCV_COPY;
pltRel = R_RISCV_JUMP_SLOT;
@@ -119,6 +141,7 @@ RISCV::RISCV() {
tlsGotRel = R_RISCV_TLS_TPREL32;
}
gotRel = symbolicRel;
+ tlsDescRel = R_RISCV_TLSDESC;
// .got[0] = _DYNAMIC
gotHeaderEntriesNum = 1;
@@ -187,6 +210,8 @@ int64_t RISCV::getImplicitAddend(const uint8_t *buf,
RelType type) const {
case R_RISCV_JUMP_SLOT:
// These relocations are defined as not having an implicit addend.
return 0;
+ case R_RISCV_TLSDESC:
+return config->is64 ? read64le(buf + 8) : read32le(buf + 4);
}
}
@@ -295,6 +320,12 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol
&s,
case R_RISCV_PCREL_LO12_I:
case R_RISCV_PCREL_LO12_S:
return R_RISCV_PC_INDIRECT;
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
+return R_TLSDESC_PC;
+ case R_RISCV_TLSDESC_CALL:
+return R_TLSDESC_CALL;
case R_RISCV_TLS_GD_HI20:
return R_TLSGD_PC;
case R_RISCV_TLS_GOT_HI20:
@@ -419,6 +450,7 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
case R_RISCV_GOT_HI20:
case R_RISCV_PCREL_HI20:
+ case R_RISCV_TLSDESC_HI20:
case R_RISCV_TLS_GD_HI20:
case R_RISCV_TLS_GOT_HI20:
case R_RISCV_TPREL_HI20:
@@ -430,6 +462,8 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
}
case R_RISCV_PCREL_LO12_I:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+ case R_RISCV_TLSDESC_ADD_LO12:
case R_RISCV_TPREL_LO12_I:
case R_RISCV_LO12_I: {
uint64_t hi = (val + 0x800) >> 12;
@@ -513,29 +547,113 @@ void RISCV::relocate(uint8_t *loc, const Relocation
&rel, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->is64)
+ write64le(loc + 8, val);
+else
+ write32le(loc + 4, val);
+break;
default:
llvm_unreachable("unknown relocation");
}
}
+static void tlsdescToIe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_LO12:
+write32le(loc, utype(AUIPC, X_A0, hi20(val))); // auipc a0,
+return;
+ case R_RISCV_TLSDESC_CALL:
+if (config->is64)
+ write32le(loc, itype(LD, X_A0, X_A0, lo12(val))); // ld a0,(a0)
+else
+ write32le(loc, itype(LW, X_A0, X_A0, lo12(val))); // lw a0,(a0)
+return;
+ default:
+llvm_unreachable("unsupported relocation for TLSDESC to IE relaxation");
+ }
+}
+
+static void tlsdescToLe(uint8_t *loc, const Relocation &rel, uint64_t val) {
+ switch (rel.type) {
+ case R_RISCV_TLSDESC_HI20:
+ case R_RISCV_TLSDESC_LOAD_LO12:
+write32le(loc, 0x0013); // nop
+return;
+ case R_RISCV_TLSDESC_ADD_L
[Lldb-commits] [flang] [libunwind] [llvm] [clang] [lldb] [libc] [clang-tools-extra] [compiler-rt] [libcxx] [lld] [ELF] Implement R_RISCV_TLSDESC for RISC-V (PR #79239)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79239 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [libcxx] [clang-tools-extra] [flang] [libc] [llvm] [lld] [compiler-rt] [lldb] [clang] [libunwind] [Driver, CodeGen] Support -mtls-dialect= (PR #79256)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79256 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [libunwind] [compiler-rt] [lld] [clang-tools-extra] [clang] [lldb] [libcxx] [flang] [llvm] [libc] [Driver, CodeGen] Support -mtls-dialect= (PR #79256)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79256
>From be08e64c2c1f433b017185ce78525ad097e609be Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 21:37:04 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
clang/include/clang/Basic/CodeGenOptions.def | 3 +++
clang/include/clang/Driver/Options.td| 5 +
clang/lib/CodeGen/BackendUtil.cpp| 1 +
clang/lib/Driver/ToolChains/Clang.cpp| 23
clang/test/CodeGen/RISCV/tls-dialect.c | 13 +++
clang/test/Driver/tls-dialect.c | 19
6 files changed, 64 insertions(+)
create mode 100644 clang/test/CodeGen/RISCV/tls-dialect.c
create mode 100644 clang/test/Driver/tls-dialect.c
diff --git a/clang/include/clang/Basic/CodeGenOptions.def
b/clang/include/clang/Basic/CodeGenOptions.def
index 2f2e45d5cf63dfa..7c0bfe328496147 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -369,6 +369,9 @@ ENUM_CODEGENOPT(VecLib, llvm::driver::VectorLibrary, 3,
llvm::driver::VectorLibr
/// The default TLS model to use.
ENUM_CODEGENOPT(DefaultTLSModel, TLSModel, 2, GeneralDynamicTLSModel)
+/// Whether to enable TLSDESC. AArch64 enables TLSDESC regardless of this
value.
+CODEGENOPT(EnableTLSDESC, 1, 0)
+
/// Bit size of immediate TLS offsets (0 == use the default).
VALUE_CODEGENOPT(TLSSize, 8, 0)
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 7f4fa33748facaf..773bc1dcda01d5c 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4419,6 +4419,8 @@ def mtls_size_EQ : Joined<["-"], "mtls-size=">,
Group,
HelpText<"Specify bit size of immediate TLS offsets (AArch64 ELF only): "
"12 (for 4KB) | 24 (for 16MB, default) | 32 (for 4GB) | 48 (for
256TB, needs -mcmodel=large)">,
MarshallingInfoInt>;
+def mtls_dialect_EQ : Joined<["-"], "mtls-dialect=">, Group,
+ Flags<[TargetSpecific]>, HelpText<"Which thread-local storage dialect to use
for dynamic accesses of TLS variables">;
def mimplicit_it_EQ : Joined<["-"], "mimplicit-it=">, Group;
def mdefault_build_attributes : Joined<["-"], "mdefault-build-attributes">,
Group;
def mno_default_build_attributes : Joined<["-"],
"mno-default-build-attributes">, Group;
@@ -7066,6 +7068,9 @@ def fexperimental_assignment_tracking_EQ : Joined<["-"],
"fexperimental-assignme
Values<"disabled,enabled,forced">,
NormalizedValues<["Disabled","Enabled","Forced"]>,
MarshallingInfoEnum, "Enabled">;
+def enable_tlsdesc : Flag<["-"], "enable-tlsdesc">,
+ MarshallingInfoFlag>;
+
} // let Visibility = [CC1Option]
//===--===//
diff --git a/clang/lib/CodeGen/BackendUtil.cpp
b/clang/lib/CodeGen/BackendUtil.cpp
index ec203f6f28bc173..7877e20d77f7724 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -401,6 +401,7 @@ static bool initTargetOptions(DiagnosticsEngine &Diags,
Options.UniqueBasicBlockSectionNames =
CodeGenOpts.UniqueBasicBlockSectionNames;
Options.TLSSize = CodeGenOpts.TLSSize;
+ Options.EnableTLSDESC = CodeGenOpts.EnableTLSDESC;
Options.EmulatedTLS = CodeGenOpts.EmulatedTLS;
Options.DebuggerTuning = CodeGenOpts.getDebuggerTuning();
Options.EmitStackSizeSection = CodeGenOpts.StackSizeSection;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index 5dc614e11aab599..93fd579eb92ba50 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -5822,6 +5822,29 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
Args.AddLastArg(CmdArgs, options::OPT_mtls_size_EQ);
}
+ if (Arg *A = Args.getLastArg(options::OPT_mtls_dialect_EQ)) {
+StringRef V = A->getValue();
+bool SupportedArgument = false, EnableTLSDESC = false;
+bool Unsupported = !Triple.isOSBinFormatELF();
+if (Triple.isRISCV()) {
+ SupportedArgument = V == "desc" || V == "trad";
+ EnableTLSDESC = V == "desc";
+} else if (Triple.isX86()) {
+ SupportedArgument = V == "gnu";
+} else {
+ Unsupported = true;
+}
+if (Unsupported) {
+ D.Diag(diag::err_drv_unsupported_opt_for_target)
+ << A->getSpelling() << TripleStr;
+} else if (!SupportedArgument) {
+ D.Diag(diag::err_drv_unsupported_option_argument_for_target)
+ << A->getSpelling() << V << TripleStr;
+} else if (EnableTLSDESC) {
+ CmdArgs.push_back("-enable-tlsdesc");
+}
+ }
+
// Add the target cpu
std::string CPU = getCPUName(D, Args, Triple, /*FromAs*/ false);
if (!CPU.empty()) {
diff --git a/clang/test/CodeG
[Lldb-commits] [lld] [libc] [openmp] [lldb] [compiler-rt] [clang] [libcxx] [llvm] [clang-tools-extra] [mlir] [pstl] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
https://github.com/MaskRay closed https://github.com/llvm/llvm-project/pull/79222 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lld] [libc] [openmp] [lldb] [compiler-rt] [clang] [libcxx] [llvm] [clang-tools-extra] [mlir] [pstl] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
@@ -0,0 +1,5 @@
+/// Some target-specific options are ignored for GPU, so %clang exits with
code 0.
+// DEFINE: %{check} = %clang -### -c -mcmodel=medium
MaskRay wrote:
In general the error reporting is done in the driver and cc1 allows and ignores
options that may be specific to other targets.
> That said, we do have other options that we do need to suppress/ignore and
> some of that does happen on cc1 level.
Perhaps we should figure out them and check whether they should be moved to the
driver
https://github.com/llvm/llvm-project/pull/79222
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https://github.com/MaskRay closed https://github.com/llvm/llvm-project/pull/79238 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [libc] [lld] [clang] [libunwind] [compiler-rt] [flang] [lldb] [openmp] [libcxx] [mlir] [llvm] [pstl] [clang-tools-extra] [ELF] Don't resolve relocations referencing SHN_ABS to tombstone
MaskRay wrote:
Fixed a typo and added an example
> ```
> // clang -g
> __attribute__((weak)) int symbol;
> int *foo() { return &symbol; }
>
> 0x0023: DW_TAG_variable [2] (0x000c)
> ...
> DW_AT_location [DW_FORM_exprloc](DW_OP_addrx 0x0)
> ```
>
>
> .debug_addr references `symbol`, which can be redefined by a symbol
> assignment or --defsym to become a SHN_ABS symbol.
https://github.com/llvm/llvm-project/pull/79238
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[Lldb-commits] [libc] [lld] [clang] [libunwind] [compiler-rt] [flang] [lldb] [openmp] [libcxx] [mlir] [llvm] [pstl] [clang-tools-extra] [ELF] Don't resolve relocations referencing SHN_ABS to tombstone
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79238
>From 97b500a7061041b5478b6b1b1094e76140e3d9c3 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:53:31 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/InputSection.cpp | 13 ++---
lld/test/ELF/dead-reloc-in-nonalloc.s | 2 +-
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp
index c728dd6c6306aa0..0e0b9783bd88a0f 100644
--- a/lld/ELF/InputSection.cpp
+++ b/lld/ELF/InputSection.cpp
@@ -961,12 +961,11 @@ void InputSection::relocateNonAlloc(uint8_t *buf,
ArrayRef rels) {
// vector. The computed value is st_value plus a non-negative offset.
// Negative values are invalid, so -1 can be used as the tombstone value.
//
- // If the referenced symbol is discarded (made Undefined), or the
- // section defining the referenced symbol is garbage collected,
- // sym.getOutputSection() is nullptr. `ds->folded` catches the ICF folded
- // case. However, resolving a relocation in .debug_line to -1 would stop
- // debugger users from setting breakpoints on the folded-in function, so
- // exclude .debug_line.
+ // If the referenced symbol is relative to a discarded section (due to
+ // --gc-sections, COMDAT, etc), it has been converted to a Undefined.
+ // `ds->folded` catches the ICF folded case. However, resolving a
+ // relocation in .debug_line to -1 would stop debugger users from setting
+ // breakpoints on the folded-in function, so exclude .debug_line.
//
// For pre-DWARF-v5 .debug_loc and .debug_ranges, -1 is a reserved value
// (base address selection entry), use 1 (which is used by GNU ld for
@@ -974,7 +973,7 @@ void InputSection::relocateNonAlloc(uint8_t *buf,
ArrayRef rels) {
//
// TODO To reduce disruption, we use 0 instead of -1 as the tombstone
// value. Enable -1 in a future release.
- if (!sym.getOutputSection() || (ds && ds->folded && !isDebugLine)) {
+ if (!ds || (ds->folded && !isDebugLine)) {
// If -z dead-reloc-in-nonalloc= is specified, respect it.
uint64_t value = SignExtend64(*tombstone);
// For a 32-bit local TU reference in .debug_names, X86_64::relocate
diff --git a/lld/test/ELF/dead-reloc-in-nonalloc.s
b/lld/test/ELF/dead-reloc-in-nonalloc.s
index 145604eb883a9af..b675fc50fc2ea2f 100644
--- a/lld/test/ELF/dead-reloc-in-nonalloc.s
+++ b/lld/test/ELF/dead-reloc-in-nonalloc.s
@@ -17,7 +17,7 @@
# AA: Contents of section .debug_info:
# AA-NEXT: [[ADDR]]
# AA: Contents of section .not_debug:
-# AA-NEXT: .
+# AA-NEXT: 2a00 .
## Specifying zero can get a behavior similar to GNU ld.
# RUN: ld.lld --icf=all -z dead-reloc-in-nonalloc=.debug_info=0 %t.o %tabs.o
-o %tzero
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https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79238 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lld] [clang] [llvm] [mlir] [pstl] [libcxx] [openmp] [lldb] [clang-tools-extra] [ELF] Don't resolve relocations referencing SHN_ABS to tombstone in non-SHF_ALLOC sections (PR #79238)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79238
>From 97b500a7061041b5478b6b1b1094e76140e3d9c3 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:53:31 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
lld/ELF/InputSection.cpp | 13 ++---
lld/test/ELF/dead-reloc-in-nonalloc.s | 2 +-
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp
index c728dd6c6306aa..0e0b9783bd88a0 100644
--- a/lld/ELF/InputSection.cpp
+++ b/lld/ELF/InputSection.cpp
@@ -961,12 +961,11 @@ void InputSection::relocateNonAlloc(uint8_t *buf,
ArrayRef rels) {
// vector. The computed value is st_value plus a non-negative offset.
// Negative values are invalid, so -1 can be used as the tombstone value.
//
- // If the referenced symbol is discarded (made Undefined), or the
- // section defining the referenced symbol is garbage collected,
- // sym.getOutputSection() is nullptr. `ds->folded` catches the ICF folded
- // case. However, resolving a relocation in .debug_line to -1 would stop
- // debugger users from setting breakpoints on the folded-in function, so
- // exclude .debug_line.
+ // If the referenced symbol is relative to a discarded section (due to
+ // --gc-sections, COMDAT, etc), it has been converted to a Undefined.
+ // `ds->folded` catches the ICF folded case. However, resolving a
+ // relocation in .debug_line to -1 would stop debugger users from setting
+ // breakpoints on the folded-in function, so exclude .debug_line.
//
// For pre-DWARF-v5 .debug_loc and .debug_ranges, -1 is a reserved value
// (base address selection entry), use 1 (which is used by GNU ld for
@@ -974,7 +973,7 @@ void InputSection::relocateNonAlloc(uint8_t *buf,
ArrayRef rels) {
//
// TODO To reduce disruption, we use 0 instead of -1 as the tombstone
// value. Enable -1 in a future release.
- if (!sym.getOutputSection() || (ds && ds->folded && !isDebugLine)) {
+ if (!ds || (ds->folded && !isDebugLine)) {
// If -z dead-reloc-in-nonalloc= is specified, respect it.
uint64_t value = SignExtend64(*tombstone);
// For a 32-bit local TU reference in .debug_names, X86_64::relocate
diff --git a/lld/test/ELF/dead-reloc-in-nonalloc.s
b/lld/test/ELF/dead-reloc-in-nonalloc.s
index 145604eb883a9a..b675fc50fc2ea2 100644
--- a/lld/test/ELF/dead-reloc-in-nonalloc.s
+++ b/lld/test/ELF/dead-reloc-in-nonalloc.s
@@ -17,7 +17,7 @@
# AA: Contents of section .debug_info:
# AA-NEXT: [[ADDR]]
# AA: Contents of section .not_debug:
-# AA-NEXT: .
+# AA-NEXT: 2a00 .
## Specifying zero can get a behavior similar to GNU ld.
# RUN: ld.lld --icf=all -z dead-reloc-in-nonalloc=.debug_info=0 %t.o %tabs.o
-o %tzero
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[Lldb-commits] [pstl] [lldb] [llvm] [openmp] [clang-tools-extra] [libcxx] [lld] [mlir] [clang] [ELF] Don't resolve relocations referencing SHN_ABS to tombstone in non-SHF_ALLOC sections (PR #79238)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79238 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [clang] [clang-tools-extra] [openmp] [lld] [libc] [libcxx] [mlir] [pstl] [compiler-rt] [llvm] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
@@ -0,0 +1,7 @@
+/// Some target-specific options are ignored for GPU, so %clang exits with
code 0.
+// DEFINE: %{gpu_opts} = --cuda-gpu-arch=sm_60
--cuda-path=%S/Inputs/CUDA/usr/local/cuda --no-cuda-version-check
+// DEFINE: %{check} = %clang -### -c %{gpu_opts} -mcmodel=medium %s
+// RUN: %{check} -fbasic-block-sections=all
+
+// REDEFINE: %{gpu_opts} = -x hip --rocm-path=%S/Inputs/rocm -nogpulib
MaskRay wrote:
Added!
https://github.com/llvm/llvm-project/pull/79222
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[Lldb-commits] [libcxx] [clang] [openmp] [lldb] [lld] [compiler-rt] [clang-tools-extra] [pstl] [mlir] [llvm] [libc] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79222
>From 3a2b2a1110e7b3348a12a6476ab014a469891062 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 15:13:49 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
clang/test/Driver/unsupported-option-gpu.c | 7 +++
1 file changed, 7 insertions(+)
create mode 100644 clang/test/Driver/unsupported-option-gpu.c
diff --git a/clang/test/Driver/unsupported-option-gpu.c
b/clang/test/Driver/unsupported-option-gpu.c
new file mode 100644
index 00..5713dbbfc7ae4d
--- /dev/null
+++ b/clang/test/Driver/unsupported-option-gpu.c
@@ -0,0 +1,7 @@
+/// Some target-specific options are ignored for GPU, so %clang exits with
code 0.
+// DEFINE: %{gpu_opts} = --cuda-gpu-arch=sm_60
--cuda-path=%S/Inputs/CUDA/usr/local/cuda --no-cuda-version-check
+// DEFINE: %{check} = %clang -### -c %{gpu_opts} -mcmodel=medium %s
+// RUN: %{check} -fbasic-block-sections=all
+
+// REDEFINE: %{gpu_opts} = -x hip --rocm-path=%S/Inputs/rocm -nogpulib
+// RUN: %{check}
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[Lldb-commits] [clang] [libc] [lldb] [llvm] [mlir] [compiler-rt] [lld] [libcxx] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
@@ -0,0 +1,7 @@
+/// Some target-specific options are ignored for GPU, so %clang exits with
code 0.
+// DEFINE: %{gpu_opts} = --cuda-gpu-arch=sm_60
--cuda-path=%S/Inputs/CUDA/usr/local/cuda --no-cuda-version-check
MaskRay wrote:
Thanks for the suggestion. Edited
https://github.com/llvm/llvm-project/pull/79222
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https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79222 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [libc] [lldb] [llvm] [mlir] [compiler-rt] [lld] [libcxx] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79222 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [libc] [lldb] [llvm] [mlir] [compiler-rt] [lld] [libcxx] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
https://github.com/MaskRay edited https://github.com/llvm/llvm-project/pull/79222 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [libc] [lldb] [llvm] [mlir] [compiler-rt] [lld] [libcxx] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
@@ -0,0 +1,7 @@
+/// Some target-specific options are ignored for GPU, so %clang exits with
code 0.
+// DEFINE: %{gpu_opts} = --cuda-gpu-arch=sm_60
--cuda-path=%S/Inputs/CUDA/usr/local/cuda --no-cuda-version-check
+// DEFINE: %{check} = %clang -### -c %{gpu_opts} -mcmodel=medium %s
+// RUN: %{check} -fbasic-block-sections=all
MaskRay wrote:
Added `-x cuda`. The test is to show we don't get an error
(`err_drv_unsupported_opt_for_target`) when compiling for x86_64 using a device
(AMDGPU/NVPTX) when certain target-specified options are specified.
I am not familiar with offloading but specifying `--cuda-host-only` would
defeat the purpose.
https://github.com/llvm/llvm-project/pull/79222
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[Lldb-commits] [clang] [libc] [lldb] [llvm] [mlir] [compiler-rt] [lld] [libcxx] [Driver] Test ignored target-specific options for AMDGPU/NVPTX (PR #79222)
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79222
>From 3a2b2a1110e7b3348a12a6476ab014a469891062 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 15:13:49 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
clang/test/Driver/unsupported-option-gpu.c | 7 +++
1 file changed, 7 insertions(+)
create mode 100644 clang/test/Driver/unsupported-option-gpu.c
diff --git a/clang/test/Driver/unsupported-option-gpu.c
b/clang/test/Driver/unsupported-option-gpu.c
new file mode 100644
index 00..5713dbbfc7ae4d
--- /dev/null
+++ b/clang/test/Driver/unsupported-option-gpu.c
@@ -0,0 +1,7 @@
+/// Some target-specific options are ignored for GPU, so %clang exits with
code 0.
+// DEFINE: %{gpu_opts} = --cuda-gpu-arch=sm_60
--cuda-path=%S/Inputs/CUDA/usr/local/cuda --no-cuda-version-check
+// DEFINE: %{check} = %clang -### -c %{gpu_opts} -mcmodel=medium %s
+// RUN: %{check} -fbasic-block-sections=all
+
+// REDEFINE: %{gpu_opts} = -x hip --rocm-path=%S/Inputs/rocm -nogpulib
+// RUN: %{check}
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[Lldb-commits] [lldb] [libclc] [libc] [clang] [compiler-rt] [mlir] [flang] [clang-tools-extra] [libcxx] [lld] [llvm] [libcxxabi] [ELF] Add internal InputFile (PR #78944)
MaskRay wrote: Hi, do you have more information (like a reproduce tarball) about a `file` that references a file of `InternalKind`? Could it be a patch in your downstream? If `file` references a file of `InternalKind`, we probably should make it `nullptr` instead. But I don't know a code path where it is the case for the upstream lld. https://github.com/llvm/llvm-project/pull/78944 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [llvm] [libunwind] [compiler-rt] [libc] [flang] [lld] [libcxx] [lldb] [libclc] [clang-tools-extra] [libcxxabi] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #
MaskRay wrote: This PR needs a rebase.. There are quite a few merge commits. Hmm, I don't know how to squash the changes to rebase them to latest main branch. `git rebase --keep-base -i main` has quite a few merge conflicts. (My lld change (https://github.com/maskray/llvm-project/tree/rv-tlsdesc) is almost complete. I want to rebase it onto the latest revision of this LLVM PR.) https://github.com/llvm/llvm-project/pull/66915 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang-tools-extra] [libclc] [compiler-rt] [lldb] [libcxxabi] [libunwind] [llvm] [libcxx] [lld] [flang] [libc] [clang] [RISCV] Support Global Dynamic TLSDESC in the RISC-V backend (PR #
@@ -89,8 +89,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine
&TM,
if ((ABI == RISCVABI::ABI_ILP32F || ABI == RISCVABI::ABI_LP64F) &&
!Subtarget.hasStdExtF()) {
errs() << "Hard-float 'f' ABI can't be used for a target that "
-"doesn't support the F instruction set extension (ignoring "
- "target-abi)\n";
+ "doesn't support the F instruction set extension (ignoring "
MaskRay wrote:
Ah, I only use `git diff -U0 --no-color --relative main... -- |
path/to/clang/tools/clang-format/clang-format-diff.py -p1 -i` :)
https://github.com/llvm/llvm-project/pull/66915
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