[Lldb-commits] [clang] [lldb] [llvm] [llvm][TargetParser] Return StringMap from getHostCPUFeatures (PR #97824)
https://github.com/tmatheson-arm approved this pull request. https://github.com/llvm/llvm-project/pull/97824 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [lldb] [llvm] [llvm][TargetParser] Return optional from getHostCPUFeatures (PR #97824)
@@ -22,13 +22,13 @@ using namespace llvm;
int main(int argc, char **argv) {
#if defined(__i386__) || defined(_M_IX86) || \
defined(__x86_64__) || defined(_M_X64)
- if (std::optional> features =
+ if (const std::optional> features =
sys::getHostCPUFeatures(features)) {
-if ((*features)["sse"])
+if (features->contains("sse"))
tmatheson-arm wrote:
`contains` will only check if the key exists in the map, but you want to
actually get the `bool` if it exists and default to `false` if it doesn't. I
think `lookup` fits better.
https://github.com/llvm/llvm-project/pull/97824
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[Lldb-commits] [clang] [lldb] [llvm] [llvm][TargetParser] Return optional from getHostCPUFeatures (PR #97824)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/97824 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [lldb] [llvm] [llvm][TargetParser] Return optional from getHostCPUFeatures (PR #97824)
@@ -15,22 +15,23 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/TargetParser/Host.h"
+#include
+
using namespace llvm;
int main(int argc, char **argv) {
#if defined(__i386__) || defined(_M_IX86) || \
defined(__x86_64__) || defined(_M_X64)
- StringMap features;
-
- if (!sys::getHostCPUFeatures(features))
+ if (std::optional> features =
+ sys::getHostCPUFeatures(features)) {
+if ((*features)["sse"])
tmatheson-arm wrote:
Maybe
```suggestion
if (features->lookup("sse"))
```
which does the same, but doesn't insert the default entry into the map.
https://github.com/llvm/llvm-project/pull/97824
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[Lldb-commits] [clang] [lldb] [llvm] [llvm][TargetParser] Return optional from getHostCPUFeatures (PR #97824)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/97824 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [lldb] [llvm] [llvm][TargetParser] Return optional from getHostCPUFeatures (PR #97824)
https://github.com/tmatheson-arm approved this pull request. https://github.com/llvm/llvm-project/pull/97824 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [lldb] [llvm] [AArch64] move extension information into tablgen (PR #90987)
https://github.com/tmatheson-arm closed https://github.com/llvm/llvm-project/pull/90987 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [lldb] [llvm] [AArch64] move extension information into tablgen (PR #90987)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/90987
>From 4b8b776348438847c2eb238dac973e93fe93294e Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Mon, 29 Apr 2024 19:57:17 +0100
Subject: [PATCH 1/6] [AArch64] move extension information into tablgen
Generate target features and FMVExtensions from tablegen.
Use MArchName/ArchKindEnumSpelling to avoid renamings.
Cases where there is simply a case difference are handled by
consistently uppercasing the AEK_ name in the emitted code.
Remove some Extensions which were not needed.
These had AEK entries but were never actually used for anything.
They are not present in Extensions[] data.
---
.../command-disassemble-aarch64-extensions.s | 2 +-
.../llvm/TargetParser/AArch64TargetParser.h | 139 +--
llvm/lib/Target/AArch64/AArch64Features.td| 216 ++
.../TargetParser/TargetParserTest.cpp | 8 +-
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 60 -
5 files changed, 236 insertions(+), 189 deletions(-)
diff --git a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
index e154f544e7cc6..685d0a84ec289 100644
--- a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
+++ b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
@@ -59,7 +59,7 @@ fn:
bdep z0.b, z1.b, z31.b// AEK_SVE2BITPERM
rax1 z0.d, z0.d, z0.d // AEK_SVE2SHA3
sm4e z0.s, z0.s, z0.s // AEK_SVE2SM4
- addqv v0.8h, p0, z0.h // AEK_SVE2p1 / AEK_SME2p1
+ addqv v0.8h, p0, z0.h // AEK_SVE2P1 / AEK_SME2P1
rcwswp x0, x1, [x2] // AEK_THE
tcommit // AEK_TME
lbl:
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 04fbaf07adfbc..1124420daf8d8 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -104,29 +104,9 @@ static_assert(FEAT_MAX < 62,
"Number of features in CPUFeatures are limited to 62 entries");
// Each ArchExtKind correponds directly to a possible -target-feature.
-enum ArchExtKind : unsigned {
- AEK_NONE = 1,
-#define ARM_EXTENSION(NAME, ENUM) ENUM,
+#define EMIT_ARCHEXTKIND_ENUM
#include "llvm/TargetParser/AArch64TargetParserDef.inc"
- AEK_NUM_EXTENSIONS,
-
- // FIXME temporary fixes for inconsistent naming.
- AEK_F32MM = AEK_MATMULFP32,
- AEK_F64MM = AEK_MATMULFP64,
- AEK_FCMA = AEK_COMPLXNUM,
- AEK_FP = AEK_FPARMV8,
- AEK_FP16 = AEK_FULLFP16,
- AEK_I8MM = AEK_MATMULINT8,
- AEK_JSCVT = AEK_JS,
- AEK_PROFILE = AEK_SPE,
- AEK_RASv2 = AEK_RASV2,
- AEK_RAND = AEK_RANDGEN,
- AEK_SIMD = AEK_NEON,
- AEK_SME2p1 = AEK_SME2P1,
- AEK_SVE2p1 = AEK_SVE2P1,
- AEK_SME_LUTv2 = AEK_SME_LUTV2,
-};
using ExtensionBitset = Bitset;
// Represents an extension that can be enabled with -march=+.
@@ -148,111 +128,8 @@ struct ExtensionInfo {
1000; // Maximum priority for FMV feature
};
-// NOTE: If adding a new extension here, consider adding it to ExtensionMap
-// in AArch64AsmParser too, if supported as an extension name by binutils.
-// clang-format off
-inline constexpr ExtensionInfo Extensions[] = {
-{"aes", AArch64::AEK_AES, "+aes", "-aes", FEAT_AES, "+fp-armv8,+neon",
150},
-{"b16b16", AArch64::AEK_B16B16, "+b16b16", "-b16b16", FEAT_INIT, "", 0},
-{"bf16", AArch64::AEK_BF16, "+bf16", "-bf16", FEAT_BF16, "+bf16", 280},
-{"brbe", AArch64::AEK_BRBE, "+brbe", "-brbe", FEAT_INIT, "", 0},
-{"bti", AArch64::AEK_NONE, {}, {}, FEAT_BTI, "+bti", 510},
-{"crc", AArch64::AEK_CRC, "+crc", "-crc", FEAT_CRC, "+crc", 110},
-{"crypto", AArch64::AEK_CRYPTO, "+crypto", "-crypto", FEAT_INIT,
"+aes,+sha2", 0},
-{"cssc", AArch64::AEK_CSSC, "+cssc", "-cssc", FEAT_INIT, "", 0},
-{"d128", AArch64::AEK_D128, "+d128", "-d128", FEAT_INIT, "", 0},
-{"dgh", AArch64::AEK_NONE, {}, {}, FEAT_DGH, "", 260},
-{"dit", AArch64::AEK_NONE, {}, {}, FEAT_DIT, "+dit", 180},
-{"dotprod", AArch64::AEK_DOTPROD, "+dotprod", "-dotprod", FEAT_DOTPROD,
"+dotprod,+fp-armv8,+neon", 104},
-{"dpb", AArch64::AEK_NONE, {}, {}, FEAT_DPB, "+ccpp", 190},
-{"dpb2", AArch64::AEK_NONE, {}, {}, FEAT_DPB2, "+ccpp,+ccdp", 200},
-{"ebf16", AArch64::AEK_NONE, {}, {}, FEAT_EBF16, "+bf16", 290},
-{"f32mm", AArch64::AEK_F32MM, "+f32mm", "-f32mm", FEAT_SVE_F32MM,
"+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350},
-{"f64mm", AArch64::AEK_F64MM, "+f64mm", "-f64mm", FEAT_SVE_F64MM,
"+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360},
-{"fcma", AArch64::AEK_FCMA, "+complxnum", "-complxnum", FEAT_FCMA,
"+fp-armv8,+neon,+complxnum", 220},
-{"flagm", AArch64::AEK_FLAGM, "+flagm", "-flagm", FEAT_FLAGM, "+flagm",
20},
-{"flagm2", AArch64::AEK_NONE, {}, {}, FEAT_FLAGM2,
[Lldb-commits] [lldb] [llvm] [AArch64] move extension information into tablgen (PR #90987)
@@ -426,30 +532,40 @@ def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", "true", "Enable architectural speculation restriction (FEAT_CSV2_2)">; def FeatureSB : Extension<"sb", "SB", - "Enable v8.5 Speculation Barrier (FEAT_SB)" >; + "Enable v8.5 Speculation Barrier (FEAT_SB)", [], + "FEAT_SB", "+sb", 470>; def FeatureSSBS : Extension<"ssbs", "SSBS", - "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)" >; + "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)", [], + "FEAT_SSBS", "", 490>; def FeaturePredRes : Extension<"predres", "PredRes", - "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)" >; + "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)", [], + "FEAT_PREDRES", "+predres", 480>; -def FeatureCacheDeepPersist : Extension<"ccdp", "CCDP", +def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "CCDP", "true", "Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >; +// NOTE: BTI now has posfeat/negfeat, which it didn't before +let ArchExtKindSpelling = "AEK_NONE" in def FeatureBranchTargetId : Extension<"bti", "BTI", -"Enable Branch Target Identification (FEAT_BTI)" >; +"Enable Branch Target Identification (FEAT_BTI)", [], +"FEAT_BTI", "+bti", 510>; +let ArchExtKindSpelling = "AEK_RAND", MArchName = "rng" in def FeatureRandGen : Extension<"rand", "RandGen", -"Enable Random Number generation instructions (FEAT_RNG)" >; +"Enable Random Number generation instructions (FEAT_RNG)", [], +"FEAT_RNG", "+rand", 10>; +let MArchName = "memtag" in def FeatureMTE : Extension<"mte", "MTE", -"Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)" >; +"Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)", [], +"FEAT_MEMTAG", "", 440>; tmatheson-arm wrote: Good point. There should be no behaviour change here caused by this patch. I've added a comment in f1d287a75139bd8a09ee9d596b10aa77a2b672b7 explaining that `"memtag"` means different things for FMV and non-FMV extensions. I've left the `SubtargetFeature` description as-is because I think it is most likely to be used for printing command line help in the future, and the FMV difference will not be relevant there. https://github.com/llvm/llvm-project/pull/90987 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [llvm] [AArch64] move extension information into tablgen (PR #90987)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/90987
>From 4b8b776348438847c2eb238dac973e93fe93294e Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Mon, 29 Apr 2024 19:57:17 +0100
Subject: [PATCH 1/5] [AArch64] move extension information into tablgen
Generate target features and FMVExtensions from tablegen.
Use MArchName/ArchKindEnumSpelling to avoid renamings.
Cases where there is simply a case difference are handled by
consistently uppercasing the AEK_ name in the emitted code.
Remove some Extensions which were not needed.
These had AEK entries but were never actually used for anything.
They are not present in Extensions[] data.
---
.../command-disassemble-aarch64-extensions.s | 2 +-
.../llvm/TargetParser/AArch64TargetParser.h | 139 +--
llvm/lib/Target/AArch64/AArch64Features.td| 216 ++
.../TargetParser/TargetParserTest.cpp | 8 +-
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 60 -
5 files changed, 236 insertions(+), 189 deletions(-)
diff --git a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
index e154f544e7cc6..685d0a84ec289 100644
--- a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
+++ b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
@@ -59,7 +59,7 @@ fn:
bdep z0.b, z1.b, z31.b// AEK_SVE2BITPERM
rax1 z0.d, z0.d, z0.d // AEK_SVE2SHA3
sm4e z0.s, z0.s, z0.s // AEK_SVE2SM4
- addqv v0.8h, p0, z0.h // AEK_SVE2p1 / AEK_SME2p1
+ addqv v0.8h, p0, z0.h // AEK_SVE2P1 / AEK_SME2P1
rcwswp x0, x1, [x2] // AEK_THE
tcommit // AEK_TME
lbl:
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 04fbaf07adfbc..1124420daf8d8 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -104,29 +104,9 @@ static_assert(FEAT_MAX < 62,
"Number of features in CPUFeatures are limited to 62 entries");
// Each ArchExtKind correponds directly to a possible -target-feature.
-enum ArchExtKind : unsigned {
- AEK_NONE = 1,
-#define ARM_EXTENSION(NAME, ENUM) ENUM,
+#define EMIT_ARCHEXTKIND_ENUM
#include "llvm/TargetParser/AArch64TargetParserDef.inc"
- AEK_NUM_EXTENSIONS,
-
- // FIXME temporary fixes for inconsistent naming.
- AEK_F32MM = AEK_MATMULFP32,
- AEK_F64MM = AEK_MATMULFP64,
- AEK_FCMA = AEK_COMPLXNUM,
- AEK_FP = AEK_FPARMV8,
- AEK_FP16 = AEK_FULLFP16,
- AEK_I8MM = AEK_MATMULINT8,
- AEK_JSCVT = AEK_JS,
- AEK_PROFILE = AEK_SPE,
- AEK_RASv2 = AEK_RASV2,
- AEK_RAND = AEK_RANDGEN,
- AEK_SIMD = AEK_NEON,
- AEK_SME2p1 = AEK_SME2P1,
- AEK_SVE2p1 = AEK_SVE2P1,
- AEK_SME_LUTv2 = AEK_SME_LUTV2,
-};
using ExtensionBitset = Bitset;
// Represents an extension that can be enabled with -march=+.
@@ -148,111 +128,8 @@ struct ExtensionInfo {
1000; // Maximum priority for FMV feature
};
-// NOTE: If adding a new extension here, consider adding it to ExtensionMap
-// in AArch64AsmParser too, if supported as an extension name by binutils.
-// clang-format off
-inline constexpr ExtensionInfo Extensions[] = {
-{"aes", AArch64::AEK_AES, "+aes", "-aes", FEAT_AES, "+fp-armv8,+neon",
150},
-{"b16b16", AArch64::AEK_B16B16, "+b16b16", "-b16b16", FEAT_INIT, "", 0},
-{"bf16", AArch64::AEK_BF16, "+bf16", "-bf16", FEAT_BF16, "+bf16", 280},
-{"brbe", AArch64::AEK_BRBE, "+brbe", "-brbe", FEAT_INIT, "", 0},
-{"bti", AArch64::AEK_NONE, {}, {}, FEAT_BTI, "+bti", 510},
-{"crc", AArch64::AEK_CRC, "+crc", "-crc", FEAT_CRC, "+crc", 110},
-{"crypto", AArch64::AEK_CRYPTO, "+crypto", "-crypto", FEAT_INIT,
"+aes,+sha2", 0},
-{"cssc", AArch64::AEK_CSSC, "+cssc", "-cssc", FEAT_INIT, "", 0},
-{"d128", AArch64::AEK_D128, "+d128", "-d128", FEAT_INIT, "", 0},
-{"dgh", AArch64::AEK_NONE, {}, {}, FEAT_DGH, "", 260},
-{"dit", AArch64::AEK_NONE, {}, {}, FEAT_DIT, "+dit", 180},
-{"dotprod", AArch64::AEK_DOTPROD, "+dotprod", "-dotprod", FEAT_DOTPROD,
"+dotprod,+fp-armv8,+neon", 104},
-{"dpb", AArch64::AEK_NONE, {}, {}, FEAT_DPB, "+ccpp", 190},
-{"dpb2", AArch64::AEK_NONE, {}, {}, FEAT_DPB2, "+ccpp,+ccdp", 200},
-{"ebf16", AArch64::AEK_NONE, {}, {}, FEAT_EBF16, "+bf16", 290},
-{"f32mm", AArch64::AEK_F32MM, "+f32mm", "-f32mm", FEAT_SVE_F32MM,
"+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350},
-{"f64mm", AArch64::AEK_F64MM, "+f64mm", "-f64mm", FEAT_SVE_F64MM,
"+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360},
-{"fcma", AArch64::AEK_FCMA, "+complxnum", "-complxnum", FEAT_FCMA,
"+fp-armv8,+neon,+complxnum", 220},
-{"flagm", AArch64::AEK_FLAGM, "+flagm", "-flagm", FEAT_FLAGM, "+flagm",
20},
-{"flagm2", AArch64::AEK_NONE, {}, {}, FEAT_FLAGM2,
[Lldb-commits] [lldb] [llvm] [AArch64] move extension information into tablgen (PR #90987)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/90987
>From 4b8b776348438847c2eb238dac973e93fe93294e Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Mon, 29 Apr 2024 19:57:17 +0100
Subject: [PATCH 1/4] [AArch64] move extension information into tablgen
Generate target features and FMVExtensions from tablegen.
Use MArchName/ArchKindEnumSpelling to avoid renamings.
Cases where there is simply a case difference are handled by
consistently uppercasing the AEK_ name in the emitted code.
Remove some Extensions which were not needed.
These had AEK entries but were never actually used for anything.
They are not present in Extensions[] data.
---
.../command-disassemble-aarch64-extensions.s | 2 +-
.../llvm/TargetParser/AArch64TargetParser.h | 139 +--
llvm/lib/Target/AArch64/AArch64Features.td| 216 ++
.../TargetParser/TargetParserTest.cpp | 8 +-
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 60 -
5 files changed, 236 insertions(+), 189 deletions(-)
diff --git a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
index e154f544e7cc6..685d0a84ec289 100644
--- a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
+++ b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
@@ -59,7 +59,7 @@ fn:
bdep z0.b, z1.b, z31.b// AEK_SVE2BITPERM
rax1 z0.d, z0.d, z0.d // AEK_SVE2SHA3
sm4e z0.s, z0.s, z0.s // AEK_SVE2SM4
- addqv v0.8h, p0, z0.h // AEK_SVE2p1 / AEK_SME2p1
+ addqv v0.8h, p0, z0.h // AEK_SVE2P1 / AEK_SME2P1
rcwswp x0, x1, [x2] // AEK_THE
tcommit // AEK_TME
lbl:
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 04fbaf07adfbc..1124420daf8d8 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -104,29 +104,9 @@ static_assert(FEAT_MAX < 62,
"Number of features in CPUFeatures are limited to 62 entries");
// Each ArchExtKind correponds directly to a possible -target-feature.
-enum ArchExtKind : unsigned {
- AEK_NONE = 1,
-#define ARM_EXTENSION(NAME, ENUM) ENUM,
+#define EMIT_ARCHEXTKIND_ENUM
#include "llvm/TargetParser/AArch64TargetParserDef.inc"
- AEK_NUM_EXTENSIONS,
-
- // FIXME temporary fixes for inconsistent naming.
- AEK_F32MM = AEK_MATMULFP32,
- AEK_F64MM = AEK_MATMULFP64,
- AEK_FCMA = AEK_COMPLXNUM,
- AEK_FP = AEK_FPARMV8,
- AEK_FP16 = AEK_FULLFP16,
- AEK_I8MM = AEK_MATMULINT8,
- AEK_JSCVT = AEK_JS,
- AEK_PROFILE = AEK_SPE,
- AEK_RASv2 = AEK_RASV2,
- AEK_RAND = AEK_RANDGEN,
- AEK_SIMD = AEK_NEON,
- AEK_SME2p1 = AEK_SME2P1,
- AEK_SVE2p1 = AEK_SVE2P1,
- AEK_SME_LUTv2 = AEK_SME_LUTV2,
-};
using ExtensionBitset = Bitset;
// Represents an extension that can be enabled with -march=+.
@@ -148,111 +128,8 @@ struct ExtensionInfo {
1000; // Maximum priority for FMV feature
};
-// NOTE: If adding a new extension here, consider adding it to ExtensionMap
-// in AArch64AsmParser too, if supported as an extension name by binutils.
-// clang-format off
-inline constexpr ExtensionInfo Extensions[] = {
-{"aes", AArch64::AEK_AES, "+aes", "-aes", FEAT_AES, "+fp-armv8,+neon",
150},
-{"b16b16", AArch64::AEK_B16B16, "+b16b16", "-b16b16", FEAT_INIT, "", 0},
-{"bf16", AArch64::AEK_BF16, "+bf16", "-bf16", FEAT_BF16, "+bf16", 280},
-{"brbe", AArch64::AEK_BRBE, "+brbe", "-brbe", FEAT_INIT, "", 0},
-{"bti", AArch64::AEK_NONE, {}, {}, FEAT_BTI, "+bti", 510},
-{"crc", AArch64::AEK_CRC, "+crc", "-crc", FEAT_CRC, "+crc", 110},
-{"crypto", AArch64::AEK_CRYPTO, "+crypto", "-crypto", FEAT_INIT,
"+aes,+sha2", 0},
-{"cssc", AArch64::AEK_CSSC, "+cssc", "-cssc", FEAT_INIT, "", 0},
-{"d128", AArch64::AEK_D128, "+d128", "-d128", FEAT_INIT, "", 0},
-{"dgh", AArch64::AEK_NONE, {}, {}, FEAT_DGH, "", 260},
-{"dit", AArch64::AEK_NONE, {}, {}, FEAT_DIT, "+dit", 180},
-{"dotprod", AArch64::AEK_DOTPROD, "+dotprod", "-dotprod", FEAT_DOTPROD,
"+dotprod,+fp-armv8,+neon", 104},
-{"dpb", AArch64::AEK_NONE, {}, {}, FEAT_DPB, "+ccpp", 190},
-{"dpb2", AArch64::AEK_NONE, {}, {}, FEAT_DPB2, "+ccpp,+ccdp", 200},
-{"ebf16", AArch64::AEK_NONE, {}, {}, FEAT_EBF16, "+bf16", 290},
-{"f32mm", AArch64::AEK_F32MM, "+f32mm", "-f32mm", FEAT_SVE_F32MM,
"+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350},
-{"f64mm", AArch64::AEK_F64MM, "+f64mm", "-f64mm", FEAT_SVE_F64MM,
"+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360},
-{"fcma", AArch64::AEK_FCMA, "+complxnum", "-complxnum", FEAT_FCMA,
"+fp-armv8,+neon,+complxnum", 220},
-{"flagm", AArch64::AEK_FLAGM, "+flagm", "-flagm", FEAT_FLAGM, "+flagm",
20},
-{"flagm2", AArch64::AEK_NONE, {}, {}, FEAT_FLAGM2,
[Lldb-commits] [lldb] [llvm] [AArch64] move extension information into tablgen (PR #90987)
@@ -426,30 +532,40 @@ def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", "true", "Enable architectural speculation restriction (FEAT_CSV2_2)">; def FeatureSB : Extension<"sb", "SB", - "Enable v8.5 Speculation Barrier (FEAT_SB)" >; + "Enable v8.5 Speculation Barrier (FEAT_SB)", [], + "FEAT_SB", "+sb", 470>; def FeatureSSBS : Extension<"ssbs", "SSBS", - "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)" >; + "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)", [], + "FEAT_SSBS", "", 490>; def FeaturePredRes : Extension<"predres", "PredRes", - "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)" >; + "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)", [], + "FEAT_PREDRES", "+predres", 480>; -def FeatureCacheDeepPersist : Extension<"ccdp", "CCDP", +def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "CCDP", "true", "Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >; +// NOTE: BTI now has posfeat/negfeat, which it didn't before +let ArchExtKindSpelling = "AEK_NONE" in def FeatureBranchTargetId : Extension<"bti", "BTI", -"Enable Branch Target Identification (FEAT_BTI)" >; +"Enable Branch Target Identification (FEAT_BTI)", [], +"FEAT_BTI", "+bti", 510>; tmatheson-arm wrote: Yes that would work, in a separate PR though. https://github.com/llvm/llvm-project/pull/90987 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [llvm] [AArch64] move extension information into tablgen (PR #90987)
@@ -11,42 +11,123 @@
// A SubtargetFeature that can be toggled from the command line, and therefore
// has an AEK_* entry in ArmExtKind.
+//
+// If Function MultiVersioning (FMV) properties are left at their defaults
+// (FEAT_INIT, no dependencies, priority 0) it indiates that this extension is
+// not an FMV feature, but can be enabled via the command line (-march, -mcpu,
+// etc).
+//
+// Conversely if the ArchExtKindSpelling is set to AEK_NONE, this indicates
+// that a feature is FMV-only, and can not be selected on the command line.
+// Such extensions should be added via FMVOnlyExtension.
class Extension<
- string TargetFeatureName,// String used for -target-feature.
+ string TargetFeatureName,// String used for -target-feature and
-march, unless overridden.
string Spelling, // The XYZ in HasXYZ and AEK_XYZ.
string Desc, // Description.
- list Implies = [] // List of dependent features.
+ list Implies = [], // List of dependent features.
+ // FMV properties
+ string _FMVBit = "FEAT_INIT",// FEAT_INIT is repurposed to indicate
"not an FMV feature"
+ string _FMVDependencies = "",
+ int _FMVPriority = 0
> : SubtargetFeature Implies>
{
string ArchExtKindSpelling = "AEK_" # Spelling; // ArchExtKind enum name.
+
+// In general, the name written on the command line should match the name
+// used for -target-feature. However, there are exceptions. Therefore we
+// add a separate field for this, to allow overriding it. Strongly prefer
+// not doing so.
+string MArchName = TargetFeatureName;
+
+// Function MultiVersioning (FMV) properties
+
+// A C++ expression giving the number of the bit in the FMV ABI.
+// Currently this is given as a value from the enum "CPUFeatures".
+// If this is not set, it indicates that this is not an FMV extension.
+string FMVBit = _FMVBit;
+
+// List of features that this feature depends on.
+// FIXME generate this from Implies.
tmatheson-arm wrote:
That would require the FMV dependencies being aligned with the existing
`SubtargetFeature` dependencies, which I believe is being considered but is a
WIP.
https://github.com/llvm/llvm-project/pull/90987
___
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[Lldb-commits] [clang] [lldb] [llvm] [AArch64][TargetParser] autogen ArchExtKind enum - renaming (PR #90320)
https://github.com/tmatheson-arm closed https://github.com/llvm/llvm-project/pull/90320 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [lldb] [llvm] [AArch64][TargetParser] autogen ArchExtKind enum - renaming (PR #90320)
tmatheson-arm wrote: Thanks for the comments everyone. Given that this requires an IR break and additions to the importer, and there is still some question about which way to go with the renaming (i.e. FEAT_ names or user-facing names) I think it makes sense to defer renaming until later. For now, I will add mechanisms to handle the various inconsistencies as in https://github.com/llvm/llvm-project/pull/90987. https://github.com/llvm/llvm-project/pull/90320 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [llvm] [AArch64] move extension information into tablgen (PR #90987)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/90987
>From 4b8b776348438847c2eb238dac973e93fe93294e Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Mon, 29 Apr 2024 19:57:17 +0100
Subject: [PATCH 1/3] [AArch64] move extension information into tablgen
Generate target features and FMVExtensions from tablegen.
Use MArchName/ArchKindEnumSpelling to avoid renamings.
Cases where there is simply a case difference are handled by
consistently uppercasing the AEK_ name in the emitted code.
Remove some Extensions which were not needed.
These had AEK entries but were never actually used for anything.
They are not present in Extensions[] data.
---
.../command-disassemble-aarch64-extensions.s | 2 +-
.../llvm/TargetParser/AArch64TargetParser.h | 139 +--
llvm/lib/Target/AArch64/AArch64Features.td| 216 ++
.../TargetParser/TargetParserTest.cpp | 8 +-
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 60 -
5 files changed, 236 insertions(+), 189 deletions(-)
diff --git a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
index e154f544e7cc6..685d0a84ec289 100644
--- a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
+++ b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
@@ -59,7 +59,7 @@ fn:
bdep z0.b, z1.b, z31.b// AEK_SVE2BITPERM
rax1 z0.d, z0.d, z0.d // AEK_SVE2SHA3
sm4e z0.s, z0.s, z0.s // AEK_SVE2SM4
- addqv v0.8h, p0, z0.h // AEK_SVE2p1 / AEK_SME2p1
+ addqv v0.8h, p0, z0.h // AEK_SVE2P1 / AEK_SME2P1
rcwswp x0, x1, [x2] // AEK_THE
tcommit // AEK_TME
lbl:
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 04fbaf07adfbc..1124420daf8d8 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -104,29 +104,9 @@ static_assert(FEAT_MAX < 62,
"Number of features in CPUFeatures are limited to 62 entries");
// Each ArchExtKind correponds directly to a possible -target-feature.
-enum ArchExtKind : unsigned {
- AEK_NONE = 1,
-#define ARM_EXTENSION(NAME, ENUM) ENUM,
+#define EMIT_ARCHEXTKIND_ENUM
#include "llvm/TargetParser/AArch64TargetParserDef.inc"
- AEK_NUM_EXTENSIONS,
-
- // FIXME temporary fixes for inconsistent naming.
- AEK_F32MM = AEK_MATMULFP32,
- AEK_F64MM = AEK_MATMULFP64,
- AEK_FCMA = AEK_COMPLXNUM,
- AEK_FP = AEK_FPARMV8,
- AEK_FP16 = AEK_FULLFP16,
- AEK_I8MM = AEK_MATMULINT8,
- AEK_JSCVT = AEK_JS,
- AEK_PROFILE = AEK_SPE,
- AEK_RASv2 = AEK_RASV2,
- AEK_RAND = AEK_RANDGEN,
- AEK_SIMD = AEK_NEON,
- AEK_SME2p1 = AEK_SME2P1,
- AEK_SVE2p1 = AEK_SVE2P1,
- AEK_SME_LUTv2 = AEK_SME_LUTV2,
-};
using ExtensionBitset = Bitset;
// Represents an extension that can be enabled with -march=+.
@@ -148,111 +128,8 @@ struct ExtensionInfo {
1000; // Maximum priority for FMV feature
};
-// NOTE: If adding a new extension here, consider adding it to ExtensionMap
-// in AArch64AsmParser too, if supported as an extension name by binutils.
-// clang-format off
-inline constexpr ExtensionInfo Extensions[] = {
-{"aes", AArch64::AEK_AES, "+aes", "-aes", FEAT_AES, "+fp-armv8,+neon",
150},
-{"b16b16", AArch64::AEK_B16B16, "+b16b16", "-b16b16", FEAT_INIT, "", 0},
-{"bf16", AArch64::AEK_BF16, "+bf16", "-bf16", FEAT_BF16, "+bf16", 280},
-{"brbe", AArch64::AEK_BRBE, "+brbe", "-brbe", FEAT_INIT, "", 0},
-{"bti", AArch64::AEK_NONE, {}, {}, FEAT_BTI, "+bti", 510},
-{"crc", AArch64::AEK_CRC, "+crc", "-crc", FEAT_CRC, "+crc", 110},
-{"crypto", AArch64::AEK_CRYPTO, "+crypto", "-crypto", FEAT_INIT,
"+aes,+sha2", 0},
-{"cssc", AArch64::AEK_CSSC, "+cssc", "-cssc", FEAT_INIT, "", 0},
-{"d128", AArch64::AEK_D128, "+d128", "-d128", FEAT_INIT, "", 0},
-{"dgh", AArch64::AEK_NONE, {}, {}, FEAT_DGH, "", 260},
-{"dit", AArch64::AEK_NONE, {}, {}, FEAT_DIT, "+dit", 180},
-{"dotprod", AArch64::AEK_DOTPROD, "+dotprod", "-dotprod", FEAT_DOTPROD,
"+dotprod,+fp-armv8,+neon", 104},
-{"dpb", AArch64::AEK_NONE, {}, {}, FEAT_DPB, "+ccpp", 190},
-{"dpb2", AArch64::AEK_NONE, {}, {}, FEAT_DPB2, "+ccpp,+ccdp", 200},
-{"ebf16", AArch64::AEK_NONE, {}, {}, FEAT_EBF16, "+bf16", 290},
-{"f32mm", AArch64::AEK_F32MM, "+f32mm", "-f32mm", FEAT_SVE_F32MM,
"+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350},
-{"f64mm", AArch64::AEK_F64MM, "+f64mm", "-f64mm", FEAT_SVE_F64MM,
"+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360},
-{"fcma", AArch64::AEK_FCMA, "+complxnum", "-complxnum", FEAT_FCMA,
"+fp-armv8,+neon,+complxnum", 220},
-{"flagm", AArch64::AEK_FLAGM, "+flagm", "-flagm", FEAT_FLAGM, "+flagm",
20},
-{"flagm2", AArch64::AEK_NONE, {}, {}, FEAT_FLAGM2,
[Lldb-commits] [lldb] [llvm] [AArch64] move extension information into tablgen (PR #90987)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/90987
>From 4b8b776348438847c2eb238dac973e93fe93294e Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Mon, 29 Apr 2024 19:57:17 +0100
Subject: [PATCH 1/3] [AArch64] move extension information into tablgen
Generate target features and FMVExtensions from tablegen.
Use MArchName/ArchKindEnumSpelling to avoid renamings.
Cases where there is simply a case difference are handled by
consistently uppercasing the AEK_ name in the emitted code.
Remove some Extensions which were not needed.
These had AEK entries but were never actually used for anything.
They are not present in Extensions[] data.
---
.../command-disassemble-aarch64-extensions.s | 2 +-
.../llvm/TargetParser/AArch64TargetParser.h | 139 +--
llvm/lib/Target/AArch64/AArch64Features.td| 216 ++
.../TargetParser/TargetParserTest.cpp | 8 +-
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 60 -
5 files changed, 236 insertions(+), 189 deletions(-)
diff --git a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
index e154f544e7cc6e..685d0a84ec2896 100644
--- a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
+++ b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
@@ -59,7 +59,7 @@ fn:
bdep z0.b, z1.b, z31.b// AEK_SVE2BITPERM
rax1 z0.d, z0.d, z0.d // AEK_SVE2SHA3
sm4e z0.s, z0.s, z0.s // AEK_SVE2SM4
- addqv v0.8h, p0, z0.h // AEK_SVE2p1 / AEK_SME2p1
+ addqv v0.8h, p0, z0.h // AEK_SVE2P1 / AEK_SME2P1
rcwswp x0, x1, [x2] // AEK_THE
tcommit // AEK_TME
lbl:
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 04fbaf07adfbcb..1124420daf8d80 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -104,29 +104,9 @@ static_assert(FEAT_MAX < 62,
"Number of features in CPUFeatures are limited to 62 entries");
// Each ArchExtKind correponds directly to a possible -target-feature.
-enum ArchExtKind : unsigned {
- AEK_NONE = 1,
-#define ARM_EXTENSION(NAME, ENUM) ENUM,
+#define EMIT_ARCHEXTKIND_ENUM
#include "llvm/TargetParser/AArch64TargetParserDef.inc"
- AEK_NUM_EXTENSIONS,
-
- // FIXME temporary fixes for inconsistent naming.
- AEK_F32MM = AEK_MATMULFP32,
- AEK_F64MM = AEK_MATMULFP64,
- AEK_FCMA = AEK_COMPLXNUM,
- AEK_FP = AEK_FPARMV8,
- AEK_FP16 = AEK_FULLFP16,
- AEK_I8MM = AEK_MATMULINT8,
- AEK_JSCVT = AEK_JS,
- AEK_PROFILE = AEK_SPE,
- AEK_RASv2 = AEK_RASV2,
- AEK_RAND = AEK_RANDGEN,
- AEK_SIMD = AEK_NEON,
- AEK_SME2p1 = AEK_SME2P1,
- AEK_SVE2p1 = AEK_SVE2P1,
- AEK_SME_LUTv2 = AEK_SME_LUTV2,
-};
using ExtensionBitset = Bitset;
// Represents an extension that can be enabled with -march=+.
@@ -148,111 +128,8 @@ struct ExtensionInfo {
1000; // Maximum priority for FMV feature
};
-// NOTE: If adding a new extension here, consider adding it to ExtensionMap
-// in AArch64AsmParser too, if supported as an extension name by binutils.
-// clang-format off
-inline constexpr ExtensionInfo Extensions[] = {
-{"aes", AArch64::AEK_AES, "+aes", "-aes", FEAT_AES, "+fp-armv8,+neon",
150},
-{"b16b16", AArch64::AEK_B16B16, "+b16b16", "-b16b16", FEAT_INIT, "", 0},
-{"bf16", AArch64::AEK_BF16, "+bf16", "-bf16", FEAT_BF16, "+bf16", 280},
-{"brbe", AArch64::AEK_BRBE, "+brbe", "-brbe", FEAT_INIT, "", 0},
-{"bti", AArch64::AEK_NONE, {}, {}, FEAT_BTI, "+bti", 510},
-{"crc", AArch64::AEK_CRC, "+crc", "-crc", FEAT_CRC, "+crc", 110},
-{"crypto", AArch64::AEK_CRYPTO, "+crypto", "-crypto", FEAT_INIT,
"+aes,+sha2", 0},
-{"cssc", AArch64::AEK_CSSC, "+cssc", "-cssc", FEAT_INIT, "", 0},
-{"d128", AArch64::AEK_D128, "+d128", "-d128", FEAT_INIT, "", 0},
-{"dgh", AArch64::AEK_NONE, {}, {}, FEAT_DGH, "", 260},
-{"dit", AArch64::AEK_NONE, {}, {}, FEAT_DIT, "+dit", 180},
-{"dotprod", AArch64::AEK_DOTPROD, "+dotprod", "-dotprod", FEAT_DOTPROD,
"+dotprod,+fp-armv8,+neon", 104},
-{"dpb", AArch64::AEK_NONE, {}, {}, FEAT_DPB, "+ccpp", 190},
-{"dpb2", AArch64::AEK_NONE, {}, {}, FEAT_DPB2, "+ccpp,+ccdp", 200},
-{"ebf16", AArch64::AEK_NONE, {}, {}, FEAT_EBF16, "+bf16", 290},
-{"f32mm", AArch64::AEK_F32MM, "+f32mm", "-f32mm", FEAT_SVE_F32MM,
"+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350},
-{"f64mm", AArch64::AEK_F64MM, "+f64mm", "-f64mm", FEAT_SVE_F64MM,
"+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360},
-{"fcma", AArch64::AEK_FCMA, "+complxnum", "-complxnum", FEAT_FCMA,
"+fp-armv8,+neon,+complxnum", 220},
-{"flagm", AArch64::AEK_FLAGM, "+flagm", "-flagm", FEAT_FLAGM, "+flagm",
20},
-{"flagm2", AArch64::AEK_NONE, {}, {}, FEAT_FLAGM2,
[Lldb-commits] [lldb] [llvm] [AArch64] move extension information into tablgen (PR #90987)
https://github.com/tmatheson-arm created
https://github.com/llvm/llvm-project/pull/90987
Generate target features and FMVExtensions from tablegen.
Use MArchName/ArchKindEnumSpelling to avoid renamings.
Cases where there is simply a case difference are handled by
consistently uppercasing the AEK_ name in the emitted code.
Remove some Extensions which were not needed.
These had AEK entries but were never actually used for anything.
They are not present in Extensions[] data.
>From 4b8b776348438847c2eb238dac973e93fe93294e Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Mon, 29 Apr 2024 19:57:17 +0100
Subject: [PATCH 1/2] [AArch64] move extension information into tablgen
Generate target features and FMVExtensions from tablegen.
Use MArchName/ArchKindEnumSpelling to avoid renamings.
Cases where there is simply a case difference are handled by
consistently uppercasing the AEK_ name in the emitted code.
Remove some Extensions which were not needed.
These had AEK entries but were never actually used for anything.
They are not present in Extensions[] data.
---
.../command-disassemble-aarch64-extensions.s | 2 +-
.../llvm/TargetParser/AArch64TargetParser.h | 139 +--
llvm/lib/Target/AArch64/AArch64Features.td| 216 ++
.../TargetParser/TargetParserTest.cpp | 8 +-
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 60 -
5 files changed, 236 insertions(+), 189 deletions(-)
diff --git a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
index e154f544e7cc6e..685d0a84ec2896 100644
--- a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
+++ b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
@@ -59,7 +59,7 @@ fn:
bdep z0.b, z1.b, z31.b// AEK_SVE2BITPERM
rax1 z0.d, z0.d, z0.d // AEK_SVE2SHA3
sm4e z0.s, z0.s, z0.s // AEK_SVE2SM4
- addqv v0.8h, p0, z0.h // AEK_SVE2p1 / AEK_SME2p1
+ addqv v0.8h, p0, z0.h // AEK_SVE2P1 / AEK_SME2P1
rcwswp x0, x1, [x2] // AEK_THE
tcommit // AEK_TME
lbl:
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 04fbaf07adfbcb..1124420daf8d80 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -104,29 +104,9 @@ static_assert(FEAT_MAX < 62,
"Number of features in CPUFeatures are limited to 62 entries");
// Each ArchExtKind correponds directly to a possible -target-feature.
-enum ArchExtKind : unsigned {
- AEK_NONE = 1,
-#define ARM_EXTENSION(NAME, ENUM) ENUM,
+#define EMIT_ARCHEXTKIND_ENUM
#include "llvm/TargetParser/AArch64TargetParserDef.inc"
- AEK_NUM_EXTENSIONS,
-
- // FIXME temporary fixes for inconsistent naming.
- AEK_F32MM = AEK_MATMULFP32,
- AEK_F64MM = AEK_MATMULFP64,
- AEK_FCMA = AEK_COMPLXNUM,
- AEK_FP = AEK_FPARMV8,
- AEK_FP16 = AEK_FULLFP16,
- AEK_I8MM = AEK_MATMULINT8,
- AEK_JSCVT = AEK_JS,
- AEK_PROFILE = AEK_SPE,
- AEK_RASv2 = AEK_RASV2,
- AEK_RAND = AEK_RANDGEN,
- AEK_SIMD = AEK_NEON,
- AEK_SME2p1 = AEK_SME2P1,
- AEK_SVE2p1 = AEK_SVE2P1,
- AEK_SME_LUTv2 = AEK_SME_LUTV2,
-};
using ExtensionBitset = Bitset;
// Represents an extension that can be enabled with -march=+.
@@ -148,111 +128,8 @@ struct ExtensionInfo {
1000; // Maximum priority for FMV feature
};
-// NOTE: If adding a new extension here, consider adding it to ExtensionMap
-// in AArch64AsmParser too, if supported as an extension name by binutils.
-// clang-format off
-inline constexpr ExtensionInfo Extensions[] = {
-{"aes", AArch64::AEK_AES, "+aes", "-aes", FEAT_AES, "+fp-armv8,+neon",
150},
-{"b16b16", AArch64::AEK_B16B16, "+b16b16", "-b16b16", FEAT_INIT, "", 0},
-{"bf16", AArch64::AEK_BF16, "+bf16", "-bf16", FEAT_BF16, "+bf16", 280},
-{"brbe", AArch64::AEK_BRBE, "+brbe", "-brbe", FEAT_INIT, "", 0},
-{"bti", AArch64::AEK_NONE, {}, {}, FEAT_BTI, "+bti", 510},
-{"crc", AArch64::AEK_CRC, "+crc", "-crc", FEAT_CRC, "+crc", 110},
-{"crypto", AArch64::AEK_CRYPTO, "+crypto", "-crypto", FEAT_INIT,
"+aes,+sha2", 0},
-{"cssc", AArch64::AEK_CSSC, "+cssc", "-cssc", FEAT_INIT, "", 0},
-{"d128", AArch64::AEK_D128, "+d128", "-d128", FEAT_INIT, "", 0},
-{"dgh", AArch64::AEK_NONE, {}, {}, FEAT_DGH, "", 260},
-{"dit", AArch64::AEK_NONE, {}, {}, FEAT_DIT, "+dit", 180},
-{"dotprod", AArch64::AEK_DOTPROD, "+dotprod", "-dotprod", FEAT_DOTPROD,
"+dotprod,+fp-armv8,+neon", 104},
-{"dpb", AArch64::AEK_NONE, {}, {}, FEAT_DPB, "+ccpp", 190},
-{"dpb2", AArch64::AEK_NONE, {}, {}, FEAT_DPB2, "+ccpp,+ccdp", 200},
-{"ebf16", AArch64::AEK_NONE, {}, {}, FEAT_EBF16, "+bf16", 290},
-{"f32mm", AArch64::AEK_F32MM, "+f32mm", "-f32mm", FEAT_SVE_F32MM,
[Lldb-commits] [clang] [lldb] [llvm] [AArch64][TargetParser] autogen ArchExtKind enum - renaming (PR #90320)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/90320 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang] [lldb] [llvm] [AArch64][TargetParser] autogen ArchExtKind enum - renaming (PR #90320)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/90320 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [clang] [llvm] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/75947
>From d3201659d87260acaf1d20a96705e290caf21693 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/test/Preprocessor/aarch64-target-features.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index db89aa7b608ad5..b3da54162da04b 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -600,6 +600,7 @@
// RUN: %clang -target aarch64-none-elf -march=armv9.1-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.2-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.3-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
+// RUN: %clang -target aarch64-none-elf -march=armv9.4-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.5-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// CHECK-V81-OR-LATER: __ARM_FEATURE_ATOMICS 1
// CHECK-V85-OR-LATER: __ARM_FEATURE_BTI 1
>From 1d4208d53830e0ef8dadad9be12e7ef2b53c6190 Mon Sep 17 00:00:00 2001
From: Oliver Stannard
Date: Wed, 1 Feb 2023 18:16:07 +
Subject: [PATCH 2/3] [AArch64] Add FEAT_PAuthLR assembler support
Add assembly/disassembly support for the new PAuthLR instructions
introduced in Armv9.5-A:
- AUTIASPPC/AUTIBSPPC
- PACIASPPC/PACIBSPPC
- PACNBIASPPC/PACNBIBSPPC
- RETAASPPC/RETABSPPC
- PACM
Documentation for these instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions/
---
llvm/lib/Target/AArch64/AArch64.td| 7 +-
.../lib/Target/AArch64/AArch64InstrFormats.td | 74 +
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 39 +
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp| 28
.../Disassembler/AArch64Disassembler.cpp | 18 +++
.../MCTargetDesc/AArch64AsmBackend.cpp| 14 ++
.../MCTargetDesc/AArch64ELFObjectWriter.cpp | 4 +
.../AArch64/MCTargetDesc/AArch64FixupKinds.h | 5 +
.../MCTargetDesc/AArch64MCCodeEmitter.cpp | 28
.../MC/AArch64/armv9.5a-pauthlr-diagnostics.s | 57 +++
llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s | 12 ++
llvm/test/MC/AArch64/armv9.5a-pauthlr.s | 151 ++
.../Disassembler/AArch64/armv9.5a-pauthlr.txt | 78 +
15 files changed, 516 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr.s
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-pauthlr.txt
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index c600bcaab2b3ea..95e171109b4eb0 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -622,6 +622,11 @@ def FeatureLdpAlignedOnly :
SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only",
"HasStpAlignedOnly",
"true", "In order to emit stp, first check if the store will be aligned to
2 * element_size">;
+// AArch64 2023 Architecture Extensions (v9.5-A)
+
+def FeaturePAuthLR : SubtargetFeature<"pauth-lr", "HasPAuthLR",
+"true", "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
+
//===--===//
// Architectures.
//
@@ -807,7 +812,7 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
-let F = [HasPAuth] in
+let F = [HasPAuth, HasPAuthLR] in
def PAUnsupported : AArch64Unsupported;
include "AArch64SchedA53.td"
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 68e87f491a09e4..92bf9f4ec2a21b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -2368,6 +2368,80 @@ class ClearAuth data, string asm>
let Inst{4-0} = Rd;
}
+// v9.5-A FEAT_PAuth_LR
+
+class SignAuthFixedRegs opcode2, bits<6> opcode, string asm>
+ : I<(outs), (ins), asm, "", "", []>,
+Sched<[WriteI, ReadI]> {
+ let Inst{31} = 0b1; // sf
+ let Inst{30} = 0b1;
+ let Inst{29} = 0b0; // S
+ let Inst{28-21} =
[Lldb-commits] [lldb] 103bbdd - [ARM] Move Triple::getARMCPUForArch into ARMTargetParser
Author: Tomas Matheson
Date: 2022-11-09T11:52:35Z
New Revision: 103bbddde66f4157b52c2b6d7532c1dd0dfcaf94
URL:
https://github.com/llvm/llvm-project/commit/103bbddde66f4157b52c2b6d7532c1dd0dfcaf94
DIFF:
https://github.com/llvm/llvm-project/commit/103bbddde66f4157b52c2b6d7532c1dd0dfcaf94.diff
LOG: [ARM] Move Triple::getARMCPUForArch into ARMTargetParser
This is very backend specific so either belongs in Toolchains/ARM or in
ARMTargetParser. Since it is used in lldb, ARMTargetParser made more sense.
This is part of an effort to move information about ARM/AArch64 architecture
versions, extensions and CPUs into their respective TargetParsers.
Differential Revision: https://reviews.llvm.org/D137564
Added:
Modified:
clang/lib/Driver/ToolChains/Arch/ARM.cpp
lldb/source/Utility/ArchSpec.cpp
llvm/include/llvm/ADT/Triple.h
llvm/include/llvm/Support/ARMTargetParser.h
llvm/lib/Support/ARMTargetParser.cpp
llvm/lib/Support/Triple.cpp
llvm/unittests/ADT/TripleTest.cpp
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
index 67dec7cadada5..bbf466ba847de 100644
--- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -938,7 +938,7 @@ StringRef arm::getARMCPUForMArch(StringRef Arch, const
llvm::Triple ) {
// We need to return an empty string here on invalid MArch values as the
// various places that call this function can't cope with a null result.
- return Triple.getARMCPUForArch(MArch);
+ return llvm::ARM::getARMCPUForArch(Triple, MArch);
}
/// getARMTargetCPU - Get the (LLVM) name of the ARM cpu we are targeting.
@@ -971,7 +971,8 @@ llvm::ARM::ArchKind arm::getLLVMArchKindForARM(StringRef
CPU, StringRef Arch,
if (ArchKind == llvm::ARM::ArchKind::INVALID)
// In case of generic Arch, i.e. "arm",
// extract arch from default cpu of the Triple
- ArchKind = llvm::ARM::parseCPUArch(Triple.getARMCPUForArch(ARMArch));
+ ArchKind =
+ llvm::ARM::parseCPUArch(llvm::ARM::getARMCPUForArch(Triple,
ARMArch));
} else {
// FIXME: horrible hack to get around the fact that Cortex-A7 is only an
// armv7k triple if it's actually been specified via "-arch armv7k".
diff --git a/lldb/source/Utility/ArchSpec.cpp
b/lldb/source/Utility/ArchSpec.cpp
index 126bedc209232..e1d7ee3ee276d 100644
--- a/lldb/source/Utility/ArchSpec.cpp
+++ b/lldb/source/Utility/ArchSpec.cpp
@@ -16,6 +16,7 @@
#include "llvm/BinaryFormat/COFF.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/BinaryFormat/MachO.h"
+#include "llvm/Support/ARMTargetParser.h"
#include "llvm/Support/Compiler.h"
using namespace lldb;
@@ -638,7 +639,7 @@ std::string ArchSpec::GetClangTargetCPU() const {
}
if (GetTriple().isARM())
-cpu = GetTriple().getARMCPUForArch("").str();
+cpu = llvm::ARM::getARMCPUForArch(GetTriple(), "").str();
return cpu;
}
diff --git a/llvm/include/llvm/ADT/Triple.h b/llvm/include/llvm/ADT/Triple.h
index dc96398dba999..5aba2730c5a8b 100644
--- a/llvm/include/llvm/ADT/Triple.h
+++ b/llvm/include/llvm/ADT/Triple.h
@@ -1024,12 +1024,6 @@ class Triple {
/// architecture if no such variant can be found.
llvm::Triple getLittleEndianArchVariant() const;
- /// Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
- ///
- /// \param Arch the architecture name (e.g., "armv7s"). If it is an empty
- /// string then the triple's arch name is used.
- StringRef getARMCPUForArch(StringRef Arch = StringRef()) const;
-
/// Tests whether the target triple is little endian.
///
/// \returns true if the triple is little endian, false otherwise.
diff --git a/llvm/include/llvm/Support/ARMTargetParser.h
b/llvm/include/llvm/Support/ARMTargetParser.h
index 5fb4090395c07..32cc31db5936a 100644
--- a/llvm/include/llvm/Support/ARMTargetParser.h
+++ b/llvm/include/llvm/Support/ARMTargetParser.h
@@ -296,6 +296,12 @@ unsigned parseArchVersion(StringRef Arch);
void fillValidCPUArchList(SmallVectorImpl );
StringRef computeDefaultTargetABI(const Triple , StringRef CPU);
+/// Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
+///
+/// \param Arch the architecture name (e.g., "armv7s"). If it is an empty
+/// string then the triple's arch name is used.
+StringRef getARMCPUForArch(const llvm::Triple , StringRef MArch = {});
+
} // namespace ARM
} // namespace llvm
diff --git a/llvm/lib/Support/ARMTargetParser.cpp
b/llvm/lib/Support/ARMTargetParser.cpp
index a68244a5e38af..43cbb409b0f04 100644
--- a/llvm/lib/Support/ARMTargetParser.cpp
+++ b/llvm/lib/Support/ARMTargetParser.cpp
@@ -643,3 +643,72 @@ StringRef ARM::computeDefaultTargetABI(const Triple ,
StringRef CPU) {
return "aapcs";
}
}
+
+StringRef ARM::getARMCPUForArch(const
