[Lldb-commits] [PATCH] D100192: [lldb][Arm/AArch64] Add basic disassemble tests for Arm/AArch64
This revision was automatically updated to reflect the committed changes. Closed by commit rG96c82166b6e3: [lldb][Arm/AArch64] Add basic disassemble tests for Arm/AArch64 (authored by DavidSpickett). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100192/new/ https://reviews.llvm.org/D100192 Files: lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py Index: lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py === --- lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py +++ lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py @@ -32,6 +32,12 @@ elif re.match("powerpc64le", arch): target = self.dbg.CreateTargetWithFileAndTargetTriple("", "powerpc64le") raw_bytes = bytearray([0x00, 0x00, 0x80, 0x38]) +elif arch == "aarch64": +target = self.dbg.CreateTargetWithFileAndTargetTriple("", "aarch64") +raw_bytes = bytearray([0x60, 0x0c, 0x80, 0x52]) +elif arch == "arm": +target = self.dbg.CreateTargetWithFileAndTargetTriple("", "arm") +raw_bytes = bytearray([0x63, 0x30, 0xa0, 0xe3]) else: target = self.dbg.CreateTargetWithFileAndTargetTriple("", "x86_64") raw_bytes = bytearray([0x48, 0x89, 0xe5]) @@ -52,6 +58,12 @@ elif re.match("powerpc64le", arch): self.assertEqual(inst.GetMnemonic(target), "li") self.assertEqual(inst.GetOperands(target), "4, 0") +elif arch == "aarch64": +self.assertEqual(inst.GetMnemonic(target), "mov") +self.assertEqual(inst.GetOperands(target), "w0, #0x63") +elif arch == "arm": +self.assertEqual(inst.GetMnemonic(target), "mov") +self.assertEqual(inst.GetOperands(target), "r3, #99") else: self.assertEqual(inst.GetMnemonic(target), "movq") self.assertEqual(inst.GetOperands(target), Index: lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py === --- lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py +++ lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py @@ -32,6 +32,12 @@ elif re.match("powerpc64le", arch): target = self.dbg.CreateTargetWithFileAndTargetTriple("", "powerpc64le") raw_bytes = bytearray([0x00, 0x00, 0x80, 0x38]) +elif arch == "aarch64": +target = self.dbg.CreateTargetWithFileAndTargetTriple("", "aarch64") +raw_bytes = bytearray([0x60, 0x0c, 0x80, 0x52]) +elif arch == "arm": +target = self.dbg.CreateTargetWithFileAndTargetTriple("", "arm") +raw_bytes = bytearray([0x63, 0x30, 0xa0, 0xe3]) else: target = self.dbg.CreateTargetWithFileAndTargetTriple("", "x86_64") raw_bytes = bytearray([0x48, 0x89, 0xe5]) @@ -52,6 +58,12 @@ elif re.match("powerpc64le", arch): self.assertEqual(inst.GetMnemonic(target), "li") self.assertEqual(inst.GetOperands(target), "4, 0") +elif arch == "aarch64": +self.assertEqual(inst.GetMnemonic(target), "mov") +self.assertEqual(inst.GetOperands(target), "w0, #0x63") +elif arch == "arm": +self.assertEqual(inst.GetMnemonic(target), "mov") +self.assertEqual(inst.GetOperands(target), "r3, #99") else: self.assertEqual(inst.GetMnemonic(target), "movq") self.assertEqual(inst.GetOperands(target), ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] D100192: [lldb][Arm/AArch64] Add basic disassemble tests for Arm/AArch64
DavidSpickett created this revision. Herald added subscribers: danielkiss, pengfei, kristof.beyls. DavidSpickett requested review of this revision. Herald added a project: LLDB. Herald added a subscriber: lldb-commits. Previously the test would fail if you built on Arm/AArch64 but did not have the x86 llvm backend enabled. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D100192 Files: lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py Index: lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py === --- lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py +++ lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py @@ -32,6 +32,12 @@ elif re.match("powerpc64le", arch): target = self.dbg.CreateTargetWithFileAndTargetTriple("", "powerpc64le") raw_bytes = bytearray([0x00, 0x00, 0x80, 0x38]) +elif arch == "aarch64": +target = self.dbg.CreateTargetWithFileAndTargetTriple("", "aarch64") +raw_bytes = bytearray([0x60, 0x0c, 0x80, 0x52]) +elif arch == "arm": +target = self.dbg.CreateTargetWithFileAndTargetTriple("", "arm") +raw_bytes = bytearray([0x63, 0x30, 0xa0, 0xe3]) else: target = self.dbg.CreateTargetWithFileAndTargetTriple("", "x86_64") raw_bytes = bytearray([0x48, 0x89, 0xe5]) @@ -52,6 +58,12 @@ elif re.match("powerpc64le", arch): self.assertEqual(inst.GetMnemonic(target), "li") self.assertEqual(inst.GetOperands(target), "4, 0") +elif arch == "aarch64": +self.assertEqual(inst.GetMnemonic(target), "mov") +self.assertEqual(inst.GetOperands(target), "w0, #0x63") +elif arch == "arm": +self.assertEqual(inst.GetMnemonic(target), "mov") +self.assertEqual(inst.GetOperands(target), "r3, #99") else: self.assertEqual(inst.GetMnemonic(target), "movq") self.assertEqual(inst.GetOperands(target), Index: lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py === --- lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py +++ lldb/test/API/python_api/disassemble-raw-data/TestDisassembleRawData.py @@ -32,6 +32,12 @@ elif re.match("powerpc64le", arch): target = self.dbg.CreateTargetWithFileAndTargetTriple("", "powerpc64le") raw_bytes = bytearray([0x00, 0x00, 0x80, 0x38]) +elif arch == "aarch64": +target = self.dbg.CreateTargetWithFileAndTargetTriple("", "aarch64") +raw_bytes = bytearray([0x60, 0x0c, 0x80, 0x52]) +elif arch == "arm": +target = self.dbg.CreateTargetWithFileAndTargetTriple("", "arm") +raw_bytes = bytearray([0x63, 0x30, 0xa0, 0xe3]) else: target = self.dbg.CreateTargetWithFileAndTargetTriple("", "x86_64") raw_bytes = bytearray([0x48, 0x89, 0xe5]) @@ -52,6 +58,12 @@ elif re.match("powerpc64le", arch): self.assertEqual(inst.GetMnemonic(target), "li") self.assertEqual(inst.GetOperands(target), "4, 0") +elif arch == "aarch64": +self.assertEqual(inst.GetMnemonic(target), "mov") +self.assertEqual(inst.GetOperands(target), "w0, #0x63") +elif arch == "arm": +self.assertEqual(inst.GetMnemonic(target), "mov") +self.assertEqual(inst.GetOperands(target), "r3, #99") else: self.assertEqual(inst.GetMnemonic(target), "movq") self.assertEqual(inst.GetOperands(target), ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits