Re: [Lldb-commits] [PATCH] D12670: [LLDB][MIPS] MIPS load/store instruction emulation for hardware watchpoints
This revision was automatically updated to reflect the committed changes.
Closed by commit rL247129: [LLDB][MIPS] MIPS load/store instruction emulation
for hardware watchpoints (authored by mohit.bhakkad).
Changed prior to commit:
http://reviews.llvm.org/D12670?vs=34132&id=34308#toc
Repository:
rL LLVM
http://reviews.llvm.org/D12670
Files:
lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
Index: lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
===
--- lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
+++ lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
@@ -131,6 +131,12 @@
Emulate_LW (llvm::MCInst& insn);
bool
+Emulate_LDST_Imm (llvm::MCInst& insn);
+
+bool
+Emulate_LDST_Reg (llvm::MCInst& insn);
+
+bool
Emulate_BEQ (llvm::MCInst& insn);
bool
Index: lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
===
--- lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
+++ lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
@@ -411,6 +411,64 @@
{ "LW", &EmulateInstructionMIPS::Emulate_LW, "LW rt,offset(base)" },
//--
+// Load/Store instructions
+//--
+/* Following list of emulated instructions are required by implementation of hardware watchpoint
+ for MIPS in lldb. As we just need the address accessed by instructions, we have generalised
+ all these instructions in 2 functions depending on their addressing modes */
+
+{ "LB", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LBrt, offset(base)" },
+{ "LBE",&EmulateInstructionMIPS::Emulate_LDST_Imm, "LBE rt, offset(base)" },
+{ "LBU",&EmulateInstructionMIPS::Emulate_LDST_Imm, "LBU rt, offset(base)" },
+{ "LBUE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LBUE rt, offset(base)" },
+{ "LDC1", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LDC1 ft, offset(base)" },
+{ "LD", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LDrt, offset(base)" },
+{ "LDL",&EmulateInstructionMIPS::Emulate_LDST_Imm, "LDL rt, offset(base)" },
+{ "LDR",&EmulateInstructionMIPS::Emulate_LDST_Imm, "LDR rt, offset(base)" },
+{ "LLD",&EmulateInstructionMIPS::Emulate_LDST_Imm, "LLD rt, offset(base)" },
+{ "LDC2", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LDC2 rt, offset(base)" },
+{ "LDXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg, "LDXC1 fd, index (base)" },
+{ "LH", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LHrt, offset(base)" },
+{ "LHE",&EmulateInstructionMIPS::Emulate_LDST_Imm, "LHE rt, offset(base)" },
+{ "LHU",&EmulateInstructionMIPS::Emulate_LDST_Imm, "LHU rt, offset(base)" },
+{ "LHUE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LHUE rt, offset(base)" },
+{ "LL", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LLrt, offset(base)" },
+{ "LLE",&EmulateInstructionMIPS::Emulate_LDST_Imm, "LLE rt, offset(base)" },
+{ "LUXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg, "LUXC1 fd, index (base)" },
+{ "LW", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWrt, offset(base)" },
+{ "LWC1", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWC1 ft, offset(base)" },
+{ "LWC2", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWC2 rt, offset(base)" },
+{ "LWE",&EmulateInstructionMIPS::Emulate_LDST_Imm, "LWE rt, offset(base)" },
+{ "LWL",&EmulateInstructionMIPS::Emulate_LDST_Imm, "LWL rt, offset(base)" },
+{ "LWLE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWLE rt, offset(base)" },
+{ "LWR",&EmulateInstructionMIPS::Emulate_LDST_Imm, "LWR rt, offset(base)" },
+{ "LWRE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWRE rt, offset(base)" },
+{ "LWXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg, "LWXC1 fd, index (base)" },
+
+{ "SB", &EmulateInstructionMIPS::Emulate_LDST_Imm,
[Lldb-commits] [PATCH] D12670: [LLDB][MIPS] MIPS load/store instruction emulation for hardware watchpoints
mohit.bhakkad created this revision.
mohit.bhakkad added a reviewer: clayborg.
mohit.bhakkad added subscribers: jaydeep, bhushan, sagar, nitesh.jain,
lldb-commits.
mohit.bhakkad set the repository for this revision to rL LLVM.
Emulate MIPS32/64 load and store instructions for HW watchpoints.
Repository:
rL LLVM
http://reviews.llvm.org/D12670
Files:
source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
===
--- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
+++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
@@ -128,13 +128,13 @@
Emulate_SD (llvm::MCInst& insn);
bool
-Emulate_SW (llvm::MCInst& insn);
+Emulate_LD (llvm::MCInst& insn);
bool
-Emulate_LW (llvm::MCInst& insn);
+Emulate_LDST_Imm (llvm::MCInst& insn);
bool
-Emulate_LD (llvm::MCInst& insn);
+Emulate_LDST_Reg (llvm::MCInst& insn);
bool
Emulate_BEQ (llvm::MCInst& insn);
Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
===
--- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
+++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
@@ -486,8 +486,65 @@
{ "SD", &EmulateInstructionMIPS64::Emulate_SD, "SD rt,offset(rs)" },
{ "LD", &EmulateInstructionMIPS64::Emulate_LD, "LD rt,offset(base)"},
-{ "SW", &EmulateInstructionMIPS64::Emulate_SW, "SW rt,offset(rs)" },
-{ "LW", &EmulateInstructionMIPS64::Emulate_LW, "LW rt,offset(rs)" },
+
+
+
+//--
+// Load/Store instructions
+//--
+/* Following list of emulated instructions are required by implementation of hardware watchpoint
+ for MIPS in lldb. As we just need the address accessed by instructions, we have generalised
+ all these instructions in 2 functions depending on their addressing modes */
+
+{ "LB", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LBrt, offset(base)" },
+{ "LBE",&EmulateInstructionMIPS64::Emulate_LDST_Imm, "LBE rt, offset(base)" },
+{ "LBU",&EmulateInstructionMIPS64::Emulate_LDST_Imm, "LBU rt, offset(base)" },
+{ "LBUE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LBUE rt, offset(base)" },
+{ "LDC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LDC1 ft, offset(base)" },
+{ "LDL",&EmulateInstructionMIPS64::Emulate_LDST_Imm, "LDL rt, offset(base)" },
+{ "LDR",&EmulateInstructionMIPS64::Emulate_LDST_Imm, "LDR rt, offset(base)" },
+{ "LLD",&EmulateInstructionMIPS64::Emulate_LDST_Imm, "LLD rt, offset(base)" },
+{ "LDC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LDC2 rt, offset(base)" },
+{ "LDXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, "LDXC1 fd, index (base)" },
+{ "LH", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LHrt, offset(base)" },
+{ "LHE",&EmulateInstructionMIPS64::Emulate_LDST_Imm, "LHE rt, offset(base)" },
+{ "LHU",&EmulateInstructionMIPS64::Emulate_LDST_Imm, "LHU rt, offset(base)" },
+{ "LHUE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LHUE rt, offset(base)" },
+{ "LL", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LLrt, offset(base)" },
+{ "LLE",&EmulateInstructionMIPS64::Emulate_LDST_Imm, "LLE rt, offset(base)" },
+{ "LUXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, "LUXC1 fd, index (base)" },
+{ "LW", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWrt, offset(rs)" },
+{ "LWC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWC1 ft, offset(base)" },
+{ "LWC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWC2 rt, offset(base)" },
+{ "LWE",&EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWE rt, offset(base)" },
+{ "LWL",&EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWL rt, offset(base)" },
+{ "LWLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWLE rt, offset(base)" },
+{ "LWR",&EmulateInstructionMIPS64::Emulat
