[Lldb-commits] [PATCH] D137519: [LLDB] Add LoongArch software breakpoint trap opcode

2022-11-09 Thread Lu Weining via Phabricator via lldb-commits
This revision was automatically updated to reflect the committed changes.
Closed by commit rG97842fcba9e3: [LLDB] Add LoongArch software breakpoint trap 
opcode (authored by seehearfeel, committed by SixWeining).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137519/new/

https://reviews.llvm.org/D137519

Files:
  lldb/source/Host/common/NativeProcessProtocol.cpp
  lldb/source/Target/Platform.cpp


Index: lldb/source/Target/Platform.cpp
===
--- lldb/source/Target/Platform.cpp
+++ lldb/source/Target/Platform.cpp
@@ -1939,6 +1939,14 @@
 }
   } break;
 
+  case llvm::Triple::loongarch32:
+  case llvm::Triple::loongarch64: {
+static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a,
+ 0x00}; // break 0x5
+trap_opcode = g_loongarch_opcode;
+trap_opcode_size = sizeof(g_loongarch_opcode);
+  } break;
+
   default:
 return 0;
   }
Index: lldb/source/Host/common/NativeProcessProtocol.cpp
===
--- lldb/source/Host/common/NativeProcessProtocol.cpp
+++ lldb/source/Host/common/NativeProcessProtocol.cpp
@@ -507,6 +507,8 @@
   static const uint8_t g_ppcle_opcode[] = {0x08, 0x00, 0xe0, 0x7f}; // trap
   static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak
   static const uint8_t g_riscv_opcode_c[] = {0x02, 0x90};   // c.ebreak
+  static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a,
+   0x00}; // break 0x5
 
   switch (GetArchitecture().GetMachine()) {
   case llvm::Triple::aarch64:
@@ -541,6 +543,10 @@
   : llvm::makeArrayRef(g_riscv_opcode);
   }
 
+  case llvm::Triple::loongarch32:
+  case llvm::Triple::loongarch64:
+return llvm::makeArrayRef(g_loongarch_opcode);
+
   default:
 return llvm::createStringError(llvm::inconvertibleErrorCode(),
"CPU type not supported!");
@@ -567,6 +573,8 @@
   case llvm::Triple::ppc64le:
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64:
+  case llvm::Triple::loongarch32:
+  case llvm::Triple::loongarch64:
 // On these architectures the PC doesn't get updated for breakpoint hits.
 return 0;
 


Index: lldb/source/Target/Platform.cpp
===
--- lldb/source/Target/Platform.cpp
+++ lldb/source/Target/Platform.cpp
@@ -1939,6 +1939,14 @@
 }
   } break;
 
+  case llvm::Triple::loongarch32:
+  case llvm::Triple::loongarch64: {
+static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a,
+ 0x00}; // break 0x5
+trap_opcode = g_loongarch_opcode;
+trap_opcode_size = sizeof(g_loongarch_opcode);
+  } break;
+
   default:
 return 0;
   }
Index: lldb/source/Host/common/NativeProcessProtocol.cpp
===
--- lldb/source/Host/common/NativeProcessProtocol.cpp
+++ lldb/source/Host/common/NativeProcessProtocol.cpp
@@ -507,6 +507,8 @@
   static const uint8_t g_ppcle_opcode[] = {0x08, 0x00, 0xe0, 0x7f}; // trap
   static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak
   static const uint8_t g_riscv_opcode_c[] = {0x02, 0x90};   // c.ebreak
+  static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a,
+   0x00}; // break 0x5
 
   switch (GetArchitecture().GetMachine()) {
   case llvm::Triple::aarch64:
@@ -541,6 +543,10 @@
   : llvm::makeArrayRef(g_riscv_opcode);
   }
 
+  case llvm::Triple::loongarch32:
+  case llvm::Triple::loongarch64:
+return llvm::makeArrayRef(g_loongarch_opcode);
+
   default:
 return llvm::createStringError(llvm::inconvertibleErrorCode(),
"CPU type not supported!");
@@ -567,6 +573,8 @@
   case llvm::Triple::ppc64le:
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64:
+  case llvm::Triple::loongarch32:
+  case llvm::Triple::loongarch64:
 // On these architectures the PC doesn't get updated for breakpoint hits.
 return 0;
 
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[Lldb-commits] [PATCH] D137519: [LLDB] Add LoongArch software breakpoint trap opcode

2022-11-06 Thread Lu Weining via Phabricator via lldb-commits
SixWeining accepted this revision.
SixWeining added a comment.

LGTM.


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[Lldb-commits] [PATCH] D137519: [LLDB] Add LoongArch software breakpoint trap opcode

2022-11-06 Thread WÁNG Xuěruì via Phabricator via lldb-commits
xen0n accepted this revision.
xen0n added a comment.
This revision is now accepted and ready to land.

You removed the formatting in the commit message and added an extra space in 
front of the patch title, all fixed for you.

The changes look good LoongArch-wise now. Thanks!


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[Lldb-commits] [PATCH] D137519: [LLDB] Add LoongArch software breakpoint trap opcode

2022-11-06 Thread Tiezhu Yang via Phabricator via lldb-commits
seehearfeel updated this revision to Diff 473542.
seehearfeel retitled this revision from "[LLDB] Add LoongArch software 
breakpoint trap opcode" to " [LLDB] Add LoongArch software breakpoint trap 
opcode".
seehearfeel edited the summary of this revision.
seehearfeel added a comment.

Use "break 0x5" in the code comment.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137519/new/

https://reviews.llvm.org/D137519

Files:
  lldb/source/Host/common/NativeProcessProtocol.cpp
  lldb/source/Target/Platform.cpp


Index: lldb/source/Target/Platform.cpp
===
--- lldb/source/Target/Platform.cpp
+++ lldb/source/Target/Platform.cpp
@@ -1939,6 +1939,14 @@
 }
   } break;
 
+  case llvm::Triple::loongarch32:
+  case llvm::Triple::loongarch64: {
+static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a,
+ 0x00}; // break 0x5
+trap_opcode = g_loongarch_opcode;
+trap_opcode_size = sizeof(g_loongarch_opcode);
+  } break;
+
   default:
 return 0;
   }
Index: lldb/source/Host/common/NativeProcessProtocol.cpp
===
--- lldb/source/Host/common/NativeProcessProtocol.cpp
+++ lldb/source/Host/common/NativeProcessProtocol.cpp
@@ -507,6 +507,8 @@
   static const uint8_t g_ppcle_opcode[] = {0x08, 0x00, 0xe0, 0x7f}; // trap
   static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak
   static const uint8_t g_riscv_opcode_c[] = {0x02, 0x90};   // c.ebreak
+  static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a,
+   0x00}; // break 0x5
 
   switch (GetArchitecture().GetMachine()) {
   case llvm::Triple::aarch64:
@@ -541,6 +543,10 @@
   : llvm::makeArrayRef(g_riscv_opcode);
   }
 
+  case llvm::Triple::loongarch32:
+  case llvm::Triple::loongarch64:
+return llvm::makeArrayRef(g_loongarch_opcode);
+
   default:
 return llvm::createStringError(llvm::inconvertibleErrorCode(),
"CPU type not supported!");
@@ -567,6 +573,8 @@
   case llvm::Triple::ppc64le:
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64:
+  case llvm::Triple::loongarch32:
+  case llvm::Triple::loongarch64:
 // On these architectures the PC doesn't get updated for breakpoint hits.
 return 0;
 


Index: lldb/source/Target/Platform.cpp
===
--- lldb/source/Target/Platform.cpp
+++ lldb/source/Target/Platform.cpp
@@ -1939,6 +1939,14 @@
 }
   } break;
 
+  case llvm::Triple::loongarch32:
+  case llvm::Triple::loongarch64: {
+static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a,
+ 0x00}; // break 0x5
+trap_opcode = g_loongarch_opcode;
+trap_opcode_size = sizeof(g_loongarch_opcode);
+  } break;
+
   default:
 return 0;
   }
Index: lldb/source/Host/common/NativeProcessProtocol.cpp
===
--- lldb/source/Host/common/NativeProcessProtocol.cpp
+++ lldb/source/Host/common/NativeProcessProtocol.cpp
@@ -507,6 +507,8 @@
   static const uint8_t g_ppcle_opcode[] = {0x08, 0x00, 0xe0, 0x7f}; // trap
   static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak
   static const uint8_t g_riscv_opcode_c[] = {0x02, 0x90};   // c.ebreak
+  static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a,
+   0x00}; // break 0x5
 
   switch (GetArchitecture().GetMachine()) {
   case llvm::Triple::aarch64:
@@ -541,6 +543,10 @@
   : llvm::makeArrayRef(g_riscv_opcode);
   }
 
+  case llvm::Triple::loongarch32:
+  case llvm::Triple::loongarch64:
+return llvm::makeArrayRef(g_loongarch_opcode);
+
   default:
 return llvm::createStringError(llvm::inconvertibleErrorCode(),
"CPU type not supported!");
@@ -567,6 +573,8 @@
   case llvm::Triple::ppc64le:
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64:
+  case llvm::Triple::loongarch32:
+  case llvm::Triple::loongarch64:
 // On these architectures the PC doesn't get updated for breakpoint hits.
 return 0;
 
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