[Lldb-commits] [PATCH] D77045: Minor fixups to LLDB AArch64 register infos macros for SVE register infos

[Muhammad Omair Javaid via Phabricator via lldb-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG2bf6c50c7fe2: Minor fixups to LLDB AArch64 register infos 
macros for SVE register infos (authored by omjavaid).
Herald added a project: LLDB.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77045/new/

https://reviews.llvm.org/D77045

Files:
  lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h


Index: lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
@@ -456,37 +456,26 @@
 static uint32_t g_d30_invalidates[] = {fpu_v30, fpu_s30, LLDB_INVALID_REGNUM};
 static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
 
-// Generates register kinds array for 64-bit general purpose registers
-#define GPR64_KIND(reg, generic_kind)  
\
+// Generates register kinds array with DWARF, EH frame and generic kind
+#define MISC_KIND(reg, type, generic_kind) 
\
   {
\
 arm64_ehframe::reg, arm64_dwarf::reg, generic_kind, LLDB_INVALID_REGNUM,   
\
-gpr_##reg  
\
+type##_##reg   
\
   }
 
-// Generates register kinds array for registers with lldb kind
-#define MISC_KIND(lldb_kind)   
\
+// Generates register kinds array for registers with only lldb kind
+#define LLDB_KIND(lldb_kind)   
\
   {
\
 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 
\
 LLDB_INVALID_REGNUM, lldb_kind 
\
   }
 
 // Generates register kinds array for vector registers
-#define VREG_KIND(reg) 
\
-  {
\
-LLDB_INVALID_REGNUM, arm64_dwarf::reg, LLDB_INVALID_REGNUM,
\
-LLDB_INVALID_REGNUM, fpu_##reg 
\
-  }
-
-// Generates register kinds array for cpsr
-#define CPSR_KIND(lldb_kind)   
\
-  {
\
-arm64_ehframe::cpsr, arm64_dwarf::cpsr, LLDB_REGNUM_GENERIC_FLAGS, 
\
-LLDB_INVALID_REGNUM, lldb_kind 
\
-  }
-
-#define MISC_GPR_KIND(lldb_kind) CPSR_KIND(lldb_kind)
-#define MISC_FPU_KIND(lldb_kind) MISC_KIND(lldb_kind)
-#define MISC_EXC_KIND(lldb_kind) MISC_KIND(lldb_kind)
+#define GPR64_KIND(reg, generic_kind) MISC_KIND(reg, gpr, generic_kind)
+#define VREG_KIND(reg) MISC_KIND(reg, fpu, LLDB_INVALID_REGNUM)
+#define MISC_GPR_KIND(lldb_kind) MISC_KIND(cpsr, gpr, 
LLDB_REGNUM_GENERIC_FLAGS)
+#define MISC_FPU_KIND(lldb_kind) LLDB_KIND(lldb_kind)
+#define MISC_EXC_KIND(lldb_kind) LLDB_KIND(lldb_kind)
 
 // Defines a 64-bit general purpose register
 #define DEFINE_GPR64(reg, generic_kind)
\
@@ -509,7 +498,7 @@
   {
\
 #wreg, nullptr, 4, 
\
 GPR_OFFSET(gpr_##xreg) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,   
\
-lldb::eEncodingUint, lldb::eFormatHex, MISC_KIND(gpr_##wreg),  
\
+lldb::eEncodingUint, lldb::eFormatHex, LLDB_KIND(gpr_##wreg),  
\
 g_contained_##xreg, g_##wreg##_invalidates, nullptr, 0 
\
   }
 
@@ -525,7 +514,7 @@
 #define DEFINE_FPU_PSEUDO(reg, size, offset, vreg) 
\
   {
\
 #reg, nullptr, size, FPU_OFFSET(fpu_##vreg - fpu_v0) + offset, 
\
-lldb::eEncodingIEEE754, lldb::eFormatFloat, MISC_KIND(fpu_##reg),  
\
+lldb::eEncodingIEEE754, lldb::eFormatFloat, LLDB_KIND(fpu_##reg),  
\
 g_contained_##vreg, g_##reg##_invalidates, nullptr, 0  
\
   }
 


Index: lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
@@ -456,37 +456,26 @@
 static uint32_t g_d30_invalidates[] = {fpu_v30, fpu_s30, LLDB_INVALID_REGNUM};
 static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
 
-// Generat

[Lldb-commits] [PATCH] D77045: Minor fixups to LLDB AArch64 register infos macros for SVE register infos

[Muhammad Omair Javaid via Phabricator via lldb-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG2bf6c50c7fe2: Minor fixups to LLDB AArch64 register infos 
macros for SVE register infos (authored by omjavaid).
Herald added a project: LLDB.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77045/new/

https://reviews.llvm.org/D77045

Files:
  lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h


Index: lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
@@ -456,37 +456,26 @@
 static uint32_t g_d30_invalidates[] = {fpu_v30, fpu_s30, LLDB_INVALID_REGNUM};
 static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
 
-// Generates register kinds array for 64-bit general purpose registers
-#define GPR64_KIND(reg, generic_kind)  
\
+// Generates register kinds array with DWARF, EH frame and generic kind
+#define MISC_KIND(reg, type, generic_kind) 
\
   {
\
 arm64_ehframe::reg, arm64_dwarf::reg, generic_kind, LLDB_INVALID_REGNUM,   
\
-gpr_##reg  
\
+type##_##reg   
\
   }
 
-// Generates register kinds array for registers with lldb kind
-#define MISC_KIND(lldb_kind)   
\
+// Generates register kinds array for registers with only lldb kind
+#define LLDB_KIND(lldb_kind)   
\
   {
\
 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 
\
 LLDB_INVALID_REGNUM, lldb_kind 
\
   }
 
 // Generates register kinds array for vector registers
-#define VREG_KIND(reg) 
\
-  {
\
-LLDB_INVALID_REGNUM, arm64_dwarf::reg, LLDB_INVALID_REGNUM,
\
-LLDB_INVALID_REGNUM, fpu_##reg 
\
-  }
-
-// Generates register kinds array for cpsr
-#define CPSR_KIND(lldb_kind)   
\
-  {
\
-arm64_ehframe::cpsr, arm64_dwarf::cpsr, LLDB_REGNUM_GENERIC_FLAGS, 
\
-LLDB_INVALID_REGNUM, lldb_kind 
\
-  }
-
-#define MISC_GPR_KIND(lldb_kind) CPSR_KIND(lldb_kind)
-#define MISC_FPU_KIND(lldb_kind) MISC_KIND(lldb_kind)
-#define MISC_EXC_KIND(lldb_kind) MISC_KIND(lldb_kind)
+#define GPR64_KIND(reg, generic_kind) MISC_KIND(reg, gpr, generic_kind)
+#define VREG_KIND(reg) MISC_KIND(reg, fpu, LLDB_INVALID_REGNUM)
+#define MISC_GPR_KIND(lldb_kind) MISC_KIND(cpsr, gpr, 
LLDB_REGNUM_GENERIC_FLAGS)
+#define MISC_FPU_KIND(lldb_kind) LLDB_KIND(lldb_kind)
+#define MISC_EXC_KIND(lldb_kind) LLDB_KIND(lldb_kind)
 
 // Defines a 64-bit general purpose register
 #define DEFINE_GPR64(reg, generic_kind)
\
@@ -509,7 +498,7 @@
   {
\
 #wreg, nullptr, 4, 
\
 GPR_OFFSET(gpr_##xreg) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,   
\
-lldb::eEncodingUint, lldb::eFormatHex, MISC_KIND(gpr_##wreg),  
\
+lldb::eEncodingUint, lldb::eFormatHex, LLDB_KIND(gpr_##wreg),  
\
 g_contained_##xreg, g_##wreg##_invalidates, nullptr, 0 
\
   }
 
@@ -525,7 +514,7 @@
 #define DEFINE_FPU_PSEUDO(reg, size, offset, vreg) 
\
   {
\
 #reg, nullptr, size, FPU_OFFSET(fpu_##vreg - fpu_v0) + offset, 
\
-lldb::eEncodingIEEE754, lldb::eFormatFloat, MISC_KIND(fpu_##reg),  
\
+lldb::eEncodingIEEE754, lldb::eFormatFloat, LLDB_KIND(fpu_##reg),  
\
 g_contained_##vreg, g_##reg##_invalidates, nullptr, 0  
\
   }
 


Index: lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
@@ -456,37 +456,26 @@
 static uint32_t g_d30_invalidates[] = {fpu_v30, fpu_s30, LLDB_INVALID_REGNUM};
 static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
 
-// Generat

[Lldb-commits] [PATCH] D77045: Minor fixups to LLDB AArch64 register infos macros for SVE register infos

[Muhammad Omair Javaid via Phabricator via lldb-commits]

omjavaid updated this revision to Diff 271533.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77045/new/

https://reviews.llvm.org/D77045

Files:
  lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h


Index: lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
@@ -456,37 +456,26 @@
 static uint32_t g_d30_invalidates[] = {fpu_v30, fpu_s30, LLDB_INVALID_REGNUM};
 static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
 
-// Generates register kinds array for 64-bit general purpose registers
-#define GPR64_KIND(reg, generic_kind)  
\
+// Generates register kinds array with DWARF, EH frame and generic kind
+#define MISC_KIND(reg, type, generic_kind) 
\
   {
\
 arm64_ehframe::reg, arm64_dwarf::reg, generic_kind, LLDB_INVALID_REGNUM,   
\
-gpr_##reg  
\
+type##_##reg   
\
   }
 
-// Generates register kinds array for registers with lldb kind
-#define MISC_KIND(lldb_kind)   
\
+// Generates register kinds array for registers with only lldb kind
+#define LLDB_KIND(lldb_kind)   
\
   {
\
 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 
\
 LLDB_INVALID_REGNUM, lldb_kind 
\
   }
 
 // Generates register kinds array for vector registers
-#define VREG_KIND(reg) 
\
-  {
\
-LLDB_INVALID_REGNUM, arm64_dwarf::reg, LLDB_INVALID_REGNUM,
\
-LLDB_INVALID_REGNUM, fpu_##reg 
\
-  }
-
-// Generates register kinds array for cpsr
-#define CPSR_KIND(lldb_kind)   
\
-  {
\
-arm64_ehframe::cpsr, arm64_dwarf::cpsr, LLDB_REGNUM_GENERIC_FLAGS, 
\
-LLDB_INVALID_REGNUM, lldb_kind 
\
-  }
-
-#define MISC_GPR_KIND(lldb_kind) CPSR_KIND(lldb_kind)
-#define MISC_FPU_KIND(lldb_kind) MISC_KIND(lldb_kind)
-#define MISC_EXC_KIND(lldb_kind) MISC_KIND(lldb_kind)
+#define GPR64_KIND(reg, generic_kind) MISC_KIND(reg, gpr, generic_kind)
+#define VREG_KIND(reg) MISC_KIND(reg, fpu, LLDB_INVALID_REGNUM)
+#define MISC_GPR_KIND(lldb_kind) MISC_KIND(cpsr, gpr, 
LLDB_REGNUM_GENERIC_FLAGS)
+#define MISC_FPU_KIND(lldb_kind) LLDB_KIND(lldb_kind)
+#define MISC_EXC_KIND(lldb_kind) LLDB_KIND(lldb_kind)
 
 // Defines a 64-bit general purpose register
 #define DEFINE_GPR64(reg, generic_kind)
\
@@ -509,7 +498,7 @@
   {
\
 #wreg, nullptr, 4, 
\
 GPR_OFFSET(gpr_##xreg) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,   
\
-lldb::eEncodingUint, lldb::eFormatHex, MISC_KIND(gpr_##wreg),  
\
+lldb::eEncodingUint, lldb::eFormatHex, LLDB_KIND(gpr_##wreg),  
\
 g_contained_##xreg, g_##wreg##_invalidates, nullptr, 0 
\
   }
 
@@ -525,7 +514,7 @@
 #define DEFINE_FPU_PSEUDO(reg, size, offset, vreg) 
\
   {
\
 #reg, nullptr, size, FPU_OFFSET(fpu_##vreg - fpu_v0) + offset, 
\
-lldb::eEncodingIEEE754, lldb::eFormatFloat, MISC_KIND(fpu_##reg),  
\
+lldb::eEncodingIEEE754, lldb::eFormatFloat, LLDB_KIND(fpu_##reg),  
\
 g_contained_##vreg, g_##reg##_invalidates, nullptr, 0  
\
   }
 


Index: lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
@@ -456,37 +456,26 @@
 static uint32_t g_d30_invalidates[] = {fpu_v30, fpu_s30, LLDB_INVALID_REGNUM};
 static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
 
-// Generates register kinds array for 64-bit general purpose registers
-#define GPR64_KIND(reg, generic_kind)  \
+// Generates register kinds array with DWARF, EH frame and generic kind
+#define MIS

[Lldb-commits] [PATCH] D77045: Minor fixups to LLDB AArch64 register infos macros for SVE register infos

[Muhammad Omair Javaid via Phabricator via lldb-commits]

omjavaid updated this revision to Diff 263105.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77045/new/

https://reviews.llvm.org/D77045

Files:
  lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h


Index: lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
@@ -456,37 +456,26 @@
 static uint32_t g_d30_invalidates[] = {fpu_v30, fpu_s30, LLDB_INVALID_REGNUM};
 static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
 
-// Generates register kinds array for 64-bit general purpose registers
-#define GPR64_KIND(reg, generic_kind)  
\
+// Generates register kinds array with DWARF, EH frame and generic kind
+#define MISC_KIND(reg, type, generic_kind) 
\
   {
\
 arm64_ehframe::reg, arm64_dwarf::reg, generic_kind, LLDB_INVALID_REGNUM,   
\
-gpr_##reg  
\
+type##_##reg   
\
   }
 
-// Generates register kinds array for registers with lldb kind
-#define MISC_KIND(lldb_kind)   
\
+// Generates register kinds array for registers with only lldb kind
+#define LLDB_KIND(lldb_kind)   
\
   {
\
 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 
\
 LLDB_INVALID_REGNUM, lldb_kind 
\
   }
 
 // Generates register kinds array for vector registers
-#define VREG_KIND(reg) 
\
-  {
\
-LLDB_INVALID_REGNUM, arm64_dwarf::reg, LLDB_INVALID_REGNUM,
\
-LLDB_INVALID_REGNUM, fpu_##reg 
\
-  }
-
-// Generates register kinds array for cpsr
-#define CPSR_KIND(lldb_kind)   
\
-  {
\
-arm64_ehframe::cpsr, arm64_dwarf::cpsr, LLDB_REGNUM_GENERIC_FLAGS, 
\
-LLDB_INVALID_REGNUM, lldb_kind 
\
-  }
-
-#define MISC_GPR_KIND(lldb_kind) CPSR_KIND(lldb_kind)
-#define MISC_FPU_KIND(lldb_kind) MISC_KIND(lldb_kind)
-#define MISC_EXC_KIND(lldb_kind) MISC_KIND(lldb_kind)
+#define GPR64_KIND(reg, generic_kind) MISC_KIND(reg, gpr, generic_kind)
+#define VREG_KIND(reg) MISC_KIND(reg, fpu, LLDB_INVALID_REGNUM)
+#define MISC_GPR_KIND(lldb_kind) MISC_KIND(cpsr, gpr, 
LLDB_REGNUM_GENERIC_FLAGS)
+#define MISC_FPU_KIND(lldb_kind) LLDB_KIND(lldb_kind)
+#define MISC_EXC_KIND(lldb_kind) LLDB_KIND(lldb_kind)
 
 // Defines a 64-bit general purpose register
 #define DEFINE_GPR64(reg, generic_kind)
\
@@ -509,7 +498,7 @@
   {
\
 #wreg, nullptr, 4, 
\
 GPR_OFFSET(gpr_##xreg) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,   
\
-lldb::eEncodingUint, lldb::eFormatHex, MISC_KIND(gpr_##wreg),  
\
+lldb::eEncodingUint, lldb::eFormatHex, LLDB_KIND(gpr_##wreg),  
\
 g_contained_##xreg, g_##wreg##_invalidates, nullptr, 0 
\
   }
 
@@ -525,7 +514,7 @@
 #define DEFINE_FPU_PSEUDO(reg, size, offset, vreg) 
\
   {
\
 #reg, nullptr, size, FPU_OFFSET(fpu_##vreg - fpu_v0) + offset, 
\
-lldb::eEncodingIEEE754, lldb::eFormatFloat, MISC_KIND(fpu_##reg),  
\
+lldb::eEncodingIEEE754, lldb::eFormatFloat, LLDB_KIND(fpu_##reg),  
\
 g_contained_##vreg, g_##reg##_invalidates, nullptr, 0  
\
   }
 


Index: lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
===
--- lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
@@ -456,37 +456,26 @@
 static uint32_t g_d30_invalidates[] = {fpu_v30, fpu_s30, LLDB_INVALID_REGNUM};
 static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
 
-// Generates register kinds array for 64-bit general purpose registers
-#define GPR64_KIND(reg, generic_kind)  \
+// Generates register kinds array with DWARF, EH frame and generic kind
+#define MIS

[Lldb-commits] [PATCH] D77045: Minor fixups to LLDB AArch64 register infos macros for SVE register infos

[Muhammad Omair Javaid via Phabricator via lldb-commits]

omjavaid added a comment.

In D77045#1966540 , @omjavaid wrote:

> In D77045#1963896 , @labath wrote:
>
> > In D77045#1956879 , @omjavaid 
> > wrote:
> >
> > > Adding a testcase would be tricky as these register overlap in memory and 
> > > we store them with overlapping offsets with their children we should not 
> > > need to invalidate the children when we write the parent but for some 
> > > strange unexplainable reason QEMU was behaving strangely and not updating 
> > > the first half in certain random cases. I just thought invalidation of 
> > > children will force a read after write for that case.
> >
> >
> > Thanks for the explanation, but I'm afraid I still don't get what is going 
> > on here. Can you walk me through the individual steps here? Something like:
> >
> > 1. user does "register write x0 xx"
> > 2. lldb translates that to the appropriate `p` packet
> > 3. ???
> > 4. user does "register read w0"
> > 5. bad value comes out because...
>
>
> Let me debug it separately from SVE and I will get back to you with an update.


I have tried to figure this out and eventually problem disappeared after 
updating test environment. I could not really figure out the exact issue.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77045/new/

https://reviews.llvm.org/D77045



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