Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions
sagar closed this revision. sagar added a comment. Committed in revision 246745 Repository: rL LLVM http://reviews.llvm.org/D12356 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions
jaydeep accepted this revision. jaydeep added a comment. This revision is now accepted and ready to land. Looks good to me Repository: rL LLVM http://reviews.llvm.org/D12356 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions
tberghammer accepted this revision. tberghammer added a comment. LGTM Repository: rL LLVM http://reviews.llvm.org/D12356 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions
sagar updated this revision to Diff 33668.
sagar marked 4 inline comments as done.
sagar added a comment.
Corrected code indent and initialized wr_val correctly.
Repository:
rL LLVM
http://reviews.llvm.org/D12356
Files:
source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
===
--- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
+++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
@@ -302,6 +302,42 @@
Emulate_BC1ANY4T (llvm::MCInst& insn);
bool
+Emulate_BNZB (llvm::MCInst& insn);
+
+bool
+Emulate_BNZH (llvm::MCInst& insn);
+
+bool
+Emulate_BNZW (llvm::MCInst& insn);
+
+bool
+Emulate_BNZD (llvm::MCInst& insn);
+
+bool
+Emulate_BZB (llvm::MCInst& insn);
+
+bool
+Emulate_BZH (llvm::MCInst& insn);
+
+bool
+Emulate_BZW (llvm::MCInst& insn);
+
+bool
+Emulate_BZD (llvm::MCInst& insn);
+
+bool
+Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz);
+
+bool
+Emulate_BNZV (llvm::MCInst& insn);
+
+bool
+Emulate_BZV (llvm::MCInst& insn);
+
+bool
+Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz);
+
+bool
nonvolatile_reg_p (uint64_t regnum);
const char *
Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
===
--- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
+++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
@@ -221,41 +221,76 @@
{
switch (reg_num)
{
-case gcc_dwarf_sp_mips64: return "r29";
-case gcc_dwarf_r30_mips64: return "r30";
-case gcc_dwarf_ra_mips64: return "r31";
-case gcc_dwarf_f0_mips64: return "f0";
-case gcc_dwarf_f1_mips64: return "f1";
-case gcc_dwarf_f2_mips64: return "f2";
-case gcc_dwarf_f3_mips64: return "f3";
-case gcc_dwarf_f4_mips64: return "f4";
-case gcc_dwarf_f5_mips64: return "f5";
-case gcc_dwarf_f6_mips64: return "f6";
-case gcc_dwarf_f7_mips64: return "f7";
-case gcc_dwarf_f8_mips64: return "f8";
-case gcc_dwarf_f9_mips64: return "f9";
-case gcc_dwarf_f10_mips64: return "f10";
-case gcc_dwarf_f11_mips64: return "f11";
-case gcc_dwarf_f12_mips64: return "f12";
-case gcc_dwarf_f13_mips64: return "f13";
-case gcc_dwarf_f14_mips64: return "f14";
-case gcc_dwarf_f15_mips64: return "f15";
-case gcc_dwarf_f16_mips64: return "f16";
-case gcc_dwarf_f17_mips64: return "f17";
-case gcc_dwarf_f18_mips64: return "f18";
-case gcc_dwarf_f19_mips64: return "f19";
-case gcc_dwarf_f20_mips64: return "f20";
-case gcc_dwarf_f21_mips64: return "f21";
-case gcc_dwarf_f22_mips64: return "f22";
-case gcc_dwarf_f23_mips64: return "f23";
-case gcc_dwarf_f24_mips64: return "f24";
-case gcc_dwarf_f25_mips64: return "f25";
-case gcc_dwarf_f26_mips64: return "f26";
-case gcc_dwarf_f27_mips64: return "f27";
-case gcc_dwarf_f28_mips64: return "f28";
-case gcc_dwarf_f29_mips64: return "f29";
-case gcc_dwarf_f30_mips64: return "f30";
-case gcc_dwarf_f31_mips64: return "f31";
+case gcc_dwarf_sp_mips64: return "r29";
+case gcc_dwarf_r30_mips64: return "r30";
+case gcc_dwarf_ra_mips64: return "r31";
+case gcc_dwarf_f0_mips64: return "f0";
+case gcc_dwarf_f1_mips64: return "f1";
+case gcc_dwarf_f2_mips64: return "f2";
+case gcc_dwarf_f3_mips64: return "f3";
+case gcc_dwarf_f4_mips64: return "f4";
+case gcc_dwarf_f5_mips64: return "f5";
+case gcc_dwarf_f6_mips64: return "f6";
+case gcc_dwarf_f7_mips64: return "f7";
+case gcc_dwarf_f8_mips64: return "f8";
+case gcc_dwarf_f9_mips64: return "f9";
+case gcc_dwarf_f10_mips64: return "f10";
+case gcc_dwarf_f11_mips64: return "f11";
+case gcc_dwarf_f12_mips64: return "f12";
+case gcc_dwarf_f13_mips64: return "f13";
+case gcc_dwarf_f14_mips64: return "f14";
+case gcc_dwarf_f15_mips64: return "f15";
+case gcc_dwarf_f16_mips64: return "f16";
+case gcc_dwarf_f17_mips64: return "f17";
+case gcc_dwarf_f18_mips64: return "f18";
+case gcc_dwarf_f19_mips64: return "f19";
+
Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions
sagar marked 7 inline comments as done. Comment at: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:3160 @@ +3159,3 @@ +if((*ptr == 0 && bnz) || (*ptr != 0 && !bnz) ) +branch_hit = false; +break; The former one is more readable. Comment at: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:3187 @@ +3186,3 @@ +context.type = eContextRelativeBranchImmediate; + +if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) I have set the type to eContextRelativeBranchImmediate for now we are using these instructions for single stepping only. Comment at: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:3230 @@ +3229,3 @@ +else +target = pc + 8; + The former one is more readable. Comment at: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:3236 @@ +3235,3 @@ +if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) +return false; + I have set the type to eContextRelativeBranchImmediate for now we are using these instructions for single stepping only. Repository: rL LLVM http://reviews.llvm.org/D12356 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions
sagar updated this revision to Diff 33567. sagar added a comment. Addressed review commenst Repository: rL LLVM http://reviews.llvm.org/D12356 Files: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h === --- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h +++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h @@ -302,6 +302,42 @@ Emulate_BC1ANY4T (llvm::MCInst& insn); bool +Emulate_BNZB (llvm::MCInst& insn); + +bool +Emulate_BNZH (llvm::MCInst& insn); + +bool +Emulate_BNZW (llvm::MCInst& insn); + +bool +Emulate_BNZD (llvm::MCInst& insn); + +bool +Emulate_BZB (llvm::MCInst& insn); + +bool +Emulate_BZH (llvm::MCInst& insn); + +bool +Emulate_BZW (llvm::MCInst& insn); + +bool +Emulate_BZD (llvm::MCInst& insn); + +bool +Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz); + +bool +Emulate_BNZV (llvm::MCInst& insn); + +bool +Emulate_BZV (llvm::MCInst& insn); + +bool +Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz); + +bool nonvolatile_reg_p (uint64_t regnum); const char * Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp === --- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp +++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp @@ -256,6 +256,41 @@ case gcc_dwarf_f29_mips64: return "f29"; case gcc_dwarf_f30_mips64: return "f30"; case gcc_dwarf_f31_mips64: return "f31"; +case gcc_dwarf_w0_mips64: return "w0"; +case gcc_dwarf_w1_mips64: return "w1"; +case gcc_dwarf_w2_mips64: return "w2"; +case gcc_dwarf_w3_mips64: return "w3"; +case gcc_dwarf_w4_mips64: return "w4"; +case gcc_dwarf_w5_mips64: return "w5"; +case gcc_dwarf_w6_mips64: return "w6"; +case gcc_dwarf_w7_mips64: return "w7"; +case gcc_dwarf_w8_mips64: return "w8"; +case gcc_dwarf_w9_mips64: return "w9"; +case gcc_dwarf_w10_mips64: return "w10"; +case gcc_dwarf_w11_mips64: return "w11"; +case gcc_dwarf_w12_mips64: return "w12"; +case gcc_dwarf_w13_mips64: return "w13"; +case gcc_dwarf_w14_mips64: return "w14"; +case gcc_dwarf_w15_mips64: return "w15"; +case gcc_dwarf_w16_mips64: return "w16"; +case gcc_dwarf_w17_mips64: return "w17"; +case gcc_dwarf_w18_mips64: return "w18"; +case gcc_dwarf_w19_mips64: return "w19"; +case gcc_dwarf_w20_mips64: return "w20"; +case gcc_dwarf_w21_mips64: return "w21"; +case gcc_dwarf_w22_mips64: return "w22"; +case gcc_dwarf_w23_mips64: return "w23"; +case gcc_dwarf_w24_mips64: return "w24"; +case gcc_dwarf_w25_mips64: return "w25"; +case gcc_dwarf_w26_mips64: return "w26"; +case gcc_dwarf_w27_mips64: return "w27"; +case gcc_dwarf_w28_mips64: return "w28"; +case gcc_dwarf_w29_mips64: return "w29"; +case gcc_dwarf_w30_mips64: return "w30"; +case gcc_dwarf_w31_mips64: return "w31"; +case gcc_dwarf_mir_mips64: return "mir"; +case gcc_dwarf_mcsr_mips64: return "mcsr"; +case gcc_dwarf_config5_mips64: return "config5"; default: break; } @@ -336,6 +371,41 @@ case gcc_dwarf_f31_mips64: return "f31"; case gcc_dwarf_fcsr_mips64: return "fcsr"; case gcc_dwarf_fir_mips64: return "fir"; +case gcc_dwarf_w0_mips64: return "w0"; +case gcc_dwarf_w1_mips64: return "w1"; +case gcc_dwarf_w2_mips64: return "w2"; +case gcc_dwarf_w3_mips64: return "w3"; +case gcc_dwarf_w4_mips64: return "w4"; +case gcc_dwarf_w5_mips64: return "w5"; +case gcc_dwarf_w6_mips64: return "w6"; +case gcc_dwarf_w7_mips64: return "w7"; +case gcc_dwarf_w8_mips64: return "w8"; +case gcc_dwarf_w9_mips64: return "w9"; +case gcc_dwarf_w10_mips64: return "w10"; +case gcc_dwarf_w11_mips64: return "w11"; +case gcc_dwarf_w12_mips64: return "w12"; +case gcc_dwarf_w13_mips64: return "w13"; +case gcc_dwarf_w14_mips64: return "w14"; +case gcc_dwarf_w15_mips64: return "w15"; +case gcc_dwarf_w16_mips64: return "w16"; +case gcc_dwarf_w17_mips64: return "w17"; +case gcc_dwarf_w18_mips64: return "
Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions
tberghammer added a comment.
I don't know too much about mips so I haven't checked if the emulation is
actually correct but the general concept looks good to me. I added a few
comments inline but they are mostly suggestions what you might want to consider.
Comment at:
source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:553-562
@@ -476,2 +552,12 @@
{ "BC1ANY4T", &EmulateInstructionMIPS64::Emulate_BC1ANY4T,
"BC1ANY4T cc, offset" },
+{ "BNZ_B", &EmulateInstructionMIPS64::Emulate_BNZB,"BNZ.b
wt,s16" },
+{ "BNZ_H", &EmulateInstructionMIPS64::Emulate_BNZH,"BNZ.h
wt,s16" },
+{ "BNZ_W", &EmulateInstructionMIPS64::Emulate_BNZW,"BNZ.w
wt,s16" },
+{ "BNZ_D", &EmulateInstructionMIPS64::Emulate_BNZD,"BNZ.d
wt,s16" },
+{ "BZ_B", &EmulateInstructionMIPS64::Emulate_BZB, "BZ.b
wt,s16" },
+{ "BZ_H", &EmulateInstructionMIPS64::Emulate_BZH, "BZ.h
wt,s16" },
+{ "BZ_W", &EmulateInstructionMIPS64::Emulate_BZW, "BZ.w
wt,s16" },
+{ "BZ_D", &EmulateInstructionMIPS64::Emulate_BZD, "BZ.d
wt,s16" },
+{ "BNZ_V", &EmulateInstructionMIPS64::Emulate_BNZV,"BNZ.V
wt,s16" },
+{ "BZ_V", &EmulateInstructionMIPS64::Emulate_BZV, "BZ.V
wt,s16" },
};
(nit): Indentation
Comment at:
source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:3138-3140
@@ +3137,5 @@
+bool success = false, branch_hit = true;
+uint32_t wt;
+int64_t offset, pc, target;
+RegisterValue reg_value;
+uint8_t * ptr = NULL;
Please initialize these variables
Comment at: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:3160
@@ +3159,3 @@
+case 1:
+if((*ptr == 0 && bnz) || (*ptr != 0 && !bnz) )
+branch_hit = false;
You can possibly write it in the following way, but I am not sure which one is
the cleaner:
```
if((*ptr == 0) == bnz)
break;
```
Comment at: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:3187
@@ +3186,3 @@
+Context context;
+context.type = eContextInvalid;
+
Using eContextInvalid as context type is fine for single stepping but if you
want these instructions to be handled correctly during emulation based stack
unwinding then you have to use eContextAbsoluteBranchRegister or
eContextRelativeBranchImmediate with the correct data (it is used by the branch
following code in the unwinder)
Comment at:
source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:3211-3213
@@ +3210,5 @@
+bool success = false;
+uint32_t wt;
+int64_t offset, pc, target;
+llvm::APInt wr_val;
+llvm::APInt fail_value = llvm::APInt::getMaxValue(128);
Please initialize these variables
Comment at: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:3230
@@ +3229,3 @@
+
+if((llvm::APInt::isSameValue(zero_value, wr_val) && !bnz) ||
(!llvm::APInt::isSameValue(zero_value, wr_val) && bnz))
+target = pc + offset;
You can possibly write it in the following way, but I am not sure which one is
the cleaner:
```
if(llvm::APInt::isSameValue(zero_value, wr_val) != bnz)
...
```
Comment at: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:3236
@@ +3235,3 @@
+Context context;
+context.type = eContextInvalid;
+
Using eContextInvalid as context type is fine for single stepping but if you
want these instructions to be handled correctly during emulation based stack
unwinding then you have to use eContextAbsoluteBranchRegister or
eContextRelativeBranchImmediate with the correct data (it is used by the branch
following code in the unwinder)
Repository:
rL LLVM
http://reviews.llvm.org/D12356
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Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions
sagar updated this revision to Diff 33323. sagar added a comment. Addressed review comments Repository: rL LLVM http://reviews.llvm.org/D12356 Files: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h === --- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h +++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h @@ -302,6 +302,42 @@ Emulate_BC1ANY4T (llvm::MCInst& insn); bool +Emulate_BNZB (llvm::MCInst& insn); + +bool +Emulate_BNZH (llvm::MCInst& insn); + +bool +Emulate_BNZW (llvm::MCInst& insn); + +bool +Emulate_BNZD (llvm::MCInst& insn); + +bool +Emulate_BZB (llvm::MCInst& insn); + +bool +Emulate_BZH (llvm::MCInst& insn); + +bool +Emulate_BZW (llvm::MCInst& insn); + +bool +Emulate_BZD (llvm::MCInst& insn); + +bool +Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz); + +bool +Emulate_BNZV (llvm::MCInst& insn); + +bool +Emulate_BZV (llvm::MCInst& insn); + +bool +Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz); + +bool nonvolatile_reg_p (uint64_t regnum); const char * Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp === --- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp +++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp @@ -256,6 +256,41 @@ case gcc_dwarf_f29_mips64: return "f29"; case gcc_dwarf_f30_mips64: return "f30"; case gcc_dwarf_f31_mips64: return "f31"; +case gcc_dwarf_w0_mips64: return "w0"; +case gcc_dwarf_w1_mips64: return "w1"; +case gcc_dwarf_w2_mips64: return "w2"; +case gcc_dwarf_w3_mips64: return "w3"; +case gcc_dwarf_w4_mips64: return "w4"; +case gcc_dwarf_w5_mips64: return "w5"; +case gcc_dwarf_w6_mips64: return "w6"; +case gcc_dwarf_w7_mips64: return "w7"; +case gcc_dwarf_w8_mips64: return "w8"; +case gcc_dwarf_w9_mips64: return "w9"; +case gcc_dwarf_w10_mips64: return "w10"; +case gcc_dwarf_w11_mips64: return "w11"; +case gcc_dwarf_w12_mips64: return "w12"; +case gcc_dwarf_w13_mips64: return "w13"; +case gcc_dwarf_w14_mips64: return "w14"; +case gcc_dwarf_w15_mips64: return "w15"; +case gcc_dwarf_w16_mips64: return "w16"; +case gcc_dwarf_w17_mips64: return "w17"; +case gcc_dwarf_w18_mips64: return "w18"; +case gcc_dwarf_w19_mips64: return "w19"; +case gcc_dwarf_w20_mips64: return "w20"; +case gcc_dwarf_w21_mips64: return "w21"; +case gcc_dwarf_w22_mips64: return "w22"; +case gcc_dwarf_w23_mips64: return "w23"; +case gcc_dwarf_w24_mips64: return "w24"; +case gcc_dwarf_w25_mips64: return "w25"; +case gcc_dwarf_w26_mips64: return "w26"; +case gcc_dwarf_w27_mips64: return "w27"; +case gcc_dwarf_w28_mips64: return "w28"; +case gcc_dwarf_w29_mips64: return "w29"; +case gcc_dwarf_w30_mips64: return "w30"; +case gcc_dwarf_w31_mips64: return "w31"; +case gcc_dwarf_mir_mips64: return "mir"; +case gcc_dwarf_mcsr_mips64: return "mcsr"; +case gcc_dwarf_config5_mips64: return "config5"; default: break; } @@ -336,6 +371,41 @@ case gcc_dwarf_f31_mips64: return "f31"; case gcc_dwarf_fcsr_mips64: return "fcsr"; case gcc_dwarf_fir_mips64: return "fir"; +case gcc_dwarf_w0_mips64: return "w0"; +case gcc_dwarf_w1_mips64: return "w1"; +case gcc_dwarf_w2_mips64: return "w2"; +case gcc_dwarf_w3_mips64: return "w3"; +case gcc_dwarf_w4_mips64: return "w4"; +case gcc_dwarf_w5_mips64: return "w5"; +case gcc_dwarf_w6_mips64: return "w6"; +case gcc_dwarf_w7_mips64: return "w7"; +case gcc_dwarf_w8_mips64: return "w8"; +case gcc_dwarf_w9_mips64: return "w9"; +case gcc_dwarf_w10_mips64: return "w10"; +case gcc_dwarf_w11_mips64: return "w11"; +case gcc_dwarf_w12_mips64: return "w12"; +case gcc_dwarf_w13_mips64: return "w13"; +case gcc_dwarf_w14_mips64: return "w14"; +case gcc_dwarf_w15_mips64: return "w15"; +case gcc_dwarf_w16_mips64: return "w16"; +case gcc_dwarf_w17_mips64: return "w17"; +case gcc_dwarf_w18_mips64: return "
Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions
clayborg resigned from this revision. clayborg removed a reviewer: clayborg. clayborg added a comment. I will defer to MIPS experts here. You might thing about adding tberghammer as a reviewer. Repository: rL LLVM http://reviews.llvm.org/D12356 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions
tberghammer added a subscriber: tberghammer. tberghammer added a comment. You added 10 new function to the emulator where the first 8 functions and the last 2 functions are almost identical. I know that the rest of the MIPS64 instruction emulator is having the same issue but I would like to see these functions to be merged into a smaller number of functions to remove code duplication. I see 2 different approach to do it and I am not sure which one is better in this case, but both of them improves the situation by a lot. - Write only 2 function (first 8, last 2) and that function then reads out the condition and the sizes from the MCInst object. I would prefer this approach, but I am not sure how difficult it is to read out data from an MCInst - Keep the 10 function for the 10 different instruction, but make these functions to call a function (one for the first 8 and one for the last 2) with passing in the constants required by the specific instruction. Both approach would reduce the amount of code in this class and help a lot in reducing the maintenance cost with removing a lot of duplicated code. Repository: rL LLVM http://reviews.llvm.org/D12356 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions
jaydeep requested changes to this revision. This revision now requires changes to proceed. Comment at: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:3117 @@ +3116,3 @@ +else +target = pc + 4; + This should be pc + 8. If branch is not taken then we need to skip the delay slot. Repository: rL LLVM http://reviews.llvm.org/D12356 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
