[llvm-branch-commits] [libunwind] 3cbd476 - [VE] Support VE in libunwind
Author: Kazushi (Jam) Marukawa
Date: 2021-01-17T15:35:02+09:00
New Revision: 3cbd476c54886e8ebac64b4145d4517732a71023
URL:
https://github.com/llvm/llvm-project/commit/3cbd476c54886e8ebac64b4145d4517732a71023
DIFF:
https://github.com/llvm/llvm-project/commit/3cbd476c54886e8ebac64b4145d4517732a71023.diff
LOG: [VE] Support VE in libunwind
Modify libunwind to support SjLj exception handling routines for VE.
In order to do that, we need to implement not only SjLj exception
handling routines but also a Registers_ve class. This implementation
of Registers_ve is incomplete. We will work on it later when we need
backtrace in libunwind.
Reviewed By: #libunwind, compnerd
Differential Revision: https://reviews.llvm.org/D94591
Added:
Modified:
libunwind/include/__libunwind_config.h
libunwind/include/libunwind.h
libunwind/src/Registers.hpp
libunwind/src/Unwind-sjlj.c
libunwind/src/libunwind.cpp
Removed:
diff --git a/libunwind/include/__libunwind_config.h
b/libunwind/include/__libunwind_config.h
index 80be357496c4..34ac6f717d6e 100644
--- a/libunwind/include/__libunwind_config.h
+++ b/libunwind/include/__libunwind_config.h
@@ -25,6 +25,7 @@
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC 31
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_HEXAGON 34
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV 64
+#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_VE143
#if defined(_LIBUNWIND_IS_NATIVE_ONLY)
# if defined(__linux__)
@@ -138,6 +139,11 @@
#error "Unsupported RISC-V ABI"
# endif
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER
_LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV
+# elif defined(__ve__)
+# define _LIBUNWIND_TARGET_VE 1
+# define _LIBUNWIND_CONTEXT_SIZE 67
+# define _LIBUNWIND_CURSOR_SIZE 79
+# define _LIBUNWIND_HIGHEST_DWARF_REGISTER
_LIBUNWIND_HIGHEST_DWARF_REGISTER_VE
# else
# error "Unsupported architecture."
# endif
@@ -154,6 +160,7 @@
# define _LIBUNWIND_TARGET_SPARC 1
# define _LIBUNWIND_TARGET_HEXAGON 1
# define _LIBUNWIND_TARGET_RISCV 1
+# define _LIBUNWIND_TARGET_VE 1
# define _LIBUNWIND_CONTEXT_SIZE 167
# define _LIBUNWIND_CURSOR_SIZE 179
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER 287
diff --git a/libunwind/include/libunwind.h b/libunwind/include/libunwind.h
index 6ec649a460b8..5bae8d02f799 100644
--- a/libunwind/include/libunwind.h
+++ b/libunwind/include/libunwind.h
@@ -947,4 +947,156 @@ enum {
UNW_RISCV_F31 = 63,
};
+// VE register numbers
+enum {
+ UNW_VE_S0 = 0,
+ UNW_VE_S1 = 1,
+ UNW_VE_S2 = 2,
+ UNW_VE_S3 = 3,
+ UNW_VE_S4 = 4,
+ UNW_VE_S5 = 5,
+ UNW_VE_S6 = 6,
+ UNW_VE_S7 = 7,
+ UNW_VE_S8 = 8,
+ UNW_VE_S9 = 9,
+ UNW_VE_S10 = 10,
+ UNW_VE_S11 = 11,
+ UNW_VE_S12 = 12,
+ UNW_VE_S13 = 13,
+ UNW_VE_S14 = 14,
+ UNW_VE_S15 = 15,
+ UNW_VE_S16 = 16,
+ UNW_VE_S17 = 17,
+ UNW_VE_S18 = 18,
+ UNW_VE_S19 = 19,
+ UNW_VE_S20 = 20,
+ UNW_VE_S21 = 21,
+ UNW_VE_S22 = 22,
+ UNW_VE_S23 = 23,
+ UNW_VE_S24 = 24,
+ UNW_VE_S25 = 25,
+ UNW_VE_S26 = 26,
+ UNW_VE_S27 = 27,
+ UNW_VE_S28 = 28,
+ UNW_VE_S29 = 29,
+ UNW_VE_S30 = 30,
+ UNW_VE_S31 = 31,
+ UNW_VE_S32 = 32,
+ UNW_VE_S33 = 33,
+ UNW_VE_S34 = 34,
+ UNW_VE_S35 = 35,
+ UNW_VE_S36 = 36,
+ UNW_VE_S37 = 37,
+ UNW_VE_S38 = 38,
+ UNW_VE_S39 = 39,
+ UNW_VE_S40 = 40,
+ UNW_VE_S41 = 41,
+ UNW_VE_S42 = 42,
+ UNW_VE_S43 = 43,
+ UNW_VE_S44 = 44,
+ UNW_VE_S45 = 45,
+ UNW_VE_S46 = 46,
+ UNW_VE_S47 = 47,
+ UNW_VE_S48 = 48,
+ UNW_VE_S49 = 49,
+ UNW_VE_S50 = 50,
+ UNW_VE_S51 = 51,
+ UNW_VE_S52 = 52,
+ UNW_VE_S53 = 53,
+ UNW_VE_S54 = 54,
+ UNW_VE_S55 = 55,
+ UNW_VE_S56 = 56,
+ UNW_VE_S57 = 57,
+ UNW_VE_S58 = 58,
+ UNW_VE_S59 = 59,
+ UNW_VE_S60 = 60,
+ UNW_VE_S61 = 61,
+ UNW_VE_S62 = 62,
+ UNW_VE_S63 = 63,
+ UNW_VE_V0 = 64 + 0,
+ UNW_VE_V1 = 64 + 1,
+ UNW_VE_V2 = 64 + 2,
+ UNW_VE_V3 = 64 + 3,
+ UNW_VE_V4 = 64 + 4,
+ UNW_VE_V5 = 64 + 5,
+ UNW_VE_V6 = 64 + 6,
+ UNW_VE_V7 = 64 + 7,
+ UNW_VE_V8 = 64 + 8,
+ UNW_VE_V9 = 64 + 9,
+ UNW_VE_V10 = 64 + 10,
+ UNW_VE_V11 = 64 + 11,
+ UNW_VE_V12 = 64 + 12,
+ UNW_VE_V13 = 64 + 13,
+ UNW_VE_V14 = 64 + 14,
+ UNW_VE_V15 = 64 + 15,
+ UNW_VE_V16 = 64 + 16,
+ UNW_VE_V17 = 64 + 17,
+ UNW_VE_V18 = 64 + 18,
+ UNW_VE_V19 = 64 + 19,
+ UNW_VE_V20 = 64 + 20,
+ UNW_VE_V21 = 64 + 21,
+ UNW_VE_V22 = 64 + 22,
+ UNW_VE_V23 = 64 + 23,
+ UNW_VE_V24 = 64 + 24,
+ UNW_VE_V25 = 64 + 25,
+ UNW_VE_V26 = 64 + 26,
+ UNW_VE_V27 = 64 + 27,
+ UNW_VE_V28 = 64 + 28,
+ UNW_VE_V29 = 64 + 29,
+ UNW_VE_V30 = 64 + 30,
+ UNW_VE_V31 = 64 + 31,
+ UNW_VE_V32 = 64 + 32,
+ UNW_VE_V33 = 64 + 33,
+ UNW_VE_V34 = 64 + 34,
+ UNW_VE_V35 = 64 + 35,
+ UNW_VE_V36 = 64 + 36,
+ UNW_VE_V37 = 64 + 37,
+ UNW_VE_V38 = 64 + 38,
+ UNW_VE_V39 = 64 + 39,
+ UNW_VE_V40 = 64 + 40,
+ UNW_VE_V41 = 64 + 41,
+ UNW_VE_V42 = 64 + 42,
[llvm-branch-commits] [llvm] 2b6a926 - [RISCV] Simplify mergeCondAndCode in RISCVCompressInstEmitter.cpp. NFC
Author: Craig Topper
Date: 2021-01-16T20:59:48-08:00
New Revision: 2b6a92625fdf11928bff1a31cdc06d7dbd193f85
URL:
https://github.com/llvm/llvm-project/commit/2b6a92625fdf11928bff1a31cdc06d7dbd193f85
DIFF:
https://github.com/llvm/llvm-project/commit/2b6a92625fdf11928bff1a31cdc06d7dbd193f85.diff
LOG: [RISCV] Simplify mergeCondAndCode in RISCVCompressInstEmitter.cpp. NFC
Instead forming a std::string and returning it to pass into another
raw_ostream, just pass the raw_ostream as a parameter.
Take StringRef as arguments instead raw_string_ostream references
making the caller responsible for converting to strings. Use
StringRef operations instead of std::string::substr.a
Added:
Modified:
llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
Removed:
diff --git a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
index 3e20a726866d..797295d2cdb6 100644
--- a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
@@ -537,20 +537,14 @@ static void printPredicates(std::vector
,
}
}
-static std::string mergeCondAndCode(raw_string_ostream ,
-raw_string_ostream ) {
- std::string S;
- raw_string_ostream CombinedStream(S);
- CombinedStream.indent(4)
- << "if ("
- << CondStream.str().substr(
- 6, CondStream.str().length() -
-10) // remove first indentation and last '&&'.
- << ") {\n";
- CombinedStream << CodeStream.str();
+static void mergeCondAndCode(raw_ostream , StringRef CondStr,
+ StringRef CodeStr) {
+ // Remove first indentation and last '&&'.
+ CondStr = CondStr.drop_front(6).drop_back(4);
+ CombinedStream.indent(4) << "if (" << CondStr << ") {\n";
+ CombinedStream << CodeStr;
CombinedStream.indent(4) << " return true;\n";
CombinedStream.indent(4) << "} // if\n";
- return CombinedStream.str();
}
void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream ,
@@ -812,7 +806,7 @@ void
RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream ,
}
if (CompressOrUncompress)
CodeStream.indent(6) << "OutInst.setLoc(MI.getLoc());\n";
-CaseStream << mergeCondAndCode(CondStream, CodeStream);
+mergeCondAndCode(CaseStream, CondStream.str(), CodeStream.str());
PrevOp = CurOp;
}
Func << CaseStream.str() << "\n";
___
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[llvm-branch-commits] [llvm] 061f681 - [RISCV] Remove an extra map lookup from RISCVCompressInstEmitter. NFC
Author: Craig Topper
Date: 2021-01-16T21:20:53-08:00
New Revision: 061f681c0dfa4d279dc656802bf81f3b9bfa3d34
URL:
https://github.com/llvm/llvm-project/commit/061f681c0dfa4d279dc656802bf81f3b9bfa3d34
DIFF:
https://github.com/llvm/llvm-project/commit/061f681c0dfa4d279dc656802bf81f3b9bfa3d34.diff
LOG: [RISCV] Remove an extra map lookup from RISCVCompressInstEmitter. NFC
When we looked up the map to see if the entry already existed,
this created the new entry for us. So save a reference to it so
we can use it to update the entry instead of looking it up again.
Also remove unnecessary StringRef constructors around string
literals on calls to this function.
Added:
Modified:
llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
Removed:
diff --git a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
index 8f781c91f461..beb9266d62ab 100644
--- a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
@@ -509,14 +509,13 @@ getReqFeatures(std::set>
,
static unsigned getPredicates(DenseMap ,
std::vector ,
Record *Rec, StringRef Name) {
- unsigned Entry = PredicateMap[Rec];
+ unsigned = PredicateMap[Rec];
if (Entry)
return Entry;
if (!Rec->isValueUnset(Name)) {
Predicates.push_back(Rec);
Entry = Predicates.size();
-PredicateMap[Rec] = Entry;
return Entry;
}
@@ -751,14 +750,16 @@ void
RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream ,
} else {
// Handling immediate operands.
if (CompressOrUncompress) {
-unsigned Entry = getPredicates(MCOpPredicateMap, MCOpPredicates,
- DestOperand.Rec, StringRef("MCOperandPredicate"));
+unsigned Entry =
+getPredicates(MCOpPredicateMap, MCOpPredicates,
DestOperand.Rec,
+ "MCOperandPredicate");
CondStream.indent(6)
<< Namespace << "ValidateMCOperand("
<< "MI.getOperand(" << OpIdx << "), STI, " << Entry << ")
&&\n";
} else {
-unsigned Entry = getPredicates(ImmLeafPredicateMap,
ImmLeafPredicates,
- DestOperand.Rec, StringRef("ImmediateCode"));
+unsigned Entry =
+getPredicates(ImmLeafPredicateMap, ImmLeafPredicates,
+ DestOperand.Rec, "ImmediateCode");
CondStream.indent(6)
<< "MI.getOperand(" << OpIdx << ").isImm() &&\n";
CondStream.indent(6) << Namespace << "ValidateMachineOperand("
@@ -774,14 +775,14 @@ void
RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream ,
case OpData::Imm: {
if (CompressOrUncompress) {
unsigned Entry = getPredicates(MCOpPredicateMap, MCOpPredicates,
-DestOperand.Rec, StringRef("MCOperandPredicate"));
+ DestOperand.Rec,
"MCOperandPredicate");
CondStream.indent(6)
<< Namespace << "ValidateMCOperand("
<< "MCOperand::createImm(" << DestOperandMap[OpNo].Data.Imm
<< "), STI, " << Entry << ") &&\n";
} else {
unsigned Entry = getPredicates(ImmLeafPredicateMap,
ImmLeafPredicates,
-DestOperand.Rec, StringRef("ImmediateCode"));
+ DestOperand.Rec, "ImmediateCode");
CondStream.indent(6)
<< Namespace
<< "ValidateMachineOperand(MachineOperand::CreateImm("
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[llvm-branch-commits] [llvm] 1327c73 - [RISCV] Few more minor cleanups to RISCVCompressInstEmitter. NFC
Author: Craig Topper
Date: 2021-01-16T21:09:43-08:00
New Revision: 1327c730bb9a0bff963af3745869cf244ae37241
URL:
https://github.com/llvm/llvm-project/commit/1327c730bb9a0bff963af3745869cf244ae37241
DIFF:
https://github.com/llvm/llvm-project/commit/1327c730bb9a0bff963af3745869cf244ae37241.diff
LOG: [RISCV] Few more minor cleanups to RISCVCompressInstEmitter. NFC
-Use StringRef instead of std::string.
-Const correct a parameter.
-Don't call StringRef::data() before printing. Just pass the StringRef.
Added:
Modified:
llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
Removed:
diff --git a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
index 797295d2cdb6..8f781c91f461 100644
--- a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
@@ -526,13 +526,13 @@ static unsigned getPredicates(DenseMap ,
return 0;
}
-static void printPredicates(std::vector ,
+static void printPredicates(const std::vector ,
StringRef Name, raw_ostream ) {
for (unsigned i = 0; i < Predicates.size(); ++i) {
StringRef Pred = Predicates[i]->getValueAsString(Name);
o << " case " << i + 1 << ": {\n"
<< " // " << Predicates[i]->getName() << "\n"
- << " " << Pred.data() << "\n"
+ << " " << Pred << "\n"
<< " }\n";
}
}
@@ -555,7 +555,7 @@ void
RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream ,
"'PassSubtarget' is false. SubTargetInfo object is needed "
"for target features.\n");
- std::string Namespace = std::string(Target.getName());
+ StringRef Namespace = Target.getName();
// Sort entries in CompressPatterns to handle instructions that can have more
// than one candidate for compression\uncompression, e.g ADD can be
@@ -624,8 +624,8 @@ void
RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream ,
std::string CaseString;
raw_string_ostream CaseStream(CaseString);
- std::string PrevOp;
- std::string CurOp;
+ StringRef PrevOp;
+ StringRef CurOp;
CaseStream << " switch (MI.getOpcode()) {\n";
CaseStream << "default: return false;\n";
@@ -648,10 +648,10 @@ void
RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream ,
IndexedMap = CompressOrCheck ?
CompressPat.DestOperandMap : CompressPat.SourceOperandMap;
-CurOp = Source.TheDef->getName().str();
+CurOp = Source.TheDef->getName();
// Check current and previous opcode to decide to continue or end a case.
if (CurOp != PrevOp) {
- if (PrevOp != "")
+ if (!PrevOp.empty())
CaseStream.indent(6) << "break;\n} // case " + PrevOp + "\n";
CaseStream.indent(4) << "case " + Namespace + "::" + CurOp + ": {\n";
}
___
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[llvm-branch-commits] [llvm] 97f7e4e - [RISC] Replace dyn_casts that are only checked by an assert with a cast. NFC
Author: Craig Topper
Date: 2021-01-16T20:23:48-08:00
New Revision: 97f7e4e8c9309e0806f9b8f8afcf8ce2ef63656c
URL:
https://github.com/llvm/llvm-project/commit/97f7e4e8c9309e0806f9b8f8afcf8ce2ef63656c
DIFF:
https://github.com/llvm/llvm-project/commit/97f7e4e8c9309e0806f9b8f8afcf8ce2ef63656c.diff
LOG: [RISC] Replace dyn_casts that are only checked by an assert with a cast.
NFC
Added:
Modified:
llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
Removed:
diff --git a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
index 9fcb6a168c3f..3e20a726866d 100644
--- a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
@@ -284,11 +284,7 @@ static bool verifyDagOpCount(CodeGenInstruction ,
DagInit *Dag,
}
static bool validateArgsTypes(Init *Arg1, Init *Arg2) {
- DefInit *Type1 = dyn_cast(Arg1);
- DefInit *Type2 = dyn_cast(Arg2);
- assert(Type1 && ("Arg1 type not found\n"));
- assert(Type2 && ("Arg2 type not found\n"));
- return Type1->getDef() == Type2->getDef();
+ return cast(Arg1)->getDef() == cast(Arg2)->getDef();
}
// Creates a mapping between the operand name in the Dag (e.g. $rs1) and
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[llvm-branch-commits] [llvm] 633c5af - [RISCV] Remove unneeded StringRef to std::string conversions in RISCVCompressInstEmitter. NFC
Author: Craig Topper
Date: 2021-01-16T20:09:45-08:00
New Revision: 633c5afccfbb0a985976aa3e6493f1a08061cb10
URL:
https://github.com/llvm/llvm-project/commit/633c5afccfbb0a985976aa3e6493f1a08061cb10
DIFF:
https://github.com/llvm/llvm-project/commit/633c5afccfbb0a985976aa3e6493f1a08061cb10.diff
LOG: [RISCV] Remove unneeded StringRef to std::string conversions in
RISCVCompressInstEmitter. NFC
Stop concatenating std::string before streaming into a raw_ostream.
Just stream the pieces.
Remove some new lines from asserts. Remove std::string concatenation
from an assert. assert strings aren't really evaluated like this at
runtime. An assertion failure will just print exactly what's between
the parentheses in the source.
Added:
Modified:
llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
Removed:
diff --git a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
index 70f518161737..9fcb6a168c3f 100644
--- a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
@@ -138,13 +138,12 @@ class RISCVCompressInstEmitter {
} // End anonymous namespace.
bool RISCVCompressInstEmitter::validateRegister(Record *Reg, Record *RegClass)
{
- assert(Reg->isSubClassOf("Register") && "Reg record should be a Register\n");
- assert(RegClass->isSubClassOf("RegisterClass") && "RegClass record should be"
-" a RegisterClass\n");
+ assert(Reg->isSubClassOf("Register") && "Reg record should be a Register");
+ assert(RegClass->isSubClassOf("RegisterClass") &&
+ "RegClass record should be a RegisterClass");
const CodeGenRegisterClass = Target.getRegisterClass(RegClass);
const CodeGenRegister *R = Target.getRegisterByName(Reg->getName().lower());
- assert((R != nullptr) &&
- ("Register" + Reg->getName().str() + " not defined!!\n").c_str());
+ assert((R != nullptr) && "Register not defined!!");
return RC.contains(R);
}
@@ -237,9 +236,9 @@ void RISCVCompressInstEmitter::addDagOperandMapping(
if (Inst.Operands[i].Rec->isSubClassOf("RegisterClass"))
PrintFatalError(
Rec->getLoc(),
-("Error in Dag '" + Dag->getAsString() + "' Found immediate: '" +
- II->getAsString() +
- "' but corresponding instruction operand expected a register!"));
+"Error in Dag '" + Dag->getAsString() + "' Found immediate: '" +
+II->getAsString() +
+"' but corresponding instruction operand expected a
register!");
// No pattern validation check possible for values of fixed immediate.
OperandMap[i].Kind = OpData::Imm;
OperandMap[i].Data.Imm = II->getValue();
@@ -526,7 +525,8 @@ static unsigned getPredicates(DenseMap ,
}
PrintFatalError(Rec->getLoc(), "No " + Name +
-" predicate on this operand at all: '" + Rec->getName().str() + "'");
+ " predicate on this operand at all: '" +
+ Rec->getName() + "'");
return 0;
}
@@ -535,7 +535,7 @@ static void printPredicates(std::vector
,
for (unsigned i = 0; i < Predicates.size(); ++i) {
StringRef Pred = Predicates[i]->getValueAsString(Name);
o << " case " << i + 1 << ": {\n"
- << " // " << Predicates[i]->getName().str() << "\n"
+ << " // " << Predicates[i]->getName() << "\n"
<< " " << Pred.data() << "\n"
<< " }\n";
}
@@ -572,16 +572,13 @@ void
RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream ,
// transformed to a C_ADD or a C_MV. When emitting 'uncompress()' function
the
// source and destination are flipped and the sort key needs to change
// accordingly.
- llvm::stable_sort(CompressPatterns,
-[EType](const CompressPat , const CompressPat ) {
- if (EType == EmitterType::Compress ||
-EType == EmitterType::CheckCompress)
-return (LHS.Source.TheDef->getName().str() <
-RHS.Source.TheDef->getName().str());
- else
-return (LHS.Dest.TheDef->getName().str() <
-RHS.Dest.TheDef->getName().str());
-});
+ llvm::stable_sort(CompressPatterns, [EType](const CompressPat ,
+ const CompressPat ) {
+if (EType == EmitterType::Compress || EType == EmitterType::CheckCompress)
+ return (LHS.Source.TheDef->getName() < RHS.Source.TheDef->getName());
+else
+ return (LHS.Dest.TheDef->getName() < RHS.Dest.TheDef->getName());
+ });
// A list of MCOperandPredicates for all operands in use, and the reverse
map.
std::vector MCOpPredicates;
@@ -685,9 +682,9 @@ void
[llvm-branch-commits] [llvm] a048ce1 - [X86] Default to -x86-pad-for-align=false to drop assembler difference with or w/o -g
Author: Fangrui Song
Date: 2021-01-16T16:39:54-08:00
New Revision: a048ce13e32daa255d26533c00da8abd0b67e819
URL:
https://github.com/llvm/llvm-project/commit/a048ce13e32daa255d26533c00da8abd0b67e819
DIFF:
https://github.com/llvm/llvm-project/commit/a048ce13e32daa255d26533c00da8abd0b67e819.diff
LOG: [X86] Default to -x86-pad-for-align=false to drop assembler difference
with or w/o -g
Fix PR48742: the D75203 assembler optimization locates MCRelaxableFragment's
within two MCSymbol's and relaxes some MCRelaxableFragment's to reduce the size
of a MCAlignFragment. A -g build has more MCSymbol's and therefore may have
different assembler output (e.g. a MCRelaxableFragment (jmp) may have 5 bytes
with -O1 while 2 bytes with -O1 -g).
`.p2align 4, 0x90` is common due to loops. For a larger program, with a
lot of temporary labels, the assembly output difference is somewhat
destined. The cost seems to overweigh the benefits so we default to
-x86-pad-for-align=false until the heuristic is improved.
Reviewed By: skan
Differential Revision: https://reviews.llvm.org/D94542
Added:
Modified:
llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
llvm/test/MC/X86/align-via-padding-corner.s
llvm/test/MC/X86/align-via-padding.s
llvm/test/MC/X86/align-via-relaxation.s
llvm/test/MC/X86/prefix-padding-32.s
llvm/test/MC/X86/prefix-padding-64.s
Removed:
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
index a7d71bd35d29..95012a148d83 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -109,7 +109,7 @@ cl::opt X86PadMaxPrefixSize(
cl::desc("Maximum number of prefixes to use for padding"));
cl::opt X86PadForAlign(
-"x86-pad-for-align", cl::init(true), cl::Hidden,
+"x86-pad-for-align", cl::init(false), cl::Hidden,
cl::desc("Pad previous instructions to implement align directives"));
cl::opt X86PadForBranchAlign(
@@ -957,6 +957,9 @@ void X86AsmBackend::finishLayout(MCAssembler const ,
if (!X86PadForAlign && !X86PadForBranchAlign)
return;
+ // The processed regions are delimitered by LabeledFragments. -g may have
more
+ // MCSymbols and therefore
diff erent relaxation results. X86PadForAlign is
+ // disabled by default to eliminate the -g vs non -g
diff erence.
DenseSet LabeledFragments;
for (const MCSymbol : Asm.symbols())
LabeledFragments.insert(S.getFragment(false));
diff --git a/llvm/test/MC/X86/align-via-padding-corner.s
b/llvm/test/MC/X86/align-via-padding-corner.s
index cc13ff7eed7f..6b8e02d198a5 100644
--- a/llvm/test/MC/X86/align-via-padding-corner.s
+++ b/llvm/test/MC/X86/align-via-padding-corner.s
@@ -1,4 +1,4 @@
- # RUN: llvm-mc -mcpu=skylake -filetype=obj -triple x86_64-pc-linux-gnu %s
-x86-pad-max-prefix-size=5 | llvm-objdump -d - | FileCheck %s
+ # RUN: llvm-mc -mcpu=skylake -filetype=obj -triple x86_64-pc-linux-gnu %s
-x86-pad-max-prefix-size=5 -x86-pad-for-align=1 | llvm-objdump -d - | FileCheck
%s
# The first test check the correctness cornercase - can't add prefixes on a
diff --git a/llvm/test/MC/X86/align-via-padding.s
b/llvm/test/MC/X86/align-via-padding.s
index d5d86da6ddca..32495fe4a3ae 100644
--- a/llvm/test/MC/X86/align-via-padding.s
+++ b/llvm/test/MC/X86/align-via-padding.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -mcpu=skylake -filetype=obj -triple x86_64-pc-linux-gnu %s
-x86-pad-max-prefix-size=5 | llvm-objdump -d --section=.text - | FileCheck %s
+# RUN: llvm-mc -mcpu=skylake -filetype=obj -triple x86_64-pc-linux-gnu %s
-x86-pad-max-prefix-size=5 -x86-pad-for-align=1 | llvm-objdump -d - | FileCheck
%s
# This test file highlights the interactions between prefix padding and
# relaxation padding.
diff --git a/llvm/test/MC/X86/align-via-relaxation.s
b/llvm/test/MC/X86/align-via-relaxation.s
index d768232655b7..394efaf6d75b 100644
--- a/llvm/test/MC/X86/align-via-relaxation.s
+++ b/llvm/test/MC/X86/align-via-relaxation.s
@@ -1,4 +1,5 @@
-# RUN: llvm-mc -mcpu=skylake -filetype=obj -triple x86_64-pc-linux-gnu
-x86-pad-max-prefix-size=0 %s | llvm-objdump -d --section=.text - | FileCheck %s
+# RUN: llvm-mc -mcpu=skylake -filetype=obj -triple x86_64-pc-linux-gnu
-x86-pad-max-prefix-size=0 %s | llvm-objdump -d - | FileCheck %s
--check-prefix=NOPAD
+# RUN: llvm-mc -mcpu=skylake -filetype=obj -triple x86_64-pc-linux-gnu
-x86-pad-max-prefix-size=0 -x86-pad-for-align=1 %s | llvm-objdump -d - |
FileCheck %s
# This test exercises only the padding via relaxation logic. The interaction
# etween prefix padding and relaxation logic can be seen in align-via-padding.s
@@ -6,6 +7,19 @@
.file "test.c"
.text
.section .text
+
+# NOPAD-LABEL: <.text>:
+# NOPAD-NEXT: 0: eb 1f jmp 0x21
+# NOPAD-NEXT: 2: eb 1d jmp 0x21
+# NOPAD-NEXT: 4: eb 1b
[llvm-branch-commits] [llvm] 5238e7b - [InstCombine] Replace one-use select operand based on condition
Author: Nikita Popov
Date: 2021-01-16T23:25:02+01:00
New Revision: 5238e7b302ffc40707677960da9d64e872745dac
URL:
https://github.com/llvm/llvm-project/commit/5238e7b302ffc40707677960da9d64e872745dac
DIFF:
https://github.com/llvm/llvm-project/commit/5238e7b302ffc40707677960da9d64e872745dac.diff
LOG: [InstCombine] Replace one-use select operand based on condition
InstCombine already performs a fold where X == Y ? f(X) : Z is
transformed to X == Y ? f(Y) : Z if f(Y) simplifies. However,
if f(X) only has one use, then we can always directly replace the
use inside the instruction. To actually be profitable, limit it to
the case where Y is a non-expr constant.
This could be further extended to replace uses further up a one-use
instruction chain, but for now this only looks one level up.
Among other things, this also subsumes D94860.
Differential Revision: https://reviews.llvm.org/D94862
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
llvm/test/Transforms/InstCombine/select-binop-cmp.ll
llvm/test/Transforms/InstCombine/select-safe-transforms.ll
Removed:
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index 5a43b8b20db9..9360adc2d3ad 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -1113,10 +1113,25 @@ Instruction
*InstCombinerImpl::foldSelectValueEquivalence(SelectInst ,
// replacement cycle.
Value *CmpLHS = Cmp.getOperand(0), *CmpRHS = Cmp.getOperand(1);
if (TrueVal != CmpLHS &&
- isGuaranteedNotToBeUndefOrPoison(CmpRHS, SQ.AC, , ))
+ isGuaranteedNotToBeUndefOrPoison(CmpRHS, SQ.AC, , )) {
if (Value *V = SimplifyWithOpReplaced(TrueVal, CmpLHS, CmpRHS, SQ,
/* AllowRefinement */ true))
return replaceOperand(Sel, Swapped ? 2 : 1, V);
+
+// Even if TrueVal does not simplify, we can directly replace a use of
+// CmpLHS with CmpRHS, as long as the instruction is not used anywhere
+// else. Only do this if CmpRHS is a constant, as profitability is not
+// clear for other cases.
+// FIXME: The replacement could be performed recursively.
+if (isa(CmpRHS) && !isa(CmpRHS))
+ if (auto *I = dyn_cast(TrueVal))
+if (I->hasOneUse())
+ for (Use : I->operands())
+if (U == CmpLHS) {
+ replaceUse(U, CmpRHS);
+ return
+}
+ }
if (TrueVal != CmpRHS &&
isGuaranteedNotToBeUndefOrPoison(CmpLHS, SQ.AC, , ))
if (Value *V = SimplifyWithOpReplaced(TrueVal, CmpRHS, CmpLHS, SQ,
diff --git a/llvm/test/Transforms/InstCombine/select-binop-cmp.ll
b/llvm/test/Transforms/InstCombine/select-binop-cmp.ll
index 55738953f60d..3573ff86e480 100644
--- a/llvm/test/Transforms/InstCombine/select-binop-cmp.ll
+++ b/llvm/test/Transforms/InstCombine/select-binop-cmp.ll
@@ -502,7 +502,7 @@ define i32 @select_xor_icmp_bad_2(i32 %x, i32 %y, i32 %z,
i32 %k) {
define i32 @select_xor_icmp_bad_3(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @select_xor_icmp_bad_3(
; CHECK-NEXT:[[A:%.*]] = icmp eq i32 [[X:%.*]], 3
-; CHECK-NEXT:[[B:%.*]] = xor i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT:[[B:%.*]] = xor i32 [[Z:%.*]], 3
; CHECK-NEXT:[[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
; CHECK-NEXT:ret i32 [[C]]
;
@@ -541,7 +541,7 @@ define i32 @select_xor_icmp_bad_5(i32 %x, i32 %y, i32 %z) {
define i32 @select_xor_icmp_bad_6(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @select_xor_icmp_bad_6(
; CHECK-NEXT:[[A_NOT:%.*]] = icmp eq i32 [[X:%.*]], 1
-; CHECK-NEXT:[[B:%.*]] = xor i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT:[[B:%.*]] = xor i32 [[Z:%.*]], 1
; CHECK-NEXT:[[C:%.*]] = select i1 [[A_NOT]], i32 [[B]], i32 [[Y:%.*]]
; CHECK-NEXT:ret i32 [[C]]
;
@@ -554,7 +554,7 @@ define i32 @select_xor_icmp_bad_6(i32 %x, i32 %y, i32 %z) {
define <2 x i8> @select_xor_icmp_vec_bad(<2 x i8> %x, <2 x i8> %y, <2 x i8>
%z) {
; CHECK-LABEL: @select_xor_icmp_vec_bad(
; CHECK-NEXT:[[A:%.*]] = icmp eq <2 x i8> [[X:%.*]],
-; CHECK-NEXT:[[B:%.*]] = xor <2 x i8> [[X]], [[Z:%.*]]
+; CHECK-NEXT:[[B:%.*]] = xor <2 x i8> [[Z:%.*]],
; CHECK-NEXT:[[C:%.*]] = select <2 x i1> [[A]], <2 x i8> [[B]], <2 x i8>
[[Y:%.*]]
; CHECK-NEXT:ret <2 x i8> [[C]]
;
@@ -581,7 +581,7 @@ define <2 x i8> @select_xor_icmp_vec_undef(<2 x i8> %x, <2
x i8> %y, <2 x i8> %z
define i32 @select_mul_icmp_bad(i32 %x, i32 %y, i32 %z, i32 %k) {
; CHECK-LABEL: @select_mul_icmp_bad(
; CHECK-NEXT:[[A:%.*]] = icmp eq i32 [[X:%.*]], 3
-; CHECK-NEXT:[[B:%.*]] = mul i32 [[X]], [[Z:%.*]]
+; CHECK-NEXT:[[B:%.*]] = mul i32 [[Z:%.*]], 3
; CHECK-NEXT:[[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]]
; CHECK-NEXT:ret i32 [[C]]
;
@@ -594,7 +594,7 @@ define i32
[llvm-branch-commits] [llvm] 32fc323 - [SimplifyCFG] markAliveBlocks(): catchswitch: preserve PostDomTree
Author: Roman Lebedev
Date: 2021-01-17T01:21:05+03:00
New Revision: 32fc32317a31fc00e7e4086d6c93dd1eab75960c
URL:
https://github.com/llvm/llvm-project/commit/32fc32317a31fc00e7e4086d6c93dd1eab75960c
DIFF:
https://github.com/llvm/llvm-project/commit/32fc32317a31fc00e7e4086d6c93dd1eab75960c.diff
LOG: [SimplifyCFG] markAliveBlocks(): catchswitch: preserve PostDomTree
When removing catchpad's from catchswitch, if that removes a successor,
we need to record that in DomTreeUpdater.
This fixes PostDomTree preservation failure in an existing test.
This appears to be the single issue that i see in my current test coverage.
Added:
Modified:
llvm/lib/Transforms/Utils/Local.cpp
Removed:
diff --git a/llvm/lib/Transforms/Utils/Local.cpp
b/llvm/lib/Transforms/Utils/Local.cpp
index 6e526cc4f105..1f94c6191554 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -2286,6 +2286,7 @@ static bool markAliveBlocks(Function ,
}
};
+ SmallMapVector NumPerSuccessorCases;
// Set of unique CatchPads.
SmallDenseMap>
@@ -2295,14 +2296,22 @@ static bool markAliveBlocks(Function ,
E = CatchSwitch->handler_end();
I != E; ++I) {
BasicBlock *HandlerBB = *I;
+++NumPerSuccessorCases[HandlerBB];
auto *CatchPad = cast(HandlerBB->getFirstNonPHI());
if (!HandlerSet.insert({CatchPad, Empty}).second) {
+ --NumPerSuccessorCases[HandlerBB];
CatchSwitch->removeHandler(I);
--I;
--E;
Changed = true;
}
}
+ std::vector Updates;
+ for (const std::pair : NumPerSuccessorCases)
+if (I.second == 0)
+ Updates.push_back({DominatorTree::Delete, BB, I.first});
+ if (DTU)
+DTU->applyUpdates(Updates);
}
Changed |= ConstantFoldTerminator(BB, true, nullptr, DTU);
___
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[llvm-branch-commits] [llvm] 2a5b576 - [ARM] Test for aligned blocks. NFC
Author: David Green
Date: 2021-01-16T22:04:48Z
New Revision: 2a5b576e3ea41c30537435d989a3dce7a409f8e2
URL:
https://github.com/llvm/llvm-project/commit/2a5b576e3ea41c30537435d989a3dce7a409f8e2
DIFF:
https://github.com/llvm/llvm-project/commit/2a5b576e3ea41c30537435d989a3dce7a409f8e2.diff
LOG: [ARM] Test for aligned blocks. NFC
Added:
llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll
Modified:
Removed:
diff --git a/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll
b/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll
new file mode 100644
index ..90bf4df53f30
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1-m.main-none-eabi -mcpu=cortex-m55 -O3 < %s |
FileCheck %s
+
+define i32 @loop(i32* nocapture readonly %x) {
+; CHECK-LABEL: loop:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT:.save {r7, lr}
+; CHECK-NEXT:push {r7, lr}
+; CHECK-NEXT:mov.w lr, #500
+; CHECK-NEXT:dls lr, lr
+; CHECK-NEXT:movs r1, #0
+; CHECK-NEXT:.p2align 2
+; CHECK-NEXT: .LBB0_1: @ %for.body
+; CHECK-NEXT:@ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:ldr r2, [r0], #4
+; CHECK-NEXT:add r1, r2
+; CHECK-NEXT:le lr, .LBB0_1
+; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
+; CHECK-NEXT:mov r0, r1
+; CHECK-NEXT:pop {r7, pc}
+entry:
+ br label %for.body
+
+for.cond.cleanup: ; preds = %for.body
+ ret i32 %add
+
+for.body: ; preds = %entry, %for.body
+ %i.07 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+ %s.06 = phi i32 [ 0, %entry ], [ %add, %for.body ]
+ %arrayidx = getelementptr inbounds i32, i32* %x, i32 %i.07
+ %0 = load i32, i32* %arrayidx, align 4
+ %add = add nsw i32 %0, %s.06
+ %inc = add nuw nsw i32 %i.07, 1
+ %exitcond.not = icmp eq i32 %inc, 500
+ br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
+}
+
+define i64 @loopif(i32* nocapture readonly %x, i32 %y, i32 %n) {
+; CHECK-LABEL: loopif:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT:.save {r7, lr}
+; CHECK-NEXT:push {r7, lr}
+; CHECK-NEXT:cmp r2, #1
+; CHECK-NEXT:blt .LBB1_4
+; CHECK-NEXT: @ %bb.1: @ %for.body.lr.ph
+; CHECK-NEXT:mov lr, r2
+; CHECK-NEXT:dls lr, r2
+; CHECK-NEXT:mov r12, r0
+; CHECK-NEXT:movs r0, #0
+; CHECK-NEXT:movs r3, #0
+; CHECK-NEXT:.p2align 2
+; CHECK-NEXT: .LBB1_2: @ %for.body
+; CHECK-NEXT:@ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:ldr r2, [r12], #4
+; CHECK-NEXT:smlal r0, r3, r2, r1
+; CHECK-NEXT:le lr, .LBB1_2
+; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup
+; CHECK-NEXT:mov r1, r3
+; CHECK-NEXT:pop {r7, pc}
+; CHECK-NEXT: .LBB1_4:
+; CHECK-NEXT:movs r0, #0
+; CHECK-NEXT:movs r3, #0
+; CHECK-NEXT:mov r1, r3
+; CHECK-NEXT:pop {r7, pc}
+entry:
+ %cmp7 = icmp sgt i32 %n, 0
+ br i1 %cmp7, label %for.body.lr.ph, label %for.cond.cleanup
+
+for.body.lr.ph: ; preds = %entry
+ %conv1 = sext i32 %y to i64
+ br label %for.body
+
+for.cond.cleanup: ; preds = %for.body, %entry
+ %s.0.lcssa = phi i64 [ 0, %entry ], [ %add, %for.body ]
+ ret i64 %s.0.lcssa
+
+for.body: ; preds = %for.body.lr.ph,
%for.body
+ %i.09 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
+ %s.08 = phi i64 [ 0, %for.body.lr.ph ], [ %add, %for.body ]
+ %arrayidx = getelementptr inbounds i32, i32* %x, i32 %i.09
+ %0 = load i32, i32* %arrayidx, align 4
+ %conv = sext i32 %0 to i64
+ %mul = mul nsw i64 %conv, %conv1
+ %add = add nsw i64 %mul, %s.08
+ %inc = add nuw nsw i32 %i.09, 1
+ %exitcond.not = icmp eq i32 %inc, %n
+ br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
+}
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[llvm-branch-commits] [llvm] 1454724 - [ARM] Align blocks that are not fallthough targets
Author: David Green
Date: 2021-01-16T22:19:35Z
New Revision: 145472421535c71a9ea60af7e5d012ab69dc85ff
URL:
https://github.com/llvm/llvm-project/commit/145472421535c71a9ea60af7e5d012ab69dc85ff
DIFF:
https://github.com/llvm/llvm-project/commit/145472421535c71a9ea60af7e5d012ab69dc85ff.diff
LOG: [ARM] Align blocks that are not fallthough targets
If the previous block in a function does not fallthough, adding nop's to
align it will never be executed. This means we can freely (except for
codesize) align more branches. This happens in constantislandspass (as
it cannot happen later) and only happens at aggressive optimization
levels as it does increase codesize.
Differential Revision: https://reviews.llvm.org/D94394
Added:
Modified:
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll
Removed:
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index e89eb0fb4502..630490f6f914 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -338,6 +338,32 @@ LLVM_DUMP_METHOD void ARMConstantIslands::dumpBBs() {
}
#endif
+// Align blocks where the previous block does not fall through. This may add
+// extra NOP's but they will not be executed. It uses the PrefLoopAlignment as
a
+// measure of how much to align, and only runs at CodeGenOpt::Aggressive.
+static bool AlignBlocks(MachineFunction *MF) {
+ if (MF->getTarget().getOptLevel() != CodeGenOpt::Aggressive ||
+ MF->getFunction().hasOptSize())
+return false;
+
+ auto *TLI = MF->getSubtarget().getTargetLowering();
+ const Align Alignment = TLI->getPrefLoopAlignment();
+ if (Alignment < 4)
+return false;
+
+ bool Changed = false;
+ bool PrevCanFallthough = true;
+ for (auto : *MF) {
+if (!PrevCanFallthough) {
+ Changed = true;
+ MBB.setAlignment(Alignment);
+}
+PrevCanFallthough = MBB.canFallThrough();
+ }
+
+ return Changed;
+}
+
bool ARMConstantIslands::runOnMachineFunction(MachineFunction ) {
MF =
MCP = mf.getConstantPool();
@@ -380,6 +406,9 @@ bool
ARMConstantIslands::runOnMachineFunction(MachineFunction ) {
MF->RenumberBlocks();
}
+ // Align any non-fallthrough blocks
+ MadeChange |= AlignBlocks(MF);
+
// Perform the initial placement of the constant pool entries. To start
with,
// we put them all at the end of the function.
std::vector CPEMIs;
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
b/llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
index b949934e51df..ea7a83b96b46 100644
--- a/llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
+++ b/llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
@@ -26,6 +26,7 @@ define i32 @add_user(i32 %arg, i32* nocapture readnone %arg1,
i16* nocapture rea
; CHECK-LE-NEXT: @ %bb.3: @ %for.cond.cleanup
; CHECK-LE-NEXT:add.w r0, r12, r1
; CHECK-LE-NEXT:pop {r4, pc}
+; CHECK-LE-NEXT:.p2align 2
; CHECK-LE-NEXT: .LBB0_4:
; CHECK-LE-NEXT:mov.w r12, #0
; CHECK-LE-NEXT:movs r1, #0
@@ -58,6 +59,7 @@ define i32 @add_user(i32 %arg, i32* nocapture readnone %arg1,
i16* nocapture rea
; CHECK-BE-NEXT: @ %bb.3: @ %for.cond.cleanup
; CHECK-BE-NEXT:add.w r0, r12, r1
; CHECK-BE-NEXT:pop {r4, r5, r6, pc}
+; CHECK-BE-NEXT:.p2align 2
; CHECK-BE-NEXT: .LBB0_4:
; CHECK-BE-NEXT:mov.w r12, #0
; CHECK-BE-NEXT:movs r1, #0
@@ -129,6 +131,7 @@ define i32 @mul_bottom_user(i32 %arg, i32* nocapture
readnone %arg1, i16* nocapt
; CHECK-LE-NEXT: @ %bb.3: @ %for.cond.cleanup
; CHECK-LE-NEXT:add.w r0, r12, r1
; CHECK-LE-NEXT:pop {r4, r5, r7, pc}
+; CHECK-LE-NEXT:.p2align 2
; CHECK-LE-NEXT: .LBB1_4:
; CHECK-LE-NEXT:mov.w r12, #0
; CHECK-LE-NEXT:movs r1, #0
@@ -161,6 +164,7 @@ define i32 @mul_bottom_user(i32 %arg, i32* nocapture
readnone %arg1, i16* nocapt
; CHECK-BE-NEXT: @ %bb.3: @ %for.cond.cleanup
; CHECK-BE-NEXT:add.w r0, r12, r1
; CHECK-BE-NEXT:pop {r4, r5, r6, pc}
+; CHECK-BE-NEXT:.p2align 2
; CHECK-BE-NEXT: .LBB1_4:
; CHECK-BE-NEXT:mov.w r12, #0
; CHECK-BE-NEXT:movs r1, #0
@@ -232,6 +236,7 @@ define i32 @mul_top_user(i32 %arg, i32* nocapture readnone
%arg1, i16* nocapture
; CHECK-LE-NEXT: @ %bb.3: @ %for.cond.cleanup
; CHECK-LE-NEXT:add.w r0, r12, r1
; CHECK-LE-NEXT:pop {r4, pc}
+; CHECK-LE-NEXT:.p2align 2
; CHECK-LE-NEXT: .LBB2_4:
; CHECK-LE-NEXT:mov.w r12, #0
; CHECK-LE-NEXT:movs r1, #0
@@ -264,6 +269,7 @@ define i32 @mul_top_user(i32 %arg, i32* nocapture readnone
%arg1, i16* nocapture
; CHECK-BE-NEXT: @ %bb.3: @ %for.cond.cleanup
; CHECK-BE-NEXT:add.w r0, r12, r1
; CHECK-BE-NEXT:pop {r4, r5, r6, pc}
+; CHECK-BE-NEXT:.p2align 2
; CHECK-BE-NEXT: .LBB2_4:
; CHECK-BE-NEXT:
[llvm-branch-commits] [llvm] bfd75bd - [NFC] Removed extra text in comments
Author: Dávid Bolvanský Date: 2021-01-16T22:48:56+01:00 New Revision: bfd75bdf3fd62d4f5e7028d4122f9ffa517f2a09 URL: https://github.com/llvm/llvm-project/commit/bfd75bdf3fd62d4f5e7028d4122f9ffa517f2a09 DIFF: https://github.com/llvm/llvm-project/commit/bfd75bdf3fd62d4f5e7028d4122f9ffa517f2a09.diff LOG: [NFC] Removed extra text in comments Added: Modified: llvm/lib/Analysis/InstructionSimplify.cpp Removed: diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp index 6a065c46d9bf..b672798aaffc 100644 --- a/llvm/lib/Analysis/InstructionSimplify.cpp +++ b/llvm/lib/Analysis/InstructionSimplify.cpp @@ -2236,7 +2236,7 @@ static Value *SimplifyOrInst(Value *Op0, Value *Op1, const SimplifyQuery , // Commute the 'or' operands. // (A ^ B) | (A & ~B) -> (A ^ B) - // (A ^ B) | (~B & A) -> (A ^ B)D94870 + // (A ^ B) | (~B & A) -> (A ^ B) // (B ^ A) | (A & ~B) -> (B ^ A) // (B ^ A) | (~B & A) -> (B ^ A) if (match(Op0, m_Xor(m_Value(A), m_Value(B))) && ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] d8fc273 - [mlir][sparse] improved sparse runtime support library
Author: Aart Bik
Date: 2021-01-16T12:16:10-08:00
New Revision: d8fc27301d18f0935ba99ead7ac61aa6a53f16e4
URL:
https://github.com/llvm/llvm-project/commit/d8fc27301d18f0935ba99ead7ac61aa6a53f16e4
DIFF:
https://github.com/llvm/llvm-project/commit/d8fc27301d18f0935ba99ead7ac61aa6a53f16e4.diff
LOG: [mlir][sparse] improved sparse runtime support library
Added the ability to read (an extended version of) the FROSTT
file format, so that we can now read in sparse tensors of arbitrary
rank. Generalized the API to deal with more than two dimensions.
Also added the ability to sort the indices of sparse tensors
lexicographically. This is an important step towards supporting
auto gen of initialization code, since sparse storage formats
are easier to initialize if the indices are sorted. Since most
external formats don't enforce such properties, it is convenient
to have this ability in our runtime support library.
Lastly, the re-entrant problem of the original implementation
is fixed by passing an opaque object around (rather than having
a single static variable, ugh!).
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D94852
Added:
mlir/integration_test/Sparse/CPU/frostt-example.mlir
mlir/integration_test/data/test.tns
Modified:
mlir/include/mlir/ExecutionEngine/CRunnerUtils.h
mlir/integration_test/CMakeLists.txt
mlir/integration_test/Sparse/CPU/matrix-market-example.mlir
mlir/lib/ExecutionEngine/SparseUtils.cpp
Removed:
diff --git a/mlir/include/mlir/ExecutionEngine/CRunnerUtils.h
b/mlir/include/mlir/ExecutionEngine/CRunnerUtils.h
index edcd8e0dc545..2d0608a8656b 100644
--- a/mlir/include/mlir/ExecutionEngine/CRunnerUtils.h
+++ b/mlir/include/mlir/ExecutionEngine/CRunnerUtils.h
@@ -198,7 +198,7 @@ class DynamicMemRefType {
};
//===--===//
-// Small runtime support "lib" for vector.print lowering during codegen.
+// Small runtime support library for vector.print lowering during codegen.
//===--===//
extern "C" MLIR_CRUNNERUTILS_EXPORT void printI64(int64_t i);
extern "C" MLIR_CRUNNERUTILS_EXPORT void printU64(uint64_t u);
@@ -210,15 +210,13 @@ extern "C" MLIR_CRUNNERUTILS_EXPORT void printComma();
extern "C" MLIR_CRUNNERUTILS_EXPORT void printNewline();
//===--===//
-// Small runtime support for sparse tensors.
+// Small runtime support library for sparse tensors.
//===--===//
-extern "C" MLIR_CRUNNERUTILS_EXPORT void openMatrixC(char *filename,
- uint64_t *mdata,
- uint64_t *ndata,
- uint64_t *nnzdata);
+extern "C" MLIR_CRUNNERUTILS_EXPORT void *openTensorC(char *filename,
+ uint64_t *idata);
extern "C" MLIR_CRUNNERUTILS_EXPORT void
-readMatrixItemC(uint64_t *idata, uint64_t *jdata, double *ddata);
-extern "C" MLIR_CRUNNERUTILS_EXPORT void closeMatrix();
-extern "C" MLIR_CRUNNERUTILS_EXPORT char *getMatrix(uint64_t id);
+readTensorItemC(void *tensor, uint64_t *idata, double *ddata);
+extern "C" MLIR_CRUNNERUTILS_EXPORT void closeTensor(void *tensor);
+extern "C" MLIR_CRUNNERUTILS_EXPORT char *getTensorFilename(uint64_t id);
#endif // EXECUTIONENGINE_CRUNNERUTILS_H_
diff --git a/mlir/integration_test/CMakeLists.txt
b/mlir/integration_test/CMakeLists.txt
index bc5ad90e1253..fb2be5256dcc 100644
--- a/mlir/integration_test/CMakeLists.txt
+++ b/mlir/integration_test/CMakeLists.txt
@@ -31,4 +31,5 @@ add_lit_testsuites(MLIR_INTEGRATION
${CMAKE_CURRENT_SOURCE_DIR}
# Copy test data over.
file(COPY ${CMAKE_CURRENT_SOURCE_DIR}/data/test.mtx
+ ${CMAKE_CURRENT_SOURCE_DIR}/data/test.tns
DESTINATION ${MLIR_INTEGRATION_TEST_DIR}/data/)
diff --git a/mlir/integration_test/Sparse/CPU/frostt-example.mlir
b/mlir/integration_test/Sparse/CPU/frostt-example.mlir
new file mode 100644
index ..8144270aa91f
--- /dev/null
+++ b/mlir/integration_test/Sparse/CPU/frostt-example.mlir
@@ -0,0 +1,149 @@
+// RUN: mlir-opt %s \
+// RUN: -convert-scf-to-std -convert-vector-to-scf \
+// RUN: -convert-linalg-to-llvm -convert-vector-to-llvm | \
+// RUN: TENSOR0="%mlir_integration_test_dir/data/test.tns" \
+// RUN: mlir-cpu-runner \
+// RUN: -e entry -entry-point-result=void \
+// RUN:
-shared-libs=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \
+// RUN: FileCheck %s
+
+module {
+ //
+ // Example of using the sparse runtime support library to read a sparse
tensor
+ // in the FROSTT file format (http://frostt.io/tensors/file-formats.html).
+ //
+
[llvm-branch-commits] [openmp] ed939f8 - [OpenMP] Added the support for hidden helper task in RTL
Author: Shilei Tian
Date: 2021-01-16T14:13:35-05:00
New Revision: ed939f853da1f2266f00ea087f778fda88848f73
URL:
https://github.com/llvm/llvm-project/commit/ed939f853da1f2266f00ea087f778fda88848f73
DIFF:
https://github.com/llvm/llvm-project/commit/ed939f853da1f2266f00ea087f778fda88848f73.diff
LOG: [OpenMP] Added the support for hidden helper task in RTL
The basic design is to create an outer-most parallel team. It is not a regular
team because it is only created when the first hidden helper task is
encountered, and is only responsible for the execution of hidden helper tasks.
We first use `pthread_create` to create a new thread, let's call it the initial
and also the main thread of the hidden helper team. This initial thread then
initializes a new root, just like what RTL does in initialization. After that,
it directly calls `__kmpc_fork_call`. It is like the initial thread encounters
a parallel region. The wrapped function for this team is, for main thread,
which is the initial thread that we create via `pthread_create` on Linux, waits
on a condition variable. The condition variable can only be signaled when RTL
is being destroyed. For other work threads, they just do nothing. The reason
that main thread needs to wait there is, in current implementation, once the
main thread finishes the wrapped function of this team, it starts to free the
team which is not what we want.
Two environment variables, `LIBOMP_NUM_HIDDEN_HELPER_THREADS` and
`LIBOMP_USE_HIDDEN_HELPER_TASK`, are also set to configure the number of
threads and enable/disable this feature. By default, the number of hidden
helper threads is 8.
Here are some open issues to be discussed:
1. The main thread goes to sleeping when the initialization is finished. As
Andrey mentioned, we might need it to be awaken from time to time to do some
stuffs. What kind of update/check should be put here?
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D77609
Added:
openmp/runtime/test/tasking/hidden_helper_task/common.h
openmp/runtime/test/tasking/hidden_helper_task/depend.cpp
openmp/runtime/test/tasking/hidden_helper_task/gtid.cpp
openmp/runtime/test/tasking/hidden_helper_task/taskgroup.cpp
Modified:
openmp/runtime/src/kmp.h
openmp/runtime/src/kmp_global.cpp
openmp/runtime/src/kmp_runtime.cpp
openmp/runtime/src/kmp_settings.cpp
openmp/runtime/src/kmp_taskdeps.h
openmp/runtime/src/kmp_tasking.cpp
openmp/runtime/src/kmp_wait_release.h
openmp/runtime/src/z_Linux_util.cpp
openmp/runtime/test/worksharing/for/kmp_sch_simd_guided.c
Removed:
diff --git a/openmp/runtime/src/kmp.h b/openmp/runtime/src/kmp.h
index 983511042fa7..8a2d44d6bd48 100644
--- a/openmp/runtime/src/kmp.h
+++ b/openmp/runtime/src/kmp.h
@@ -2334,7 +2334,8 @@ typedef struct kmp_tasking_flags { /* Total struct must
be exactly 32 bits */
unsigned priority_specified : 1; /* set if the compiler provides priority
setting for the task */
unsigned detachable : 1; /* 1 == can detach */
- unsigned reserved : 9; /* reserved for compiler use */
+ unsigned hidden_helper : 1; /* 1 == hidden helper task */
+ unsigned reserved : 8; /* reserved for compiler use */
/* Library flags */ /* Total library flags must be 16 bits */
unsigned tasktype : 1; /* task is either explicit(1) or implicit (0) */
@@ -2382,6 +2383,18 @@ struct kmp_taskdata { /* aligned during dynamic
allocation */
kmp_depnode_t
*td_depnode; // Pointer to graph node if this task has dependencies
kmp_task_team_t *td_task_team;
+ // The parent task team. Usually we could access it via
+ // parent_task->td_task_team, but it is possible to be nullptr because of
late
+ // initialization. Sometimes we must use it. Since the td_task_team of the
+ // encountering thread is never nullptr, we set it when this task is created.
+ kmp_task_team_t *td_parent_task_team;
+ // The global thread id of the encountering thread. We need it because when a
+ // regular task depends on a hidden helper task, and the hidden helper task
+ // is finished on a hidden helper thread, it will call __kmp_release_deps to
+ // release all dependences. If now the task is a regular task, we need to
pass
+ // the encountering gtid such that the task will be picked up and executed by
+ // its encountering team instead of hidden helper team.
+ kmp_int32 encountering_gtid;
size_t td_size_alloc; // Size of task structure, including shareds etc.
#if defined(KMP_GOMP_COMPAT)
// 4 or 8 byte integers for the loop bounds in GOMP_taskloop
@@ -2449,10 +2462,16 @@ typedef struct kmp_base_task_team {
kmp_int32 tt_max_threads; // # entries allocated for threads_data array
kmp_int32 tt_found_proxy_tasks; // found proxy tasks since last barrier
kmp_int32 tt_untied_task_encountered;
+ // There is hidden
[llvm-branch-commits] [llvm] 49b96cd - [SLP] remove opcode field from reduction data class
Author: Sanjay Patel
Date: 2021-01-16T13:55:52-05:00
New Revision: 49b96cd9ef2f81d193641796b8a85781292faf7a
URL:
https://github.com/llvm/llvm-project/commit/49b96cd9ef2f81d193641796b8a85781292faf7a
DIFF:
https://github.com/llvm/llvm-project/commit/49b96cd9ef2f81d193641796b8a85781292faf7a.diff
LOG: [SLP] remove opcode field from reduction data class
This is NFC-intended and another step towards supporting
intrinsics as reduction candidates.
The remaining bits of the OperationData class do not make
much sense as-is, so I will try to improve that, but I'm
trying to take minimal steps because it's still not clear
how this was intended to work.
Added:
Modified:
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index a8d8ef5024d7..8dd318a880fc 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -6430,40 +6430,15 @@ class HorizontalReduction {
// Use map vector to make stable output.
MapVector ExtraArgs;
- /// Contains info about operation, like its opcode, left and right operands.
+ /// This wraps functionality around a RecurKind (reduction kind).
+ /// TODO: Remove this class if callers can use the 'Kind' value directly?
class OperationData {
-/// Opcode of the instruction.
-unsigned Opcode = 0;
-
/// Kind of the reduction operation.
RecurKind Kind = RecurKind::None;
+bool IsLeafValue = false;
/// Checks if the reduction operation can be vectorized.
-bool isVectorizable() const {
- switch (Kind) {
- case RecurKind::Add:
-return Opcode == Instruction::Add;
- case RecurKind::Mul:
-return Opcode == Instruction::Mul;
- case RecurKind::Or:
-return Opcode == Instruction::Or;
- case RecurKind::And:
-return Opcode == Instruction::And;
- case RecurKind::Xor:
-return Opcode == Instruction::Xor;
- case RecurKind::FAdd:
-return Opcode == Instruction::FAdd;
- case RecurKind::FMul:
-return Opcode == Instruction::FMul;
- case RecurKind::SMax:
- case RecurKind::SMin:
- case RecurKind::UMax:
- case RecurKind::UMin:
-return Opcode == Instruction::ICmp;
- default:
-return false;
- }
-}
+bool isVectorizable() const { return Kind != RecurKind::None; }
/// Creates reduction operation with the current opcode.
Value *createOp(IRBuilder<> , Value *LHS, Value *RHS,
@@ -6505,19 +6480,17 @@ class HorizontalReduction {
public:
explicit OperationData() = default;
-/// Construction for reduced values. They are identified by opcode only and
-/// don't have associated LHS/RHS values.
-explicit OperationData(Instruction ) {
- Opcode = I.getOpcode();
-}
+/// Constructor for reduced values. They are identified by the bool only.
+explicit OperationData(Instruction ) { IsLeafValue = true; }
/// Constructor for reduction operations with opcode and type.
-OperationData(unsigned Opcode, RecurKind RdxKind)
-: Opcode(Opcode), Kind(RdxKind) {
+OperationData(RecurKind RdxKind) : Kind(RdxKind) {
assert(Kind != RecurKind::None && "Expected reduction operation.");
}
-explicit operator bool() const { return Opcode; }
+explicit operator bool() const {
+ return IsLeafValue || Kind != RecurKind::None;
+}
/// Return true if this operation is any kind of minimum or maximum.
bool isMinMax() const {
@@ -6580,8 +6553,7 @@ class HorizontalReduction {
/// Add all reduction operations for the reduction instruction \p I.
void addReductionOps(Instruction *I, ReductionOpsListType ) {
- assert(Kind != RecurKind::None && !!*this &&
- "Expected reduction operation.");
+ assert(Kind != RecurKind::None && "Expected reduction operation.");
if (isMinMax()) {
ReductionOps[0].emplace_back(cast(I)->getCondition());
ReductionOps[1].emplace_back(I);
@@ -6592,13 +6564,10 @@ class HorizontalReduction {
/// Checks if instruction is associative and can be vectorized.
bool isAssociative(Instruction *I) const {
- assert(Kind != RecurKind::None && *this &&
- "Expected reduction operation.");
- if (RecurrenceDescriptor::isIntMinMaxRecurrenceKind(Kind)) {
-assert(Opcode == Instruction::ICmp &&
- "Only integer compare operation is expected.");
+ assert(Kind != RecurKind::None && "Expected reduction operation.");
+ if (RecurrenceDescriptor::isIntMinMaxRecurrenceKind(Kind))
return true;
- }
+
return I->isAssociative();
}
@@ -6610,9 +6579,7 @@ class HorizontalReduction {
/// Checks if two operation data are both a reduction op or both a
[llvm-branch-commits] [llvm] fcfcc3c - [SLP] fix typos; NFC
Author: Sanjay Patel
Date: 2021-01-16T13:55:52-05:00
New Revision: fcfcc3cc6b16e4fd7d7d2d07937634cca360b46e
URL:
https://github.com/llvm/llvm-project/commit/fcfcc3cc6b16e4fd7d7d2d07937634cca360b46e
DIFF:
https://github.com/llvm/llvm-project/commit/fcfcc3cc6b16e4fd7d7d2d07937634cca360b46e.diff
LOG: [SLP] fix typos; NFC
Added:
Modified:
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index d5e6dfed8e2c..a8d8ef5024d7 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -6784,7 +6784,7 @@ class HorizontalReduction {
/// Try to find a reduction tree.
bool matchAssociativeReduction(PHINode *Phi, Instruction *B) {
assert((!Phi || is_contained(Phi->operands(), B)) &&
- "Thi phi needs to use the binary operator");
+ "Phi needs to use the binary operator");
RdxTreeInst = getOperationData(B);
@@ -6831,7 +6831,7 @@ class HorizontalReduction {
const OperationData OpData = getOperationData(TreeN);
bool IsReducedValue = OpData != RdxTreeInst;
- // Postorder vist.
+ // Postorder visit.
if (IsReducedValue || EdgeToVisit == OpData.getNumberOfOperands()) {
if (IsReducedValue)
ReducedVals.push_back(TreeN);
___
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[llvm-branch-commits] [llvm] 48dbac5 - [SLP] remove unnecessary use of 'OperationData'
Author: Sanjay Patel
Date: 2021-01-16T13:55:52-05:00
New Revision: 48dbac5b6b0bc7a03e9af42cb99176abba8d0467
URL:
https://github.com/llvm/llvm-project/commit/48dbac5b6b0bc7a03e9af42cb99176abba8d0467
DIFF:
https://github.com/llvm/llvm-project/commit/48dbac5b6b0bc7a03e9af42cb99176abba8d0467.diff
LOG: [SLP] remove unnecessary use of 'OperationData'
This is another NFC-intended patch to allow matching
intrinsics (example: maxnum) as candidates for reductions.
It's possible that the loop/if logic can be reduced now,
but it's still difficult to understand how this all works.
Added:
Modified:
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index cf7c05e30d06..d5e6dfed8e2c 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -6814,8 +6814,11 @@ class HorizontalReduction {
ReductionRoot = B;
-// The operation data for the leaf values that we perform a reduction on.
-OperationData RdxLeafVal;
+// The opcode for leaf values that we perform a reduction on.
+// For example: load(x) + load(y) + load(z) + fptoui(w)
+// The leaf opcode for 'w' does not match, so we don't include it as a
+// potential candidate for the reduction.
+unsigned LeafOpcode = 0;
// Post order traverse the reduction tree starting at B. We only handle
true
// trees containing only binary operators.
@@ -6859,9 +6862,9 @@ class HorizontalReduction {
auto *I = dyn_cast(NextV);
const OperationData EdgeOpData = getOperationData(I);
// Continue analysis if the next operand is a reduction operation or
- // (possibly) a reduced value. If the reduced value opcode is not set,
+ // (possibly) a leaf value. If the leaf value opcode is not set,
// the first met operation != reduction operation is considered as the
- // reduced value class.
+ // leaf opcode.
// Only handle trees in the current basic block.
// Each tree node needs to have minimal number of users except for the
// ultimate reduction.
@@ -6869,7 +6872,7 @@ class HorizontalReduction {
if (I && I != Phi && I != B &&
RdxTreeInst.hasSameParent(I, B->getParent(), IsRdxInst) &&
RdxTreeInst.hasRequiredNumberOfUses(I, IsRdxInst) &&
- (!RdxLeafVal || EdgeOpData == RdxLeafVal || IsRdxInst)) {
+ (!LeafOpcode || LeafOpcode == I->getOpcode() || IsRdxInst)) {
if (IsRdxInst) {
// We need to be able to reassociate the reduction operations.
if (!EdgeOpData.isAssociative(I)) {
@@ -6877,8 +6880,8 @@ class HorizontalReduction {
markExtraArg(Stack.back(), I);
continue;
}
-} else if (!RdxLeafVal) {
- RdxLeafVal = EdgeOpData;
+} else if (!LeafOpcode) {
+ LeafOpcode = I->getOpcode();
}
Stack.push_back(std::make_pair(I, EdgeOpData.getFirstOperandIndex()));
continue;
___
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[llvm-branch-commits] [llvm] 63bedc8 - [InstSimplify] Handle commutativity for 'and' and 'outer or' for (~A & B) | ~(A | B) --> ~A
Author: Dávid Bolvanský
Date: 2021-01-16T19:42:50+01:00
New Revision: 63bedc80da36cf5eb71b06b453c186e057607bf4
URL:
https://github.com/llvm/llvm-project/commit/63bedc80da36cf5eb71b06b453c186e057607bf4
DIFF:
https://github.com/llvm/llvm-project/commit/63bedc80da36cf5eb71b06b453c186e057607bf4.diff
LOG: [InstSimplify] Handle commutativity for 'and' and 'outer or' for (~A & B)
| ~(A | B) --> ~A
Reviewed By: lebedev.ri
Differential Revision: https://reviews.llvm.org/D94870
Added:
Modified:
llvm/lib/Analysis/InstructionSimplify.cpp
llvm/test/Transforms/InstSimplify/or.ll
Removed:
diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp
b/llvm/lib/Analysis/InstructionSimplify.cpp
index 73f046dcb8de..6a065c46d9bf 100644
--- a/llvm/lib/Analysis/InstructionSimplify.cpp
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp
@@ -2224,7 +2224,7 @@ static Value *SimplifyOrInst(Value *Op0, Value *Op1,
const SimplifyQuery ,
if (Value *V = simplifyLogicOfAddSub(Op0, Op1, Instruction::Or))
return V;
- Value *A, *B;
+ Value *A, *B, *NotA;
// (A & ~B) | (A ^ B) -> (A ^ B)
// (~B & A) | (A ^ B) -> (A ^ B)
// (A & ~B) | (B ^ A) -> (B ^ A)
@@ -2236,7 +2236,7 @@ static Value *SimplifyOrInst(Value *Op0, Value *Op1,
const SimplifyQuery ,
// Commute the 'or' operands.
// (A ^ B) | (A & ~B) -> (A ^ B)
- // (A ^ B) | (~B & A) -> (A ^ B)
+ // (A ^ B) | (~B & A) -> (A ^ B)D94870
// (B ^ A) | (A & ~B) -> (B ^ A)
// (B ^ A) | (~B & A) -> (B ^ A)
if (match(Op0, m_Xor(m_Value(A), m_Value(B))) &&
@@ -2253,6 +2253,7 @@ static Value *SimplifyOrInst(Value *Op0, Value *Op1,
const SimplifyQuery ,
match(Op1, m_c_Xor(m_Not(m_Specific(A)), m_Specific(B)
return Op1;
+ // Commute the 'or' operands.
// (~A ^ B) | (A & B) -> (~A ^ B)
// (~A ^ B) | (B & A) -> (~A ^ B)
// (B ^ ~A) | (A & B) -> (B ^ ~A)
@@ -2266,9 +2267,20 @@ static Value *SimplifyOrInst(Value *Op0, Value *Op1,
const SimplifyQuery ,
// (~A & B) | ~(B | A) --> ~A
// (B & ~A) | ~(A | B) --> ~A
// (B & ~A) | ~(B | A) --> ~A
- if (match(Op0, m_And(m_Not(m_Value(A)), m_Value(B))) &&
+ if (match(Op0, m_c_And(m_CombineAnd(m_Value(NotA), m_Not(m_Value(A))),
+ m_Value(B))) &&
match(Op1, m_Not(m_c_Or(m_Specific(A), m_Specific(B)
-return cast(Op0)->getOperand(0);
+return NotA;
+
+ // Commute the 'or' operands.
+ // ~(A | B) | (~A & B) --> ~A
+ // ~(B | A) | (~A & B) --> ~A
+ // ~(A | B) | (B & ~A) --> ~A
+ // ~(B | A) | (B & ~A) --> ~A
+ if (match(Op1, m_c_And(m_CombineAnd(m_Value(NotA), m_Not(m_Value(A))),
+ m_Value(B))) &&
+ match(Op0, m_Not(m_c_Or(m_Specific(A), m_Specific(B)
+return NotA;
if (Value *V = simplifyAndOrOfCmps(Q, Op0, Op1, false))
return V;
diff --git a/llvm/test/Transforms/InstSimplify/or.ll
b/llvm/test/Transforms/InstSimplify/or.ll
index 68d2af4a4041..7f347193be9a 100644
--- a/llvm/test/Transforms/InstSimplify/or.ll
+++ b/llvm/test/Transforms/InstSimplify/or.ll
@@ -399,11 +399,7 @@ define i32 @and_or_not_or4_use3(i32 %A, i32 %B) {
define i32 @and_or_not_or5(i32 %A, i32 %B) {
; CHECK-LABEL: @and_or_not_or5(
; CHECK-NEXT:[[I:%.*]] = xor i32 [[A:%.*]], -1
-; CHECK-NEXT:[[I2:%.*]] = and i32 [[B:%.*]], [[I]]
-; CHECK-NEXT:[[I3:%.*]] = or i32 [[B]], [[A]]
-; CHECK-NEXT:[[I4:%.*]] = xor i32 [[I3]], -1
-; CHECK-NEXT:[[I5:%.*]] = or i32 [[I2]], [[I4]]
-; CHECK-NEXT:ret i32 [[I5]]
+; CHECK-NEXT:ret i32 [[I]]
;
%i = xor i32 %A, -1
%i2 = and i32 %B, %i
@@ -416,11 +412,7 @@ define i32 @and_or_not_or5(i32 %A, i32 %B) {
define i32 @and_or_not_or6(i32 %A, i32 %B) {
; CHECK-LABEL: @and_or_not_or6(
; CHECK-NEXT:[[I:%.*]] = xor i32 [[A:%.*]], -1
-; CHECK-NEXT:[[I2:%.*]] = and i32 [[I]], [[B:%.*]]
-; CHECK-NEXT:[[I3:%.*]] = or i32 [[B]], [[A]]
-; CHECK-NEXT:[[I4:%.*]] = xor i32 [[I3]], -1
-; CHECK-NEXT:[[I5:%.*]] = or i32 [[I4]], [[I2]]
-; CHECK-NEXT:ret i32 [[I5]]
+; CHECK-NEXT:ret i32 [[I]]
;
%i = xor i32 %A, -1
%i2 = and i32 %i, %B
@@ -433,11 +425,7 @@ define i32 @and_or_not_or6(i32 %A, i32 %B) {
define i32 @and_or_not_or7(i32 %A, i32 %B) {
; CHECK-LABEL: @and_or_not_or7(
; CHECK-NEXT:[[I:%.*]] = xor i32 [[A:%.*]], -1
-; CHECK-NEXT:[[I2:%.*]] = and i32 [[B:%.*]], [[I]]
-; CHECK-NEXT:[[I3:%.*]] = or i32 [[B]], [[A]]
-; CHECK-NEXT:[[I4:%.*]] = xor i32 [[I3]], -1
-; CHECK-NEXT:[[I5:%.*]] = or i32 [[I4]], [[I2]]
-; CHECK-NEXT:ret i32 [[I5]]
+; CHECK-NEXT:ret i32 [[I]]
;
%i = xor i32 %A, -1
%i2 = and i32 %B, %i
@@ -450,11 +438,7 @@ define i32 @and_or_not_or7(i32 %A, i32 %B) {
define i32 @and_or_not_or8(i32 %A, i32 %B) {
; CHECK-LABEL: @and_or_not_or8(
; CHECK-NEXT:[[I:%.*]] = xor i32 [[B:%.*]], -1
-; CHECK-NEXT:[[I2:%.*]] = and i32 [[A:%.*]], [[I]]
-; CHECK-NEXT:[[I3:%.*]] = or i32 [[B]],
[llvm-branch-commits] [llvm] 372eb2b - [ARM] Add low overhead loops terminators to AnalyzeBranch
Author: David Green
Date: 2021-01-16T18:30:21Z
New Revision: 372eb2bbb6fb903ce76266e659dfefbaee67722b
URL:
https://github.com/llvm/llvm-project/commit/372eb2bbb6fb903ce76266e659dfefbaee67722b
DIFF:
https://github.com/llvm/llvm-project/commit/372eb2bbb6fb903ce76266e659dfefbaee67722b.diff
LOG: [ARM] Add low overhead loops terminators to AnalyzeBranch
This treats low overhead loop branches the same as jump tables and
indirect branches in analyzeBranch - they cannot be analyzed but the
direct branches on the end of the block may be removed. This helps
remove the unnecessary branches earlier, which can help produce better
codegen (and change block layout in a number of cases).
Differential Revision: https://reviews.llvm.org/D94392
Added:
Modified:
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/sibling-loops.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
llvm/test/CodeGen/Thumb2/mve-gather-tailpred.ll
llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
llvm/test/CodeGen/Thumb2/mve-scatter-increment.ll
llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
llvm/test/CodeGen/Thumb2/mve-vldshuffle.ll
Removed:
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index fa564f50f679..54586e0c256b 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -374,7 +374,8 @@ bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock ,
}
if (isIndirectBranchOpcode(I->getOpcode()) ||
-isJumpTableBranchOpcode(I->getOpcode())) {
+isJumpTableBranchOpcode(I->getOpcode()) ||
+isLowOverheadTerminatorOpcode(I->getOpcode())) {
// Indirect branches and jump tables can't be analyzed, but we still want
// to clean up any instructions at the tail of the basic block.
CantAnalyze = true;
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index deb008025b1d..b14f7e480856 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -634,6 +634,11 @@ static inline bool isJumpTableBranchOpcode(int Opc) {
Opc == ARM::t2BR_JT;
}
+static inline bool isLowOverheadTerminatorOpcode(int Opc) {
+ return Opc == ARM::t2DoLoopStartTP || Opc == ARM::t2WhileLoopStart ||
+ Opc == ARM::t2LoopEnd || Opc == ARM::t2LoopEndDec;
+}
+
static inline
bool isIndirectBranchOpcode(int Opc) {
return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
index fec6ff7c2154..ec574ad827a4 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
@@ -330,9 +330,9 @@ define arm_aapcs_vfpcc float @fast_float_half_mac(half*
nocapture readonly %b, h
; CHECK-NEXT:vdup.32 q1, r12
; CHECK-NEXT:vdup.32 q2, r12
; CHECK-NEXT:vstrw.32 q0, [sp] @ 16-byte Spill
-; CHECK-NEXT:b .LBB2_4
+; CHECK-NEXT:b .LBB2_5
; CHECK-NEXT: .LBB2_2: @ %cond.load25
-; CHECK-NEXT:@ in Loop: Header=BB2_4 Depth=1
+; CHECK-NEXT:@ in Loop: Header=BB2_5 Depth=1
; CHECK-NEXT:vmovx.f16 s0, s28
; CHECK-NEXT:vmov r4, s28
; CHECK-NEXT:vmov r2, s0
@@ -344,7 +344,7 @@ define arm_aapcs_vfpcc float @fast_float_half_mac(half*
nocapture readonly %b, h
; CHECK-NEXT:vmov r2, s0
; CHECK-NEXT:vmov.16 q6[3], r2
; CHECK-NEXT: .LBB2_3: @ %else26
-; CHECK-NEXT:@ in Loop: Header=BB2_4 Depth=1
+; CHECK-NEXT:@ in Loop: Header=BB2_5 Depth=1
; CHECK-NEXT:vmul.f16 q0, q6, q5
; CHECK-NEXT:adds r0, #8
; CHECK-NEXT:vcvtt.f32.f16 s23, s1
@@ -355,9 +355,18 @@ define arm_aapcs_vfpcc float @fast_float_half_mac(half*
nocapture readonly %b, h
; CHECK-NEXT:vcvtb.f32.f16 s20, s0
; CHECK-NEXT:vadd.f32 q5, q3, q5
; CHECK-NEXT:subs.w lr, lr, #1
-; CHECK-NEXT:bne .LBB2_4
-; CHECK-NEXT:b .LBB2_21
-; CHECK-NEXT: .LBB2_4: @ %vector.body
+; CHECK-NEXT:bne .LBB2_5
+; CHECK-NEXT: @ %bb.4: @ %middle.block
+; CHECK-NEXT:vdup.32 q0, r12
+; CHECK-NEXT:vcmp.u32 cs, q0, q4
+; CHECK-NEXT:vpsel q0, q5, q3
+; CHECK-NEXT:vmov.f32 s4, s2
+; CHECK-NEXT:vmov.f32 s5, s3
[llvm-branch-commits] [llvm] c1ab698 - [ARM] Remove LLC tests from transform/hardware loop tests.
Author: David Green
Date: 2021-01-16T18:30:21Z
New Revision: c1ab698dce8dd4e751e63142ebb333d5b90bb8dc
URL:
https://github.com/llvm/llvm-project/commit/c1ab698dce8dd4e751e63142ebb333d5b90bb8dc
DIFF:
https://github.com/llvm/llvm-project/commit/c1ab698dce8dd4e751e63142ebb333d5b90bb8dc.diff
LOG: [ARM] Remove LLC tests from transform/hardware loop tests.
We now have a lot of llc tests for hardware loops in CodeGen, which test
a larger variety of loops and are easier to maintain. This removes the
llc from mixed llc/opt tests.
Added:
Modified:
llvm/test/Transforms/HardwareLoops/ARM/structure.ll
Removed:
diff --git a/llvm/test/Transforms/HardwareLoops/ARM/structure.ll
b/llvm/test/Transforms/HardwareLoops/ARM/structure.ll
index 480823fe7db8..f8ef14e2da4d 100644
--- a/llvm/test/Transforms/HardwareLoops/ARM/structure.ll
+++ b/llvm/test/Transforms/HardwareLoops/ARM/structure.ll
@@ -1,7 +1,5 @@
; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops %s -S -o -
| \
; RUN: FileCheck %s
-; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi %s -o - | \
-; RUN: FileCheck %s --check-prefix=CHECK-LLC
; RUN: opt -mtriple=thumbv8.1m.main -loop-unroll -unroll-remainder=false -S <
%s | \
; RUN: llc -mtriple=thumbv8.1m.main | FileCheck %s
--check-prefix=CHECK-UNROLL
; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops \
@@ -65,15 +63,6 @@ do.end:
; CHECK-NOT: [[LOOP_DEC1:%[^ ]+]] = call i1 @llvm.loop.decrement.i32(i32 1)
; CHECK-NOT: br i1 [[LOOP_DEC1]], label %while.cond1.preheader.us, label
%while.end7
-; CHECK-LLC: nested:
-; CHECK-LLC-NOT:mov lr, r1
-; CHECK-LLC:dls lr, r1
-; CHECK-LLC-NOT:mov lr, r1
-; CHECK-LLC: [[LOOP_HEADER:\.LBB[0-9._]+]]:
-; CHECK-LLC:le lr, [[LOOP_HEADER]]
-; CHECK-LLC-NOT:b [[LOOP_EXIT:\.LBB[0-9._]+]]
-; CHECK-LLC: [[LOOP_EXIT:\.LBB[0-9._]+]]:
-
define void @nested(i32* nocapture %A, i32 %N) {
entry:
%cmp20 = icmp eq i32 %N, 0
@@ -363,12 +352,6 @@ for.body:
; CHECK: call i1 @llvm.test.set.loop.iterations.i32(i32 %N)
; CHECK: call i32 @llvm.loop.decrement.reg.i32(
-; CHECK-LLC-LABEL: unroll_inc_unsigned:
-; CHECK-LLC: wls lr, r3, [[EXIT:.LBB[0-9_]+]]
-; CHECK-LLC: [[HEADER:.LBB[0-9_]+]]:
-; CHECK-LLC: le lr, [[HEADER]]
-; CHECK-LLC-NEXT: [[EXIT]]:
-
; TODO: We should be able to support the unrolled loop body.
; CHECK-UNROLL-LABEL: unroll_inc_unsigned
; CHECK-UNROLL: [[PREHEADER:.LBB[0-9_]+]]: @ %for.body.preheader
@@ -407,14 +390,6 @@ for.body:
; CHECK: call i32 @llvm.start.loop.iterations.i32(i32 %N)
; CHECK: call i32 @llvm.loop.decrement.reg.i32(
-; TODO: An unnecessary register is being held to hold COUNT, lr should just
-; be used instead.
-; CHECK-LLC-LABEL: unroll_dec_int:
-; CHECK-LLC: dls lr, r3
-; CHECK-LLC-NOT: mov lr, r3
-; CHECK-LLC: [[HEADER:.LBB[0-9_]+]]:
-; CHECK-LLC: le lr, [[HEADER]]
-
; CHECK-UNROLL-LABEL: unroll_dec_int:
; CHECK-UNROLL: wls lr, {{.*}}, [[PROLOGUE_EXIT:.LBB[0-9_]+]]
; CHECK-UNROLL-NEXT: [[PROLOGUE:.LBB[0-9_]+]]:
___
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[llvm-branch-commits] [llvm] 416854d - [InstSimplify] Precommit new testcases; NFC
Author: Dávid Bolvanský
Date: 2021-01-16T19:11:58+01:00
New Revision: 416854d0f7cda90def07e9b4aee14505f222b0b3
URL:
https://github.com/llvm/llvm-project/commit/416854d0f7cda90def07e9b4aee14505f222b0b3
DIFF:
https://github.com/llvm/llvm-project/commit/416854d0f7cda90def07e9b4aee14505f222b0b3.diff
LOG: [InstSimplify] Precommit new testcases; NFC
Added:
Modified:
llvm/test/Transforms/InstSimplify/or.ll
Removed:
diff --git a/llvm/test/Transforms/InstSimplify/or.ll
b/llvm/test/Transforms/InstSimplify/or.ll
index 7e7361d12395..68d2af4a4041 100644
--- a/llvm/test/Transforms/InstSimplify/or.ll
+++ b/llvm/test/Transforms/InstSimplify/or.ll
@@ -395,3 +395,71 @@ define i32 @and_or_not_or4_use3(i32 %A, i32 %B) {
%i5 = or i32 %i4, %i2
ret i32 %i5
}
+
+define i32 @and_or_not_or5(i32 %A, i32 %B) {
+; CHECK-LABEL: @and_or_not_or5(
+; CHECK-NEXT:[[I:%.*]] = xor i32 [[A:%.*]], -1
+; CHECK-NEXT:[[I2:%.*]] = and i32 [[B:%.*]], [[I]]
+; CHECK-NEXT:[[I3:%.*]] = or i32 [[B]], [[A]]
+; CHECK-NEXT:[[I4:%.*]] = xor i32 [[I3]], -1
+; CHECK-NEXT:[[I5:%.*]] = or i32 [[I2]], [[I4]]
+; CHECK-NEXT:ret i32 [[I5]]
+;
+ %i = xor i32 %A, -1
+ %i2 = and i32 %B, %i
+ %i3 = or i32 %B, %A
+ %i4 = xor i32 %i3, -1
+ %i5 = or i32 %i2, %i4
+ ret i32 %i5
+}
+
+define i32 @and_or_not_or6(i32 %A, i32 %B) {
+; CHECK-LABEL: @and_or_not_or6(
+; CHECK-NEXT:[[I:%.*]] = xor i32 [[A:%.*]], -1
+; CHECK-NEXT:[[I2:%.*]] = and i32 [[I]], [[B:%.*]]
+; CHECK-NEXT:[[I3:%.*]] = or i32 [[B]], [[A]]
+; CHECK-NEXT:[[I4:%.*]] = xor i32 [[I3]], -1
+; CHECK-NEXT:[[I5:%.*]] = or i32 [[I4]], [[I2]]
+; CHECK-NEXT:ret i32 [[I5]]
+;
+ %i = xor i32 %A, -1
+ %i2 = and i32 %i, %B
+ %i3 = or i32 %B, %A
+ %i4 = xor i32 %i3, -1
+ %i5 = or i32 %i4, %i2
+ ret i32 %i5
+}
+
+define i32 @and_or_not_or7(i32 %A, i32 %B) {
+; CHECK-LABEL: @and_or_not_or7(
+; CHECK-NEXT:[[I:%.*]] = xor i32 [[A:%.*]], -1
+; CHECK-NEXT:[[I2:%.*]] = and i32 [[B:%.*]], [[I]]
+; CHECK-NEXT:[[I3:%.*]] = or i32 [[B]], [[A]]
+; CHECK-NEXT:[[I4:%.*]] = xor i32 [[I3]], -1
+; CHECK-NEXT:[[I5:%.*]] = or i32 [[I4]], [[I2]]
+; CHECK-NEXT:ret i32 [[I5]]
+;
+ %i = xor i32 %A, -1
+ %i2 = and i32 %B, %i
+ %i3 = or i32 %B, %A
+ %i4 = xor i32 %i3, -1
+ %i5 = or i32 %i4, %i2
+ ret i32 %i5
+}
+
+define i32 @and_or_not_or8(i32 %A, i32 %B) {
+; CHECK-LABEL: @and_or_not_or8(
+; CHECK-NEXT:[[I:%.*]] = xor i32 [[B:%.*]], -1
+; CHECK-NEXT:[[I2:%.*]] = and i32 [[A:%.*]], [[I]]
+; CHECK-NEXT:[[I3:%.*]] = or i32 [[B]], [[A]]
+; CHECK-NEXT:[[I4:%.*]] = xor i32 [[I3]], -1
+; CHECK-NEXT:[[I5:%.*]] = or i32 [[I4]], [[I2]]
+; CHECK-NEXT:ret i32 [[I5]]
+;
+ %i = xor i32 %B, -1
+ %i2 = and i32 %A, %i
+ %i3 = or i32 %B, %A
+ %i4 = xor i32 %i3, -1
+ %i5 = or i32 %i4, %i2
+ ret i32 %i5
+}
___
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[llvm-branch-commits] [llvm] 2082b10 - [llvm] Use *::empty (NFC)
Author: Kazu Hirata
Date: 2021-01-16T09:40:55-08:00
New Revision: 2082b10d100e8dbaffc2ba8f497db5d2ab61beb2
URL:
https://github.com/llvm/llvm-project/commit/2082b10d100e8dbaffc2ba8f497db5d2ab61beb2
DIFF:
https://github.com/llvm/llvm-project/commit/2082b10d100e8dbaffc2ba8f497db5d2ab61beb2.diff
LOG: [llvm] Use *::empty (NFC)
Added:
Modified:
llvm/lib/Analysis/CGSCCPassManager.cpp
llvm/lib/CodeGen/BranchFolding.cpp
llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
llvm/lib/CodeGen/PHIElimination.cpp
llvm/lib/CodeGen/RegisterScavenging.cpp
llvm/lib/Object/SymbolSize.cpp
llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
llvm/lib/Target/X86/X86CmovConversion.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Transforms/Scalar/SROA.cpp
llvm/tools/llvm-exegesis/lib/Target.cpp
llvm/tools/llvm-readobj/ELFDumper.cpp
Removed:
diff --git a/llvm/lib/Analysis/CGSCCPassManager.cpp
b/llvm/lib/Analysis/CGSCCPassManager.cpp
index 4aa7a4b2a61e..3230e9036b8e 100644
--- a/llvm/lib/Analysis/CGSCCPassManager.cpp
+++ b/llvm/lib/Analysis/CGSCCPassManager.cpp
@@ -833,7 +833,7 @@ incorporateNewSCCRange(const SCCRangeT ,
LazyCallGraph ,
CGSCCAnalysisManager , CGSCCUpdateResult ) {
using SCC = LazyCallGraph::SCC;
- if (NewSCCRange.begin() == NewSCCRange.end())
+ if (NewSCCRange.empty())
return C;
// Add the current SCC to the worklist as its shape has changed.
diff --git a/llvm/lib/CodeGen/BranchFolding.cpp
b/llvm/lib/CodeGen/BranchFolding.cpp
index fd0936ae05e8..fd3f465fb390 100644
--- a/llvm/lib/CodeGen/BranchFolding.cpp
+++ b/llvm/lib/CodeGen/BranchFolding.cpp
@@ -1403,7 +1403,7 @@ bool BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
LLVM_DEBUG(dbgs() << "\nMerging into block: " << PrevBB
<< "From MBB: " << *MBB);
// Remove redundant DBG_VALUEs first.
- if (PrevBB.begin() != PrevBB.end()) {
+ if (!PrevBB.empty()) {
MachineBasicBlock::iterator PrevBBIter = PrevBB.end();
--PrevBBIter;
MachineBasicBlock::iterator MBBIter = MBB->begin();
diff --git a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
index 1171e4b9519d..662bd1a3646f 100644
--- a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
+++ b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
@@ -434,7 +434,7 @@ class StatepointState {
// To insert reload at the end of MBB, insert it before last instruction
// and then swap them.
-assert(MBB->begin() != MBB->end() && "Empty block");
+assert(!MBB->empty() && "Empty block");
--It;
TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, );
MachineInstr *Reload = It->getPrevNode();
diff --git a/llvm/lib/CodeGen/PHIElimination.cpp
b/llvm/lib/CodeGen/PHIElimination.cpp
index c486319f142f..8148b64d8443 100644
--- a/llvm/lib/CodeGen/PHIElimination.cpp
+++ b/llvm/lib/CodeGen/PHIElimination.cpp
@@ -394,8 +394,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock ,
}
LiveInterval = LIS->getInterval(DestReg);
-assert(DestLI.begin() != DestLI.end() &&
- "PHIs should have nonempty LiveIntervals.");
+assert(!DestLI.empty() && "PHIs should have nonempty LiveIntervals.");
if (DestLI.endIndex().isDead()) {
// A dead PHI's live range begins and ends at the start of the MBB, but
// the lowered copy, which will still be dead, needs to begin and end at
diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp
b/llvm/lib/CodeGen/RegisterScavenging.cpp
index 93e8e27d12aa..a833895c115d 100644
--- a/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -91,7 +91,7 @@ void RegScavenger::enterBasicBlockEnd(MachineBasicBlock )
{
LiveUnits.addLiveOuts(MBB);
// Move internal iterator at the last instruction of the block.
- if (MBB.begin() != MBB.end()) {
+ if (!MBB.empty()) {
MBBI = std::prev(MBB.end());
Tracking = true;
}
diff --git a/llvm/lib/Object/SymbolSize.cpp b/llvm/lib/Object/SymbolSize.cpp
index 84eed4d169d3..97baabec084b 100644
--- a/llvm/lib/Object/SymbolSize.cpp
+++ b/llvm/lib/Object/SymbolSize.cpp
@@ -48,7 +48,7 @@ llvm::object::computeSymbolSizes(const ObjectFile ) {
if (const auto *E = dyn_cast()) {
auto Syms = E->symbols();
-if (Syms.begin() == Syms.end())
+if (Syms.empty())
Syms = E->getDynamicSymbolIterators();
for (ELFSymbolRef Sym : Syms)
Ret.push_back({Sym, Sym.getSize()});
diff --git a/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
b/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
index 3f76bdd0d680..3530c2b7b717 100644
--- a/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
+++
[llvm-branch-commits] [llvm] 19aacdb - [llvm] Construct SmallVector with iterator ranges (NFC)
Author: Kazu Hirata
Date: 2021-01-16T09:40:53-08:00
New Revision: 19aacdb715aea1de56a47b807a555335610a11c2
URL:
https://github.com/llvm/llvm-project/commit/19aacdb715aea1de56a47b807a555335610a11c2
DIFF:
https://github.com/llvm/llvm-project/commit/19aacdb715aea1de56a47b807a555335610a11c2.diff
LOG: [llvm] Construct SmallVector with iterator ranges (NFC)
Added:
Modified:
llvm/include/llvm/Support/GenericDomTree.h
llvm/lib/Analysis/ScalarEvolution.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/lib/IR/LLVMContextImpl.cpp
llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
llvm/lib/Transforms/Utils/Debugify.cpp
llvm/lib/Transforms/Utils/LCSSA.cpp
llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
llvm/lib/Transforms/Vectorize/VPlan.cpp
Removed:
diff --git a/llvm/include/llvm/Support/GenericDomTree.h
b/llvm/include/llvm/Support/GenericDomTree.h
index 28b2537bc481..18e08dbcd175 100644
--- a/llvm/include/llvm/Support/GenericDomTree.h
+++ b/llvm/include/llvm/Support/GenericDomTree.h
@@ -839,9 +839,7 @@ class DominatorTreeBase {
"NewBB should have a single successor!");
NodeRef NewBBSucc = *GraphT::child_begin(NewBB);
-SmallVector PredBlocks;
-for (auto Pred : children>(NewBB))
- PredBlocks.push_back(Pred);
+SmallVector PredBlocks(children>(NewBB));
assert(!PredBlocks.empty() && "No predblocks?");
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp
b/llvm/lib/Analysis/ScalarEvolution.cpp
index 8ec23559cc59..2f5c91aafd39 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -3274,8 +3274,7 @@ const SCEV *ScalarEvolution::getUDivExactExpr(const SCEV
*LHS,
// first element of the mulexpr.
if (const auto *LHSCst = dyn_cast(Mul->getOperand(0))) {
if (LHSCst == RHSCst) {
-SmallVector Operands;
-Operands.append(Mul->op_begin() + 1, Mul->op_end());
+SmallVector Operands(drop_begin(Mul->operands(), 1));
return getMulExpr(Operands);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 2ef3d9947169..ee781d4aa1dd 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2194,7 +2194,7 @@ void SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
if (Node->isStrictFPOpcode()) {
EVT RetVT = Node->getValueType(0);
-SmallVector Ops(Node->op_begin() + 1, Node->op_end());
+SmallVector Ops(drop_begin(Node->ops(), 1));
TargetLowering::MakeLibCallOptions CallOptions;
// FIXME: This doesn't support tail calls.
std::pair Tmp = TLI.makeLibCall(DAG, LC, RetVT,
diff --git a/llvm/lib/IR/LLVMContextImpl.cpp b/llvm/lib/IR/LLVMContextImpl.cpp
index d96376356fcf..e998138ec3cb 100644
--- a/llvm/lib/IR/LLVMContextImpl.cpp
+++ b/llvm/lib/IR/LLVMContextImpl.cpp
@@ -176,7 +176,7 @@ unsigned MDNodeOpsKey::calculateHash(MDNode *N, unsigned
Offset) {
unsigned Hash = hash_combine_range(N->op_begin() + Offset, N->op_end());
#ifndef NDEBUG
{
-SmallVector MDs(N->op_begin() + Offset, N->op_end());
+SmallVector MDs(drop_begin(N->operands(), Offset));
unsigned RawHash = calculateHash(MDs);
assert(Hash == RawHash &&
"Expected hash of MDOperand to equal hash of Metadata*");
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
index 3fc57d69b8e8..4fca8bec7423 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
@@ -54,13 +54,10 @@ char AMDGPUAlwaysInline::ID = 0;
static void
recursivelyVisitUsers(GlobalValue ,
SmallPtrSetImpl ) {
- SmallVector Stack;
+ SmallVector Stack(GV.users());
SmallPtrSet Visited;
- for (User *U : GV.users())
-Stack.push_back(U);
-
while (!Stack.empty()) {
User *U = Stack.pop_back_val();
if (!Visited.insert(U).second)
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index 2b2142cc6c21..e1ab64c8c37b 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -2854,7 +2854,7 @@ bool NVPTXDAGToDAGISel::tryTextureIntrinsic(SDNode *N) {
}
// Copy over operands
- SmallVector Ops(N->op_begin() + 1, N->op_end());
+ SmallVector Ops(drop_begin(N->ops(), 1));
Ops.push_back(N->getOperand(0)); // Move chain to the back.
ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops));
@@ -3363,7 +3363,7 @@ bool NVPTXDAGToDAGISel::trySurfaceIntrinsic(SDNode
[llvm-branch-commits] [llvm] ba0fc7e - [StringExtras] Fix comment typos (NFC)
Author: Kazu Hirata
Date: 2021-01-16T09:40:51-08:00
New Revision: ba0fc7e1f8d57a7a7dce1a2d604b12e5210dc10f
URL:
https://github.com/llvm/llvm-project/commit/ba0fc7e1f8d57a7a7dce1a2d604b12e5210dc10f
DIFF:
https://github.com/llvm/llvm-project/commit/ba0fc7e1f8d57a7a7dce1a2d604b12e5210dc10f.diff
LOG: [StringExtras] Fix comment typos (NFC)
Added:
Modified:
llvm/include/llvm/ADT/StringExtras.h
Removed:
diff --git a/llvm/include/llvm/ADT/StringExtras.h
b/llvm/include/llvm/ADT/StringExtras.h
index 10596cf82398..68e89508cba9 100644
--- a/llvm/include/llvm/ADT/StringExtras.h
+++ b/llvm/include/llvm/ADT/StringExtras.h
@@ -470,9 +470,9 @@ inline std::string join_items(Sep Separator, Args &&...
Items) {
/// list from a loop like so:
///
/// \code
-/// ListSeparator SD;
+/// ListSeparator LS;
/// for (auto : C)
-/// OS << SD << I.getName();
+/// OS << LS << I.getName();
/// \end
class ListSeparator {
bool First = true;
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[llvm-branch-commits] [llvm] bca16e2 - [LTO] Remove options to disable inlining, vectorization & GVNLoadPRE.
Author: Florian Hahn
Date: 2021-01-16T16:29:15Z
New Revision: bca16e2fbb451f125c13f811f9f5a37bb38e54e2
URL:
https://github.com/llvm/llvm-project/commit/bca16e2fbb451f125c13f811f9f5a37bb38e54e2
DIFF:
https://github.com/llvm/llvm-project/commit/bca16e2fbb451f125c13f811f9f5a37bb38e54e2.diff
LOG: [LTO] Remove options to disable inlining, vectorization & GVNLoadPRE.
This patch removes some ancient options as a clean-up before moving
code-gen to use LTOBackend in D94487.
I think it would preferable to remove those ancient options, because
1. There are no corresponding options in LTOBackend based tools,
2. There are no unit tests for them,
3. They are not passed through by Clang,
4. At least for GNVLoadPRE, users could just use GVN's `enable-load-pre`.
Alternatively we could add support for those options to lto::Config &
co, but I think it would be better to remove them, unless they are
actually used in practice.
Reviewed By: steven_wu, tejohnson
Differential Revision: https://reviews.llvm.org/D94783
Added:
Modified:
llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h
llvm/lib/LTO/LTOCodeGenerator.cpp
llvm/tools/llvm-lto/llvm-lto.cpp
llvm/tools/lto/lto.cpp
Removed:
diff --git a/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h
b/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h
index d7ccc0d5a6c5..a817969abc58 100644
--- a/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h
+++ b/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h
@@ -145,9 +145,7 @@ struct LTOCodeGenerator {
/// \note It is up to the linker to remove the intermediate output file. Do
/// not try to remove the object file in LTOCodeGenerator's destructor as we
/// don't who (LTOCodeGenerator or the output file) will last longer.
- bool compile_to_file(const char **Name, bool DisableVerify,
- bool DisableInline, bool DisableGVNLoadPRE,
- bool DisableVectorization);
+ bool compile_to_file(const char **Name, bool DisableVerify);
/// As with compile_to_file(), this function compiles the merged module into
/// single output file. Instead of returning the output file path to the
@@ -155,15 +153,12 @@ struct LTOCodeGenerator {
/// to the caller. This function should delete the intermediate file once
/// its content is brought to memory. Return NULL if the compilation was not
/// successful.
- std::unique_ptr compile(bool DisableVerify, bool DisableInline,
-bool DisableGVNLoadPRE,
-bool DisableVectorization);
+ std::unique_ptr compile(bool DisableVerify);
/// Optimizes the merged module. Returns true on success.
///
/// Calls \a verifyMergedModuleOnce().
- bool optimize(bool DisableVerify, bool DisableInline, bool DisableGVNLoadPRE,
-bool DisableVectorization);
+ bool optimize(bool DisableVerify);
/// Compiles the merged optimized module into a single output file. It brings
/// the output to a buffer, and returns the buffer to the caller. Return NULL
diff --git a/llvm/lib/LTO/LTOCodeGenerator.cpp
b/llvm/lib/LTO/LTOCodeGenerator.cpp
index 890e9adf17e5..cb30db193259 100644
--- a/llvm/lib/LTO/LTOCodeGenerator.cpp
+++ b/llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -326,22 +326,15 @@ LTOCodeGenerator::compileOptimized() {
return std::move(*BufferOrErr);
}
-bool LTOCodeGenerator::compile_to_file(const char **Name, bool DisableVerify,
- bool DisableInline,
- bool DisableGVNLoadPRE,
- bool DisableVectorization) {
- if (!optimize(DisableVerify, DisableInline, DisableGVNLoadPRE,
-DisableVectorization))
+bool LTOCodeGenerator::compile_to_file(const char **Name, bool DisableVerify) {
+ if (!optimize(DisableVerify))
return false;
return compileOptimizedToFile(Name);
}
-std::unique_ptr
-LTOCodeGenerator::compile(bool DisableVerify, bool DisableInline,
- bool DisableGVNLoadPRE, bool DisableVectorization) {
- if (!optimize(DisableVerify, DisableInline, DisableGVNLoadPRE,
-DisableVectorization))
+std::unique_ptr LTOCodeGenerator::compile(bool DisableVerify) {
+ if (!optimize(DisableVerify))
return nullptr;
return compileOptimized();
@@ -534,9 +527,7 @@ void LTOCodeGenerator::finishOptimizationRemarks() {
}
/// Optimize merged modules using various IPO passes
-bool LTOCodeGenerator::optimize(bool DisableVerify, bool DisableInline,
-bool DisableGVNLoadPRE,
-bool DisableVectorization) {
+bool LTOCodeGenerator::optimize(bool DisableVerify) {
if (!this->determineTarget())
return false;
@@ -585,11 +576,9 @@ bool LTOCodeGenerator::optimize(bool DisableVerify, bool
DisableInline,
Triple
[llvm-branch-commits] [llvm] bdd4dda - [InstSimplify] Update comments, remove redundant tests
Author: Dávid Bolvanský
Date: 2021-01-16T16:31:23+01:00
New Revision: bdd4dda58b0de08bd3474fb8d4589a9ba9349e88
URL:
https://github.com/llvm/llvm-project/commit/bdd4dda58b0de08bd3474fb8d4589a9ba9349e88
DIFF:
https://github.com/llvm/llvm-project/commit/bdd4dda58b0de08bd3474fb8d4589a9ba9349e88.diff
LOG: [InstSimplify] Update comments, remove redundant tests
Added:
Modified:
llvm/lib/Analysis/InstructionSimplify.cpp
llvm/test/Transforms/InstCombine/or.ll
Removed:
diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp
b/llvm/lib/Analysis/InstructionSimplify.cpp
index 6266e922f8c9..73f046dcb8de 100644
--- a/llvm/lib/Analysis/InstructionSimplify.cpp
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp
@@ -2264,6 +2264,8 @@ static Value *SimplifyOrInst(Value *Op0, Value *Op1,
const SimplifyQuery ,
// (~A & B) | ~(A | B) --> ~A
// (~A & B) | ~(B | A) --> ~A
+ // (B & ~A) | ~(A | B) --> ~A
+ // (B & ~A) | ~(B | A) --> ~A
if (match(Op0, m_And(m_Not(m_Value(A)), m_Value(B))) &&
match(Op1, m_Not(m_c_Or(m_Specific(A), m_Specific(B)
return cast(Op0)->getOperand(0);
diff --git a/llvm/test/Transforms/InstCombine/or.ll
b/llvm/test/Transforms/InstCombine/or.ll
index 0fc75fe082f8..22ba395ebe9f 100644
--- a/llvm/test/Transforms/InstCombine/or.ll
+++ b/llvm/test/Transforms/InstCombine/or.ll
@@ -1369,113 +1369,3 @@ define i32 @test5_use3(i32 %x, i32 %y) {
%or1 = or i32 %xor, %neg
ret i32 %or1
}
-
-define i32 @test6(i32 %A, i32 %B) {
-; CHECK-LABEL: @test6(
-; CHECK-NEXT:[[I:%.*]] = xor i32 [[B:%.*]], -1
-; CHECK-NEXT:[[I2:%.*]] = and i32 [[I]], [[A:%.*]]
-; CHECK-NEXT:[[I3:%.*]] = or i32 [[B]], [[A]]
-; CHECK-NEXT:[[I4:%.*]] = xor i32 [[I3]], -1
-; CHECK-NEXT:[[I5:%.*]] = or i32 [[I2]], [[I4]]
-; CHECK-NEXT:ret i32 [[I5]]
-;
- %i = xor i32 %B, -1
- %i2 = and i32 %i, %A
- %i3 = or i32 %B, %A
- %i4 = xor i32 %i3, -1
- %i5 = or i32 %i2, %i4
- ret i32 %i5
-}
-
-define i32 @test7(i32 %A, i32 %B) {
-; CHECK-LABEL: @test7(
-; CHECK-NEXT:[[I:%.*]] = xor i32 [[A:%.*]], -1
-; CHECK-NEXT:[[I2:%.*]] = and i32 [[I]], [[B:%.*]]
-; CHECK-NEXT:[[I3:%.*]] = or i32 [[B]], [[A]]
-; CHECK-NEXT:[[I4:%.*]] = xor i32 [[I3]], -1
-; CHECK-NEXT:[[I5:%.*]] = or i32 [[I2]], [[I4]]
-; CHECK-NEXT:ret i32 [[I5]]
-;
- %i = xor i32 %A, -1
- %i2 = and i32 %i, %B
- %i3 = or i32 %B, %A
- %i4 = xor i32 %i3, -1
- %i5 = or i32 %i2, %i4
- ret i32 %i5
-}
-
-define <4 x i32> @test8_vec(<4 x i32> %A, <4 x i32> %B) {
-; CHECK-LABEL: @test8_vec(
-; CHECK-NEXT:[[I:%.*]] = xor <4 x i32> [[A:%.*]],
-; CHECK-NEXT:[[I2:%.*]] = and <4 x i32> [[I]], [[B:%.*]]
-; CHECK-NEXT:[[I3:%.*]] = or <4 x i32> [[B]], [[A]]
-; CHECK-NEXT:[[I4:%.*]] = xor <4 x i32> [[I3]],
-; CHECK-NEXT:[[I5:%.*]] = or <4 x i32> [[I2]], [[I4]]
-; CHECK-NEXT:ret <4 x i32> [[I5]]
-;
- %i = xor <4 x i32> %A,
- %i2 = and <4 x i32> %i, %B
- %i3 = or <4 x i32> %B, %A
- %i4 = xor <4 x i32> %i3,
- %i5 = or <4 x i32> %i2, %i4
- ret <4 x i32> %i5
-}
-
-define i32 @test9_use(i32 %A, i32 %B) {
-; CHECK-LABEL: @test9_use(
-; CHECK-NEXT:[[I:%.*]] = xor i32 [[A:%.*]], -1
-; CHECK-NEXT:[[I2:%.*]] = and i32 [[I]], [[B:%.*]]
-; CHECK-NEXT:tail call void @use(i32 [[I2]])
-; CHECK-NEXT:[[I3:%.*]] = or i32 [[B]], [[A]]
-; CHECK-NEXT:[[I4:%.*]] = xor i32 [[I3]], -1
-; CHECK-NEXT:[[I5:%.*]] = or i32 [[I2]], [[I4]]
-; CHECK-NEXT:ret i32 [[I5]]
-;
- %i = xor i32 %A, -1
- %i2 = and i32 %i, %B
- tail call void @use(i32 %i2)
- %i3 = or i32 %B, %A
- %i4 = xor i32 %i3, -1
- %i5 = or i32 %i2, %i4
- ret i32 %i5
-}
-
-define i32 @test9_use2(i32 %A, i32 %B) {
-; CHECK-LABEL: @test9_use2(
-; CHECK-NEXT:[[I:%.*]] = or i32 [[B:%.*]], [[A:%.*]]
-; CHECK-NEXT:[[I2:%.*]] = xor i32 [[I]], -1
-; CHECK-NEXT:tail call void @use(i32 [[I2]])
-; CHECK-NEXT:[[I3:%.*]] = xor i32 [[A]], -1
-; CHECK-NEXT:[[I4:%.*]] = and i32 [[I3]], [[B]]
-; CHECK-NEXT:[[I5:%.*]] = or i32 [[I4]], [[I2]]
-; CHECK-NEXT:ret i32 [[I5]]
-;
- %i = or i32 %B, %A
- %i2 = xor i32 %i, -1
- tail call void @use(i32 %i2)
- %i3 = xor i32 %A, -1
- %i4 = and i32 %i3, %B
- %i5 = or i32 %i4, %i2
- ret i32 %i5
-}
-
-define i32 @test9_use3(i32 %A, i32 %B) {
-; CHECK-LABEL: @test9_use3(
-; CHECK-NEXT:[[I:%.*]] = or i32 [[B:%.*]], [[A:%.*]]
-; CHECK-NEXT:[[I2:%.*]] = xor i32 [[I]], -1
-; CHECK-NEXT:tail call void @use(i32 [[I2]])
-; CHECK-NEXT:[[I3:%.*]] = xor i32 [[A]], -1
-; CHECK-NEXT:[[I4:%.*]] = and i32 [[I3]], [[B]]
-; CHECK-NEXT:tail call void @use(i32 [[I4]])
-; CHECK-NEXT:[[I5:%.*]] = or i32 [[I4]], [[I2]]
-; CHECK-NEXT:ret i32 [[I5]]
-;
- %i = or i32 %B, %A
- %i2 = xor i32 %i, -1
- tail call void @use(i32 %i2)
- %i3 = xor i32 %A, -1
- %i4 = and i32 %i3, %B
- tail call void @use(i32 %i4)
- %i5 = or i32 %i4, %i2
- ret i32 %i5
-}
[llvm-branch-commits] [llvm] 098dbf1 - [RISCV] Correct alignment settings for vector registers.
Author: Hsiangkai Wang
Date: 2021-01-16T23:21:29+08:00
New Revision: 098dbf190a5586d02f48b84eb41b93b701cdeb97
URL:
https://github.com/llvm/llvm-project/commit/098dbf190a5586d02f48b84eb41b93b701cdeb97
DIFF:
https://github.com/llvm/llvm-project/commit/098dbf190a5586d02f48b84eb41b93b701cdeb97.diff
LOG: [RISCV] Correct alignment settings for vector registers.
According to "9. Vector Memory Alignment Constraints" in V
specification, the alignment of vector memory access is aligned to the
size of the element. In our current implementation, we support ELEN up
to 64. We could assume the alignment of vector registers is 64 under the
assumption.
Differential Revision: https://reviews.llvm.org/D94751
Added:
Modified:
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 99f74bfc2a09..75615fd334b7 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -386,11 +386,10 @@ let RegAltNameIndices = [ABIRegAltName] in {
class VReg regTypes, dag regList, int Vlmul>
: RegisterClass<"RISCV",
regTypes,
- // FIXME: Spill alignment set to 16 bytes.
- 128,
+ 64, // The maximum supported ELEN is 64.
regList> {
int VLMul = Vlmul;
- int Size = !mul(Vlmul, 64); // FIXME: assuming ELEN=64
+ int Size = !mul(Vlmul, 64);
}
def VR : VReg<[vint8mf2_t, vint8mf4_t, vint8mf8_t,
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[llvm-branch-commits] [llvm] a4e2a51 - [InstSimplify] Add (~A & B) | ~(A | B) --> ~A
Author: Dávid Bolvanský
Date: 2021-01-16T15:43:34+01:00
New Revision: a4e2a5145a29af678139f33e94ab3df0fc973e59
URL:
https://github.com/llvm/llvm-project/commit/a4e2a5145a29af678139f33e94ab3df0fc973e59
DIFF:
https://github.com/llvm/llvm-project/commit/a4e2a5145a29af678139f33e94ab3df0fc973e59.diff
LOG: [InstSimplify] Add (~A & B) | ~(A | B) --> ~A
Added:
Modified:
llvm/lib/Analysis/InstructionSimplify.cpp
llvm/test/Transforms/InstSimplify/or.ll
Removed:
diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp
b/llvm/lib/Analysis/InstructionSimplify.cpp
index 2ae4228495e3..6266e922f8c9 100644
--- a/llvm/lib/Analysis/InstructionSimplify.cpp
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp
@@ -2262,6 +2262,12 @@ static Value *SimplifyOrInst(Value *Op0, Value *Op1,
const SimplifyQuery ,
match(Op0, m_c_Xor(m_Not(m_Specific(A)), m_Specific(B)
return Op0;
+ // (~A & B) | ~(A | B) --> ~A
+ // (~A & B) | ~(B | A) --> ~A
+ if (match(Op0, m_And(m_Not(m_Value(A)), m_Value(B))) &&
+ match(Op1, m_Not(m_c_Or(m_Specific(A), m_Specific(B)
+return cast(Op0)->getOperand(0);
+
if (Value *V = simplifyAndOrOfCmps(Q, Op0, Op1, false))
return V;
diff --git a/llvm/test/Transforms/InstSimplify/or.ll
b/llvm/test/Transforms/InstSimplify/or.ll
index e8284264c612..7e7361d12395 100644
--- a/llvm/test/Transforms/InstSimplify/or.ll
+++ b/llvm/test/Transforms/InstSimplify/or.ll
@@ -301,3 +301,97 @@ define i32 @poison(i32 %x) {
%v = or i32 %x, poison
ret i32 %v
}
+
+declare void @use(i32)
+
+define i32 @and_or_not_or(i32 %A, i32 %B) {
+; CHECK-LABEL: @and_or_not_or(
+; CHECK-NEXT:[[I:%.*]] = xor i32 [[B:%.*]], -1
+; CHECK-NEXT:ret i32 [[I]]
+;
+ %i = xor i32 %B, -1
+ %i2 = and i32 %i, %A
+ %i3 = or i32 %B, %A
+ %i4 = xor i32 %i3, -1
+ %i5 = or i32 %i2, %i4
+ ret i32 %i5
+}
+
+define i32 @and_or_not_or2(i32 %A, i32 %B) {
+; CHECK-LABEL: @and_or_not_or2(
+; CHECK-NEXT:[[I:%.*]] = xor i32 [[A:%.*]], -1
+; CHECK-NEXT:ret i32 [[I]]
+;
+ %i = xor i32 %A, -1
+ %i2 = and i32 %i, %B
+ %i3 = or i32 %B, %A
+ %i4 = xor i32 %i3, -1
+ %i5 = or i32 %i2, %i4
+ ret i32 %i5
+}
+
+define <4 x i32> @and_or_not_or3_vec(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: @and_or_not_or3_vec(
+; CHECK-NEXT:[[I:%.*]] = xor <4 x i32> [[A:%.*]],
+; CHECK-NEXT:ret <4 x i32> [[I]]
+;
+ %i = xor <4 x i32> %A,
+ %i2 = and <4 x i32> %i, %B
+ %i3 = or <4 x i32> %B, %A
+ %i4 = xor <4 x i32> %i3,
+ %i5 = or <4 x i32> %i2, %i4
+ ret <4 x i32> %i5
+}
+
+define i32 @and_or_not_or4_use(i32 %A, i32 %B) {
+; CHECK-LABEL: @and_or_not_or4_use(
+; CHECK-NEXT:[[I:%.*]] = xor i32 [[A:%.*]], -1
+; CHECK-NEXT:[[I2:%.*]] = and i32 [[I]], [[B:%.*]]
+; CHECK-NEXT:tail call void @use(i32 [[I2]])
+; CHECK-NEXT:ret i32 [[I]]
+;
+ %i = xor i32 %A, -1
+ %i2 = and i32 %i, %B
+ tail call void @use(i32 %i2)
+ %i3 = or i32 %B, %A
+ %i4 = xor i32 %i3, -1
+ %i5 = or i32 %i2, %i4
+ ret i32 %i5
+}
+
+define i32 @and_or_not_or4_use2(i32 %A, i32 %B) {
+; CHECK-LABEL: @and_or_not_or4_use2(
+; CHECK-NEXT:[[I:%.*]] = or i32 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT:[[I2:%.*]] = xor i32 [[I]], -1
+; CHECK-NEXT:tail call void @use(i32 [[I2]])
+; CHECK-NEXT:[[I3:%.*]] = xor i32 [[A]], -1
+; CHECK-NEXT:ret i32 [[I3]]
+;
+ %i = or i32 %B, %A
+ %i2 = xor i32 %i, -1
+ tail call void @use(i32 %i2)
+ %i3 = xor i32 %A, -1
+ %i4 = and i32 %i3, %B
+ %i5 = or i32 %i4, %i2
+ ret i32 %i5
+}
+
+define i32 @and_or_not_or4_use3(i32 %A, i32 %B) {
+; CHECK-LABEL: @and_or_not_or4_use3(
+; CHECK-NEXT:[[I:%.*]] = or i32 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT:[[I2:%.*]] = xor i32 [[I]], -1
+; CHECK-NEXT:tail call void @use(i32 [[I2]])
+; CHECK-NEXT:[[I3:%.*]] = xor i32 [[A]], -1
+; CHECK-NEXT:[[I4:%.*]] = and i32 [[I3]], [[B]]
+; CHECK-NEXT:tail call void @use(i32 [[I4]])
+; CHECK-NEXT:ret i32 [[I3]]
+;
+ %i = or i32 %B, %A
+ %i2 = xor i32 %i, -1
+ tail call void @use(i32 %i2)
+ %i3 = xor i32 %A, -1
+ %i4 = and i32 %i3, %B
+ tail call void @use(i32 %i4)
+ %i5 = or i32 %i4, %i2
+ ret i32 %i5
+}
___
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[llvm-branch-commits] [llvm] 9fc814e - [Tests] Added tests for new instcombine or simplification; NFC
Author: Dávid Bolvanský
Date: 2021-01-16T15:43:33+01:00
New Revision: 9fc814ed59669d8f1d06cde5714c17fac652f2a1
URL:
https://github.com/llvm/llvm-project/commit/9fc814ed59669d8f1d06cde5714c17fac652f2a1
DIFF:
https://github.com/llvm/llvm-project/commit/9fc814ed59669d8f1d06cde5714c17fac652f2a1.diff
LOG: [Tests] Added tests for new instcombine or simplification; NFC
Added:
Modified:
llvm/test/Transforms/InstCombine/or.ll
Removed:
diff --git a/llvm/test/Transforms/InstCombine/or.ll
b/llvm/test/Transforms/InstCombine/or.ll
index ff6244526563..0fc75fe082f8 100644
--- a/llvm/test/Transforms/InstCombine/or.ll
+++ b/llvm/test/Transforms/InstCombine/or.ll
@@ -1370,3 +1370,112 @@ define i32 @test5_use3(i32 %x, i32 %y) {
ret i32 %or1
}
+define i32 @test6(i32 %A, i32 %B) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT:[[I:%.*]] = xor i32 [[B:%.*]], -1
+; CHECK-NEXT:[[I2:%.*]] = and i32 [[I]], [[A:%.*]]
+; CHECK-NEXT:[[I3:%.*]] = or i32 [[B]], [[A]]
+; CHECK-NEXT:[[I4:%.*]] = xor i32 [[I3]], -1
+; CHECK-NEXT:[[I5:%.*]] = or i32 [[I2]], [[I4]]
+; CHECK-NEXT:ret i32 [[I5]]
+;
+ %i = xor i32 %B, -1
+ %i2 = and i32 %i, %A
+ %i3 = or i32 %B, %A
+ %i4 = xor i32 %i3, -1
+ %i5 = or i32 %i2, %i4
+ ret i32 %i5
+}
+
+define i32 @test7(i32 %A, i32 %B) {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT:[[I:%.*]] = xor i32 [[A:%.*]], -1
+; CHECK-NEXT:[[I2:%.*]] = and i32 [[I]], [[B:%.*]]
+; CHECK-NEXT:[[I3:%.*]] = or i32 [[B]], [[A]]
+; CHECK-NEXT:[[I4:%.*]] = xor i32 [[I3]], -1
+; CHECK-NEXT:[[I5:%.*]] = or i32 [[I2]], [[I4]]
+; CHECK-NEXT:ret i32 [[I5]]
+;
+ %i = xor i32 %A, -1
+ %i2 = and i32 %i, %B
+ %i3 = or i32 %B, %A
+ %i4 = xor i32 %i3, -1
+ %i5 = or i32 %i2, %i4
+ ret i32 %i5
+}
+
+define <4 x i32> @test8_vec(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: @test8_vec(
+; CHECK-NEXT:[[I:%.*]] = xor <4 x i32> [[A:%.*]],
+; CHECK-NEXT:[[I2:%.*]] = and <4 x i32> [[I]], [[B:%.*]]
+; CHECK-NEXT:[[I3:%.*]] = or <4 x i32> [[B]], [[A]]
+; CHECK-NEXT:[[I4:%.*]] = xor <4 x i32> [[I3]],
+; CHECK-NEXT:[[I5:%.*]] = or <4 x i32> [[I2]], [[I4]]
+; CHECK-NEXT:ret <4 x i32> [[I5]]
+;
+ %i = xor <4 x i32> %A,
+ %i2 = and <4 x i32> %i, %B
+ %i3 = or <4 x i32> %B, %A
+ %i4 = xor <4 x i32> %i3,
+ %i5 = or <4 x i32> %i2, %i4
+ ret <4 x i32> %i5
+}
+
+define i32 @test9_use(i32 %A, i32 %B) {
+; CHECK-LABEL: @test9_use(
+; CHECK-NEXT:[[I:%.*]] = xor i32 [[A:%.*]], -1
+; CHECK-NEXT:[[I2:%.*]] = and i32 [[I]], [[B:%.*]]
+; CHECK-NEXT:tail call void @use(i32 [[I2]])
+; CHECK-NEXT:[[I3:%.*]] = or i32 [[B]], [[A]]
+; CHECK-NEXT:[[I4:%.*]] = xor i32 [[I3]], -1
+; CHECK-NEXT:[[I5:%.*]] = or i32 [[I2]], [[I4]]
+; CHECK-NEXT:ret i32 [[I5]]
+;
+ %i = xor i32 %A, -1
+ %i2 = and i32 %i, %B
+ tail call void @use(i32 %i2)
+ %i3 = or i32 %B, %A
+ %i4 = xor i32 %i3, -1
+ %i5 = or i32 %i2, %i4
+ ret i32 %i5
+}
+
+define i32 @test9_use2(i32 %A, i32 %B) {
+; CHECK-LABEL: @test9_use2(
+; CHECK-NEXT:[[I:%.*]] = or i32 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT:[[I2:%.*]] = xor i32 [[I]], -1
+; CHECK-NEXT:tail call void @use(i32 [[I2]])
+; CHECK-NEXT:[[I3:%.*]] = xor i32 [[A]], -1
+; CHECK-NEXT:[[I4:%.*]] = and i32 [[I3]], [[B]]
+; CHECK-NEXT:[[I5:%.*]] = or i32 [[I4]], [[I2]]
+; CHECK-NEXT:ret i32 [[I5]]
+;
+ %i = or i32 %B, %A
+ %i2 = xor i32 %i, -1
+ tail call void @use(i32 %i2)
+ %i3 = xor i32 %A, -1
+ %i4 = and i32 %i3, %B
+ %i5 = or i32 %i4, %i2
+ ret i32 %i5
+}
+
+define i32 @test9_use3(i32 %A, i32 %B) {
+; CHECK-LABEL: @test9_use3(
+; CHECK-NEXT:[[I:%.*]] = or i32 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT:[[I2:%.*]] = xor i32 [[I]], -1
+; CHECK-NEXT:tail call void @use(i32 [[I2]])
+; CHECK-NEXT:[[I3:%.*]] = xor i32 [[A]], -1
+; CHECK-NEXT:[[I4:%.*]] = and i32 [[I3]], [[B]]
+; CHECK-NEXT:tail call void @use(i32 [[I4]])
+; CHECK-NEXT:[[I5:%.*]] = or i32 [[I4]], [[I2]]
+; CHECK-NEXT:ret i32 [[I5]]
+;
+ %i = or i32 %B, %A
+ %i2 = xor i32 %i, -1
+ tail call void @use(i32 %i2)
+ %i3 = xor i32 %A, -1
+ %i4 = and i32 %i3, %B
+ tail call void @use(i32 %i4)
+ %i5 = or i32 %i4, %i2
+ ret i32 %i5
+}
___
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[llvm-branch-commits] [llvm] 25c1578 - Fix llvm::Optional build breaks in MSVC using std::is_trivially_copyable
Author: James Player
Date: 2021-01-16T09:37:04-05:00
New Revision: 25c1578a46ff93f920b7ad4e3057465902ced8f5
URL:
https://github.com/llvm/llvm-project/commit/25c1578a46ff93f920b7ad4e3057465902ced8f5
DIFF:
https://github.com/llvm/llvm-project/commit/25c1578a46ff93f920b7ad4e3057465902ced8f5.diff
LOG: Fix llvm::Optional build breaks in MSVC using std::is_trivially_copyable
Current code breaks this version of MSVC due to a mismatch between
`std::is_trivially_copyable` and `llvm::is_trivially_copyable` for `std::pair`
instantiations. Hence I was attempting to use `std::is_trivially_copyable` to
set `llvm::is_trivially_copyable::value`.
I spent some time root causing an `llvm::Optional` build error on MSVC 16.8.3
related to the change described above:
```
62>C:\src\ocg_llvm\llvm-project\llvm\include\llvm/ADT/BreadthFirstIterator.h(96,12):
error C2280: 'llvm::Optional::NodeSubset>
*,llvm::Optional::ChildIterator>>>
::Optional::NodeSubset>
*,llvm::Optional::ChildIterator>>>::operator =(const
llvm::Optional::NodeSubset>
*,llvm::Optional::ChildIterator>>> &)': attempting to reference
a deleted function (compiling source file
C:\src\ocg_llvm\llvm-project\llvm\unittests\ADT\BreadthFirstIteratorTest.cpp)
...
```
The "trivial" specialization of `optional_detail::OptionalStorage` assumes that
the value type is trivially copy constructible and trivially copy assignable.
The specialization is invoked based on a check of `is_trivially_copyable`
alone, which does not imply both `is_trivially_copy_assignable` and
`is_trivially_copy_constructible` are true.
[[ https://en.cppreference.com/w/cpp/named_req/TriviallyCopyable | According to
the spec ]], a deleted assignment operator does not make
`is_trivially_copyable` false. So I think all these properties need to be
checked explicitly in order to specialize `OptionalStorage` to the "trivial"
version:
```
/// Storage for any type.
template ::value
&& std::is_trivially_copy_assignable::value>
class OptionalStorage {
```
Above fixed my build break in MSVC, but I think we need to explicitly check
`is_trivially_copy_constructible` too since it might be possible the copy
constructor is deleted. Also would be ideal to move over to
`std::is_trivially_copyable` instead of the `llvm` namespace verson.
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D93510
Added:
Modified:
llvm/include/llvm/ADT/Optional.h
llvm/unittests/ADT/OptionalTest.cpp
Removed:
diff --git a/llvm/include/llvm/ADT/Optional.h
b/llvm/include/llvm/ADT/Optional.h
index daa9ee627fa9..a285c81d1be8 100644
--- a/llvm/include/llvm/ADT/Optional.h
+++ b/llvm/include/llvm/ADT/Optional.h
@@ -33,7 +33,30 @@ namespace optional_detail {
struct in_place_t {};
/// Storage for any type.
-template ::value>
+//
+// The specialization condition intentionally uses
+// llvm::is_trivially_copy_constructible instead of
+// std::is_trivially_copy_constructible. GCC versions prior to 7.4 may
+// instantiate the copy constructor of `T` when
+// std::is_trivially_copy_constructible is instantiated. This causes
+// compilation to fail if we query the trivially copy constructible property of
+// a class which is not copy constructible.
+//
+// The current implementation of OptionalStorage insists that in order to use
+// the trivial specialization, the value_type must be trivially copy
+// constructible and trivially copy assignable due to =default implementations
+// of the copy/move constructor/assignment. It does not follow that this is
+// necessarily the case std::is_trivially_copyable is true (hence the expanded
+// specialization condition).
+//
+// The move constructible / assignable conditions emulate the remaining
behavior
+// of std::is_trivially_copyable.
+template ::value
&&
+ std::is_trivially_copy_assignable::value &&
+ (std::is_trivially_move_constructible::value
||
+ !std::is_move_constructible::value) &&
+ (std::is_trivially_move_assignable::value ||
+ !std::is_move_assignable::value))>
class OptionalStorage {
union {
char empty;
diff --git a/llvm/unittests/ADT/OptionalTest.cpp
b/llvm/unittests/ADT/OptionalTest.cpp
index c7fa796a2d7f..d40e21255f80 100644
--- a/llvm/unittests/ADT/OptionalTest.cpp
+++ b/llvm/unittests/ADT/OptionalTest.cpp
@@ -8,6 +8,7 @@
#include "llvm/ADT/Optional.h"
#include "llvm/ADT/SmallString.h"
+#include "llvm/ADT/StringMap.h"
#include "llvm/Support/raw_ostream.h"
#include "gtest/gtest-spi.h"
#include "gtest/gtest.h"
@@ -390,6 +391,143 @@ TEST(OptionalTest, ImmovableEmplace) {
EXPECT_EQ(0u, Immovable::Destructions);
}
+// Craft a class which is_trivially_copyable, but not
+// is_trivially_copy_constructible.
+struct NonTCopy {
+ NonTCopy() =
[llvm-branch-commits] [clang] b765eaf - [ASTMatchers] Add support for CXXRewrittenBinaryOperator
Author: Stephen Kelly
Date: 2021-01-16T13:44:22Z
New Revision: b765eaf9a617bd3da30f47ece731b33593929885
URL:
https://github.com/llvm/llvm-project/commit/b765eaf9a617bd3da30f47ece731b33593929885
DIFF:
https://github.com/llvm/llvm-project/commit/b765eaf9a617bd3da30f47ece731b33593929885.diff
LOG: [ASTMatchers] Add support for CXXRewrittenBinaryOperator
Differential Revision: https://reviews.llvm.org/D94130
Added:
Modified:
clang/docs/LibASTMatchersReference.html
clang/include/clang/AST/ASTNodeTraverser.h
clang/include/clang/AST/ExprCXX.h
clang/include/clang/ASTMatchers/ASTMatchers.h
clang/include/clang/ASTMatchers/ASTMatchersInternal.h
clang/lib/ASTMatchers/ASTMatchFinder.cpp
clang/lib/ASTMatchers/ASTMatchersInternal.cpp
clang/lib/ASTMatchers/Dynamic/Registry.cpp
clang/unittests/AST/ASTTraverserTest.cpp
clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
Removed:
diff --git a/clang/docs/LibASTMatchersReference.html
b/clang/docs/LibASTMatchersReference.html
index 453d8f16c25a..912da6e62c2f 100644
--- a/clang/docs/LibASTMatchersReference.html
+++ b/clang/docs/LibASTMatchersReference.html
@@ -498,6 +498,42 @@ Traverse Mode
+
+
+
+
+
+
+ Rewritten binary operators
+
+binaryOperator(
+ hasOperatorName(""),
+ hasRHS(integerLiteral(equals(0)))
+ )
+
+given:
+
+#include compare
+
+class HasSpaceship {
+public:
+ int x;
+ bool operator==(const HasSpaceship&) const = default;
+ std::strong_ordering operator<=>(const HasSpaceship&) const = default;
+};
+
+bool isLess(const HasSpaceship& a, const HasSpaceship& b) {
+ return a < b;
+}
+
+
+
+1 match found.
+
+
+No match found.
+
+
@@ -1523,6 +1559,25 @@ Node Matchers
+Matcherhttps://clang.llvm.org/doxygen/classclang_1_1Stmt.html;>StmtcxxRewrittenBinaryOperatorMatcherhttps://clang.llvm.org/doxygen/classclang_1_1CXXRewrittenBinaryOperator.html;>CXXRewrittenBinaryOperator...
+Matches
rewritten binary operators
+
+Example matches use of "":
+ #include compare
+ struct HasSpaceshipMem {
+int a;
+constexpr auto operator=(const HasSpaceshipMem) const =
default;
+ };
+ void compare() {
+HasSpaceshipMem hs1, hs2;
+if (hs1 hs2)
+return;
+ }
+See also the binaryOperation() matcher for more-general matching
+of this AST node.
+
+
+
Matcherhttps://clang.llvm.org/doxygen/classclang_1_1Stmt.html;>StmtcxxStaticCastExprMatcherhttps://clang.llvm.org/doxygen/classclang_1_1CXXStaticCastExpr.html;>CXXStaticCastExpr...
Matches a C++
static_cast expression.
@@ -3405,6 +3460,53 @@ Narrowing Matchers
+Matcherhttps://clang.llvm.org/doxygen/classclang_1_1CXXRewrittenBinaryOperator.html;>CXXRewrittenBinaryOperatorhasAnyOperatorNameStringRef, ...,
StringRef
+Matches operator
expressions (binary or unary) that have any of the
+specified names.
+
+ hasAnyOperatorName("+", "-")
+ Is equivalent to
+ anyOf(hasOperatorName("+"), hasOperatorName("-"))
+
+
+
+Matcherhttps://clang.llvm.org/doxygen/classclang_1_1CXXRewrittenBinaryOperator.html;>CXXRewrittenBinaryOperatorhasOperatorNamestd::string
Name
+Matches the
operator Name of operator expressions (binary or
+unary).
+
+Example matches a || b (matcher = binaryOperator(hasOperatorName("||")))
+ !(a || b)
+
+
+
+Matcherhttps://clang.llvm.org/doxygen/classclang_1_1CXXRewrittenBinaryOperator.html;>CXXRewrittenBinaryOperatorisAssignmentOperator
+Matches all
kinds of assignment operators.
+
+Example 1: matches a += b (matcher = binaryOperator(isAssignmentOperator()))
+ if (a == b)
+a += b;
+
+Example 2: matches s1 = s2
+ (matcher = cxxOperatorCallExpr(isAssignmentOperator()))
+ struct S { S operator=(const S); };
+ void x() { S s1, s2; s1 = s2; }
+
+
+
+Matcherhttps://clang.llvm.org/doxygen/classclang_1_1CXXRewrittenBinaryOperator.html;>CXXRewrittenBinaryOperatorisComparisonOperator
+Matches
comparison operators.
+
+Example 1: matches a == b (matcher = binaryOperator(isComparisonOperator()))
+ if (a == b)
+a += b;
+
+Example 2: matches s1 s2
+ (matcher = cxxOperatorCallExpr(isComparisonOperator()))
+ struct S { bool operator(const S other); };
+ void x(S s1, S s2) { bool b1 = s1 s2; }
+
+
+
Matcherhttps://clang.llvm.org/doxygen/classclang_1_1CXXUnresolvedConstructExpr.html;>CXXUnresolvedConstructExprargumentCountIsunsigned N
Checks that a call
expression or a constructor call expression has
a specific number of arguments (including absent default arguments).
@@ -5174,8 +5276,8 @@ Narrowing Matchers
-Matcherhttps://clang.llvm.org/doxygen/classclang_1_1UnaryOperator.html;>UnaryOperatorhasAnyOperatorNameStringRef, ...,
StringRef
-Matches operator
expressions (binary or unary) that have any of the
+Matcherhttps://clang.llvm.org/doxygen/classclang_1_1UnaryOperator.html;>UnaryOperatorhasAnyOperatorNameStringRef, ...,
StringRef
[llvm-branch-commits] [clang] e810e95 - [ASTMatchers] Add binaryOperation matcher
Author: Stephen Kelly
Date: 2021-01-16T13:44:09Z
New Revision: e810e95e4bb908d1c8844e2c6f7da999732cabc9
URL:
https://github.com/llvm/llvm-project/commit/e810e95e4bb908d1c8844e2c6f7da999732cabc9
DIFF:
https://github.com/llvm/llvm-project/commit/e810e95e4bb908d1c8844e2c6f7da999732cabc9.diff
LOG: [ASTMatchers] Add binaryOperation matcher
This is a simple utility which allows matching on binaryOperator and
cxxOperatorCallExpr. It can also be extended to support
cxxRewrittenBinaryOperator.
Add generic support for MapAnyOfMatchers to auto-marshalling functions.
Differential Revision: https://reviews.llvm.org/D94129
Added:
Modified:
clang/docs/LibASTMatchersReference.html
clang/docs/tools/dump_ast_matchers.py
clang/include/clang/ASTMatchers/ASTMatchers.h
clang/lib/ASTMatchers/ASTMatchersInternal.cpp
clang/lib/ASTMatchers/Dynamic/Marshallers.h
clang/lib/ASTMatchers/Dynamic/Registry.cpp
clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
Removed:
diff --git a/clang/docs/LibASTMatchersReference.html
b/clang/docs/LibASTMatchersReference.html
index 497e2d4584a2..453d8f16c25a 100644
--- a/clang/docs/LibASTMatchersReference.html
+++ b/clang/docs/LibASTMatchersReference.html
@@ -1206,6 +1206,7 @@ Node Matchers
Example matches a || b
!(a || b)
+See also the binaryOperation() matcher for more-general matching.
@@ -1505,6 +1506,8 @@ Node Matchers
ostream operator (ostream out, int i) { };
ostream o; int b = 1, c = 1;
o b c;
+See also the binaryOperation() matcher for more-general matching of binary
+uses of this AST node.
@@ -5438,6 +5441,48 @@ AST Traversal Matchers
Return
typeNameParameters
+Matcher*binaryOperationMatcher*...Matcher*
+Matches nodes which
can be used with binary operators.
+
+The code
+ var1 != var2;
+might be represented in the clang AST as a binaryOperator or a
+cxxOperatorCallExpr, depending on
+
+* whether the types of var1 and var2 are fundamental (binaryOperator) or at
+ least one is a class type (cxxOperatorCallExpr)
+* whether the code appears in a template declaration, if at least one of the
+ vars is a dependent-type (binaryOperator)
+
+This matcher elides details in places where the matchers for the nodes are
+compatible.
+
+Given
+ binaryOperation(
+hasOperatorName("!="),
+hasLHS(expr().bind("lhs")),
+hasRHS(expr().bind("rhs"))
+ )
+matches each use of "!=" in:
+ struct S{
+ bool operator!=(const S) const;
+ };
+
+ void foo()
+ {
+ 1 != 2;
+ S() != S();
+ }
+
+ templatetypename T
+ void templ()
+ {
+ 1 != 2;
+ T() != S();
+ }
+
+
+
Matcher*eachOfMatcher*, ...,
Matcher*
Matches if any of the given
matchers matches.
diff --git a/clang/docs/tools/dump_ast_matchers.py
b/clang/docs/tools/dump_ast_matchers.py
index d3aff1284f60..18afbdd36c6e 100755
--- a/clang/docs/tools/dump_ast_matchers.py
+++ b/clang/docs/tools/dump_ast_matchers.py
@@ -379,6 +379,14 @@ def act_on_decl(declaration, comment, allowed_types):
add_matcher('*', name, 'Matcher<*>, ..., Matcher<*>', comment)
return
+m = re.match(
+r"""^.*MapAnyOfMatcher<.*>\s*
+ ([a-zA-Z]*);$""",
+declaration, flags=re.X)
+if m:
+ name = m.groups()[0]
+ add_matcher('*', name, 'Matcher<*>...Matcher<*>', comment)
+ return
# Parse free standing matcher functions, like:
# Matcher Name(Matcher InnerMatcher) {
diff --git a/clang/include/clang/ASTMatchers/ASTMatchers.h
b/clang/include/clang/ASTMatchers/ASTMatchers.h
index e81ac4cb7bf8..8140e20c9cad 100644
--- a/clang/include/clang/ASTMatchers/ASTMatchers.h
+++ b/clang/include/clang/ASTMatchers/ASTMatchers.h
@@ -1971,6 +1971,8 @@ extern const internal::VariadicDynCastAllOfMatcher
/// ostream int b = 1, c = 1;
/// o << b << c;
/// \endcode
+/// See also the binaryOperation() matcher for more-general matching of binary
+/// uses of this AST node.
extern const internal::VariadicDynCastAllOfMatcher
cxxOperatorCallExpr;
@@ -2393,6 +2395,7 @@ extern const internal::VariadicDynCastAllOfMatcher stmtExpr;
/// \code
/// !(a || b)
/// \endcode
+/// See also the binaryOperation() matcher for more-general matching.
extern const internal::VariadicDynCastAllOfMatcher
binaryOperator;
@@ -2729,6 +2732,53 @@ auto mapAnyOf(internal::VariadicDynCastAllOfMatcher const &...) {
return internal::MapAnyOfHelper();
}
+/// Matches nodes which can be used with binary operators.
+///
+/// The code
+/// \code
+/// var1 != var2;
+/// \endcode
+/// might be represented in the clang AST as a binaryOperator or a
+/// cxxOperatorCallExpr, depending on
+///
+/// * whether the types of var1 and var2 are fundamental (binaryOperator) or at
+/// least one is a class type (cxxOperatorCallExpr)
+/// * whether the code appears in a template declaration, if at least one of
the
+/// vars is a
[llvm-branch-commits] [llvm] 4f15556 - [LegalizeDAG] Handle NeedInvert when expanding BR_CC
Author: Bjorn Pettersson
Date: 2021-01-16T14:33:19+01:00
New Revision: 4f155567317d3187bc18be866b3f3b5352f1bfa5
URL:
https://github.com/llvm/llvm-project/commit/4f155567317d3187bc18be866b3f3b5352f1bfa5
DIFF:
https://github.com/llvm/llvm-project/commit/4f155567317d3187bc18be866b3f3b5352f1bfa5.diff
LOG: [LegalizeDAG] Handle NeedInvert when expanding BR_CC
This is a follow-up fix to commit 03c8d6a0c4bd0016bdfd1e5.
Seems like we now end up with NeedInvert being set in the result
from LegalizeSetCCCondCode more often than in the past, so we
need to handle NeedInvert when expanding BR_CC.
Not sure how to deal with the "Tmp4.getNode()" case properly,
but current assumption is that that code path isn't impacted
by the changes in 03c8d6a0c4bd0016bdfd1e5 so we can simply move
the old assert into the if-branch and only handle NeedInvert in the
else-branch.
I think that the test case added here, for PowerPC, might have
failed also before commit 03c8d6a0c4bd0016bdfd1e5. But we started
to hit the assert more often downstream when having merged that
commit.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D94762
Added:
llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll
Modified:
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Removed:
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 2437b07e7d0e..2ef3d9947169 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3966,16 +3966,16 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
(void)Legalized;
assert(Legalized && "Can't legalize BR_CC with legal condition!");
-assert(!NeedInvert && "Don't know how to invert BR_CC!");
-
// If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
// node.
if (Tmp4.getNode()) {
+ assert(!NeedInvert && "Don't know how to invert BR_CC!");
+
Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
Tmp4, Tmp2, Tmp3, Node->getOperand(4));
} else {
Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
- Tmp4 = DAG.getCondCode(ISD::SETNE);
+ Tmp4 = DAG.getCondCode(NeedInvert ? ISD::SETEQ : ISD::SETNE);
Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
Tmp2, Tmp3, Node->getOperand(4));
}
diff --git a/llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll
b/llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll
new file mode 100644
index ..1e109d0ea4a7
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O1 -mtriple powerpc -mattr=+spe -o - %s | FileCheck %s
+
+; This used to hit an assert
+;
+; ../lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:3971: bool
{anonymous}::SelectionDAGLegalize::ExpandNode(llvm::SDNode*): Assertion
`!NeedInvert && "Don't know how to invert BR_CC!"' failed.
+
+define void @test_fcmpueq_legalize_br_cc_with_invert(float %a) {
+; CHECK-LABEL: test_fcmpueq_legalize_br_cc_with_invert:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lis 4, .LCPI0_0@ha
+; CHECK-NEXT:lwz 4, .LCPI0_0@l(4)
+; CHECK-NEXT: .LBB0_1: # %l1
+; CHECK-NEXT:#
+; CHECK-NEXT:efscmplt 7, 3, 4
+; CHECK-NEXT:efscmpgt 0, 3, 4
+; CHECK-NEXT:mfcr 5 # cr7
+; CHECK-NEXT:mcrf 7, 0
+; CHECK-NEXT:mfcr 6 # cr7
+; CHECK-NEXT:rlwinm 5, 5, 30, 31, 31
+; CHECK-NEXT:rlwinm 6, 6, 30, 31, 31
+; CHECK-NEXT:or. 5, 6, 5
+; CHECK-NEXT:beq 0, .LBB0_1
+; CHECK-NEXT: # %bb.2: # %l2
+; CHECK-NEXT:blr
+entry:
+ br label %l1
+l1:
+ %fcmp = fcmp ueq float %a, 0xC6306B344000
+ br i1 %fcmp, label %l1, label %l2
+l2:
+ ret void
+}
___
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[llvm-branch-commits] [clang] dbe056c - [ASTMatchers] Make cxxOperatorCallExpr matchers API-compatible with n-ary operators
Author: Stephen Kelly
Date: 2021-01-16T12:53:11Z
New Revision: dbe056c2e37f00b9f33ab63bba73dbb004e13562
URL:
https://github.com/llvm/llvm-project/commit/dbe056c2e37f00b9f33ab63bba73dbb004e13562
DIFF:
https://github.com/llvm/llvm-project/commit/dbe056c2e37f00b9f33ab63bba73dbb004e13562.diff
LOG: [ASTMatchers] Make cxxOperatorCallExpr matchers API-compatible with n-ary
operators
This makes them composable with mapAnyOf().
Differential Revision: https://reviews.llvm.org/D94128
Added:
Modified:
clang/docs/LibASTMatchersReference.html
clang/include/clang/ASTMatchers/ASTMatchers.h
clang/include/clang/ASTMatchers/ASTMatchersInternal.h
clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
Removed:
diff --git a/clang/docs/LibASTMatchersReference.html
b/clang/docs/LibASTMatchersReference.html
index e5de645266b7..497e2d4584a2 100644
--- a/clang/docs/LibASTMatchersReference.html
+++ b/clang/docs/LibASTMatchersReference.html
@@ -3232,6 +3232,16 @@ Narrowing Matchers
+Matcherhttps://clang.llvm.org/doxygen/classclang_1_1CXXOperatorCallExpr.html;>CXXOperatorCallExprhasAnyOperatorNameStringRef, ...,
StringRef
+Matches operator
expressions (binary or unary) that have any of the
+specified names.
+
+ hasAnyOperatorName("+", "-")
+ Is equivalent to
+ anyOf(hasOperatorName("+"), hasOperatorName("-"))
+
+
+
Matcherhttps://clang.llvm.org/doxygen/classclang_1_1CXXOperatorCallExpr.html;>CXXOperatorCallExprhasAnyOverloadedOperatorNameStringRef,
..., StringRef
Matches overloaded operator names.
@@ -3244,6 +3254,15 @@ Narrowing Matchers
+Matcherhttps://clang.llvm.org/doxygen/classclang_1_1CXXOperatorCallExpr.html;>CXXOperatorCallExprhasOperatorNamestd::string
Name
+Matches the
operator Name of operator expressions (binary or
+unary).
+
+Example matches a || b (matcher = binaryOperator(hasOperatorName("||")))
+ !(a || b)
+
+
+
Matcherhttps://clang.llvm.org/doxygen/classclang_1_1CXXOperatorCallExpr.html;>CXXOperatorCallExprhasOverloadedOperatorNameStringRef
Name
Matches
overloaded operator names.
@@ -5152,8 +5171,8 @@ Narrowing Matchers
-Matcherhttps://clang.llvm.org/doxygen/classclang_1_1UnaryOperator.html;>UnaryOperatorhasAnyOperatorNameStringRef, ...,
StringRef
-Matches operator
expressions (binary or unary) that have any of the
+Matcherhttps://clang.llvm.org/doxygen/classclang_1_1UnaryOperator.html;>UnaryOperatorhasAnyOperatorNameStringRef, ...,
StringRef
+Matches operator
expressions (binary or unary) that have any of the
specified names.
hasAnyOperatorName("+", "-")
@@ -5162,8 +5181,8 @@ Narrowing Matchers
-Matcherhttps://clang.llvm.org/doxygen/classclang_1_1UnaryOperator.html;>UnaryOperatorhasOperatorNamestd::string
Name
-Matches the
operator Name of operator expressions (binary or
+Matcherhttps://clang.llvm.org/doxygen/classclang_1_1UnaryOperator.html;>UnaryOperatorhasOperatorNamestd::string
Name
+Matches the
operator Name of operator expressions (binary or
unary).
Example matches a || b (matcher = binaryOperator(hasOperatorName("||")))
@@ -5689,16 +5708,16 @@ AST Traversal Matchers
-Matcherhttps://clang.llvm.org/doxygen/classclang_1_1ArraySubscriptExpr.html;>ArraySubscriptExprhasLHSMatcherhttps://clang.llvm.org/doxygen/classclang_1_1Expr.html;>Expr
InnerMatcher
-Matches the left hand side
of binary operator expressions.
+Matcherhttps://clang.llvm.org/doxygen/classclang_1_1ArraySubscriptExpr.html;>ArraySubscriptExprhasLHSMatcherhttps://clang.llvm.org/doxygen/classclang_1_1Expr.html;>Expr
InnerMatcher
+Matches the left hand side
of binary operator expressions.
Example matches a (matcher = binaryOperator(hasLHS()))
a || b
-Matcherhttps://clang.llvm.org/doxygen/classclang_1_1ArraySubscriptExpr.html;>ArraySubscriptExprhasRHSMatcherhttps://clang.llvm.org/doxygen/classclang_1_1Expr.html;>Expr
InnerMatcher
-Matches the right hand side
of binary operator expressions.
+Matcherhttps://clang.llvm.org/doxygen/classclang_1_1ArraySubscriptExpr.html;>ArraySubscriptExprhasRHSMatcherhttps://clang.llvm.org/doxygen/classclang_1_1Expr.html;>Expr
InnerMatcher
+Matches the right hand side
of binary operator expressions.
Example matches b (matcher = binaryOperator(hasRHS()))
a || b
@@ -5749,7 +5768,7 @@ AST Traversal Matchers
-Matcherhttps://clang.llvm.org/doxygen/classclang_1_1BinaryOperator.html;>BinaryOperatorhasEitherOperandMatcherhttps://clang.llvm.org/doxygen/classclang_1_1Expr.html;>Expr
InnerMatcher
+Matcherhttps://clang.llvm.org/doxygen/classclang_1_1BinaryOperator.html;>BinaryOperatorhasEitherOperandMatcherhttps://clang.llvm.org/doxygen/classclang_1_1Expr.html;>Expr
InnerMatcher
Matches if either
the left hand side or the right hand side of a
binary operator matches.
@@ -5763,7 +5782,7 @@ AST Traversal Matchers
[llvm-branch-commits] [clang] a710145 - [ASTMatchers] Add mapAnyOf matcher
Author: Stephen Kelly
Date: 2021-01-16T12:53:11Z
New Revision: a7101450a42e4f1ed5af1a38a6def08f1b5b58fe
URL:
https://github.com/llvm/llvm-project/commit/a7101450a42e4f1ed5af1a38a6def08f1b5b58fe
DIFF:
https://github.com/llvm/llvm-project/commit/a7101450a42e4f1ed5af1a38a6def08f1b5b58fe.diff
LOG: [ASTMatchers] Add mapAnyOf matcher
Make it possible to compose a matcher for different base nodes.
This accepts one or more node matcher functors and zero or more
matchers, composing the latter into the former.
This allows composing of matchers where the same inner matcher name is
used for the same concept, but with a different node functor. Currently,
there is a limitation that the nodes must be in the same "clade", so
while
mapAnyOf(ifStmt, forStmt).with(hasBody(stmt()))
can be used, functionDecl can not be added to the tuple.
It is possible to use this in clang-query, but it will require changes
to the QueryParser, so is deferred to a future review.
Differential Revision: https://reviews.llvm.org/D94127
Added:
Modified:
clang/docs/LibASTMatchersReference.html
clang/docs/tools/dump_ast_matchers.py
clang/include/clang/ASTMatchers/ASTMatchers.h
clang/include/clang/ASTMatchers/ASTMatchersInternal.h
clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
Removed:
diff --git a/clang/docs/LibASTMatchersReference.html
b/clang/docs/LibASTMatchersReference.html
index 18acfc48..e5de645266b7 100644
--- a/clang/docs/LibASTMatchersReference.html
+++ b/clang/docs/LibASTMatchersReference.html
@@ -2593,6 +2593,29 @@ Narrowing Matchers
+unspecifiedmapAnyOfnodeMatcherFunction...
+Matches any of the
NodeMatchers with InnerMatchers nested within
+
+Given
+ if (true);
+ for (; true; );
+with the matcher
+ mapAnyOf(ifStmt, forStmt).with(
+hasCondition(cxxBoolLiteralExpr(equals(true)))
+).bind("trueCond")
+matches the if and the for. It is equivalent to:
+ auto trueCond = hasCondition(cxxBoolLiteralExpr(equals(true)));
+ anyOf(
+ifStmt(trueCond).bind("trueCond"),
+forStmt(trueCond).bind("trueCond")
+);
+
+The with() chain-call accepts zero or more matchers which are combined
+as-if with allOf() in each of the node matchers.
+Usable as: Any Matcher
+
+
+
Matcher*unlessMatcher*
Matches if the provided
matcher does not match.
@@ -2980,7 +3003,7 @@ Narrowing Matchers
Matcherhttps://clang.llvm.org/doxygen/classclang_1_1CXXDependentScopeMemberExpr.html;>CXXDependentScopeMemberExprhasMemberNamestd::string N
-Matches
template-dependent, but known, member names
+Matches
template-dependent, but known, member names.
In template declarations, dependent members are not resolved and so can
not be matched to particular named declarations.
diff --git a/clang/docs/tools/dump_ast_matchers.py
b/clang/docs/tools/dump_ast_matchers.py
index 045833be7673..d3aff1284f60 100755
--- a/clang/docs/tools/dump_ast_matchers.py
+++ b/clang/docs/tools/dump_ast_matchers.py
@@ -119,8 +119,15 @@ def add_matcher(result_type, name, args, comment,
is_dyncast=False):
ids[name] += 1
args = unify_arguments(args)
result_type = unify_type(result_type)
+
+ docs_result_type = esc('Matcher<%s>' % result_type);
+
+ if name == 'mapAnyOf':
+args = "nodeMatcherFunction..."
+docs_result_type = "unspecified"
+
matcher_html = TD_TEMPLATE % {
-'result': esc('Matcher<%s>' % result_type),
+'result': docs_result_type,
'name': name,
'args': esc(args),
'comment': esc(strip_doxygen(comment)),
@@ -135,7 +142,7 @@ def add_matcher(result_type, name, args, comment,
is_dyncast=False):
# exclude known narrowing matchers that also take other matchers as
# arguments.
elif ('Matcher<' not in args or
-name in ['allOf', 'anyOf', 'anything', 'unless']):
+name in ['allOf', 'anyOf', 'anything', 'unless', 'mapAnyOf']):
dict = narrowing_matchers
lookup = result_type + name + esc(args)
else:
diff --git a/clang/include/clang/ASTMatchers/ASTMatchers.h
b/clang/include/clang/ASTMatchers/ASTMatchers.h
index a45e08345fb3..dd99e6a420af 100644
--- a/clang/include/clang/ASTMatchers/ASTMatchers.h
+++ b/clang/include/clang/ASTMatchers/ASTMatchers.h
@@ -847,6 +847,12 @@ traverse(TraversalKind TK, const
internal::PolymorphicMatcherWithParam2<
TK, InnerMatcher);
}
+template
+internal::Matcher::Type>
+traverse(TraversalKind TK, const internal::MapAnyOfHelper )
{
+ return traverse(TK, InnerMatcher.with());
+}
+
/// Matches expressions that match InnerMatcher after any implicit AST
/// nodes are stripped off.
///
@@ -2693,6 +2699,36 @@ extern const internal::VariadicDynCastAllOfMatcher
unaryExprOrTypeTraitExpr;
+/// Matches any of the \p NodeMatchers with InnerMatchers nested within
+///
+/// Given
+/// \code
+/// if (true);
+/// for (; true; );
+/// \endcode
+/// with the matcher
+/// \code
+/// mapAnyOf(ifStmt, forStmt).with(
[llvm-branch-commits] [llvm] f0a0ec2 - [InstCombine] Add more tests for select operand replacement (NFC)
Author: Nikita Popov
Date: 2021-01-16T13:10:59+01:00
New Revision: f0a0ec2d085b0bc53e20643b740b20b49cfd9bd5
URL:
https://github.com/llvm/llvm-project/commit/f0a0ec2d085b0bc53e20643b740b20b49cfd9bd5
DIFF:
https://github.com/llvm/llvm-project/commit/f0a0ec2d085b0bc53e20643b740b20b49cfd9bd5.diff
LOG: [InstCombine] Add more tests for select operand replacement (NFC)
Added:
Modified:
llvm/test/Transforms/InstCombine/select-binop-cmp.ll
Removed:
diff --git a/llvm/test/Transforms/InstCombine/select-binop-cmp.ll
b/llvm/test/Transforms/InstCombine/select-binop-cmp.ll
index c4a9d0941b96..55738953f60d 100644
--- a/llvm/test/Transforms/InstCombine/select-binop-cmp.ll
+++ b/llvm/test/Transforms/InstCombine/select-binop-cmp.ll
@@ -1084,4 +1084,104 @@ define i32 @select_sdiv_icmp_bad(i32 %x, i32 %y, i32
%z) {
ret i32 %C
}
+define i32 @select_replace_one_use(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_replace_one_use(
+; CHECK-NEXT:[[C:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT:[[SUB:%.*]] = sub i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT:[[S:%.*]] = select i1 [[C]], i32 [[SUB]], i32 [[Y]]
+; CHECK-NEXT:ret i32 [[S]]
+;
+ %c = icmp eq i32 %x, 0
+ %sub = sub i32 %x, %y
+ %s = select i1 %c, i32 %sub, i32 %y
+ ret i32 %s
+}
+
+define i32 @select_replace_multi_use(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_replace_multi_use(
+; CHECK-NEXT:[[C:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT:[[SUB:%.*]] = sub i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT:call void @use_i32(i32 [[SUB]])
+; CHECK-NEXT:[[S:%.*]] = select i1 [[C]], i32 [[SUB]], i32 [[Y]]
+; CHECK-NEXT:ret i32 [[S]]
+;
+ %c = icmp eq i32 %x, 0
+ %sub = sub i32 %x, %y
+ call void @use_i32(i32 %sub)
+ %s = select i1 %c, i32 %sub, i32 %y
+ ret i32 %s
+}
+
+define i32 @select_replace_fold(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_replace_fold(
+; CHECK-NEXT:[[C:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT:[[FSHR:%.*]] = call i32 @llvm.fshr.i32(i32 [[Y:%.*]], i32
[[Z:%.*]], i32 [[X]])
+; CHECK-NEXT:[[S:%.*]] = select i1 [[C]], i32 [[FSHR]], i32 [[Y]]
+; CHECK-NEXT:ret i32 [[S]]
+;
+ %c = icmp eq i32 %x, 0
+ %fshr = call i32 @llvm.fshr.i32(i32 %y, i32 %z, i32 %x)
+ %s = select i1 %c, i32 %fshr, i32 %y
+ ret i32 %s
+}
+
+define i32 @select_replace_multiple_ops(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_replace_multiple_ops(
+; CHECK-NEXT:[[C:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT:[[CALL:%.*]] = call i32 @dummy_call(i32 [[X]], i32 [[X]], i32
[[X]])
+; CHECK-NEXT:[[S:%.*]] = select i1 [[C]], i32 [[CALL]], i32 [[Y:%.*]]
+; CHECK-NEXT:ret i32 [[S]]
+;
+ %c = icmp eq i32 %x, 0
+ %call = call i32 @dummy_call(i32 %x, i32 %x, i32 %x)
+ %s = select i1 %c, i32 %call, i32 %y
+ ret i32 %s
+}
+
+define i32 @select_replace_nested(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_replace_nested(
+; CHECK-NEXT:[[C:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT:[[SUB:%.*]] = sub i32 [[Y:%.*]], [[X]]
+; CHECK-NEXT:[[ADD:%.*]] = add i32 [[SUB]], [[Z:%.*]]
+; CHECK-NEXT:[[S:%.*]] = select i1 [[C]], i32 [[ADD]], i32 [[Y]]
+; CHECK-NEXT:ret i32 [[S]]
+;
+ %c = icmp eq i32 %x, 0
+ %sub = sub i32 %y, %x
+ %add = add i32 %sub, %z
+ %s = select i1 %c, i32 %add, i32 %y
+ ret i32 %s
+}
+
+define i32 @select_replace_constexpr(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @select_replace_constexpr(
+; CHECK-NEXT:[[C:%.*]] = icmp eq i32 [[X:%.*]], ptrtoint (i32* @g to i32)
+; CHECK-NEXT:[[ADD:%.*]] = add i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT:[[S:%.*]] = select i1 [[C]], i32 [[ADD]], i32 [[Z:%.*]]
+; CHECK-NEXT:ret i32 [[S]]
+;
+ %c = icmp eq i32 %x, ptrtoint (i32* @g to i32)
+ %add = add i32 %x, %y
+ %s = select i1 %c, i32 %add, i32 %z
+ ret i32 %s
+}
+
+define <2 x i32> @select_replace_undef(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @select_replace_undef(
+; CHECK-NEXT:[[C:%.*]] = icmp eq <2 x i32> [[X:%.*]],
+; CHECK-NEXT:[[SUB:%.*]] = sub <2 x i32> [[X]], [[Y:%.*]]
+; CHECK-NEXT:[[S:%.*]] = select <2 x i1> [[C]], <2 x i32> [[SUB]], <2 x
i32> [[Y]]
+; CHECK-NEXT:ret <2 x i32> [[S]]
+;
+ %c = icmp eq <2 x i32> %x,
+ %sub = sub <2 x i32> %x, %y
+ %s = select <2 x i1> %c, <2 x i32> %sub, <2 x i32> %y
+ ret <2 x i32> %s
+}
+
+@g = global i32 0
+declare i32 @llvm.fshr.i32(i32, i32, i32)
+declare i32 @dummy_call(i32, i32, i32)
+declare void @use_i32(i32)
+
!0 = !{!"branch_weights", i32 2, i32 10}
___
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[llvm-branch-commits] [llvm] e0a979c - [InstCombine] Add more tests to select-safe-transforms.ll (NFC)
Author: Juneyoung Lee
Date: 2021-01-16T19:49:12+09:00
New Revision: e0a979ccadd81c71d78be816e893dd1bcd6508ee
URL:
https://github.com/llvm/llvm-project/commit/e0a979ccadd81c71d78be816e893dd1bcd6508ee
DIFF:
https://github.com/llvm/llvm-project/commit/e0a979ccadd81c71d78be816e893dd1bcd6508ee.diff
LOG: [InstCombine] Add more tests to select-safe-transforms.ll (NFC)
Added:
Modified:
llvm/test/Transforms/InstCombine/select-safe-transforms.ll
Removed:
diff --git a/llvm/test/Transforms/InstCombine/select-safe-transforms.ll
b/llvm/test/Transforms/InstCombine/select-safe-transforms.ll
index 48067bf9d67f..b16985ba1b75 100644
--- a/llvm/test/Transforms/InstCombine/select-safe-transforms.ll
+++ b/llvm/test/Transforms/InstCombine/select-safe-transforms.ll
@@ -14,6 +14,19 @@ define i1 @cond_eq_and(i8 %X, i8 %Y, i8 noundef %C) {
ret i1 %res
}
+define i1 @cond_eq_and_const(i8 %X, i8 %Y) {
+; CHECK-LABEL: @cond_eq_and_const(
+; CHECK-NEXT:[[COND:%.*]] = icmp eq i8 [[X:%.*]], 10
+; CHECK-NEXT:[[LHS:%.*]] = icmp ult i8 [[X]], [[Y:%.*]]
+; CHECK-NEXT:[[RES:%.*]] = select i1 [[COND]], i1 [[LHS]], i1 false
+; CHECK-NEXT:ret i1 [[RES]]
+;
+ %cond = icmp eq i8 %X, 10
+ %lhs = icmp ult i8 %X, %Y
+ %res = select i1 %cond, i1 %lhs, i1 false
+ ret i1 %res
+}
+
define i1 @cond_eq_or(i8 %X, i8 %Y, i8 noundef %C) {
; CHECK-LABEL: @cond_eq_or(
; CHECK-NEXT:[[COND:%.*]] = icmp ne i8 [[X:%.*]], [[C:%.*]]
@@ -27,6 +40,19 @@ define i1 @cond_eq_or(i8 %X, i8 %Y, i8 noundef %C) {
ret i1 %res
}
+define i1 @cond_eq_or_const(i8 %X, i8 %Y) {
+; CHECK-LABEL: @cond_eq_or_const(
+; CHECK-NEXT:[[COND:%.*]] = icmp ne i8 [[X:%.*]], 10
+; CHECK-NEXT:[[LHS:%.*]] = icmp ult i8 [[X]], [[Y:%.*]]
+; CHECK-NEXT:[[RES:%.*]] = select i1 [[COND]], i1 true, i1 [[LHS]]
+; CHECK-NEXT:ret i1 [[RES]]
+;
+ %cond = icmp ne i8 %X, 10
+ %lhs = icmp ult i8 %X, %Y
+ %res = select i1 %cond, i1 true, i1 %lhs
+ ret i1 %res
+}
+
define i1 @merge_and(i1 %X, i1 %Y) {
; CHECK-LABEL: @merge_and(
; CHECK-NEXT:[[C:%.*]] = select i1 [[X:%.*]], i1 [[Y:%.*]], i1 false
___
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[llvm-branch-commits] [llvm] 668827b - Introduce llvm.noalias.decl intrinsic
Author: Jeroen Dobbelaere
Date: 2021-01-16T09:20:45+01:00
New Revision: 668827b6485664dbcf6caa2756fe2f6579ab1885
URL:
https://github.com/llvm/llvm-project/commit/668827b6485664dbcf6caa2756fe2f6579ab1885
DIFF:
https://github.com/llvm/llvm-project/commit/668827b6485664dbcf6caa2756fe2f6579ab1885.diff
LOG: Introduce llvm.noalias.decl intrinsic
The ``llvm.experimental.noalias.scope.decl`` intrinsic identifies where a
noalias
scope is declared. When the intrinsic is duplicated, a decision must
also be made about the scope: depending on the reason of the duplication,
the scope might need to be duplicated as well.
Reviewed By: nikic, jdoerfert
Differential Revision: https://reviews.llvm.org/D93039
Added:
llvm/test/Verifier/noalias_scope_decl.ll
Modified:
llvm/docs/LangRef.rst
llvm/include/llvm/IR/IRBuilder.h
llvm/include/llvm/IR/Intrinsics.h
llvm/include/llvm/IR/Intrinsics.td
llvm/lib/CodeGen/IntrinsicLowering.cpp
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/IR/IRBuilder.cpp
llvm/lib/IR/Verifier.cpp
Removed:
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index a6f6e8281a72..ccf1feb420eb 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -19603,6 +19603,82 @@ Semantics:
This function returns the same values as the libm ``trunc`` functions
would and handles error conditions in the same way.
+.. _int_experimental_noalias_scope_decl:
+
+'``llvm.experimental.noalias.scope.decl``' Intrinsic
+
+
+Syntax:
+"""
+
+
+::
+
+ declare void @llvm.experimental.noalias.scope.decl(metadata
!id.scope.list)
+
+Overview:
+"
+
+The ``llvm.experimental.noalias.scope.decl`` intrinsic identifies where a
+noalias scope is declared. When the intrinsic is duplicated, a decision must
+also be made about the scope: depending on the reason of the duplication,
+the scope might need to be duplicated as well.
+
+
+Arguments:
+""
+
+The ``!id.scope.list`` argument is metadata that is a list of ``noalias``
+metadata references. The format is identical to that required for ``noalias``
+metadata. This list must have exactly one element.
+
+Semantics:
+""
+
+The ``llvm.experimental.noalias.scope.decl`` intrinsic identifies where a
+noalias scope is declared. When the intrinsic is duplicated, a decision must
+also be made about the scope: depending on the reason of the duplication,
+the scope might need to be duplicated as well.
+
+For example, when the intrinsic is used inside a loop body, and that loop is
+unrolled, the associated noalias scope must also be duplicated. Otherwise, the
+noalias property it signifies would spill across loop iterations, whereas it
+was only valid within a single iteration.
+
+.. code-block:: llvm
+
+ ; This examples shows two possible positions for noalias.decl and how they
impact the semantics:
+ ; If it is outside the loop (Version 1), then %a and %b are noalias across
*all* iterations.
+ ; If it is inside the loop (Version 2), then %a and %b are noalias only
within *one* iteration.
+ declare void @decl_in_loop(i8* %a.base, i8* %b.base) {
+ entry:
+; call void @llvm.experimental.noalias.scope.decl(metadata !2) ; Version
1: noalias decl outside loop
+br label %loop
+
+ loop:
+%a = phi i8* [ %a.base, %entry ], [ %a.inc, %loop ]
+%b = phi i8* [ %b.base, %entry ], [ %b.inc, %loop ]
+; call void @llvm.experimental.noalias.scope.decl(metadata !2) ; Version
2: noalias decl inside loop
+%val = load i8, i8* %a, !alias.scope !2
+store i8 %val, i8* %b, !noalias !2
+%a.inc = getelementptr inbounds i8, i8* %a, i64 1
+%b.inc = getelementptr inbounds i8, i8* %b, i64 1
+%cond = call i1 @cond()
+br i1 %cond, label %loop, label %exit
+
+ exit:
+ret void
+ }
+
+ !0 = !{!0} ; domain
+ !1 = !{!1, !0} ; scope
+ !2 = !{!1} ; scope list
+
+Multiple calls to `@llvm.experimental.noalias.scope.decl` for the same scope
+are possible, but one should never dominate another. Violations are pointed out
+by the verifier as they indicate a problem in either a transformation pass or
+the input.
+
Floating Point Environment Manipulation intrinsics
--
diff --git a/llvm/include/llvm/IR/IRBuilder.h
b/llvm/include/llvm/IR/IRBuilder.h
index c9074abe88c2..9cefc9aa764c 100644
--- a/llvm/include/llvm/IR/IRBuilder.h
+++ b/llvm/include/llvm/IR/IRBuilder.h
@@ -858,6 +858,13 @@ class IRBuilderBase {
CallInst *CreateAssumption(Value *Cond,
ArrayRef OpBundles =
llvm::None);
+ /// Create a llvm.experimental.noalias.scope.decl intrinsic call.
+ Instruction *CreateNoAliasScopeDeclaration(Value *Scope);
+ Instruction *CreateNoAliasScopeDeclaration(MDNode *ScopeTag) {
+return
