[llvm-branch-commits] [lldb] 069d90a - Revert "Fix error in unrecognized register name handling for "SBFrame.registe…"

2024-04-11 Thread via llvm-branch-commits 

Author: Chelsea Cassanova
Date: 2024-04-11T20:12:43-07:00
New Revision: 069d90a500ed02067f3f1a5d01c7827623353b85

URL: 
https://github.com/llvm/llvm-project/commit/069d90a500ed02067f3f1a5d01c7827623353b85
DIFF: 
https://github.com/llvm/llvm-project/commit/069d90a500ed02067f3f1a5d01c7827623353b85.diff

LOG: Revert "Fix error in unrecognized register name handling for 
"SBFrame.registe…"

This reverts commit 9a36077e4db30c7da603620762036d4a430e4e62.

Added: 


Modified: 
lldb/bindings/interface/SBFrameExtensions.i
lldb/test/API/python_api/frame/TestFrames.py

Removed: 




diff  --git a/lldb/bindings/interface/SBFrameExtensions.i 
b/lldb/bindings/interface/SBFrameExtensions.i
index e0472280666ab9..43b22ed7a6b325 100644
--- a/lldb/bindings/interface/SBFrameExtensions.i
+++ b/lldb/bindings/interface/SBFrameExtensions.i
@@ -44,16 +44,6 @@ STRING_EXTENSION_OUTSIDE(SBFrame)
 def __init__(self, regs):
 self.regs = regs
 
-def __iter__(self):
-return self.get_registers()
-
-def get_registers(self):
-for i in range(0,len(self.regs)):
-rs = self.regs[i]
-for j in range (0,rs.num_children):
-reg = rs.GetChildAtIndex(j)
-yield reg
-  
 def __getitem__(self, key):
 if type(key) is str:
 for i in range(0,len(self.regs)):
@@ -62,7 +52,7 @@ STRING_EXTENSION_OUTSIDE(SBFrame)
 reg = rs.GetChildAtIndex(j)
 if reg.name == key: return reg
 else:
-return SBValue()
+return lldb.SBValue()
 
 return registers_access(self.registers)
 

diff  --git a/lldb/test/API/python_api/frame/TestFrames.py 
b/lldb/test/API/python_api/frame/TestFrames.py
index dfa96d51830bae..a82b129bc8099d 100644
--- a/lldb/test/API/python_api/frame/TestFrames.py
+++ b/lldb/test/API/python_api/frame/TestFrames.py
@@ -73,19 +73,7 @@ def test_get_arg_vals_for_call_stack(self):
 gpr_reg_set = lldbutil.get_GPRs(frame)
 pc_value = gpr_reg_set.GetChildMemberWithName("pc")
 self.assertTrue(pc_value, "We should have a valid PC.")
-# Make sure we can also get this from the "register" property:
-iterator_pc_value = 0
-found_pc = False
-for reg in frame.register:
-if reg.name == "pc":
-found_pc = True
-iterator_pc_value = int(reg.GetValue(), 0)
-break
-
 pc_value_int = int(pc_value.GetValue(), 0)
-self.assertTrue(found_pc, "Found the PC value in the register 
list")
-self.assertEqual(iterator_pc_value, pc_value_int, "The methods 
of finding pc match")
-
 # Make sure on arm targets we dont mismatch PC value on the 
basis of thumb bit.
 # Frame PC will not have thumb bit set in case of a thumb
 # instruction as PC.



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[llvm-branch-commits] gn build: Embed libc++abi.a objects into libc++.a. (PR #88463)

2024-04-11 Thread via llvm-branch-commits 

https://github.com/pcc created https://github.com/llvm/llvm-project/pull/88463

This matches the default CMake behavior.



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[llvm-branch-commits] [llvm] release/18.x: [Codegen][X86] Fix /HOTPATCH with clang-cl and inline asm (#87639) (PR #88388)

2024-04-11 Thread Shengchen Kan via llvm-branch-commits 

https://github.com/KanRobert approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/88388
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[llvm-branch-commits] [llvm] release/18.x: Prepend all library intrinsics with `#` when building for Arm64EC (PR #88016)

2024-04-11 Thread Daniel Paoliello via llvm-branch-commits 

https://github.com/dpaoliello edited 
https://github.com/llvm/llvm-project/pull/88016
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[llvm-branch-commits] [clang] Fix override keyword being print to the left side (PR #88453)

2024-04-11 Thread via llvm-branch-commits 

llvmbot wrote:




@llvm/pr-subscribers-clang

Author: Giuliano Belinassi (giulianobelinassi)


Changes

Previously, the `override` keyword in C++ was being print in the left side of a 
method decl, which is unsupported by C++ standard. This commit fixes that by 
setting the `CanPrintOnLeft` field to 0, forcing it to be print on the right 
side of the decl.

This comes from the fact that #87281 won't be backported into clang-18. 
However since classes with `override` keyword is broken in LLVM-18, I think 
this is still worth fixing.

@vgvassilev Please check if it works in your test cases.

Notice that this PR targets release/18.x, and not the main branch.

---
Full diff: https://github.com/llvm/llvm-project/pull/88453.diff


2 Files Affected:

- (modified) clang/include/clang/Basic/Attr.td (+2) 
- (added) clang/test/AST/ast-dump-override-final.cpp (+20) 


``diff
diff --git a/clang/include/clang/Basic/Attr.td 
b/clang/include/clang/Basic/Attr.td
index 58838b01b4fd7c..dbf2dd2120fb69 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -1590,6 +1590,7 @@ def RegCall : DeclOrTypeAttr {
 }
 
 def Final : InheritableAttr {
+  let CanPrintOnLeft = 0;
   let Spellings = [CustomKeyword<"final">, CustomKeyword<"sealed">];
   let Accessors = [Accessor<"isSpelledAsSealed", [CustomKeyword<"sealed">]>];
   let SemaHandler = 0;
@@ -2472,6 +2473,7 @@ def Overloadable : Attr {
 }
 
 def Override : InheritableAttr {
+  let CanPrintOnLeft = 0;
   let Spellings = [CustomKeyword<"override">];
   let SemaHandler = 0;
   // Omitted from docs, since this is language syntax, not an attribute, as far
diff --git a/clang/test/AST/ast-dump-override-final.cpp 
b/clang/test/AST/ast-dump-override-final.cpp
new file mode 100644
index 00..c1cee6b01565f6
--- /dev/null
+++ b/clang/test/AST/ast-dump-override-final.cpp
@@ -0,0 +1,20 @@
+// This file contain tests to check if override and final are dumped in the
+// correct positions.
+
+// RUN: %clang_cc1 -ast-print -x c++ %s -o - | FileCheck %s
+
+// CHECK: class A {
+class A {
+  // CHECK-NEXT: virtual void f();
+  virtual void f();
+
+  // CHECK-NEXT: virtual void g() final;
+  virtual void g() final;
+} AA;
+
+// CHECK: class B : public A {
+class B : public A {
+  // CHECK-NEXT: virtual void f() override {
+  virtual void f() override {
+  };
+} B;

``




https://github.com/llvm/llvm-project/pull/88453
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[llvm-branch-commits] [clang] Fix override keyword being print to the left side (PR #88453)

2024-04-11 Thread via llvm-branch-commits 

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[llvm-branch-commits] [clang] Fix override keyword being print to the left side (PR #88453)

2024-04-11 Thread Giuliano Belinassi via llvm-branch-commits 

https://github.com/giulianobelinassi created 
https://github.com/llvm/llvm-project/pull/88453

Previously, the `override` keyword in C++ was being print in the left side of a 
method decl, which is unsupported by C++ standard. This commit fixes that by 
setting the `CanPrintOnLeft` field to 0, forcing it to be print on the right 
side of the decl.

This comes from the fact that #87281 won't be backported into clang-18. However 
since classes with `override` keyword is broken in LLVM-18, I think this is 
still worth fixing.

@vgvassilev Please check if it works in your test cases.

Notice that this PR targets release/18.x, and not the main branch.

>From d3052932fa4e7e0fe24436b94bc76b2155c36c7f Mon Sep 17 00:00:00 2001
From: Giuliano Belinassi 
Date: Thu, 11 Apr 2024 20:09:49 -0300
Subject: [PATCH] Fix override keyword being print to the left side

Previously, the `override` keyword in C++ was being print in the left
side of a method decl, which is unsupported by C++ standard. This commit
fixes that by setting the `CanPrintOnLeft` field to 0, forcing it to be
print on the right side of the decl.

Signed-off-by: Giuliano Belinassi 
---
 clang/include/clang/Basic/Attr.td  |  2 ++
 clang/test/AST/ast-dump-override-final.cpp | 20 
 2 files changed, 22 insertions(+)
 create mode 100644 clang/test/AST/ast-dump-override-final.cpp

diff --git a/clang/include/clang/Basic/Attr.td 
b/clang/include/clang/Basic/Attr.td
index 58838b01b4fd7c..dbf2dd2120fb69 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -1590,6 +1590,7 @@ def RegCall : DeclOrTypeAttr {
 }
 
 def Final : InheritableAttr {
+  let CanPrintOnLeft = 0;
   let Spellings = [CustomKeyword<"final">, CustomKeyword<"sealed">];
   let Accessors = [Accessor<"isSpelledAsSealed", [CustomKeyword<"sealed">]>];
   let SemaHandler = 0;
@@ -2472,6 +2473,7 @@ def Overloadable : Attr {
 }
 
 def Override : InheritableAttr {
+  let CanPrintOnLeft = 0;
   let Spellings = [CustomKeyword<"override">];
   let SemaHandler = 0;
   // Omitted from docs, since this is language syntax, not an attribute, as far
diff --git a/clang/test/AST/ast-dump-override-final.cpp 
b/clang/test/AST/ast-dump-override-final.cpp
new file mode 100644
index 00..c1cee6b01565f6
--- /dev/null
+++ b/clang/test/AST/ast-dump-override-final.cpp
@@ -0,0 +1,20 @@
+// This file contain tests to check if override and final are dumped in the
+// correct positions.
+
+// RUN: %clang_cc1 -ast-print -x c++ %s -o - | FileCheck %s
+
+// CHECK: class A {
+class A {
+  // CHECK-NEXT: virtual void f();
+  virtual void f();
+
+  // CHECK-NEXT: virtual void g() final;
+  virtual void g() final;
+} AA;
+
+// CHECK: class B : public A {
+class B : public A {
+  // CHECK-NEXT: virtual void f() override {
+  virtual void f() override {
+  };
+} B;

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[llvm-branch-commits] [NFC]Extract the heuristic to find vtable for an indirect call into a helper function (PR #81024)

2024-04-11 Thread Mingming Liu via llvm-branch-commits 

https://github.com/minglotus-6 converted_to_draft 
https://github.com/llvm/llvm-project/pull/81024
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[llvm-branch-commits] [clang] [CIR][NFC] Add scaffolding for the CIR dialect and CIROps.td (PR #86080)

2024-04-11 Thread Nathan Lanza via llvm-branch-commits 


@@ -0,0 +1,16 @@
+# This replicates part of the add_mlir_dialect cmake function from MLIR that
+# cannot be used here. This happens because it expects to be run inside MLIR
+# directory which is not the case for CIR (and also FIR, both have similar
+# workarounds).
+
+# Equivalent to add_mlir_dialect(CIROps cir)
+set(LLVM_TARGET_DEFINITIONS CIROps.td)
+mlir_tablegen(CIROps.h.inc -gen-op-decls)
+mlir_tablegen(CIROps.cpp.inc -gen-op-defs)
+mlir_tablegen(CIROpsTypes.h.inc -gen-typedef-decls)
+mlir_tablegen(CIROpsTypes.cpp.inc -gen-typedef-defs)
+mlir_tablegen(CIROpsDialect.h.inc -gen-dialect-decls)
+mlir_tablegen(CIROpsDialect.cpp.inc -gen-dialect-defs)
+add_public_tablegen_target(MLIRCIROpsIncGen)
+add_dependencies(mlir-headers MLIRCIROpsIncGen)

lanza wrote:

> You're not generating the dialect doc?

These series of diffs are made by taking the tip of clangir and removing what 
we don't need to get a reviewable chunk of code up for a single diff. I guess 
while chunking this I just excluded it. It's in upstream clangir. (See 
https://github.com/llvm/clangir/blob/main/clang/include/clang/CIR/Dialect/IR/CMakeLists.txt#L17).
 

> Also: can these lines be abstracted by just calling the add_mlir_dialect 
> macro?

For reasons described at the top of the file that did not work. Perhaps that 
suggests a refactor of `add_mlir_dialect`, but don't intend to address that 
here. 

https://github.com/llvm/llvm-project/pull/86080
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[llvm-branch-commits] [clang] [CIR][NFC] Add scaffolding for the CIR dialect and CIROps.td (PR #86080)

2024-04-11 Thread Nathan Lanza via llvm-branch-commits 

https://github.com/lanza updated https://github.com/llvm/llvm-project/pull/86080

>From 435869501bb0788d8b22d847c3a870dbfbf94126 Mon Sep 17 00:00:00 2001
From: Nathan Lanza 
Date: Thu, 21 Mar 2024 04:57:16 +
Subject: [PATCH 1/2] fix MLIRCIROpsIncGen

Created using spr 1.3.5
---
 .../clang/CIR/Dialect/IR/CIRDialect.td| 46 +++
 clang/include/clang/CIR/Dialect/IR/CIROps.td  | 18 
 2 files changed, 64 insertions(+)
 create mode 100644 clang/include/clang/CIR/Dialect/IR/CIRDialect.td

diff --git a/clang/include/clang/CIR/Dialect/IR/CIRDialect.td 
b/clang/include/clang/CIR/Dialect/IR/CIRDialect.td
new file mode 100644
index 00..8f756fa422e5f3
--- /dev/null
+++ b/clang/include/clang/CIR/Dialect/IR/CIRDialect.td
@@ -0,0 +1,46 @@
+//===- CIRTypes.td - CIR dialect types -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file declares the CIR dialect.
+//
+//===--===//
+
+#ifndef MLIR_CIR_DIALECT_CIR
+#define MLIR_CIR_DIALECT_CIR
+
+include "mlir/IR/OpBase.td"
+
+def CIR_Dialect : Dialect {
+  let name = "cir";
+
+  // A short one-line summary of our dialect.
+  let summary = "A high-level dialect for analyzing and optimizing Clang "
+"supported languages";
+
+  let cppNamespace = "::mlir::cir";
+
+  let useDefaultAttributePrinterParser = 0;
+  let useDefaultTypePrinterParser = 0;
+
+  let extraClassDeclaration = [{
+void registerAttributes();
+void registerTypes();
+
+::mlir::Type parseType(::mlir::DialectAsmParser ) const override;
+void printType(::mlir::Type type,
+   ::mlir::DialectAsmPrinter ) const override;
+
+::mlir::Attribute parseAttribute(::mlir::DialectAsmParser ,
+ ::mlir::Type type) const override;
+
+void printAttribute(::mlir::Attribute attr,
+::mlir::DialectAsmPrinter ) const override;
+  }];
+}
+
+#endif // MLIR_CIR_DIALECT_CIR
diff --git a/clang/include/clang/CIR/Dialect/IR/CIROps.td 
b/clang/include/clang/CIR/Dialect/IR/CIROps.td
index e69de29bb2d1d6..cfc62986b0b9d1 100644
--- a/clang/include/clang/CIR/Dialect/IR/CIROps.td
+++ b/clang/include/clang/CIR/Dialect/IR/CIROps.td
@@ -0,0 +1,18 @@
+//===-- CIROps.td - CIR dialect definition -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+///
+/// \file
+/// Definition of the CIR dialect
+///
+//===--===//
+
+#ifndef MLIR_CIR_DIALECT_CIR_OPS
+#define MLIR_CIR_DIALECT_CIR_OPS
+
+include "clang/CIR/Dialect/IR/CIRDialect.td"
+#endif // MLIR_CIR_DIALECT_CIR_OPS

>From fe44284534be0752d95634251289a5c74c06afe7 Mon Sep 17 00:00:00 2001
From: Nathan Lanza 
Date: Thu, 21 Mar 2024 05:12:26 +
Subject: [PATCH 2/2] add some guts to CIRDialect.cpp and MLIRCIR lib

Created using spr 1.3.5
---
 clang/lib/CIR/Dialect/IR/CIRDialect.cpp | 11 +++
 clang/lib/CIR/Dialect/IR/CMakeLists.txt |  3 +++
 2 files changed, 14 insertions(+)

diff --git a/clang/lib/CIR/Dialect/IR/CIRDialect.cpp 
b/clang/lib/CIR/Dialect/IR/CIRDialect.cpp
index e69de29bb2d1d6..8abf39119e04f7 100644
--- a/clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+++ b/clang/lib/CIR/Dialect/IR/CIRDialect.cpp
@@ -0,0 +1,11 @@
+//===- CIRDialect.cpp - MLIR CIR ops implementation 
---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file implements the CIR dialect and its operations.
+//
+//===--===//
diff --git a/clang/lib/CIR/Dialect/IR/CMakeLists.txt 
b/clang/lib/CIR/Dialect/IR/CMakeLists.txt
index e69de29bb2d1d6..0d7476b555705d 100644
--- a/clang/lib/CIR/Dialect/IR/CMakeLists.txt
+++ b/clang/lib/CIR/Dialect/IR/CMakeLists.txt
@@ -0,0 +1,3 @@
+add_clang_library(MLIRCIR
+  CIRDialect.cpp
+  )

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[llvm-branch-commits] [clang] [CIR][NFC] Add scaffolding for the CIR dialect and CIROps.td (PR #86080)

2024-04-11 Thread Nathan Lanza via llvm-branch-commits 

https://github.com/lanza updated https://github.com/llvm/llvm-project/pull/86080

>From 435869501bb0788d8b22d847c3a870dbfbf94126 Mon Sep 17 00:00:00 2001
From: Nathan Lanza 
Date: Thu, 21 Mar 2024 04:57:16 +
Subject: [PATCH 1/2] fix MLIRCIROpsIncGen

Created using spr 1.3.5
---
 .../clang/CIR/Dialect/IR/CIRDialect.td| 46 +++
 clang/include/clang/CIR/Dialect/IR/CIROps.td  | 18 
 2 files changed, 64 insertions(+)
 create mode 100644 clang/include/clang/CIR/Dialect/IR/CIRDialect.td

diff --git a/clang/include/clang/CIR/Dialect/IR/CIRDialect.td 
b/clang/include/clang/CIR/Dialect/IR/CIRDialect.td
new file mode 100644
index 00..8f756fa422e5f3
--- /dev/null
+++ b/clang/include/clang/CIR/Dialect/IR/CIRDialect.td
@@ -0,0 +1,46 @@
+//===- CIRTypes.td - CIR dialect types -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file declares the CIR dialect.
+//
+//===--===//
+
+#ifndef MLIR_CIR_DIALECT_CIR
+#define MLIR_CIR_DIALECT_CIR
+
+include "mlir/IR/OpBase.td"
+
+def CIR_Dialect : Dialect {
+  let name = "cir";
+
+  // A short one-line summary of our dialect.
+  let summary = "A high-level dialect for analyzing and optimizing Clang "
+"supported languages";
+
+  let cppNamespace = "::mlir::cir";
+
+  let useDefaultAttributePrinterParser = 0;
+  let useDefaultTypePrinterParser = 0;
+
+  let extraClassDeclaration = [{
+void registerAttributes();
+void registerTypes();
+
+::mlir::Type parseType(::mlir::DialectAsmParser ) const override;
+void printType(::mlir::Type type,
+   ::mlir::DialectAsmPrinter ) const override;
+
+::mlir::Attribute parseAttribute(::mlir::DialectAsmParser ,
+ ::mlir::Type type) const override;
+
+void printAttribute(::mlir::Attribute attr,
+::mlir::DialectAsmPrinter ) const override;
+  }];
+}
+
+#endif // MLIR_CIR_DIALECT_CIR
diff --git a/clang/include/clang/CIR/Dialect/IR/CIROps.td 
b/clang/include/clang/CIR/Dialect/IR/CIROps.td
index e69de29bb2d1d6..cfc62986b0b9d1 100644
--- a/clang/include/clang/CIR/Dialect/IR/CIROps.td
+++ b/clang/include/clang/CIR/Dialect/IR/CIROps.td
@@ -0,0 +1,18 @@
+//===-- CIROps.td - CIR dialect definition -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+///
+/// \file
+/// Definition of the CIR dialect
+///
+//===--===//
+
+#ifndef MLIR_CIR_DIALECT_CIR_OPS
+#define MLIR_CIR_DIALECT_CIR_OPS
+
+include "clang/CIR/Dialect/IR/CIRDialect.td"
+#endif // MLIR_CIR_DIALECT_CIR_OPS

>From fe44284534be0752d95634251289a5c74c06afe7 Mon Sep 17 00:00:00 2001
From: Nathan Lanza 
Date: Thu, 21 Mar 2024 05:12:26 +
Subject: [PATCH 2/2] add some guts to CIRDialect.cpp and MLIRCIR lib

Created using spr 1.3.5
---
 clang/lib/CIR/Dialect/IR/CIRDialect.cpp | 11 +++
 clang/lib/CIR/Dialect/IR/CMakeLists.txt |  3 +++
 2 files changed, 14 insertions(+)

diff --git a/clang/lib/CIR/Dialect/IR/CIRDialect.cpp 
b/clang/lib/CIR/Dialect/IR/CIRDialect.cpp
index e69de29bb2d1d6..8abf39119e04f7 100644
--- a/clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+++ b/clang/lib/CIR/Dialect/IR/CIRDialect.cpp
@@ -0,0 +1,11 @@
+//===- CIRDialect.cpp - MLIR CIR ops implementation 
---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file implements the CIR dialect and its operations.
+//
+//===--===//
diff --git a/clang/lib/CIR/Dialect/IR/CMakeLists.txt 
b/clang/lib/CIR/Dialect/IR/CMakeLists.txt
index e69de29bb2d1d6..0d7476b555705d 100644
--- a/clang/lib/CIR/Dialect/IR/CMakeLists.txt
+++ b/clang/lib/CIR/Dialect/IR/CMakeLists.txt
@@ -0,0 +1,3 @@
+add_clang_library(MLIRCIR
+  CIRDialect.cpp
+  )

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[llvm-branch-commits] [clang] [CIR][NFC] Add scaffolding for the CIR dialect and CIROps.td (PR #86080)

2024-04-11 Thread Nathan Lanza via llvm-branch-commits 


@@ -0,0 +1,7 @@
+set(MLIR_MAIN_SRC_DIR ${LLVM_MAIN_SRC_DIR}/../mlir/include ) # --src-root
+set(MLIR_INCLUDE_DIR ${LLVM_MAIN_SRC_DIR}/../mlir/include ) # --includedir
+set(MLIR_TABLEGEN_OUTPUT_DIR ${CMAKE_BINARY_DIR}/tools/mlir/include)
+include_directories(SYSTEM ${MLIR_INCLUDE_DIR})
+include_directories(SYSTEM ${MLIR_TABLEGEN_OUTPUT_DIR})

lanza wrote:

`SYSTEM` wasn't necessary! Removing in update.

https://github.com/llvm/llvm-project/pull/86080
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[llvm-branch-commits] [mlir] Add dpas and named barrier ops (PR #88439)

2024-04-11 Thread via llvm-branch-commits 

llvmbot wrote:




@llvm/pr-subscribers-mlir

Author: Chao Chen (chencha3)


Changes

This PR adds definition of dpas op, atomic op, named barrier and related ops. 

---
Full diff: https://github.com/llvm/llvm-project/pull/88439.diff


8 Files Affected:

- (modified) mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt (+3-3) 
- (modified) mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h (+2-1) 
- (modified) mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td (+1) 
- (modified) mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td (+3-1) 
- (modified) mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td (+151-3) 
- (modified) mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td (+11) 
- (modified) mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp (+23) 
- (modified) mlir/test/Dialect/XeGPU/XeGPUOps.mlir (+56-1) 


``diff
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt 
b/mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt
index f1740e9ed929a6..3f8cac4dc07c3c 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt
@@ -2,12 +2,12 @@ add_mlir_dialect(XeGPU xegpu)
 add_mlir_doc(XeGPU XeGPU Dialects/ -gen-dialect-doc -dialect=xegpu)
 
 set(LLVM_TARGET_DEFINITIONS XeGPU.td)
-mlir_tablegen(XeGPUAttrs.h.inc -gen-attrdef-decls)
-mlir_tablegen(XeGPUAttrs.cpp.inc -gen-attrdef-defs)
+mlir_tablegen(XeGPUAttrs.h.inc -gen-attrdef-decls -attrdefs-dialect=xegpu)
+mlir_tablegen(XeGPUAttrs.cpp.inc -gen-attrdef-defs -attrdefs-dialect=xegpu)
 add_public_tablegen_target(MLIRXeGPUAttrsIncGen)
 add_dependencies(mlir-headers MLIRXeGPUAttrsIncGen)
 
-set(LLVM_TARGET_DEFINITIONS XeGPU.td)
+set(LLVM_TARGET_DEFINITIONS XeGPUAttrs.td)
 mlir_tablegen(XeGPUEnums.h.inc -gen-enum-decls)
 mlir_tablegen(XeGPUEnums.cpp.inc -gen-enum-defs)
 add_public_tablegen_target(MLIRXeGPUEnumsIncGen)
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h 
b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
index eca9255ff3974b..7ac0cf77fe59bb 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
@@ -10,6 +10,7 @@
 #define MLIR_DIALECT_XEGPU_IR_XEGPU_H
 
 #include "mlir/Bytecode/BytecodeOpInterface.h"
+#include "mlir/Dialect/Arith/IR/Arith.h"
 #include "mlir/IR/BuiltinTypes.h"
 #include "mlir/IR/Dialect.h"
 #include "mlir/IR/TypeUtilities.h"
@@ -19,7 +20,7 @@
 
 namespace mlir {
 namespace xegpu {
-// placeholder
+class TensorDescType;
 } // namespace xegpu
 } // namespace mlir
 
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td 
b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
index 6579d07ec26215..c14cba4990a738 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
@@ -10,6 +10,7 @@
 #define MLIR_DIALECT_XEGPU_IR_XEGPUATTRS_TD
 
 include "mlir/Dialect/XeGPU/IR/XeGPUDialect.td"
+include "mlir/IR/AttrTypeBase.td"
 include "mlir/IR/EnumAttr.td"
 
 class XeGPUAttr traits = [],
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td 
b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
index c2f09319c790e0..765f218f95d269 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
@@ -17,12 +17,14 @@ def XeGPU_Dialect : Dialect {
 let summary = "The XeGPU dialect that models Intel GPU's ISA";
 let description = [{
   The XeGPU dialect models Intel Xe ISA semantics but works at vector and
-  TensorDesc data type. It provides 1:1 mappings to match Xe instructions 
+  TensorDesc data type. It provides 1:1 mappings to match Xe instructions
   like DPAS and 2D block load. The matrix size being processed at this 
level
   exactly matches the hardware instructions or the intrinsic supported by
   the lower-level GPU compiler.
 }];
 
+let dependentDialects = ["arith::ArithDialect"];
+
 let useDefaultTypePrinterParser = true;
 let useDefaultAttributePrinterParser = true;
 }
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td 
b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
index a031a75984a536..3423609b76c706 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
@@ -9,7 +9,7 @@
 #ifndef MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD
 #define MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD
 
-include "mlir/IR/AttrTypeBase.td"
+include "mlir/Dialect/Arith/IR/ArithBase.td"
 include "mlir/Dialect/XeGPU/IR/XeGPUAttrs.td"
 include "mlir/Dialect/XeGPU/IR/XeGPUDialect.td"
 include "mlir/Dialect/XeGPU/IR/XeGPUTypes.td"
@@ -35,7 +35,7 @@ class XeGPU_Op traits = []>:
 
 static ::mlir::ParseResult parseProperties(::mlir::OpAsmParser ,
  ::mlir::OperationState ) {
-  if (mlir::succeeded(parser.parseLess())) {
+  if (mlir::succeeded(parser.parseOptionalLess())) {
 if (parser.parseAttribute(result.propertiesAttr) || 
parser.parseGreater())
   return failure();
   }
@@ -253,7 +253,7 @@ def

[llvm-branch-commits] [mlir] Add dpas and named barrier ops (PR #88439)

2024-04-11 Thread via llvm-branch-commits 

llvmbot wrote:




@llvm/pr-subscribers-mlir-gpu

Author: Chao Chen (chencha3)


Changes

This PR adds definition of dpas op, atomic op, named barrier and related ops. 

---
Full diff: https://github.com/llvm/llvm-project/pull/88439.diff


8 Files Affected:

- (modified) mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt (+3-3) 
- (modified) mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h (+2-1) 
- (modified) mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td (+1) 
- (modified) mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td (+3-1) 
- (modified) mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td (+151-3) 
- (modified) mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td (+11) 
- (modified) mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp (+23) 
- (modified) mlir/test/Dialect/XeGPU/XeGPUOps.mlir (+56-1) 


``diff
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt 
b/mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt
index f1740e9ed929a6..3f8cac4dc07c3c 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt
@@ -2,12 +2,12 @@ add_mlir_dialect(XeGPU xegpu)
 add_mlir_doc(XeGPU XeGPU Dialects/ -gen-dialect-doc -dialect=xegpu)
 
 set(LLVM_TARGET_DEFINITIONS XeGPU.td)
-mlir_tablegen(XeGPUAttrs.h.inc -gen-attrdef-decls)
-mlir_tablegen(XeGPUAttrs.cpp.inc -gen-attrdef-defs)
+mlir_tablegen(XeGPUAttrs.h.inc -gen-attrdef-decls -attrdefs-dialect=xegpu)
+mlir_tablegen(XeGPUAttrs.cpp.inc -gen-attrdef-defs -attrdefs-dialect=xegpu)
 add_public_tablegen_target(MLIRXeGPUAttrsIncGen)
 add_dependencies(mlir-headers MLIRXeGPUAttrsIncGen)
 
-set(LLVM_TARGET_DEFINITIONS XeGPU.td)
+set(LLVM_TARGET_DEFINITIONS XeGPUAttrs.td)
 mlir_tablegen(XeGPUEnums.h.inc -gen-enum-decls)
 mlir_tablegen(XeGPUEnums.cpp.inc -gen-enum-defs)
 add_public_tablegen_target(MLIRXeGPUEnumsIncGen)
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h 
b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
index eca9255ff3974b..7ac0cf77fe59bb 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
@@ -10,6 +10,7 @@
 #define MLIR_DIALECT_XEGPU_IR_XEGPU_H
 
 #include "mlir/Bytecode/BytecodeOpInterface.h"
+#include "mlir/Dialect/Arith/IR/Arith.h"
 #include "mlir/IR/BuiltinTypes.h"
 #include "mlir/IR/Dialect.h"
 #include "mlir/IR/TypeUtilities.h"
@@ -19,7 +20,7 @@
 
 namespace mlir {
 namespace xegpu {
-// placeholder
+class TensorDescType;
 } // namespace xegpu
 } // namespace mlir
 
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td 
b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
index 6579d07ec26215..c14cba4990a738 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
@@ -10,6 +10,7 @@
 #define MLIR_DIALECT_XEGPU_IR_XEGPUATTRS_TD
 
 include "mlir/Dialect/XeGPU/IR/XeGPUDialect.td"
+include "mlir/IR/AttrTypeBase.td"
 include "mlir/IR/EnumAttr.td"
 
 class XeGPUAttr traits = [],
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td 
b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
index c2f09319c790e0..765f218f95d269 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
@@ -17,12 +17,14 @@ def XeGPU_Dialect : Dialect {
 let summary = "The XeGPU dialect that models Intel GPU's ISA";
 let description = [{
   The XeGPU dialect models Intel Xe ISA semantics but works at vector and
-  TensorDesc data type. It provides 1:1 mappings to match Xe instructions 
+  TensorDesc data type. It provides 1:1 mappings to match Xe instructions
   like DPAS and 2D block load. The matrix size being processed at this 
level
   exactly matches the hardware instructions or the intrinsic supported by
   the lower-level GPU compiler.
 }];
 
+let dependentDialects = ["arith::ArithDialect"];
+
 let useDefaultTypePrinterParser = true;
 let useDefaultAttributePrinterParser = true;
 }
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td 
b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
index a031a75984a536..3423609b76c706 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
@@ -9,7 +9,7 @@
 #ifndef MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD
 #define MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD
 
-include "mlir/IR/AttrTypeBase.td"
+include "mlir/Dialect/Arith/IR/ArithBase.td"
 include "mlir/Dialect/XeGPU/IR/XeGPUAttrs.td"
 include "mlir/Dialect/XeGPU/IR/XeGPUDialect.td"
 include "mlir/Dialect/XeGPU/IR/XeGPUTypes.td"
@@ -35,7 +35,7 @@ class XeGPU_Op traits = []>:
 
 static ::mlir::ParseResult parseProperties(::mlir::OpAsmParser ,
  ::mlir::OperationState ) {
-  if (mlir::succeeded(parser.parseLess())) {
+  if (mlir::succeeded(parser.parseOptionalLess())) {
 if (parser.parseAttribute(result.propertiesAttr) || 
parser.parseGreater())
   return failure();
   }
@@ -253,7 +253,7 @@ def

[llvm-branch-commits] [mlir] Add dpas and named barrier ops (PR #88439)

2024-04-11 Thread Chao Chen via llvm-branch-commits 

https://github.com/chencha3 created 
https://github.com/llvm/llvm-project/pull/88439

This PR adds definition of dpas op, atomic op, named barrier and related ops. 

>From 6021411059863c9a2bfdfc91e35628328e709a8c Mon Sep 17 00:00:00 2001
From: Chao Chen 
Date: Thu, 11 Apr 2024 15:46:26 -0500
Subject: [PATCH] Add dpas and named barrier ops

---
 .../mlir/Dialect/XeGPU/IR/CMakeLists.txt  |   6 +-
 mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h|   3 +-
 .../mlir/Dialect/XeGPU/IR/XeGPUAttrs.td   |   1 +
 .../mlir/Dialect/XeGPU/IR/XeGPUDialect.td |   4 +-
 .../include/mlir/Dialect/XeGPU/IR/XeGPUOps.td | 154 +-
 .../mlir/Dialect/XeGPU/IR/XeGPUTypes.td   |  11 ++
 mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp|  23 +++
 mlir/test/Dialect/XeGPU/XeGPUOps.mlir |  57 ++-
 8 files changed, 250 insertions(+), 9 deletions(-)

diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt 
b/mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt
index f1740e9ed929a6..3f8cac4dc07c3c 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt
@@ -2,12 +2,12 @@ add_mlir_dialect(XeGPU xegpu)
 add_mlir_doc(XeGPU XeGPU Dialects/ -gen-dialect-doc -dialect=xegpu)
 
 set(LLVM_TARGET_DEFINITIONS XeGPU.td)
-mlir_tablegen(XeGPUAttrs.h.inc -gen-attrdef-decls)
-mlir_tablegen(XeGPUAttrs.cpp.inc -gen-attrdef-defs)
+mlir_tablegen(XeGPUAttrs.h.inc -gen-attrdef-decls -attrdefs-dialect=xegpu)
+mlir_tablegen(XeGPUAttrs.cpp.inc -gen-attrdef-defs -attrdefs-dialect=xegpu)
 add_public_tablegen_target(MLIRXeGPUAttrsIncGen)
 add_dependencies(mlir-headers MLIRXeGPUAttrsIncGen)
 
-set(LLVM_TARGET_DEFINITIONS XeGPU.td)
+set(LLVM_TARGET_DEFINITIONS XeGPUAttrs.td)
 mlir_tablegen(XeGPUEnums.h.inc -gen-enum-decls)
 mlir_tablegen(XeGPUEnums.cpp.inc -gen-enum-defs)
 add_public_tablegen_target(MLIRXeGPUEnumsIncGen)
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h 
b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
index eca9255ff3974b..7ac0cf77fe59bb 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
@@ -10,6 +10,7 @@
 #define MLIR_DIALECT_XEGPU_IR_XEGPU_H
 
 #include "mlir/Bytecode/BytecodeOpInterface.h"
+#include "mlir/Dialect/Arith/IR/Arith.h"
 #include "mlir/IR/BuiltinTypes.h"
 #include "mlir/IR/Dialect.h"
 #include "mlir/IR/TypeUtilities.h"
@@ -19,7 +20,7 @@
 
 namespace mlir {
 namespace xegpu {
-// placeholder
+class TensorDescType;
 } // namespace xegpu
 } // namespace mlir
 
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td 
b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
index 6579d07ec26215..c14cba4990a738 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
@@ -10,6 +10,7 @@
 #define MLIR_DIALECT_XEGPU_IR_XEGPUATTRS_TD
 
 include "mlir/Dialect/XeGPU/IR/XeGPUDialect.td"
+include "mlir/IR/AttrTypeBase.td"
 include "mlir/IR/EnumAttr.td"
 
 class XeGPUAttr traits = [],
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td 
b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
index c2f09319c790e0..765f218f95d269 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
@@ -17,12 +17,14 @@ def XeGPU_Dialect : Dialect {
 let summary = "The XeGPU dialect that models Intel GPU's ISA";
 let description = [{
   The XeGPU dialect models Intel Xe ISA semantics but works at vector and
-  TensorDesc data type. It provides 1:1 mappings to match Xe instructions 
+  TensorDesc data type. It provides 1:1 mappings to match Xe instructions
   like DPAS and 2D block load. The matrix size being processed at this 
level
   exactly matches the hardware instructions or the intrinsic supported by
   the lower-level GPU compiler.
 }];
 
+let dependentDialects = ["arith::ArithDialect"];
+
 let useDefaultTypePrinterParser = true;
 let useDefaultAttributePrinterParser = true;
 }
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td 
b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
index a031a75984a536..3423609b76c706 100644
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
@@ -9,7 +9,7 @@
 #ifndef MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD
 #define MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD
 
-include "mlir/IR/AttrTypeBase.td"
+include "mlir/Dialect/Arith/IR/ArithBase.td"
 include "mlir/Dialect/XeGPU/IR/XeGPUAttrs.td"
 include "mlir/Dialect/XeGPU/IR/XeGPUDialect.td"
 include "mlir/Dialect/XeGPU/IR/XeGPUTypes.td"
@@ -35,7 +35,7 @@ class XeGPU_Op traits = []>:
 
 static ::mlir::ParseResult parseProperties(::mlir::OpAsmParser ,
  ::mlir::OperationState ) {
-  if (mlir::succeeded(parser.parseLess())) {
+  if (mlir::succeeded(parser.parseOptionalLess())) {
 if (parser.parseAttribute(result.propertiesAttr) || 
parser.parseGreater())

[llvm-branch-commits] [clang] [CIR][cmake] Add support for cmake variable CLANG_ENABLE_CIR (PR #86078)

2024-04-11 Thread Nathan Lanza via llvm-branch-commits 

https://github.com/lanza updated https://github.com/llvm/llvm-project/pull/86078

>From 0118187ba99172c6d892e4a05596085c0e637eb9 Mon Sep 17 00:00:00 2001
From: Nathan Lanza 
Date: Thu, 21 Mar 2024 04:09:56 +
Subject: [PATCH] add lit usage

Created using spr 1.3.5
---
 clang/test/lit.site.cfg.py.in | 1 +
 1 file changed, 1 insertion(+)

diff --git a/clang/test/lit.site.cfg.py.in b/clang/test/lit.site.cfg.py.in
index ef75770a2c3c9a..6641811c588395 100644
--- a/clang/test/lit.site.cfg.py.in
+++ b/clang/test/lit.site.cfg.py.in
@@ -27,6 +27,7 @@ config.clang_default_pie_on_linux = 
@CLANG_DEFAULT_PIE_ON_LINUX@
 config.clang_default_cxx_stdlib = "@CLANG_DEFAULT_CXX_STDLIB@"
 config.clang_staticanalyzer = @CLANG_ENABLE_STATIC_ANALYZER@
 config.clang_staticanalyzer_z3 = @LLVM_WITH_Z3@
+config.clang_enable_cir = @CLANG_ENABLE_CIR@
 config.clang_examples = @CLANG_BUILD_EXAMPLES@
 config.enable_shared = @ENABLE_SHARED@
 config.enable_backtrace = @ENABLE_BACKTRACES@

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[llvm-branch-commits] [clang] [CIR][cmake] Add support for cmake variable CLANG_ENABLE_CIR (PR #86078)

2024-04-11 Thread Nathan Lanza via llvm-branch-commits 

https://github.com/lanza updated https://github.com/llvm/llvm-project/pull/86078

>From 0118187ba99172c6d892e4a05596085c0e637eb9 Mon Sep 17 00:00:00 2001
From: Nathan Lanza 
Date: Thu, 21 Mar 2024 04:09:56 +
Subject: [PATCH] add lit usage

Created using spr 1.3.5
---
 clang/test/lit.site.cfg.py.in | 1 +
 1 file changed, 1 insertion(+)

diff --git a/clang/test/lit.site.cfg.py.in b/clang/test/lit.site.cfg.py.in
index ef75770a2c3c9a..6641811c588395 100644
--- a/clang/test/lit.site.cfg.py.in
+++ b/clang/test/lit.site.cfg.py.in
@@ -27,6 +27,7 @@ config.clang_default_pie_on_linux = 
@CLANG_DEFAULT_PIE_ON_LINUX@
 config.clang_default_cxx_stdlib = "@CLANG_DEFAULT_CXX_STDLIB@"
 config.clang_staticanalyzer = @CLANG_ENABLE_STATIC_ANALYZER@
 config.clang_staticanalyzer_z3 = @LLVM_WITH_Z3@
+config.clang_enable_cir = @CLANG_ENABLE_CIR@
 config.clang_examples = @CLANG_BUILD_EXAMPLES@
 config.enable_shared = @ENABLE_SHARED@
 config.enable_backtrace = @ENABLE_BACKTRACES@

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[llvm-branch-commits] [lldb] 79a4eb5 - Revert "[lldb][lit] Add MallocNanoZone envvar to Darwin ASan builds (#88431)"

2024-04-11 Thread via llvm-branch-commits 

Author: Chelsea Cassanova
Date: 2024-04-11T13:41:48-07:00
New Revision: 79a4eb5047d8c90568b04ad5fb90e6421e1aba69

URL: 
https://github.com/llvm/llvm-project/commit/79a4eb5047d8c90568b04ad5fb90e6421e1aba69
DIFF: 
https://github.com/llvm/llvm-project/commit/79a4eb5047d8c90568b04ad5fb90e6421e1aba69.diff

LOG: Revert "[lldb][lit] Add MallocNanoZone envvar to Darwin ASan builds 
(#88431)"

This reverts commit 4df854e1a98ed47c955838d2c94bf2913c50041f.

Added: 


Modified: 
lldb/test/API/lit.cfg.py
lldb/test/Shell/lit.cfg.py

Removed: 




diff  --git a/lldb/test/API/lit.cfg.py b/lldb/test/API/lit.cfg.py
index 9ea389c639a013..f9497b632fc504 100644
--- a/lldb/test/API/lit.cfg.py
+++ b/lldb/test/API/lit.cfg.py
@@ -121,7 +121,6 @@ def delete_module_cache(path):
 config.environment["DYLD_INSERT_LIBRARIES"] = 
find_sanitizer_runtime(
 "libclang_rt.asan_osx_dynamic.dylib"
 )
-config.environment["MallocNanoZone"] = "0"
 
 if "Thread" in config.llvm_use_sanitizer:
 config.environment["TSAN_OPTIONS"] = "halt_on_error=1"

diff  --git a/lldb/test/Shell/lit.cfg.py b/lldb/test/Shell/lit.cfg.py
index 345627835d2bf2..31afe5151c0661 100644
--- a/lldb/test/Shell/lit.cfg.py
+++ b/lldb/test/Shell/lit.cfg.py
@@ -52,8 +52,6 @@
 # Enable sanitizer runtime flags.
 config.environment["ASAN_OPTIONS"] = "detect_stack_use_after_return=1"
 config.environment["TSAN_OPTIONS"] = "halt_on_error=1"
-if "Darwin" in config.host_os:
-config.environment["MallocNanoZone"] = "0"
 
 # Support running the test suite under the lldb-repro wrapper. This makes it
 # possible to capture a test suite run and then rerun all the test from the



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[llvm-branch-commits] [libcxx] release/18.x: [libc++] Fix -Wgnu-include-next in stddef.h (#88214) (PR #88419)

2024-04-11 Thread Louis Dionne via llvm-branch-commits 

https://github.com/ldionne approved this pull request.


https://github.com/llvm/llvm-project/pull/88419
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[llvm-branch-commits] [llvm] release/18.x: github-upload-release.py: Fix bug preventing release creation (#84571) (PR #88425)

2024-04-11 Thread via llvm-branch-commits 

llvmbot wrote:

@boomanaiden154 What do you think about merging this PR to the release branch?

https://github.com/llvm/llvm-project/pull/88425
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[llvm-branch-commits] [llvm] release/18.x: github-upload-release.py: Fix bug preventing release creation (#84571) (PR #88425)

2024-04-11 Thread via llvm-branch-commits 

https://github.com/llvmbot milestoned 
https://github.com/llvm/llvm-project/pull/88425
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[llvm-branch-commits] [llvm] release/18.x: github-upload-release.py: Fix bug preventing release creation (#84571) (PR #88425)

2024-04-11 Thread via llvm-branch-commits 

https://github.com/llvmbot created 
https://github.com/llvm/llvm-project/pull/88425

Backport 0b9ce71a256d86c08f2b52ad2e337395b8f54b41

Requested by: @tstellar

>From 51a29dc68dadfaae2169bece88465d22e94203ca Mon Sep 17 00:00:00 2001
From: Tom Stellard 
Date: Fri, 8 Mar 2024 21:17:27 -0800
Subject: [PATCH] github-upload-release.py: Fix bug preventing release creation
 (#84571)

After aa02002491333c42060373bc84f1ff5d2c76b4ce we started passing the
user name to the create_release function and this was being interpreted
as the git tag.

(cherry picked from commit 0b9ce71a256d86c08f2b52ad2e337395b8f54b41)
---
 llvm/utils/release/github-upload-release.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/utils/release/github-upload-release.py 
b/llvm/utils/release/github-upload-release.py
index 14ec05062d88c8..8343dee937f78f 100755
--- a/llvm/utils/release/github-upload-release.py
+++ b/llvm/utils/release/github-upload-release.py
@@ -107,6 +107,6 @@ def upload_files(repo, release, files):
 sys.exit(1)
 
 if args.command == "create":
-create_release(llvm_repo, args.release, args.user)
+create_release(llvm_repo, args.release)
 if args.command == "upload":
 upload_files(llvm_repo, args.release, args.files)

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[llvm-branch-commits] [libcxx] release/18.x: [libc++] Fix -Wgnu-include-next in stddef.h (#88214) (PR #88421)

2024-04-11 Thread Ian Anderson via llvm-branch-commits 

https://github.com/ian-twilightcoder closed 
https://github.com/llvm/llvm-project/pull/88421
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[llvm-branch-commits] [libcxx] release/18.x: [libc++] Fix -Wgnu-include-next in stddef.h (#88214) (PR #88421)

2024-04-11 Thread Ian Anderson via llvm-branch-commits 

ian-twilightcoder wrote:

Already covered by https://github.com/llvm/llvm-project/pull/88419

https://github.com/llvm/llvm-project/pull/88421
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[llvm-branch-commits] [llvm] [BOLT][BAT] Fix handling of split functions (PR #87569)

2024-04-11 Thread Maksim Panchenko via llvm-branch-commits 

https://github.com/maksfb approved this pull request.


https://github.com/llvm/llvm-project/pull/87569
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[llvm-branch-commits] [llvm] [BOLT] Cover all call sites in writeBATYAML (PR #87743)

2024-04-11 Thread Maksim Panchenko via llvm-branch-commits 

https://github.com/maksfb approved this pull request.


https://github.com/llvm/llvm-project/pull/87743
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[llvm-branch-commits] [libcxx] release/18.x: [libc++] Fix -Wgnu-include-next in stddef.h (#88214) (PR #88421)

2024-04-11 Thread via llvm-branch-commits 

llvmbot wrote:




@llvm/pr-subscribers-libcxx

Author: None (llvmbot)


Changes

Backport 3c4b673af05f53e8a4d1a382b5c86367ea512c9e

Requested by: @ian-twilightcoder

---
Full diff: https://github.com/llvm/llvm-project/pull/88421.diff


1 Files Affected:

- (modified) libcxx/include/stddef.h (+4-4) 


``diff
diff --git a/libcxx/include/stddef.h b/libcxx/include/stddef.h
index 470b5408336c6d..1583e78e3739ba 100644
--- a/libcxx/include/stddef.h
+++ b/libcxx/include/stddef.h
@@ -26,6 +26,10 @@
 
 #include <__config>
 
+#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
+#  pragma GCC system_header
+#endif
+
 // Note: This include is outside of header guards because we sometimes get 
included multiple times
 //   with different defines and the underlying  will know how to 
deal with that.
 #include_next 
@@ -33,10 +37,6 @@
 #ifndef _LIBCPP_STDDEF_H
 #  define _LIBCPP_STDDEF_H
 
-#  if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
-#pragma GCC system_header
-#  endif
-
 #  ifdef __cplusplus
 typedef decltype(nullptr) nullptr_t;
 #  endif

``




https://github.com/llvm/llvm-project/pull/88421
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[llvm-branch-commits] [libcxx] release/18.x: [libc++] Fix -Wgnu-include-next in stddef.h (#88214) (PR #88421)

2024-04-11 Thread via llvm-branch-commits 

https://github.com/llvmbot created 
https://github.com/llvm/llvm-project/pull/88421

Backport 3c4b673af05f53e8a4d1a382b5c86367ea512c9e

Requested by: @ian-twilightcoder

>From bfa3ddfbdb19d4b4305faf4c9b44568121bc3317 Mon Sep 17 00:00:00 2001
From: Louis Dionne 
Date: Thu, 11 Apr 2024 12:36:56 -0400
Subject: [PATCH] [libc++] Fix -Wgnu-include-next in stddef.h (#88214)

As reported in #86843, we must have #pragma GCC system_header before we
use #include_next, otherwise the compiler may not understand that we're
in a system header and may issue a diagnostic for our usage of

(cherry picked from commit 3c4b673af05f53e8a4d1a382b5c86367ea512c9e)
---
 libcxx/include/stddef.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/libcxx/include/stddef.h b/libcxx/include/stddef.h
index 470b5408336c6d..1583e78e3739ba 100644
--- a/libcxx/include/stddef.h
+++ b/libcxx/include/stddef.h
@@ -26,6 +26,10 @@
 
 #include <__config>
 
+#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
+#  pragma GCC system_header
+#endif
+
 // Note: This include is outside of header guards because we sometimes get 
included multiple times
 //   with different defines and the underlying  will know how to 
deal with that.
 #include_next 
@@ -33,10 +37,6 @@
 #ifndef _LIBCPP_STDDEF_H
 #  define _LIBCPP_STDDEF_H
 
-#  if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
-#pragma GCC system_header
-#  endif
-
 #  ifdef __cplusplus
 typedef decltype(nullptr) nullptr_t;
 #  endif

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[llvm-branch-commits] [libcxx] release/18.x: [libc++] Fix -Wgnu-include-next in stddef.h (#88214) (PR #88421)

2024-04-11 Thread via llvm-branch-commits 

https://github.com/llvmbot milestoned 
https://github.com/llvm/llvm-project/pull/88421
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[llvm-branch-commits] [libcxx] release/18.x: [libc++] Fix -Wgnu-include-next in stddef.h (#88214) (PR #88419)

2024-04-11 Thread Ian Anderson via llvm-branch-commits 

ian-twilightcoder wrote:

We should take this in LLVM 18 because it's a regression from 
https://github.com/llvm/llvm-project/pull/87374

https://github.com/llvm/llvm-project/pull/88419
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[llvm-branch-commits] [libcxx] release/18.x: [libc++] Fix -Wgnu-include-next in stddef.h (#88214) (PR #88419)

2024-04-11 Thread Ian Anderson via llvm-branch-commits 

https://github.com/ian-twilightcoder approved this pull request.


https://github.com/llvm/llvm-project/pull/88419
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[llvm-branch-commits] [libcxx] release/18.x: [libc++] Fix -Wgnu-include-next in stddef.h (#88214) (PR #88419)

2024-04-11 Thread via llvm-branch-commits 

llvmbot wrote:




@llvm/pr-subscribers-libcxx

Author: None (llvmbot)


Changes

Backport 3c4b673af05f53e8a4d1a382b5c86367ea512c9e

Requested by: @ldionne

---
Full diff: https://github.com/llvm/llvm-project/pull/88419.diff


1 Files Affected:

- (modified) libcxx/include/stddef.h (+4-4) 


``diff
diff --git a/libcxx/include/stddef.h b/libcxx/include/stddef.h
index 470b5408336c6d..1583e78e3739ba 100644
--- a/libcxx/include/stddef.h
+++ b/libcxx/include/stddef.h
@@ -26,6 +26,10 @@
 
 #include <__config>
 
+#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
+#  pragma GCC system_header
+#endif
+
 // Note: This include is outside of header guards because we sometimes get 
included multiple times
 //   with different defines and the underlying  will know how to 
deal with that.
 #include_next 
@@ -33,10 +37,6 @@
 #ifndef _LIBCPP_STDDEF_H
 #  define _LIBCPP_STDDEF_H
 
-#  if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
-#pragma GCC system_header
-#  endif
-
 #  ifdef __cplusplus
 typedef decltype(nullptr) nullptr_t;
 #  endif

``




https://github.com/llvm/llvm-project/pull/88419
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[llvm-branch-commits] [libcxx] release/18.x: [libc++] Fix -Wgnu-include-next in stddef.h (#88214) (PR #88419)

2024-04-11 Thread via llvm-branch-commits 

llvmbot wrote:

@mordante What do you think about merging this PR to the release branch?

https://github.com/llvm/llvm-project/pull/88419
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[llvm-branch-commits] [libcxx] release/18.x: [libc++] Fix -Wgnu-include-next in stddef.h (#88214) (PR #88419)

2024-04-11 Thread via llvm-branch-commits 

https://github.com/llvmbot milestoned 
https://github.com/llvm/llvm-project/pull/88419
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[llvm-branch-commits] [libcxx] release/18.x: [libc++] Fix -Wgnu-include-next in stddef.h (#88214) (PR #88419)

2024-04-11 Thread via llvm-branch-commits 

https://github.com/llvmbot created 
https://github.com/llvm/llvm-project/pull/88419

Backport 3c4b673af05f53e8a4d1a382b5c86367ea512c9e

Requested by: @ldionne

>From 27a78c496678eb73677981b4b6b0d380dd7e28bb Mon Sep 17 00:00:00 2001
From: Louis Dionne 
Date: Thu, 11 Apr 2024 12:36:56 -0400
Subject: [PATCH] [libc++] Fix -Wgnu-include-next in stddef.h (#88214)

As reported in #86843, we must have #pragma GCC system_header before we
use #include_next, otherwise the compiler may not understand that we're
in a system header and may issue a diagnostic for our usage of

(cherry picked from commit 3c4b673af05f53e8a4d1a382b5c86367ea512c9e)
---
 libcxx/include/stddef.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/libcxx/include/stddef.h b/libcxx/include/stddef.h
index 470b5408336c6d..1583e78e3739ba 100644
--- a/libcxx/include/stddef.h
+++ b/libcxx/include/stddef.h
@@ -26,6 +26,10 @@
 
 #include <__config>
 
+#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
+#  pragma GCC system_header
+#endif
+
 // Note: This include is outside of header guards because we sometimes get 
included multiple times
 //   with different defines and the underlying  will know how to 
deal with that.
 #include_next 
@@ -33,10 +37,6 @@
 #ifndef _LIBCPP_STDDEF_H
 #  define _LIBCPP_STDDEF_H
 
-#  if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
-#pragma GCC system_header
-#  endif
-
 #  ifdef __cplusplus
 typedef decltype(nullptr) nullptr_t;
 #  endif

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[llvm-branch-commits] [libcxx] release/18.x: [libc++] Simplify the implementation of (#86843) (PR #87374)

2024-04-11 Thread Louis Dionne via llvm-branch-commits 

ldionne wrote:

> As mentioned on #86843, this breaks using `-pedantic` in code that includes 
> libc++ headers. Since this got cherry-picked, we also must cherry-pick #88214.

I just started that process here: 
https://github.com/llvm/llvm-project/pull/88214#issuecomment-2050203419

https://github.com/llvm/llvm-project/pull/87374
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[llvm-branch-commits] [clang] [compiler-rt] [flang] [libc] [libcxx] [llvm] [mlir] [NFC][IndirectCallProm] Refactor function-based conditional devirtualization and indirect call value profile update in

2024-04-11 Thread Mingming Liu via llvm-branch-commits 

https://github.com/minglotus-6 updated 
https://github.com/llvm/llvm-project/pull/80762

error: too big or took too long to generate
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[llvm-branch-commits] [llvm] Backport: Prepend all library intrinsics with `#` when building for Arm64EC (PR #88016)

2024-04-11 Thread Daniel Paoliello via llvm-branch-commits 

https://github.com/dpaoliello updated 
https://github.com/llvm/llvm-project/pull/88016

>From 83514c75b37e1e02b7f7aca0225072d1068eaffb Mon Sep 17 00:00:00 2001
From: Daniel Paoliello 
Date: Fri, 5 Apr 2024 12:06:47 -0700
Subject: [PATCH] Prepend all library intrinsics with `#` when building for
 Arm64EC (#87542)

While attempting to build some Rust code, I was getting linker errors
due to missing functions that are implemented in `compiler-rt`. Turns
out that when `compiler-rt` is built for Arm64EC, all its function names
are mangled with the leading `#`.

This change removes the hard-coded list of library-implemented
intrinsics to mangle for Arm64EC, and instead assumes that they all must
be mangled.
---
 .../Target/AArch64/AArch64ISelLowering.cpp| 42 ---
 llvm/lib/Target/AArch64/AArch64ISelLowering.h |  3 ++
 2 files changed, 11 insertions(+), 34 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 196aa50cf4060b..95d8ab95b2c097 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1658,40 +1658,14 @@ AArch64TargetLowering::AArch64TargetLowering(const 
TargetMachine ,
   setMaxAtomicSizeInBitsSupported(128);
 
   if (Subtarget->isWindowsArm64EC()) {
-// FIXME: are there other intrinsics we need to add here?
-setLibcallName(RTLIB::MEMCPY, "#memcpy");
-setLibcallName(RTLIB::MEMSET, "#memset");
-setLibcallName(RTLIB::MEMMOVE, "#memmove");
-setLibcallName(RTLIB::REM_F32, "#fmodf");
-setLibcallName(RTLIB::REM_F64, "#fmod");
-setLibcallName(RTLIB::FMA_F32, "#fmaf");
-setLibcallName(RTLIB::FMA_F64, "#fma");
-setLibcallName(RTLIB::SQRT_F32, "#sqrtf");
-setLibcallName(RTLIB::SQRT_F64, "#sqrt");
-setLibcallName(RTLIB::CBRT_F32, "#cbrtf");
-setLibcallName(RTLIB::CBRT_F64, "#cbrt");
-setLibcallName(RTLIB::LOG_F32, "#logf");
-setLibcallName(RTLIB::LOG_F64, "#log");
-setLibcallName(RTLIB::LOG2_F32, "#log2f");
-setLibcallName(RTLIB::LOG2_F64, "#log2");
-setLibcallName(RTLIB::LOG10_F32, "#log10f");
-setLibcallName(RTLIB::LOG10_F64, "#log10");
-setLibcallName(RTLIB::EXP_F32, "#expf");
-setLibcallName(RTLIB::EXP_F64, "#exp");
-setLibcallName(RTLIB::EXP2_F32, "#exp2f");
-setLibcallName(RTLIB::EXP2_F64, "#exp2");
-setLibcallName(RTLIB::EXP10_F32, "#exp10f");
-setLibcallName(RTLIB::EXP10_F64, "#exp10");
-setLibcallName(RTLIB::SIN_F32, "#sinf");
-setLibcallName(RTLIB::SIN_F64, "#sin");
-setLibcallName(RTLIB::COS_F32, "#cosf");
-setLibcallName(RTLIB::COS_F64, "#cos");
-setLibcallName(RTLIB::POW_F32, "#powf");
-setLibcallName(RTLIB::POW_F64, "#pow");
-setLibcallName(RTLIB::LDEXP_F32, "#ldexpf");
-setLibcallName(RTLIB::LDEXP_F64, "#ldexp");
-setLibcallName(RTLIB::FREXP_F32, "#frexpf");
-setLibcallName(RTLIB::FREXP_F64, "#frexp");
+// FIXME: are there intrinsics we need to exclude from this?
+for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
+  auto code = static_cast(i);
+  auto libcallName = getLibcallName(code);
+  if ((libcallName != nullptr) && (libcallName[0] != '#')) {
+setLibcallName(code, Saver.save(Twine("#") + libcallName).data());
+  }
+}
   }
 }
 
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 541a810fb5cba0..74d0c4bde8dd2e 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1001,6 +1001,9 @@ class AArch64TargetLowering : public TargetLowering {
   /// make the right decision when generating code for different targets.
   const AArch64Subtarget *Subtarget;
 
+  llvm::BumpPtrAllocator BumpAlloc;
+  llvm::StringSaver Saver{BumpAlloc};
+
   bool isExtFreeImpl(const Instruction *Ext) const override;
 
   void addTypeForNEON(MVT VT);

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[llvm-branch-commits] [llvm] [NFC][IndirectCallProm] Refactor function-based conditional devirtualization and indirect call value profile update into one helper function (PR #80762)

2024-04-11 Thread Mingming Liu via llvm-branch-commits 

https://github.com/minglotus-6 converted_to_draft 
https://github.com/llvm/llvm-project/pull/80762
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[llvm-branch-commits] [flang] [mlir] [MLIR][Flang][OpenMP] Make omp.wsloop into a loop wrapper (PR #88403)

2024-04-11 Thread via llvm-branch-commits 

llvmbot wrote:



@llvm/pr-subscribers-mlir

@llvm/pr-subscribers-mlir-openmp

Author: Sergio Afonso (skatrak)


Changes

This patch updates the definition of `omp.wsloop` to enforce the restrictions 
of a wrapper operation. Given the widespread use of this operation, the changes 
introduced in this patch are several:

- Update the MLIR definition of the `omp.wsloop`, as well as parser/printer, 
builder and verifier.
- Update verifiers for `omp.ordered.region`, `omp.cancel` and 
`omp.cancellation_point` to correctly check for a parent `omp.wsloop`.
- Update MLIR to LLVM IR translation of `omp.wsloop` to keep working after the 
change in representation. Another patch should be created to reduce the current 
code duplication between `omp.wsloop` and `omp.simd` after introducing a common 
`omp.loop_nest` operation.
- Update the `scf.parallel` lowering pass to OpenMP to produce the new expected 
representation.
- Update flang lowering to implement `omp.wsloop` representation changes, 
including changes to `lastprivate`, and `reduction` handling to avoid adding 
operations into a wrapper and attach entry block arguments to the right 
operation.
- Fix unit tests broken due to the representation change.

---

Patch is 758.19 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/88403.diff


110 Files Affected:

- (modified) flang/lib/Lower/OpenMP/DataSharingProcessor.cpp (+27-21) 
- (modified) flang/lib/Lower/OpenMP/OpenMP.cpp (+43-74) 
- (modified) flang/test/Fir/convert-to-llvm-openmp-and-fir.fir (+61-47) 
- (modified) flang/test/Lower/OpenMP/FIR/copyin.f90 (+11-5) 
- (modified) flang/test/Lower/OpenMP/FIR/lastprivate-commonblock.f90 (+4-1) 
- (modified) flang/test/Lower/OpenMP/FIR/location.f90 (+10-7) 
- (modified) flang/test/Lower/OpenMP/FIR/parallel-lastprivate-clause-scalar.f90 
(+36-12) 
- (modified) flang/test/Lower/OpenMP/FIR/parallel-private-clause-fixes.f90 
(+26-23) 
- (modified) flang/test/Lower/OpenMP/FIR/parallel-private-clause.f90 (+60-54) 
- (modified) flang/test/Lower/OpenMP/FIR/parallel-wsloop-firstpriv.f90 (+10-2) 
- (modified) flang/test/Lower/OpenMP/FIR/parallel-wsloop.f90 (+74-54) 
- (modified) flang/test/Lower/OpenMP/FIR/stop-stmt-in-region.f90 (+21-18) 
- (modified) flang/test/Lower/OpenMP/FIR/target.f90 (+4-1) 
- (modified) flang/test/Lower/OpenMP/FIR/unstructured.f90 (+110-89) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-chunks.f90 (+28-19) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-collapse.f90 (+16-13) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-monotonic.f90 (+17-13) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-nonmonotonic.f90 (+17-14) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-ordered.f90 (+12-6) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-reduction-add-byref.f90 
(+106-85) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-reduction-add.f90 (+106-85) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand-byref.f90 (+3-1) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand.f90 (+3-1) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor-byref.f90 (+3-1) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor.f90 (+3-1) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior-byref.f90 (+3-1) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior.f90 (+3-1) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv-byref.f90 
(+75-69) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv.f90 
(+75-69) 
- (modified) 
flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv-byref.f90 (+75-69) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv.f90 
(+75-69) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-reduction-max-byref.f90 
(+18-13) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-reduction-max.f90 (+18-13) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-reduction-min-byref.f90 
(+18-14) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-reduction-min.f90 (+18-14) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-simd.f90 (+16-13) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop-variable.f90 (+93-79) 
- (modified) flang/test/Lower/OpenMP/FIR/wsloop.f90 (+36-30) 
- (modified) flang/test/Lower/OpenMP/Todo/omp-default-clause-inner-loop.f90 
(+4-1) 
- (modified) flang/test/Lower/OpenMP/copyin.f90 (+17-11) 
- (modified) flang/test/Lower/OpenMP/default-clause-byref.f90 (+4-1) 
- (modified) flang/test/Lower/OpenMP/default-clause.f90 (+4-1) 
- (modified) flang/test/Lower/OpenMP/hlfir-wsloop.f90 (+7-5) 
- (modified) flang/test/Lower/OpenMP/lastprivate-commonblock.f90 (+31-28) 
- (modified) flang/test/Lower/OpenMP/lastprivate-iv.f90 (+48-42) 
- (modified) flang/test/Lower/OpenMP/location.f90 (+10-7) 
- (modified) flang/test/Lower/OpenMP/parallel-lastprivate-clause-scalar.f90 
(+36-12) 
- (modified) flang/test/Lower/OpenMP/parallel-private-clause-fixes.f90 (+26-23) 
- (modified)

[llvm-branch-commits] [llvm] release/18x:[X86] Fix typo: QWORD alignment is greater than or equal to 8, not greater than 8 (#87819) (PR #88394)

2024-04-11 Thread via llvm-branch-commits 

llvmbot wrote:




@llvm/pr-subscribers-backend-x86

Author: AtariDreams (AtariDreams)


Changes

Align(8) is QWORD aligned, but this was checking to see if alignment was 
greater than that, when it should have been checking for being greater than OR 
EQUAL to Align(8).

This bug was introduced in
https://github.com/llvm/llvm-project/commit/6a6af30d433d7 during the transition 
to the Align type.

(cherry picked from commit 8389b3bf60ef3fbd04c6efc5ff4d4605d10e7fc5)

---
Full diff: https://github.com/llvm/llvm-project/pull/88394.diff


2 Files Affected:

- (modified) llvm/lib/Target/X86/X86SelectionDAGInfo.cpp (+2-2) 
- (modified) llvm/test/CodeGen/X86/memset-minsize.ll (+13) 


``diff
diff --git a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp 
b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
index 7c630a2b0da080..0bff1884933d86 100644
--- a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
+++ b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
@@ -80,13 +80,13 @@ SDValue X86SelectionDAGInfo::EmitTargetCodeForMemset(
 uint64_t Val = ValC->getZExtValue() & 255;
 
 // If the value is a constant, then we can potentially use larger sets.
-if (Alignment > Align(2)) {
+if (Alignment >= Align(4)) {
   // DWORD aligned
   AVT = MVT::i32;
   ValReg = X86::EAX;
   Val = (Val << 8)  | Val;
   Val = (Val << 16) | Val;
-  if (Subtarget.is64Bit() && Alignment > Align(8)) { // QWORD aligned
+  if (Subtarget.is64Bit() && Alignment >= Align(8)) { // QWORD aligned
 AVT = MVT::i64;
 ValReg = X86::RAX;
 Val = (Val << 32) | Val;
diff --git a/llvm/test/CodeGen/X86/memset-minsize.ll 
b/llvm/test/CodeGen/X86/memset-minsize.ll
index 76d2928db3a9e9..cc0f2156262bba 100644
--- a/llvm/test/CodeGen/X86/memset-minsize.ll
+++ b/llvm/test/CodeGen/X86/memset-minsize.ll
@@ -136,4 +136,17 @@ entry:
   ret void
 }
 
+define void @small_memset_to_rep_stos_64(ptr %ptr) minsize nounwind {
+; CHECK-LABEL: small_memset_to_rep_stos_64:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:pushq $16
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:xorl %eax, %eax
+; CHECK-NEXT:rep;stosq %rax, %es:(%rdi)
+; CHECK-NEXT:retq
+entry:
+  call void @llvm.memset.p0.i64(ptr align 8 %ptr, i8 0, i64 128, i1 false)
+  ret void
+}
+
 declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1)

``




https://github.com/llvm/llvm-project/pull/88394
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[llvm-branch-commits] [llvm] release/18x:[X86] Fix typo: QWORD alignment is greater than or equal to 8, not greater than 8 (#87819) (PR #88394)

2024-04-11 Thread via llvm-branch-commits 

https://github.com/AtariDreams created 
https://github.com/llvm/llvm-project/pull/88394

Align(8) is QWORD aligned, but this was checking to see if alignment was 
greater than that, when it should have been checking for being greater than OR 
EQUAL to Align(8).

This bug was introduced in
https://github.com/llvm/llvm-project/commit/6a6af30d433d7 during the transition 
to the Align type.

(cherry picked from commit 8389b3bf60ef3fbd04c6efc5ff4d4605d10e7fc5)

>From ff7d79299e3b13c087373f6879ff3b6737b4ab1a Mon Sep 17 00:00:00 2001
From: Rose 
Date: Thu, 11 Apr 2024 10:18:11 -0400
Subject: [PATCH] release/18x:[X86] Fix typo: QWORD alignment is greater than
 or equal to 8, not greater than 8 (#87819)

Align(8) is QWORD aligned, but this was checking to see if alignment was
greater than that, when it should have been checking for being greater
than OR EQUAL to Align(8).

This bug was introduced in
https://github.com/llvm/llvm-project/commit/6a6af30d433d7 during the
transition to the Align type.

(cherry picked from commit 8389b3bf60ef3fbd04c6efc5ff4d4605d10e7fc5)
---
 llvm/lib/Target/X86/X86SelectionDAGInfo.cpp |  4 ++--
 llvm/test/CodeGen/X86/memset-minsize.ll | 13 +
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp 
b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
index 7c630a2b0da080..0bff1884933d86 100644
--- a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
+++ b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
@@ -80,13 +80,13 @@ SDValue X86SelectionDAGInfo::EmitTargetCodeForMemset(
 uint64_t Val = ValC->getZExtValue() & 255;
 
 // If the value is a constant, then we can potentially use larger sets.
-if (Alignment > Align(2)) {
+if (Alignment >= Align(4)) {
   // DWORD aligned
   AVT = MVT::i32;
   ValReg = X86::EAX;
   Val = (Val << 8)  | Val;
   Val = (Val << 16) | Val;
-  if (Subtarget.is64Bit() && Alignment > Align(8)) { // QWORD aligned
+  if (Subtarget.is64Bit() && Alignment >= Align(8)) { // QWORD aligned
 AVT = MVT::i64;
 ValReg = X86::RAX;
 Val = (Val << 32) | Val;
diff --git a/llvm/test/CodeGen/X86/memset-minsize.ll 
b/llvm/test/CodeGen/X86/memset-minsize.ll
index 76d2928db3a9e9..cc0f2156262bba 100644
--- a/llvm/test/CodeGen/X86/memset-minsize.ll
+++ b/llvm/test/CodeGen/X86/memset-minsize.ll
@@ -136,4 +136,17 @@ entry:
   ret void
 }
 
+define void @small_memset_to_rep_stos_64(ptr %ptr) minsize nounwind {
+; CHECK-LABEL: small_memset_to_rep_stos_64:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:pushq $16
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:xorl %eax, %eax
+; CHECK-NEXT:rep;stosq %rax, %es:(%rdi)
+; CHECK-NEXT:retq
+entry:
+  call void @llvm.memset.p0.i64(ptr align 8 %ptr, i8 0, i64 128, i1 false)
+  ret void
+}
+
 declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1)

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[llvm-branch-commits] [llvm] release/18.x: [Codegen][X86] Fix /HOTPATCH with clang-cl and inline asm (#87639) (PR #88388)

2024-04-11 Thread Phoebe Wang via llvm-branch-commits 

https://github.com/phoebewang approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/88388
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[llvm-branch-commits] [llvm] release/18.x: [Codegen][X86] Fix /HOTPATCH with clang-cl and inline asm (#87639) (PR #88388)

2024-04-11 Thread via llvm-branch-commits 

sylvain-audi wrote:

> It think this should be good to go, but ideally I'd like someone else to sign 
> off please. @phoebewang @KanRobert @sylvain-audi

I think it's safe and good to go too. 

https://github.com/llvm/llvm-project/pull/88388
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[llvm-branch-commits] [llvm] release/18.x: [Codegen][X86] Fix /HOTPATCH with clang-cl and inline asm (#87639) (PR #88388)

2024-04-11 Thread Alexandre Ganea via llvm-branch-commits 

https://github.com/aganea approved this pull request.

It think this should be good to go, but ideally I'd like someone else to sign 
off please. @phoebewang @KanRobert @sylvain-audi 

https://github.com/llvm/llvm-project/pull/88388
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[llvm-branch-commits] [llvm] release/18.x: [Codegen][X86] Fix /HOTPATCH with clang-cl and inline asm (#87639) (PR #88388)

2024-04-11 Thread via llvm-branch-commits 

https://github.com/llvmbot updated 
https://github.com/llvm/llvm-project/pull/88388

>From c1af15c96589dab527294c4bdde86e9b8e28557e Mon Sep 17 00:00:00 2001
From: Alexandre Ganea <37383324+aga...@users.noreply.github.com>
Date: Mon, 8 Apr 2024 20:02:19 -0400
Subject: [PATCH] [Codegen][X86] Fix /HOTPATCH with clang-cl and inline asm
 (#87639)

This fixes an edge case where functions starting with inline assembly
would assert while trying to lower that inline asm instruction.

After this PR, for now we always add a no-op (xchgw in this case) without
considering the size of the next inline asm instruction. We might want
to revisit this in the future.

This fixes Unreal Engine 5.3.2 compilation with clang-cl and /HOTPATCH.

Should close https://github.com/llvm/llvm-project/issues/56234

(cherry picked from commit ec1af63dde58c735fe60d6f2aafdb10fa93f410d)
---
 llvm/lib/Target/X86/X86MCInstLower.cpp  |  4 +++-
 llvm/test/CodeGen/X86/patchable-prologue.ll | 17 +
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp 
b/llvm/lib/Target/X86/X86MCInstLower.cpp
index 58ebe023cd61ec..7ce0aa22b99795 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -959,8 +959,10 @@ void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr 
,
   SmallString<256> Code;
   unsigned MinSize = MI.getOperand(0).getImm();
 
-  if (NextMI != MI.getParent()->end()) {
+  if (NextMI != MI.getParent()->end() && !NextMI->isInlineAsm()) {
 // Lower the next MachineInstr to find its byte size.
+// If the next instruction is inline assembly, we skip lowering it for now,
+// and assume we should always generate NOPs.
 MCInst MCI;
 MCIL.Lower(&*NextMI, MCI);
 
diff --git a/llvm/test/CodeGen/X86/patchable-prologue.ll 
b/llvm/test/CodeGen/X86/patchable-prologue.ll
index 71a392845fdea3..43761e3d1e1eb9 100644
--- a/llvm/test/CodeGen/X86/patchable-prologue.ll
+++ b/llvm/test/CodeGen/X86/patchable-prologue.ll
@@ -193,3 +193,20 @@ do.body:  ; preds 
= %do.body, %entry
 do.end:   ; preds = %do.body
   ret void
 }
+
+
+; Test that inline asm is properly hotpatched. We currently don't examine the
+; asm instruction when printing it, thus we always emit patching NOPs.
+
+; 64: inline_asm:
+; 64-NEXT: # %bb.0:
+; 64-NEXT: xchgw   %ax, %ax# encoding: [0x66,0x90]
+; 64-NEXT: #APP
+; 64-NEXT: int3# encoding: [0xcc]
+; 64-NEXT: #NO_APP
+
+define dso_local void @inline_asm() 
"patchable-function"="prologue-short-redirect" {
+entry:
+  call void asm sideeffect "int3", "~{dirflag},~{fpsr},~{flags}"()
+  ret void
+}

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[llvm-branch-commits] [llvm] release/18.x: [Codegen][X86] Fix /HOTPATCH with clang-cl and inline asm (#87639) (PR #88388)

2024-04-11 Thread via llvm-branch-commits 

llvmbot wrote:




@llvm/pr-subscribers-backend-x86

Author: None (llvmbot)


Changes

Backport ec1af63dde58c735fe60d6f2aafdb10fa93f410d

Requested by: @aganea

---
Full diff: https://github.com/llvm/llvm-project/pull/88388.diff


2 Files Affected:

- (modified) llvm/lib/Target/X86/X86MCInstLower.cpp (+3-1) 
- (modified) llvm/test/CodeGen/X86/patchable-prologue.ll (+17) 


``diff
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp 
b/llvm/lib/Target/X86/X86MCInstLower.cpp
index 58ebe023cd61ec..7ce0aa22b99795 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -959,8 +959,10 @@ void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr 
,
   SmallString<256> Code;
   unsigned MinSize = MI.getOperand(0).getImm();
 
-  if (NextMI != MI.getParent()->end()) {
+  if (NextMI != MI.getParent()->end() && !NextMI->isInlineAsm()) {
 // Lower the next MachineInstr to find its byte size.
+// If the next instruction is inline assembly, we skip lowering it for now,
+// and assume we should always generate NOPs.
 MCInst MCI;
 MCIL.Lower(&*NextMI, MCI);
 
diff --git a/llvm/test/CodeGen/X86/patchable-prologue.ll 
b/llvm/test/CodeGen/X86/patchable-prologue.ll
index 71a392845fdea3..43761e3d1e1eb9 100644
--- a/llvm/test/CodeGen/X86/patchable-prologue.ll
+++ b/llvm/test/CodeGen/X86/patchable-prologue.ll
@@ -193,3 +193,20 @@ do.body:  ; preds 
= %do.body, %entry
 do.end:   ; preds = %do.body
   ret void
 }
+
+
+; Test that inline asm is properly hotpatched. We currently don't examine the
+; asm instruction when printing it, thus we always emit patching NOPs.
+
+; 64: inline_asm:
+; 64-NEXT: # %bb.0:
+; 64-NEXT: xchgw   %ax, %ax# encoding: [0x66,0x90]
+; 64-NEXT: #APP
+; 64-NEXT: int3# encoding: [0xcc]
+; 64-NEXT: #NO_APP
+
+define dso_local void @inline_asm() 
"patchable-function"="prologue-short-redirect" {
+entry:
+  call void asm sideeffect "int3", "~{dirflag},~{fpsr},~{flags}"()
+  ret void
+}

``




https://github.com/llvm/llvm-project/pull/88388
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[llvm-branch-commits] [llvm] release/18.x: [Codegen][X86] Fix /HOTPATCH with clang-cl and inline asm (#87639) (PR #88388)

2024-04-11 Thread via llvm-branch-commits 

https://github.com/llvmbot created 
https://github.com/llvm/llvm-project/pull/88388

Backport ec1af63dde58c735fe60d6f2aafdb10fa93f410d

Requested by: @aganea

>From 1a41fa5d1d9838bf03fa13b9ca8fb911a74c924f Mon Sep 17 00:00:00 2001
From: Alexandre Ganea <37383324+aga...@users.noreply.github.com>
Date: Mon, 8 Apr 2024 20:02:19 -0400
Subject: [PATCH] [Codegen][X86] Fix /HOTPATCH with clang-cl and inline asm
 (#87639)

This fixes an edge case where functions starting with inline assembly
would assert while trying to lower that inline asm instruction.

After this PR, for now we always add a no-op (xchgw in this case) without
considering the size of the next inline asm instruction. We might want
to revisit this in the future.

This fixes Unreal Engine 5.3.2 compilation with clang-cl and /HOTPATCH.

Should close https://github.com/llvm/llvm-project/issues/56234

(cherry picked from commit ec1af63dde58c735fe60d6f2aafdb10fa93f410d)
---
 llvm/lib/Target/X86/X86MCInstLower.cpp  |  4 +++-
 llvm/test/CodeGen/X86/patchable-prologue.ll | 17 +
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp 
b/llvm/lib/Target/X86/X86MCInstLower.cpp
index 58ebe023cd61ec..7ce0aa22b99795 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -959,8 +959,10 @@ void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr 
,
   SmallString<256> Code;
   unsigned MinSize = MI.getOperand(0).getImm();
 
-  if (NextMI != MI.getParent()->end()) {
+  if (NextMI != MI.getParent()->end() && !NextMI->isInlineAsm()) {
 // Lower the next MachineInstr to find its byte size.
+// If the next instruction is inline assembly, we skip lowering it for now,
+// and assume we should always generate NOPs.
 MCInst MCI;
 MCIL.Lower(&*NextMI, MCI);
 
diff --git a/llvm/test/CodeGen/X86/patchable-prologue.ll 
b/llvm/test/CodeGen/X86/patchable-prologue.ll
index 71a392845fdea3..43761e3d1e1eb9 100644
--- a/llvm/test/CodeGen/X86/patchable-prologue.ll
+++ b/llvm/test/CodeGen/X86/patchable-prologue.ll
@@ -193,3 +193,20 @@ do.body:  ; preds 
= %do.body, %entry
 do.end:   ; preds = %do.body
   ret void
 }
+
+
+; Test that inline asm is properly hotpatched. We currently don't examine the
+; asm instruction when printing it, thus we always emit patching NOPs.
+
+; 64: inline_asm:
+; 64-NEXT: # %bb.0:
+; 64-NEXT: xchgw   %ax, %ax# encoding: [0x66,0x90]
+; 64-NEXT: #APP
+; 64-NEXT: int3# encoding: [0xcc]
+; 64-NEXT: #NO_APP
+
+define dso_local void @inline_asm() 
"patchable-function"="prologue-short-redirect" {
+entry:
+  call void asm sideeffect "int3", "~{dirflag},~{fpsr},~{flags}"()
+  ret void
+}

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[llvm-branch-commits] [llvm] release/18.x: [Codegen][X86] Fix /HOTPATCH with clang-cl and inline asm (#87639) (PR #88388)

2024-04-11 Thread via llvm-branch-commits 

llvmbot wrote:

@aganea What do you think about merging this PR to the release branch?

https://github.com/llvm/llvm-project/pull/88388
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[llvm-branch-commits] [llvm] release/18.x: [Codegen][X86] Fix /HOTPATCH with clang-cl and inline asm (#87639) (PR #88388)

2024-04-11 Thread via llvm-branch-commits 

https://github.com/llvmbot milestoned 
https://github.com/llvm/llvm-project/pull/88388
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[llvm-branch-commits] [clang] [llvm] [LV][LAA] Vectorize math lib calls with mem write-only attribute (PR #78432)

2024-04-11 Thread Paschalis Mpeis via llvm-branch-commits 

https://github.com/paschalis-mpeis updated 
https://github.com/llvm/llvm-project/pull/78432

>From a74ba110994e4535cd6c9206aa02d50503fb5577 Mon Sep 17 00:00:00 2001
From: Paschalis Mpeis 
Date: Tue, 27 Feb 2024 15:00:28 +
Subject: [PATCH 1/7] [AArch64][TLI] Add TLI mappings for ArmPL modf, sincos,
 sincospi

---
 llvm/include/llvm/Analysis/VecFuncs.def   |  6 ++
 .../AArch64/veclib-function-calls.ll  | 66 ++-
 llvm/test/Transforms/Util/add-TLI-mappings.ll | 32 +++--
 3 files changed, 67 insertions(+), 37 deletions(-)

diff --git a/llvm/include/llvm/Analysis/VecFuncs.def 
b/llvm/include/llvm/Analysis/VecFuncs.def
index 394e4a05fbc0cf..10f1333cf8885c 100644
--- a/llvm/include/llvm/Analysis/VecFuncs.def
+++ b/llvm/include/llvm/Analysis/VecFuncs.def
@@ -1005,6 +1005,8 @@ TLI_DEFINE_VECFUNC("llvm.log2.f32", "armpl_svlog2_f32_x", 
SCALABLE(4), MASKED, "
 
 TLI_DEFINE_VECFUNC("modf", "armpl_vmodfq_f64", FIXED(2), NOMASK, 
"_ZGV_LLVM_N2vl8")
 TLI_DEFINE_VECFUNC("modff", "armpl_vmodfq_f32", FIXED(4), NOMASK, 
"_ZGV_LLVM_N4vl4")
+TLI_DEFINE_VECFUNC("modf", "armpl_svmodf_f64_x", SCALABLE(2), MASKED, 
"_ZGVsMxvl8")
+TLI_DEFINE_VECFUNC("modff", "armpl_svmodf_f32_x", SCALABLE(4), MASKED, 
"_ZGVsMxvl4")
 
 TLI_DEFINE_VECFUNC("nextafter", "armpl_vnextafterq_f64", FIXED(2), NOMASK, 
"_ZGV_LLVM_N2vv")
 TLI_DEFINE_VECFUNC("nextafterf", "armpl_vnextafterq_f32", FIXED(4), NOMASK, 
"_ZGV_LLVM_N4vv")
@@ -1033,9 +1035,13 @@ TLI_DEFINE_VECFUNC("llvm.sin.f32", "armpl_svsin_f32_x", 
SCALABLE(4), MASKED, "_Z
 
 TLI_DEFINE_VECFUNC("sincos", "armpl_vsincosq_f64", FIXED(2), NOMASK, 
"_ZGV_LLVM_N2vl8l8")
 TLI_DEFINE_VECFUNC("sincosf", "armpl_vsincosq_f32", FIXED(4), NOMASK, 
"_ZGV_LLVM_N4vl4l4")
+TLI_DEFINE_VECFUNC("sincos", "armpl_svsincos_f64_x", SCALABLE(2), MASKED, 
"_ZGVsMxvl8l8")
+TLI_DEFINE_VECFUNC("sincosf", "armpl_svsincos_f32_x", SCALABLE(4), MASKED, 
"_ZGVsMxvl4l4")
 
 TLI_DEFINE_VECFUNC("sincospi", "armpl_vsincospiq_f64", FIXED(2), NOMASK, 
"_ZGV_LLVM_N2vl8l8")
 TLI_DEFINE_VECFUNC("sincospif", "armpl_vsincospiq_f32", FIXED(4), NOMASK, 
"_ZGV_LLVM_N4vl4l4")
+TLI_DEFINE_VECFUNC("sincospi", "armpl_svsincospi_f64_x", SCALABLE(2), MASKED, 
"_ZGVsMxvl8l8")
+TLI_DEFINE_VECFUNC("sincospif", "armpl_svsincospi_f32_x", SCALABLE(4), MASKED, 
"_ZGVsMxvl4l4")
 
 TLI_DEFINE_VECFUNC("sinh", "armpl_vsinhq_f64", FIXED(2), NOMASK, 
"_ZGV_LLVM_N2v")
 TLI_DEFINE_VECFUNC("sinhf", "armpl_vsinhq_f32", FIXED(4), NOMASK, 
"_ZGV_LLVM_N4v")
diff --git 
a/llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll 
b/llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
index dd1495626eb984..d9cc630482fc80 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
@@ -2925,11 +2925,12 @@ define void @modf_f64(ptr noalias %a, ptr noalias %b, 
ptr noalias %c) {
 ;
 ; ARMPL-SVE-LABEL: define void @modf_f64
 ; ARMPL-SVE-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias 
[[C:%.*]]) #[[ATTR0]] {
-; ARMPL-SVE:[[DATA:%.*]] = call double @modf(double [[NUM:%.*]], ptr 
[[GEPB:%.*]]) #[[ATTR4:[0-9]+]]
+; ARMPL-SVE:[[TMP23:%.*]] = call  
@armpl_svmodf_f64_x( [[WIDE_MASKED_LOAD:%.*]], ptr 
[[TMP22:%.*]],  [[ACTIVE_LANE_MASK:%.*]])
 ;
 ; ARMPL-SVE-NOPRED-LABEL: define void @modf_f64
 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr 
noalias [[C:%.*]]) #[[ATTR0]] {
-; ARMPL-SVE-NOPRED:[[TMP5:%.*]] = call <2 x double> @armpl_vmodfq_f64(<2 x 
double> [[WIDE_LOAD:%.*]], ptr [[TMP4:%.*]])
+; ARMPL-SVE-NOPRED:[[TMP17:%.*]] = call  
@armpl_svmodf_f64_x( [[WIDE_LOAD:%.*]], ptr [[TMP16:%.*]], 
 shufflevector ( insertelement ( poison, i1 true, i64 0),  poison,  
zeroinitializer))
+; ARMPL-SVE-NOPRED:[[DATA:%.*]] = call double @modf(double [[NUM:%.*]], 
ptr [[GEPB:%.*]]) #[[ATTR64:[0-9]+]]
 ;
 entry:
   br label %for.body
@@ -2970,11 +2971,12 @@ define void @modf_f32(ptr noalias %a, ptr noalias %b, 
ptr noalias %c) {
 ;
 ; ARMPL-SVE-LABEL: define void @modf_f32
 ; ARMPL-SVE-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias 
[[C:%.*]]) #[[ATTR0]] {
-; ARMPL-SVE:[[DATA:%.*]] = call float @modff(float [[NUM:%.*]], ptr 
[[GEPB:%.*]]) #[[ATTR5:[0-9]+]]
+; ARMPL-SVE:[[TMP23:%.*]] = call  
@armpl_svmodf_f32_x( [[WIDE_MASKED_LOAD:%.*]], ptr 
[[TMP22:%.*]],  [[ACTIVE_LANE_MASK:%.*]])
 ;
 ; ARMPL-SVE-NOPRED-LABEL: define void @modf_f32
 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr 
noalias [[C:%.*]]) #[[ATTR0]] {
-; ARMPL-SVE-NOPRED:[[TMP5:%.*]] = call <4 x float> @armpl_vmodfq_f32(<4 x 
float> [[WIDE_LOAD:%.*]], ptr [[TMP4:%.*]])
+; ARMPL-SVE-NOPRED:[[TMP17:%.*]] = call  
@armpl_svmodf_f32_x( [[WIDE_LOAD:%.*]], ptr [[TMP16:%.*]], 
 shufflevector ( insertelement ( poison, i1 true, i64 0),  poison,  
zeroinitializer))
+; ARMPL-SVE-NOPRED:[[DATA:%.*]] = call float @modff(float [[NUM:%.*]], ptr 
[[GEPB:%.*]])

[llvm-branch-commits] [llvm] [BOLT] Cover all call sites in writeBATYAML (PR #87743)

2024-04-11 Thread Amir Ayupov via llvm-branch-commits 

https://github.com/aaupov updated 
https://github.com/llvm/llvm-project/pull/87743

>From 251020f10d1e6a7a888164748f78acc6994e0ab3 Mon Sep 17 00:00:00 2001
From: Amir Ayupov 
Date: Fri, 5 Apr 2024 07:36:40 -0700
Subject: [PATCH] Remove stats logging

Created using spr 1.3.4
---
 bolt/lib/Profile/DataAggregator.cpp | 13 -
 1 file changed, 13 deletions(-)

diff --git a/bolt/lib/Profile/DataAggregator.cpp 
b/bolt/lib/Profile/DataAggregator.cpp
index 119d082c50c18c..1d0737167c808e 100644
--- a/bolt/lib/Profile/DataAggregator.cpp
+++ b/bolt/lib/Profile/DataAggregator.cpp
@@ -2395,19 +2395,6 @@ std::error_code 
DataAggregator::writeBATYAML(BinaryContext ,
 !YamlBB.CallSites.empty())
   YamlBF.Blocks.emplace_back(YamlBB);
   }
-
-  for (const auto &[BranchOffset, _] : Branches.InterIndex) {
-bool Matched =
-llvm::any_of(llvm::make_second_range(BFBranches),
- [&](const std::vector ) {
-   return llvm::is_contained(BranchOffsets,
- BranchOffset);
- });
-if (!Matched && opts::Verbosity >= 1)
-  errs() << "BOLT-WARNING: Couldn't match call site "
- << formatv("{0}@{1:x} to YAML profile\n", FuncName,
-BranchOffset);
-  }
   BP.Functions.emplace_back(YamlBF);
 }
   }

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[llvm-branch-commits] [llvm] [BOLT] Cover all call sites in writeBATYAML (PR #87743)

2024-04-11 Thread Amir Ayupov via llvm-branch-commits 

https://github.com/aaupov updated 
https://github.com/llvm/llvm-project/pull/87743

>From 251020f10d1e6a7a888164748f78acc6994e0ab3 Mon Sep 17 00:00:00 2001
From: Amir Ayupov 
Date: Fri, 5 Apr 2024 07:36:40 -0700
Subject: [PATCH] Remove stats logging

Created using spr 1.3.4
---
 bolt/lib/Profile/DataAggregator.cpp | 13 -
 1 file changed, 13 deletions(-)

diff --git a/bolt/lib/Profile/DataAggregator.cpp 
b/bolt/lib/Profile/DataAggregator.cpp
index 119d082c50c18c..1d0737167c808e 100644
--- a/bolt/lib/Profile/DataAggregator.cpp
+++ b/bolt/lib/Profile/DataAggregator.cpp
@@ -2395,19 +2395,6 @@ std::error_code 
DataAggregator::writeBATYAML(BinaryContext ,
 !YamlBB.CallSites.empty())
   YamlBF.Blocks.emplace_back(YamlBB);
   }
-
-  for (const auto &[BranchOffset, _] : Branches.InterIndex) {
-bool Matched =
-llvm::any_of(llvm::make_second_range(BFBranches),
- [&](const std::vector ) {
-   return llvm::is_contained(BranchOffsets,
- BranchOffset);
- });
-if (!Matched && opts::Verbosity >= 1)
-  errs() << "BOLT-WARNING: Couldn't match call site "
- << formatv("{0}@{1:x} to YAML profile\n", FuncName,
-BranchOffset);
-  }
   BP.Functions.emplace_back(YamlBF);
 }
   }

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[llvm-branch-commits] [llvm] [BOLT][BAT] Fix handling of split functions (PR #87569)

2024-04-11 Thread Amir Ayupov via llvm-branch-commits 

https://github.com/aaupov updated 
https://github.com/llvm/llvm-project/pull/87569

>From a3b0326428924a9565c673ffc6bc899ee788a19b Mon Sep 17 00:00:00 2001
From: Amir Ayupov 
Date: Fri, 5 Apr 2024 07:40:41 -0700
Subject: [PATCH] Move comment to NumColdSamples

Created using spr 1.3.4
---
 bolt/include/bolt/Profile/DataAggregator.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/bolt/include/bolt/Profile/DataAggregator.h 
b/bolt/include/bolt/Profile/DataAggregator.h
index 659a8488d1534c..3b8624585c19bd 100644
--- a/bolt/include/bolt/Profile/DataAggregator.h
+++ b/bolt/include/bolt/Profile/DataAggregator.h
@@ -225,6 +225,10 @@ class DataAggregator : public DataReader {
   /// Aggregation statistics
   uint64_t NumInvalidTraces{0};
   uint64_t NumLongRangeTraces{0};
+  /// Specifies how many samples were recorded in cold areas if we are dealing
+  /// with profiling data collected in a bolted binary. For LBRs, incremented
+  /// for the source of the branch to avoid counting cold activity twice (one
+  /// for source and another for destination).
   uint64_t NumColdSamples{0};
 
   /// Looks into system PATH for Linux Perf and set up the aggregator to use it

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[llvm-branch-commits] [llvm] [BOLT][BAT] Fix handling of split functions (PR #87569)

2024-04-11 Thread Amir Ayupov via llvm-branch-commits 

https://github.com/aaupov updated 
https://github.com/llvm/llvm-project/pull/87569

>From a3b0326428924a9565c673ffc6bc899ee788a19b Mon Sep 17 00:00:00 2001
From: Amir Ayupov 
Date: Fri, 5 Apr 2024 07:40:41 -0700
Subject: [PATCH] Move comment to NumColdSamples

Created using spr 1.3.4
---
 bolt/include/bolt/Profile/DataAggregator.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/bolt/include/bolt/Profile/DataAggregator.h 
b/bolt/include/bolt/Profile/DataAggregator.h
index 659a8488d1534c..3b8624585c19bd 100644
--- a/bolt/include/bolt/Profile/DataAggregator.h
+++ b/bolt/include/bolt/Profile/DataAggregator.h
@@ -225,6 +225,10 @@ class DataAggregator : public DataReader {
   /// Aggregation statistics
   uint64_t NumInvalidTraces{0};
   uint64_t NumLongRangeTraces{0};
+  /// Specifies how many samples were recorded in cold areas if we are dealing
+  /// with profiling data collected in a bolted binary. For LBRs, incremented
+  /// for the source of the branch to avoid counting cold activity twice (one
+  /// for source and another for destination).
   uint64_t NumColdSamples{0};
 
   /// Looks into system PATH for Linux Perf and set up the aggregator to use it

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[llvm-branch-commits] [llvm] [BOLT] Emit empty FDE for injected functions (PR #87967)

2024-04-11 Thread Amir Ayupov via llvm-branch-commits 

https://github.com/aaupov updated 
https://github.com/llvm/llvm-project/pull/87967

>From c856716bbb987e09ee86b31287808736ef4f2f9b Mon Sep 17 00:00:00 2001
From: Amir Ayupov 
Date: Tue, 9 Apr 2024 04:52:43 -0700
Subject: [PATCH 1/3] Added test

Created using spr 1.3.4
---
 bolt/include/bolt/Core/BinaryFunction.h |  3 ++-
 bolt/lib/Core/BinaryEmitter.cpp |  4 ++--
 bolt/test/X86/patch-entries.test| 23 ++-
 3 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/bolt/include/bolt/Core/BinaryFunction.h 
b/bolt/include/bolt/Core/BinaryFunction.h
index bc047fefa3151c..26d2d01f862671 100644
--- a/bolt/include/bolt/Core/BinaryFunction.h
+++ b/bolt/include/bolt/Core/BinaryFunction.h
@@ -1402,7 +1402,8 @@ class BinaryFunction {
 
   /// Return true if the function has CFI instructions
   bool hasCFI() const {
-return !FrameInstructions.empty() || !CIEFrameInstructions.empty();
+return !FrameInstructions.empty() || !CIEFrameInstructions.empty() ||
+   IsInjected;
   }
 
   /// Return unique number associated with the function.
diff --git a/bolt/lib/Core/BinaryEmitter.cpp b/bolt/lib/Core/BinaryEmitter.cpp
index 56bd65a51600d1..97d19b75200f51 100644
--- a/bolt/lib/Core/BinaryEmitter.cpp
+++ b/bolt/lib/Core/BinaryEmitter.cpp
@@ -347,7 +347,7 @@ bool BinaryEmitter::emitFunction(BinaryFunction ,
   }
 
   // Emit CFI start
-  if (Function.hasCFI() || Function.isInjected()) {
+  if (Function.hasCFI()) {
 Streamer.emitCFIStartProc(/*IsSimple=*/false);
 if (Function.getPersonalityFunction() != nullptr)
   Streamer.emitCFIPersonality(Function.getPersonalityFunction(),
@@ -394,7 +394,7 @@ bool BinaryEmitter::emitFunction(BinaryFunction ,
 Streamer.emitBytes(BC.MIB->getTrapFillValue());
 
   // Emit CFI end
-  if (Function.hasCFI() || Function.isInjected())
+  if (Function.hasCFI())
 Streamer.emitCFIEndProc();
 
   MCSymbol *EndSymbol = Function.getFunctionEndLabel(FF.getFragmentNum());
diff --git a/bolt/test/X86/patch-entries.test b/bolt/test/X86/patch-entries.test
index 54f358f273e793..331f8a312f4820 100644
--- a/bolt/test/X86/patch-entries.test
+++ b/bolt/test/X86/patch-entries.test
@@ -7,4 +7,25 @@ REQUIRES: system-linux
 
 RUN: %clang %cflags -no-pie -g %p/Inputs/patch-entries.c -fuse-ld=lld -o 
%t.exe \
 RUN:   -Wl,-q -I%p/../Inputs
-RUN: llvm-bolt -relocs %t.exe -o %t.out --update-debug-sections --force-patch
+RUN: llvm-bolt -relocs %t.exe -o %t.out --update-debug-sections --force-patch \
+RUN:   --enable-bat
+
+# Check that patched functions can be disassembled (override FDE from the
+# original function)
+# PREAGG: B X:0 #foo.org.0# 1 0
+RUN: link_fdata %s %t.out %t.preagg PREAGG
+RUN: perf2bolt %t.out -p %t.preagg --pa -o %t.yaml --profile-format=yaml \
+RUN:   -print-disasm -print-only=foo.org.0/1 2>&1 | FileCheck %s
+CHECK-NOT: BOLT-WARNING: sizes differ for function foo.org.0/1. FDE : 23; 
symbol table : 5. Using max size.
+CHECK: Binary Function "foo.org.0/1(*2)" after disassembly {
+
+# Check the expected eh_frame contents
+RUN: llvm-nm --print-size %t.out > %t.foo
+RUN: llvm-objdump %t.out --dwarf=frames >> %t.foo
+RUN: FileCheck %s --input-file %t.foo --check-prefix=CHECK-FOO
+CHECK-FOO: [[#FOO:]] {{.*}} foo
+CHECK-FOO: [[#ORG:]] {{.*}} foo.org.0
+# patched FDE comes first
+CHECK-FOO: FDE {{.*}} pc=00[[#ORG]]...00[[#ORG+5]]
+# original FDE comes second
+CHECK-FOO: FDE {{.*}} pc=00[[#ORG]]...00[[#ORG+23]]

>From ed991a81eb7975c41c5db75fa772329752911c00 Mon Sep 17 00:00:00 2001
From: Amir Ayupov 
Date: Tue, 9 Apr 2024 15:23:28 -0700
Subject: [PATCH 2/3] Fix test

Created using spr 1.3.4
---
 bolt/test/X86/patch-entries.test | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/bolt/test/X86/patch-entries.test b/bolt/test/X86/patch-entries.test
index 331f8a312f4820..2821501fd9baad 100644
--- a/bolt/test/X86/patch-entries.test
+++ b/bolt/test/X86/patch-entries.test
@@ -16,7 +16,7 @@ RUN:   --enable-bat
 RUN: link_fdata %s %t.out %t.preagg PREAGG
 RUN: perf2bolt %t.out -p %t.preagg --pa -o %t.yaml --profile-format=yaml \
 RUN:   -print-disasm -print-only=foo.org.0/1 2>&1 | FileCheck %s
-CHECK-NOT: BOLT-WARNING: sizes differ for function foo.org.0/1. FDE : 23; 
symbol table : 5. Using max size.
+CHECK-NOT: BOLT-WARNING: sizes differ for function foo.org.0/1
 CHECK: Binary Function "foo.org.0/1(*2)" after disassembly {
 
 # Check the expected eh_frame contents
@@ -28,4 +28,4 @@ CHECK-FOO: [[#ORG:]] {{.*}} foo.org.0
 # patched FDE comes first
 CHECK-FOO: FDE {{.*}} pc=00[[#ORG]]...00[[#ORG+5]]
 # original FDE comes second
-CHECK-FOO: FDE {{.*}} pc=00[[#ORG]]...00[[#ORG+23]]
+CHECK-FOO: FDE {{.*}} pc=00[[#ORG]]

>From cb1096ef2e86d7f7ff628e033cf88a46268533d6 Mon Sep 17 00:00:00 2001
From: Amir Ayupov 
Date: Tue, 9 Apr 2024 16:40:21 -0700
Subject: [PATCH 3/3] Update test

Created using spr 1.3.4
---
 bolt/test/X86/patch-entries.test | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git

[llvm-branch-commits] [llvm] [BOLT] Emit empty FDE for injected functions (PR #87967)

2024-04-11 Thread Amir Ayupov via llvm-branch-commits 

https://github.com/aaupov updated 
https://github.com/llvm/llvm-project/pull/87967

>From c856716bbb987e09ee86b31287808736ef4f2f9b Mon Sep 17 00:00:00 2001
From: Amir Ayupov 
Date: Tue, 9 Apr 2024 04:52:43 -0700
Subject: [PATCH 1/3] Added test

Created using spr 1.3.4
---
 bolt/include/bolt/Core/BinaryFunction.h |  3 ++-
 bolt/lib/Core/BinaryEmitter.cpp |  4 ++--
 bolt/test/X86/patch-entries.test| 23 ++-
 3 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/bolt/include/bolt/Core/BinaryFunction.h 
b/bolt/include/bolt/Core/BinaryFunction.h
index bc047fefa3151c..26d2d01f862671 100644
--- a/bolt/include/bolt/Core/BinaryFunction.h
+++ b/bolt/include/bolt/Core/BinaryFunction.h
@@ -1402,7 +1402,8 @@ class BinaryFunction {
 
   /// Return true if the function has CFI instructions
   bool hasCFI() const {
-return !FrameInstructions.empty() || !CIEFrameInstructions.empty();
+return !FrameInstructions.empty() || !CIEFrameInstructions.empty() ||
+   IsInjected;
   }
 
   /// Return unique number associated with the function.
diff --git a/bolt/lib/Core/BinaryEmitter.cpp b/bolt/lib/Core/BinaryEmitter.cpp
index 56bd65a51600d1..97d19b75200f51 100644
--- a/bolt/lib/Core/BinaryEmitter.cpp
+++ b/bolt/lib/Core/BinaryEmitter.cpp
@@ -347,7 +347,7 @@ bool BinaryEmitter::emitFunction(BinaryFunction ,
   }
 
   // Emit CFI start
-  if (Function.hasCFI() || Function.isInjected()) {
+  if (Function.hasCFI()) {
 Streamer.emitCFIStartProc(/*IsSimple=*/false);
 if (Function.getPersonalityFunction() != nullptr)
   Streamer.emitCFIPersonality(Function.getPersonalityFunction(),
@@ -394,7 +394,7 @@ bool BinaryEmitter::emitFunction(BinaryFunction ,
 Streamer.emitBytes(BC.MIB->getTrapFillValue());
 
   // Emit CFI end
-  if (Function.hasCFI() || Function.isInjected())
+  if (Function.hasCFI())
 Streamer.emitCFIEndProc();
 
   MCSymbol *EndSymbol = Function.getFunctionEndLabel(FF.getFragmentNum());
diff --git a/bolt/test/X86/patch-entries.test b/bolt/test/X86/patch-entries.test
index 54f358f273e793..331f8a312f4820 100644
--- a/bolt/test/X86/patch-entries.test
+++ b/bolt/test/X86/patch-entries.test
@@ -7,4 +7,25 @@ REQUIRES: system-linux
 
 RUN: %clang %cflags -no-pie -g %p/Inputs/patch-entries.c -fuse-ld=lld -o 
%t.exe \
 RUN:   -Wl,-q -I%p/../Inputs
-RUN: llvm-bolt -relocs %t.exe -o %t.out --update-debug-sections --force-patch
+RUN: llvm-bolt -relocs %t.exe -o %t.out --update-debug-sections --force-patch \
+RUN:   --enable-bat
+
+# Check that patched functions can be disassembled (override FDE from the
+# original function)
+# PREAGG: B X:0 #foo.org.0# 1 0
+RUN: link_fdata %s %t.out %t.preagg PREAGG
+RUN: perf2bolt %t.out -p %t.preagg --pa -o %t.yaml --profile-format=yaml \
+RUN:   -print-disasm -print-only=foo.org.0/1 2>&1 | FileCheck %s
+CHECK-NOT: BOLT-WARNING: sizes differ for function foo.org.0/1. FDE : 23; 
symbol table : 5. Using max size.
+CHECK: Binary Function "foo.org.0/1(*2)" after disassembly {
+
+# Check the expected eh_frame contents
+RUN: llvm-nm --print-size %t.out > %t.foo
+RUN: llvm-objdump %t.out --dwarf=frames >> %t.foo
+RUN: FileCheck %s --input-file %t.foo --check-prefix=CHECK-FOO
+CHECK-FOO: [[#FOO:]] {{.*}} foo
+CHECK-FOO: [[#ORG:]] {{.*}} foo.org.0
+# patched FDE comes first
+CHECK-FOO: FDE {{.*}} pc=00[[#ORG]]...00[[#ORG+5]]
+# original FDE comes second
+CHECK-FOO: FDE {{.*}} pc=00[[#ORG]]...00[[#ORG+23]]

>From ed991a81eb7975c41c5db75fa772329752911c00 Mon Sep 17 00:00:00 2001
From: Amir Ayupov 
Date: Tue, 9 Apr 2024 15:23:28 -0700
Subject: [PATCH 2/3] Fix test

Created using spr 1.3.4
---
 bolt/test/X86/patch-entries.test | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/bolt/test/X86/patch-entries.test b/bolt/test/X86/patch-entries.test
index 331f8a312f4820..2821501fd9baad 100644
--- a/bolt/test/X86/patch-entries.test
+++ b/bolt/test/X86/patch-entries.test
@@ -16,7 +16,7 @@ RUN:   --enable-bat
 RUN: link_fdata %s %t.out %t.preagg PREAGG
 RUN: perf2bolt %t.out -p %t.preagg --pa -o %t.yaml --profile-format=yaml \
 RUN:   -print-disasm -print-only=foo.org.0/1 2>&1 | FileCheck %s
-CHECK-NOT: BOLT-WARNING: sizes differ for function foo.org.0/1. FDE : 23; 
symbol table : 5. Using max size.
+CHECK-NOT: BOLT-WARNING: sizes differ for function foo.org.0/1
 CHECK: Binary Function "foo.org.0/1(*2)" after disassembly {
 
 # Check the expected eh_frame contents
@@ -28,4 +28,4 @@ CHECK-FOO: [[#ORG:]] {{.*}} foo.org.0
 # patched FDE comes first
 CHECK-FOO: FDE {{.*}} pc=00[[#ORG]]...00[[#ORG+5]]
 # original FDE comes second
-CHECK-FOO: FDE {{.*}} pc=00[[#ORG]]...00[[#ORG+23]]
+CHECK-FOO: FDE {{.*}} pc=00[[#ORG]]

>From cb1096ef2e86d7f7ff628e033cf88a46268533d6 Mon Sep 17 00:00:00 2001
From: Amir Ayupov 
Date: Tue, 9 Apr 2024 16:40:21 -0700
Subject: [PATCH 3/3] Update test

Created using spr 1.3.4
---
 bolt/test/X86/patch-entries.test | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git

[llvm-branch-commits] [llvm] release/18.x: [InstSimplify] Make sure the simplified value doesn't generate poison in threadBinOpOverSelect (#87075) (PR #88353)

2024-04-11 Thread Nikita Popov via llvm-branch-commits 

https://github.com/nikic approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/88353
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[llvm-branch-commits] [llvm] [BOLT] Emit empty FDE for injected functions (PR #87967)

2024-04-11 Thread Davide Italiano via llvm-branch-commits 

https://github.com/dcci approved this pull request.


https://github.com/llvm/llvm-project/pull/87967
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[llvm-branch-commits] [libcxx] [libc++][TZDB] Adds sys_info formatter. (PR #85896)

2024-04-11 Thread Mark de Wever via llvm-branch-commits 

https://github.com/mordante updated 
https://github.com/llvm/llvm-project/pull/85896

>From de4ba883c354ab8510fb0e5e4ad2a09d93000c30 Mon Sep 17 00:00:00 2001
From: Mark de Wever 
Date: Sun, 10 Mar 2024 17:49:39 +0100
Subject: [PATCH] [libc++][TZDB] Adds sys_info formatter.

Implements parts of:
- P0355 Extending  to Calendars and Time Zones
- P1361 Integration of chrono with text formatting
---
 libcxx/docs/Status/FormatPaper.csv|   2 +-
 libcxx/include/__chrono/convert_to_tm.h   |   5 +
 libcxx/include/__chrono/formatter.h   |  44 +-
 libcxx/include/__chrono/ostream.h |  20 +++
 libcxx/include/__chrono/sys_info.h|   2 +-
 libcxx/include/chrono |   5 +
 .../time.zone.info.sys/ostream.pass.cpp   |  74 ++
 .../time/time.syn/formatter.sys_info.pass.cpp | 137 ++
 .../time.zone.info.sys/ostream.pass.cpp   |  52 +++
 .../concept.formattable.compile.pass.cpp  |   2 +-
 10 files changed, 337 insertions(+), 6 deletions(-)
 create mode 100644 
libcxx/test/libcxx/time/time.zone/time.zone.info/time.zone.info.sys/ostream.pass.cpp
 create mode 100644 libcxx/test/std/time/time.syn/formatter.sys_info.pass.cpp
 create mode 100644 
libcxx/test/std/time/time.zone/time.zone.info/time.zone.info.sys/ostream.pass.cpp

diff --git a/libcxx/docs/Status/FormatPaper.csv 
b/libcxx/docs/Status/FormatPaper.csv
index e9d407e79e2539..8ace18815f5375 100644
--- a/libcxx/docs/Status/FormatPaper.csv
+++ b/libcxx/docs/Status/FormatPaper.csv
@@ -24,7 +24,7 @@ Section,Description,Dependencies,Assignee,Status,First 
released version
 `[time.syn] `_,"Formatter 
``chrono::year_month_weekday``",,Mark de Wever,|Complete|,16.0
 `[time.syn] `_,"Formatter 
``chrono::year_month_weekday_last``",,Mark de Wever,|Complete|,16.0
 `[time.syn] `_,"Formatter 
``chrono::hh_mm_ss>``",,Mark de Wever,|Complete|,17.0
-`[time.syn] `_,"Formatter ``chrono::sys_info``",A 
 implementation,Mark de Wever,,
+`[time.syn] `_,"Formatter 
``chrono::sys_info``",,Mark de Wever,|Complete|,19.0
 `[time.syn] `_,"Formatter 
``chrono::local_info``",A  implementation,Mark de Wever,,
 `[time.syn] `_,"Formatter 
``chrono::zoned_time``",A  
implementation,Mark de Wever,,
 
diff --git a/libcxx/include/__chrono/convert_to_tm.h 
b/libcxx/include/__chrono/convert_to_tm.h
index 1301cd6f1f1ada..d2c5cf922ba671 100644
--- a/libcxx/include/__chrono/convert_to_tm.h
+++ b/libcxx/include/__chrono/convert_to_tm.h
@@ -20,6 +20,7 @@
 #include <__chrono/month_weekday.h>
 #include <__chrono/monthday.h>
 #include <__chrono/statically_widen.h>
+#include <__chrono/sys_info.h>
 #include <__chrono/system_clock.h>
 #include <__chrono/time_point.h>
 #include <__chrono/weekday.h>
@@ -171,6 +172,10 @@ _LIBCPP_HIDE_FROM_ABI _Tm __convert_to_tm(const _ChronoT& 
__value) {
   if (__value.hours().count() > 
std::numeric_limits::max())
 std::__throw_format_error("Formatting hh_mm_ss, encountered an hour 
overflow");
 __result.tm_hour = __value.hours().count();
+#  if !defined(_LIBCPP_HAS_NO_INCOMPLETE_TZDB)
+  } else if constexpr (same_as<_ChronoT, chrono::sys_info>) {
+// Has no time information.
+#  endif
   } else
 static_assert(sizeof(_ChronoT) == 0, "Add the missing type 
specialization");
 
diff --git a/libcxx/include/__chrono/formatter.h 
b/libcxx/include/__chrono/formatter.h
index 217979e88c93db..79192fa103fbdb 100644
--- a/libcxx/include/__chrono/formatter.h
+++ b/libcxx/include/__chrono/formatter.h
@@ -24,6 +24,7 @@
 #include <__chrono/ostream.h>
 #include <__chrono/parser_std_format_spec.h>
 #include <__chrono/statically_widen.h>
+#include <__chrono/sys_info.h>
 #include <__chrono/system_clock.h>
 #include <__chrono/time_point.h>
 #include <__chrono/weekday.h>
@@ -185,10 +186,11 @@ __format_zone_offset(basic_stringstream<_CharT>& __sstr, 
chrono::seconds __offse
 
   chrono::hh_mm_ss __hms{__offset};
   std::ostreambuf_iterator<_CharT> __out_it{__sstr};
+  // Note HMS does not allow formatting hours > 23, but the offset is not 
limited to 24H.
+  std::format_to(__out_it, _LIBCPP_STATICALLY_WIDEN(_CharT, "{:02}"), 
__hms.hours().count());
   if (__modifier)
-std::format_to(__out_it, _LIBCPP_STATICALLY_WIDEN(_CharT, "{:%H:%M}"), 
__hms);
-  else
-std::format_to(__out_it, _LIBCPP_STATICALLY_WIDEN(_CharT, "{:%H%M}"), 
__hms);
+__sstr << _CharT(':');
+  std::format_to(__out_it, _LIBCPP_STATICALLY_WIDEN(_CharT, "{:02}"), 
__hms.minutes().count());
 }
 
 // Helper to store the time zone information needed for formatting.
@@ -202,6 +204,12 @@ struct _LIBCPP_HIDE_FROM_ABI __time_zone {
 template 
 _LIBCPP_HIDE_FROM_ABI __time_zone __convert_to_time_zone([[maybe_unused]] 
const _Tp& __value) {
   __time_zone __result;
+#  if