[llvm-branch-commits] [llvm] 244ad22 - [ARM][MachineOutliner] Add stack fixup feature
Author: Yvan Roux
Date: 2021-01-19T10:59:09+01:00
New Revision: 244ad228f34363b508cd1096c99d8f1bbe999d85
URL:
https://github.com/llvm/llvm-project/commit/244ad228f34363b508cd1096c99d8f1bbe999d85
DIFF:
https://github.com/llvm/llvm-project/commit/244ad228f34363b508cd1096c99d8f1bbe999d85.diff
LOG: [ARM][MachineOutliner] Add stack fixup feature
This patch handles cases where we have to save/restore the link register
into the stack and and load/store instruction which use the stack are
part of the outlined region. It checks that there will be no overflow
introduced by the new offset and fixup these instructions accordingly.
Differential Revision: https://reviews.llvm.org/D92934
Added:
llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir
llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir
Modified:
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/test/CodeGen/ARM/machine-outliner-default.mir
llvm/test/CodeGen/ARM/machine-outliner-no-lr-save.mir
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.generated.expected
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.nogenerated.expected
Removed:
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 143bf6641e6f..112eb59e173d 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -5914,6 +5914,112 @@ outliner::OutlinedFunction
ARMBaseInstrInfo::getOutliningCandidateInfo(
NumBytesToCreateFrame, FrameID);
}
+bool ARMBaseInstrInfo::checkAndUpdateStackOffset(MachineInstr *MI,
+ int64_t Fixup,
+ bool Updt) const {
+ int SPIdx = MI->findRegisterUseOperandIdx(ARM::SP);
+ unsigned AddrMode = (MI->getDesc().TSFlags & ARMII::AddrModeMask);
+ if (SPIdx < 0)
+// No SP operand
+return true;
+ else if (SPIdx != 1 && (AddrMode != ARMII::AddrModeT2_i8s4 || SPIdx != 2))
+// If SP is not the base register we can't do much
+return false;
+
+ // Stack might be involved but addressing mode doesn't handle any offset.
+ // Rq: AddrModeT1_[1|2|4] don't operate on SP
+ if (AddrMode == ARMII::AddrMode1// Arithmetic instructions
+ || AddrMode == ARMII::AddrMode4 // Load/Store Multiple
+ || AddrMode == ARMII::AddrMode6 // Neon Load/Store Multiple
+ || AddrMode == ARMII::AddrModeT2_so // SP can't be used as based register
+ || AddrMode == ARMII::AddrModeT2_pc // PCrel access
+ || AddrMode == ARMII::AddrMode2 // Used by PRE and POST indexed LD/ST
+ || AddrMode == ARMII::AddrModeNone)
+return false;
+
+ unsigned NumOps = MI->getDesc().getNumOperands();
+ unsigned ImmIdx = NumOps - 3;
+
+ const MachineOperand = MI->getOperand(ImmIdx);
+ assert(Offset.isImm() && "Is not an immediate");
+ int64_t OffVal = Offset.getImm();
+
+ if (OffVal < 0)
+// Don't override data if the are below SP.
+return false;
+
+ unsigned NumBits = 0;
+ unsigned Scale = 1;
+
+ switch (AddrMode) {
+ case ARMII::AddrMode3:
+if (ARM_AM::getAM3Op(OffVal) == ARM_AM::sub)
+ return false;
+OffVal = ARM_AM::getAM3Offset(OffVal);
+NumBits = 8;
+break;
+ case ARMII::AddrMode5:
+if (ARM_AM::getAM5Op(OffVal) == ARM_AM::sub)
+ return false;
+OffVal = ARM_AM::getAM5Offset(OffVal);
+NumBits = 8;
+Scale = 4;
+break;
+ case ARMII::AddrMode5FP16:
+if (ARM_AM::getAM5FP16Op(OffVal) == ARM_AM::sub)
+ return false;
+OffVal = ARM_AM::getAM5FP16Offset(OffVal);
+NumBits = 8;
+Scale = 2;
+break;
+ case ARMII::AddrModeT2_i8:
+NumBits = 8;
+break;
+ case ARMII::AddrModeT2_i8s4:
+ case ARMII::AddrModeT2_ldrex:
+NumBits = 8;
+Scale = 4;
+break;
+ case ARMII::AddrModeT2_i12:
+ case ARMII::AddrMode_i12:
+NumBits = 12;
+break;
+ case ARMII::AddrModeT2_i7:
+NumBits = 7;
+break;
+ case ARMII::AddrModeT2_i7s2:
+NumBits = 7;
+Scale = 2;
+break;
+ case ARMII::AddrModeT2_i7s4:
+NumBits = 7;
+Scale = 4;
+break;
+ case ARMII::AddrModeT1_s: // SP-relative LD/ST
+NumBits = 8;
+Scale = 4;
+break;
+ default:
+llvm_unreachable("Unsupported addressing mode!");
+ }
+ // Make sure the offset is encodable for instructions that scale the
+ // immediate.
+ if (((OffVal * Scale + Fixup) & (Scale - 1)) != 0)
+return false;
+ OffVal += Fixup / Scale;
+
+ unsigned Mask = (1 << NumBits) - 1;
+
+ if (OffVal <= Mask) {
+if (Updt)
+ MI->getOperand(ImmIdx).setImm(OffVal);
+return true;
+ }
+
+ return false;
+
+}
+
bool
[llvm-branch-commits] [clang] 0c41b1c - [Driver][MachineOutliner] Support outlining option with LTO
Author: Yvan Roux
Date: 2021-01-06T16:01:38+01:00
New Revision: 0c41b1c9f93c09966b87126820d3cf41d8eebbf9
URL:
https://github.com/llvm/llvm-project/commit/0c41b1c9f93c09966b87126820d3cf41d8eebbf9
DIFF:
https://github.com/llvm/llvm-project/commit/0c41b1c9f93c09966b87126820d3cf41d8eebbf9.diff
LOG: [Driver][MachineOutliner] Support outlining option with LTO
This patch propagates the -moutline flag when LTO is enabled and avoids
passing it explicitly to the linker plugin.
Differential Revision: https://reviews.llvm.org/D93385
Added:
clang/test/Driver/arm-machine-outliner.c
Modified:
clang/lib/Driver/ToolChains/Clang.cpp
clang/lib/Driver/ToolChains/CommonArgs.cpp
clang/lib/Driver/ToolChains/CommonArgs.h
Removed:
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index f8b9bf25373e..917601836c0a 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -6396,26 +6396,7 @@ void Clang::ConstructJob(Compilation , const JobAction
,
options::OPT_fno_cxx_static_destructors, true))
CmdArgs.push_back("-fno-c++-static-destructors");
- if (Arg *A = Args.getLastArg(options::OPT_moutline,
- options::OPT_mno_outline)) {
-if (A->getOption().matches(options::OPT_moutline)) {
- // We only support -moutline in AArch64 and ARM targets right now. If
- // we're not compiling for these, emit a warning and ignore the flag.
- // Otherwise, add the proper mllvm flags.
- if (!(Triple.isARM() || Triple.isThumb() ||
-Triple.getArch() == llvm::Triple::aarch64 ||
-Triple.getArch() == llvm::Triple::aarch64_32)) {
-D.Diag(diag::warn_drv_moutline_unsupported_opt) <<
Triple.getArchName();
- } else {
-CmdArgs.push_back("-mllvm");
-CmdArgs.push_back("-enable-machine-outliner");
- }
-} else {
- // Disable all outlining behaviour.
- CmdArgs.push_back("-mllvm");
- CmdArgs.push_back("-enable-machine-outliner=never");
-}
- }
+ addMachineOutlinerArgs(D, Args, CmdArgs, Triple, /*IsLTO=*/false);
if (Arg *A = Args.getLastArg(options::OPT_moutline_atomics,
options::OPT_mno_outline_atomics)) {
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index fe5e7536d380..6a95aa5ec628 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -624,6 +624,9 @@ void tools::addLTOOptions(const ToolChain , const
ArgList ,
// Handle remarks hotness/threshold related options.
renderRemarksHotnessOptions(Args, CmdArgs);
+
+ addMachineOutlinerArgs(D, Args, CmdArgs, ToolChain.getEffectiveTriple(),
+ /*IsLTO=*/true);
}
void tools::addArchSpecificRPath(const ToolChain , const ArgList ,
@@ -1586,3 +1589,36 @@ unsigned tools::getOrCheckAMDGPUCodeObjectVersion(
}
return CodeObjVer;
}
+
+void tools::addMachineOutlinerArgs(const Driver ,
+ const llvm::opt::ArgList ,
+ llvm::opt::ArgStringList ,
+ const llvm::Triple , bool IsLTO) {
+ auto addArg = [&, IsLTO](const Twine ) {
+if (IsLTO) {
+ CmdArgs.push_back(Args.MakeArgString("-plugin-opt=" + Arg));
+} else {
+ CmdArgs.push_back("-mllvm");
+ CmdArgs.push_back(Args.MakeArgString(Arg));
+}
+ };
+
+ if (Arg *A = Args.getLastArg(options::OPT_moutline,
+ options::OPT_mno_outline)) {
+if (A->getOption().matches(options::OPT_moutline)) {
+ // We only support -moutline in AArch64 and ARM targets right now. If
+ // we're not compiling for these, emit a warning and ignore the flag.
+ // Otherwise, add the proper mllvm flags.
+ if (!(Triple.isARM() || Triple.isThumb() ||
+Triple.getArch() == llvm::Triple::aarch64 ||
+Triple.getArch() == llvm::Triple::aarch64_32)) {
+D.Diag(diag::warn_drv_moutline_unsupported_opt) <<
Triple.getArchName();
+ } else {
+addArg(Twine("-enable-machine-outliner"));
+ }
+} else {
+ // Disable all outlining behaviour.
+ addArg(Twine("-enable-machine-outliner=never"));
+}
+ }
+}
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.h
b/clang/lib/Driver/ToolChains/CommonArgs.h
index 9a365f376022..187c340d1c3c 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.h
+++ b/clang/lib/Driver/ToolChains/CommonArgs.h
@@ -141,6 +141,10 @@ void addX86AlignBranchArgs(const Driver , const
llvm::opt::ArgList ,
unsigned getOrCheckAMDGPUCodeObjectVersion(const Driver ,
const llvm::opt::ArgList ,
bool Diagnose = false);
+
+void addMachineOutlinerArgs(const
[llvm-branch-commits] [llvm] 923ca0b - [ARM][MachineOutliner] Fix costs model.
Author: Yvan Roux
Date: 2020-12-17T16:08:23+01:00
New Revision: 923ca0b411f78a3d218ff660a5b7a8b9099bdaa4
URL:
https://github.com/llvm/llvm-project/commit/923ca0b411f78a3d218ff660a5b7a8b9099bdaa4
DIFF:
https://github.com/llvm/llvm-project/commit/923ca0b411f78a3d218ff660a5b7a8b9099bdaa4.diff
LOG: [ARM][MachineOutliner] Fix costs model.
Fix candidates calls costs models allocation and prepare stack fixups
handling.
Differential Revision: https://reviews.llvm.org/D92933
Added:
llvm/test/CodeGen/ARM/machine-outliner-stack-use.mir
Modified:
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/test/CodeGen/ARM/machine-outliner-calls.mir
Removed:
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 20823ee6d44a..2d937930d89f 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -5824,31 +5824,43 @@ outliner::OutlinedFunction
ARMBaseInstrInfo::getOutliningCandidateInfo(
else if (C.UsedInSequence.available(ARM::SP)) {
NumBytesNoStackCalls += Costs.CallDefault;
C.setCallInfo(MachineOutlinerDefault, Costs.CallDefault);
-SetCandidateCallInfo(MachineOutlinerDefault, Costs.CallDefault);
CandidatesWithoutStackFixups.push_back(C);
- } else
-return outliner::OutlinedFunction();
-}
+ }
-// Does every candidate's MBB contain a call? If so, then we might have a
-// call in the range.
-if (FlagsSetInAll & MachineOutlinerMBBFlags::HasCalls) {
- // check if the range contains a call. These require a save + restore of
- // the link register.
- if (std::any_of(FirstCand.front(), FirstCand.back(),
- [](const MachineInstr ) { return MI.isCall(); }))
-NumBytesToCreateFrame += Costs.SaveRestoreLROnStack;
-
- // Handle the last instruction separately. If it is tail call, then the
- // last instruction is a call, we don't want to save + restore in this
- // case. However, it could be possible that the last instruction is a
- // call without it being valid to tail call this sequence. We should
- // consider this as well.
- else if (FrameID != MachineOutlinerThunk &&
- FrameID != MachineOutlinerTailCall &&
FirstCand.back()->isCall())
-NumBytesToCreateFrame += Costs.SaveRestoreLROnStack;
+ // If we outline this, we need to modify the stack. Pretend we don't
+ // outline this by saving all of its bytes.
+ else
+NumBytesNoStackCalls += SequenceSize;
}
-RepeatedSequenceLocs = CandidatesWithoutStackFixups;
+
+// If there are no places where we have to save LR, then note that we don't
+// have to update the stack. Otherwise, give every candidate the default
+// call type
+if (NumBytesNoStackCalls <=
+RepeatedSequenceLocs.size() * Costs.CallDefault) {
+ RepeatedSequenceLocs = CandidatesWithoutStackFixups;
+ FrameID = MachineOutlinerNoLRSave;
+} else
+ SetCandidateCallInfo(MachineOutlinerDefault, Costs.CallDefault);
+ }
+
+ // Does every candidate's MBB contain a call? If so, then we might have a
+ // call in the range.
+ if (FlagsSetInAll & MachineOutlinerMBBFlags::HasCalls) {
+// check if the range contains a call. These require a save + restore of
+// the link register.
+if (std::any_of(FirstCand.front(), FirstCand.back(),
+[](const MachineInstr ) { return MI.isCall(); }))
+ NumBytesToCreateFrame += Costs.SaveRestoreLROnStack;
+
+// Handle the last instruction separately. If it is tail call, then the
+// last instruction is a call, we don't want to save + restore in this
+// case. However, it could be possible that the last instruction is a
+// call without it being valid to tail call this sequence. We should
+// consider this as well.
+else if (FrameID != MachineOutlinerThunk &&
+ FrameID != MachineOutlinerTailCall && FirstCand.back()->isCall())
+ NumBytesToCreateFrame += Costs.SaveRestoreLROnStack;
}
return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
diff --git a/llvm/test/CodeGen/ARM/machine-outliner-calls.mir
b/llvm/test/CodeGen/ARM/machine-outliner-calls.mir
index a9a2a1357e10..f18eeb81a35b 100644
--- a/llvm/test/CodeGen/ARM/machine-outliner-calls.mir
+++ b/llvm/test/CodeGen/ARM/machine-outliner-calls.mir
@@ -88,15 +88,15 @@ body: |
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
- ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_3
+ ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_4
; CHECK: bb.1:
- ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_3
+ ; CHECK: tBL 14 /* CC::al */, $noreg,
[llvm-branch-commits] [lld] 03a77d0 - [LLD][ELF] Fix typo in relocation-model-pic.ll
Author: Yvan Roux Date: 2020-12-09T15:38:50+01:00 New Revision: 03a77d04b412df5cc2a43b9708466a4928df60b1 URL: https://github.com/llvm/llvm-project/commit/03a77d04b412df5cc2a43b9708466a4928df60b1 DIFF: https://github.com/llvm/llvm-project/commit/03a77d04b412df5cc2a43b9708466a4928df60b1.diff LOG: [LLD][ELF] Fix typo in relocation-model-pic.ll Should fix non-x86 bot failures. Added: Modified: lld/test/ELF/lto/relocation-model-pic.ll Removed: diff --git a/lld/test/ELF/lto/relocation-model-pic.ll b/lld/test/ELF/lto/relocation-model-pic.ll index f0eae4685392..d3242fdb8d66 100644 --- a/lld/test/ELF/lto/relocation-model-pic.ll +++ b/lld/test/ELF/lto/relocation-model-pic.ll @@ -1,4 +1,4 @@ -; REQUIRE: x86 +; REQUIRES: x86 ; RUN: llvm-as %s -o %t.o ; RUN: ld.lld %t.o -o %t -save-temps -shared ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
