[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)
https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/92871 This doesn't take effect as we have overrided `enablePostRAScheduler` and we should use the `FeaturePostRAScheduler` feature in processor definitions. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: Pengcheng Wang (wangpc-pp)
Changes
This doesn't take effect as we have overrided `enablePostRAScheduler`
and we should use the `FeaturePostRAScheduler` feature in processor
definitions.
---
Full diff: https://github.com/llvm/llvm-project/pull/92871.diff
6 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64SchedA510.td (-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedA55.td (-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedA64FX.td (-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedThunderX.td (-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td (-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td (-1)
``diff
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA510.td
b/llvm/lib/Target/AArch64/AArch64SchedA510.td
index 9456878946151..715f9fe4e050e 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA510.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA510.td
@@ -21,7 +21,6 @@ def CortexA510Model : SchedMachineModel {
let LoadLatency = 3;// Cycles for loads to access the cache.
// Most loads have a latency of 2, but some have
higher latencies.
// 3 seems to be a good tradeoff
- let PostRAScheduler = 1;// Enable PostRA scheduler pass.
let CompleteModel = 0; // Covers instructions applicable to Cortex-A510.
// FIXME: Remove when all errors have been fixed.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA55.td
b/llvm/lib/Target/AArch64/AArch64SchedA55.td
index cb77be350d124..7f508062dbdde 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA55.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA55.td
@@ -26,7 +26,6 @@ def CortexA55Model : SchedMachineModel {
// a latency of 3, but some have a latency of 4
// or 5. Setting it 4 looked to be good
trade-off.
let MispredictPenalty = 8; // A branch direction mispredict.
- let PostRAScheduler = 1;// Enable PostRA scheduler pass.
let CompleteModel = 0; // Covers instructions applicable to Cortex-A55.
list UnsupportedFeatures = [HasSVE, HasMTE];
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
index d6fe84a2c9c9b..f738f754f61cd 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
@@ -17,7 +17,6 @@ def A64FXModel : SchedMachineModel {
let MispredictPenalty = 12; // Extra cycles for mispredicted branch.
// Determined via a mix of micro-arch details and experimentation.
let LoopMicroOpBufferSize = 128;
- let PostRAScheduler = 1; // Using PostRA sched.
let CompleteModel = 1;
list UnsupportedFeatures = !listconcat(SMEUnsupported.F,
SVEUnsupported.F,
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
b/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
index 8df3f56e45738..aa7456ce0d58f 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
@@ -22,7 +22,6 @@ def ThunderXT8XModel : SchedMachineModel {
let MicroOpBufferSize = 0; // ThunderX T88/T81/T83 are in-order.
let LoadLatency = 3;// Optimistic load latency.
let MispredictPenalty = 8; // Branch mispredict penalty.
- let PostRAScheduler = 1;// Use PostRA scheduler.
let CompleteModel = 1;
list UnsupportedFeatures = !listconcat(SVEUnsupported.F,
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
b/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
index ef4baa3dedff9..ad14b12d496fe 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
@@ -22,7 +22,6 @@ def ThunderX2T99Model : SchedMachineModel {
let MispredictPenalty = 12; // Extra cycles for mispredicted branch.
// Determined via a mix of micro-arch details and experimentation.
let LoopMicroOpBufferSize = 128;
- let PostRAScheduler = 1; // Using PostRA sched.
let CompleteModel = 1;
list UnsupportedFeatures = !listconcat(SVEUnsupported.F,
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
b/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
index 796bd4b8b5c9a..29e2537dd92aa 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
@@ -21,7 +21,6 @@ def ThunderX3T110Model : SchedMachineModel {
let MispredictPenalty = 12; // Extra cycles for mispredicted branch.
// Determined via a mix of micro-arch details and experimentation.
let LoopMicroOpBufferSize = 128; // FIXME: might be much bigger in TX3.
- let PostRAScheduler = 1; // Using PostRA sched.
let CompleteModel = 1;
list UnsupportedFeatures = !listconcat(SVEUnsupported.F,
``
https://github.com/llvm/llvm-proje
[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)
https://github.com/asl requested changes to this pull request. Submit your PRs to `main` branch https://github.com/llvm/llvm-project/pull/92871 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)
wangpc-pp wrote: > Submit your PRs to `main` branch I used [spr](https://getcord.github.io/spr/) to create this PR, so I think it's OK. https://github.com/llvm/llvm-project/pull/92871 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)
dc03-work wrote: > > Submit your PRs to `main` branch > > I used [spr](https://getcord.github.io/spr/) to create this PR, so I think > it's OK. No, your target branch is wrong. Either you should want to merge into `main` or into a branch for another PR created by `spr`. However, in this case it appears you are targeting the same branch as your source. https://github.com/llvm/llvm-project/pull/92871 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)
wangpc-pp wrote: > > > Submit your PRs to `main` branch > > > > > > I used [spr](https://getcord.github.io/spr/) to create this PR, so I think > > it's OK. > > No, your target branch is wrong. Either you should want to merge into `main` > or into a branch for another PR created by `spr`. However, in this case it > appears you are targeting the same branch as your source. These are two different branches: wangpc-pp wants to merge 1 commit into users/wangpc-pp/spr/main.aarch64-remove-usage-of-postrascheduler from users/wangpc-pp/spr/aarch64-remove-usage-of-postrascheduler https://github.com/llvm/llvm-project/pull/92871 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)
dc03-work wrote: > > > > Submit your PRs to `main` branch > > > > > > > > > I used [spr](https://getcord.github.io/spr/) to create this PR, so I > > > think it's OK. > > > > > > No, your target branch is wrong. Either you should want to merge into > > `main` or into a branch for another PR created by `spr`. However, in this > > case it appears you are targeting the same branch as your source. > > These are two different branches: wangpc-pp wants to merge 1 commit into > users/wangpc-pp/spr/main.aarch64-remove-usage-of-postrascheduler from > users/wangpc-pp/spr/aarch64-remove-usage-of-postrascheduler Okay, but looking at the commits of the target: https://github.com/llvm/llvm-project/commits/users/wangpc-pp/spr/main.aarch64-remove-usage-of-postrascheduler/, it appears that spr has squashed all main commits into one commit. Anyways, this isn't the main branch. Change your PR to target the `main` branch. https://github.com/llvm/llvm-project/pull/92871 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/92871 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/92871 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)
wangpc-pp wrote: These branches are created by `spr`, which is out of my control, and we can merge it into `main` branch via `spr land`. These branches are just magics behind `spr`, please don't obsess over this. `spr` is a tool that the community suggests, I have used it for a long time and I haven't met any issue. https://github.com/llvm/llvm-project/pull/92871 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
