[llvm-branch-commits] [clang] [llvm] release/18.x: MIPS: Fix asm constraints "f" and "r" for softfloat (#79116) (PR #83105)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/83105 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] release/18.x: MIPS: Fix asm constraints "f" and "r" for softfloat (#79116) (PR #83105)
https://github.com/llvmbot updated
https://github.com/llvm/llvm-project/pull/83105
>From 461274b81d8641eab64d494accddc81d7db8a09e Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 27 Feb 2024 14:08:36 +0800
Subject: [PATCH] MIPS: Fix asm constraints "f" and "r" for softfloat (#79116)
This include 2 fixes:
1. Disallow 'f' for softfloat.
2. Allow 'r' for softfloat.
Currently, 'f' is accpeted by clang, then LLVM meets an internal error.
'r' is rejected by LLVM by: couldn't allocate input reg for constraint
'r'.
Fixes: #64241, #63632
-
Co-authored-by: Fangrui Song
(cherry picked from commit c88beb4112d5bbf07d76a615ab7f13ba2ba023e6)
---
clang/lib/Basic/Targets/Mips.h| 4 +-
.../CodeGen/Mips/inline-asm-constraints.c | 11 +
clang/test/Sema/inline-asm-validate-mips.c| 9
llvm/lib/Target/Mips/MipsISelLowering.cpp | 10 ++--
.../Mips/inlineasm-constraints-softfloat.ll | 48 +++
5 files changed, 78 insertions(+), 4 deletions(-)
create mode 100644 clang/test/CodeGen/Mips/inline-asm-constraints.c
create mode 100644 clang/test/Sema/inline-asm-validate-mips.c
create mode 100644 llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index f46b95abfd75c7..23d4e1b598fa1e 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -237,12 +237,14 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
case 'r': // CPU registers.
case 'd': // Equivalent to "r" unless generating MIPS16 code.
case 'y': // Equivalent to "r", backward compatibility only.
-case 'f': // floating-point registers.
case 'c': // $25 for indirect jumps
case 'l': // lo register
case 'x': // hilo register pair
Info.setAllowsRegister();
return true;
+case 'f': // floating-point registers.
+ Info.setAllowsRegister();
+ return FloatABI != SoftFloat;
case 'I': // Signed 16-bit constant
case 'J': // Integer 0
case 'K': // Unsigned 16-bit constant
diff --git a/clang/test/CodeGen/Mips/inline-asm-constraints.c
b/clang/test/CodeGen/Mips/inline-asm-constraints.c
new file mode 100644
index 00..88afe8735083b4
--- /dev/null
+++ b/clang/test/CodeGen/Mips/inline-asm-constraints.c
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -emit-llvm -triple mips -target-feature +soft-float %s -o -
| FileCheck %s --check-prefix=SOFT_FLOAT
+
+// SOFT_FLOAT: call void asm sideeffect "", "r,~{$1}"(float %1)
+void read_float(float *p) {
+ __asm__("" ::"r"(*p));
+}
+
+// SOFT_FLOAT: call void asm sideeffect "", "r,~{$1}"(double %1)
+void read_double(double *p) {
+ __asm__("" :: "r"(*p));
+}
diff --git a/clang/test/Sema/inline-asm-validate-mips.c
b/clang/test/Sema/inline-asm-validate-mips.c
new file mode 100644
index 00..7da248fe417b5c
--- /dev/null
+++ b/clang/test/Sema/inline-asm-validate-mips.c
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -triple mips64 -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple mips64 -target-feature +soft-float -fsyntax-only
-verify=softfloat %s
+
+// expected-no-diagnostics
+
+void test_f(float p) {
+ float result = p;
+ __asm__("" :: "f"(result)); // softfloat-error{{invalid input constraint 'f'
in asm}}
+}
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp
b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index d431d3d91494f6..88b226eaaccfab 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4128,14 +4128,18 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
case 'y': // Same as 'r'. Exists for compatibility.
case 'r':
- if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 || VT == MVT::i1) {
+ if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
+ VT == MVT::i1) ||
+ (VT == MVT::f32 && Subtarget.useSoftFloat())) {
if (Subtarget.inMips16Mode())
return std::make_pair(0U, ::CPU16RegsRegClass);
return std::make_pair(0U, ::GPR32RegClass);
}
- if (VT == MVT::i64 && !Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ !Subtarget.isGP64bit())
return std::make_pair(0U, ::GPR32RegClass);
- if (VT == MVT::i64 && Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ Subtarget.isGP64bit())
return std::make_pair(0U, ::GPR64RegClass);
// This will generate an error message
return std::make_pair(0U, nullptr);
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
b/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
new file mode 100644
index 00..705570f808ce00
--- /dev/null
+++
[llvm-branch-commits] [clang] [llvm] release/18.x: MIPS: Fix asm constraints "f" and "r" for softfloat (#79116) (PR #83105)
https://github.com/MaskRay approved this pull request. https://github.com/llvm/llvm-project/pull/83105 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] release/18.x: MIPS: Fix asm constraints "f" and "r" for softfloat (#79116) (PR #83105)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: None (llvmbot)
Changes
Backport c88beb4112d5bbf07d76a615ab7f13ba2ba023e6
Requested by: @brad0
---
Full diff: https://github.com/llvm/llvm-project/pull/83105.diff
5 Files Affected:
- (modified) clang/lib/Basic/Targets/Mips.h (+3-1)
- (added) clang/test/CodeGen/Mips/inline-asm-constraints.c (+11)
- (added) clang/test/Sema/inline-asm-validate-mips.c (+9)
- (modified) llvm/lib/Target/Mips/MipsISelLowering.cpp (+7-3)
- (added) llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll (+48)
``diff
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index f46b95abfd75c7..23d4e1b598fa1e 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -237,12 +237,14 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
case 'r': // CPU registers.
case 'd': // Equivalent to "r" unless generating MIPS16 code.
case 'y': // Equivalent to "r", backward compatibility only.
-case 'f': // floating-point registers.
case 'c': // $25 for indirect jumps
case 'l': // lo register
case 'x': // hilo register pair
Info.setAllowsRegister();
return true;
+case 'f': // floating-point registers.
+ Info.setAllowsRegister();
+ return FloatABI != SoftFloat;
case 'I': // Signed 16-bit constant
case 'J': // Integer 0
case 'K': // Unsigned 16-bit constant
diff --git a/clang/test/CodeGen/Mips/inline-asm-constraints.c
b/clang/test/CodeGen/Mips/inline-asm-constraints.c
new file mode 100644
index 00..88afe8735083b4
--- /dev/null
+++ b/clang/test/CodeGen/Mips/inline-asm-constraints.c
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -emit-llvm -triple mips -target-feature +soft-float %s -o -
| FileCheck %s --check-prefix=SOFT_FLOAT
+
+// SOFT_FLOAT: call void asm sideeffect "", "r,~{$1}"(float %1)
+void read_float(float *p) {
+ __asm__("" ::"r"(*p));
+}
+
+// SOFT_FLOAT: call void asm sideeffect "", "r,~{$1}"(double %1)
+void read_double(double *p) {
+ __asm__("" :: "r"(*p));
+}
diff --git a/clang/test/Sema/inline-asm-validate-mips.c
b/clang/test/Sema/inline-asm-validate-mips.c
new file mode 100644
index 00..7da248fe417b5c
--- /dev/null
+++ b/clang/test/Sema/inline-asm-validate-mips.c
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -triple mips64 -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple mips64 -target-feature +soft-float -fsyntax-only
-verify=softfloat %s
+
+// expected-no-diagnostics
+
+void test_f(float p) {
+ float result = p;
+ __asm__("" :: "f"(result)); // softfloat-error{{invalid input constraint 'f'
in asm}}
+}
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp
b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index d431d3d91494f6..88b226eaaccfab 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4128,14 +4128,18 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
case 'y': // Same as 'r'. Exists for compatibility.
case 'r':
- if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 || VT == MVT::i1) {
+ if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
+ VT == MVT::i1) ||
+ (VT == MVT::f32 && Subtarget.useSoftFloat())) {
if (Subtarget.inMips16Mode())
return std::make_pair(0U, ::CPU16RegsRegClass);
return std::make_pair(0U, ::GPR32RegClass);
}
- if (VT == MVT::i64 && !Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ !Subtarget.isGP64bit())
return std::make_pair(0U, ::GPR32RegClass);
- if (VT == MVT::i64 && Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ Subtarget.isGP64bit())
return std::make_pair(0U, ::GPR64RegClass);
// This will generate an error message
return std::make_pair(0U, nullptr);
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
b/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
new file mode 100644
index 00..705570f808ce00
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -march=mips < %s | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -march=mips64 < %s | FileCheck %s --check-prefix=MIPS64
+
+define dso_local void @read_double(ptr nocapture noundef readonly %0)
local_unnamed_addr #0 {
+; MIPS32-LABEL: read_double:
+; MIPS32: # %bb.0:
+; MIPS32-NEXT:lw $2, 4($4)
+; MIPS32-NEXT:lw $3, 0($4)
+; MIPS32-NEXT:#APP
+; MIPS32-NEXT:#NO_APP
+; MIPS32-NEXT:jr $ra
+; MIPS32-NEXT:nop
+;
+; MIPS64-LABEL: read_double:
+; MIPS64: # %bb.0:
+; MIPS64-NEXT:ld
[llvm-branch-commits] [clang] [llvm] release/18.x: MIPS: Fix asm constraints "f" and "r" for softfloat (#79116) (PR #83105)
llvmbot wrote: @MaskRay What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/83105 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] release/18.x: MIPS: Fix asm constraints "f" and "r" for softfloat (#79116) (PR #83105)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/83105 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] release/18.x: MIPS: Fix asm constraints "f" and "r" for softfloat (#79116) (PR #83105)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/83105
Backport c88beb4112d5bbf07d76a615ab7f13ba2ba023e6
Requested by: @brad0
>From e223881b2e4c0b1a02f9ea7926f69fce33534a94 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 27 Feb 2024 14:08:36 +0800
Subject: [PATCH] MIPS: Fix asm constraints "f" and "r" for softfloat (#79116)
This include 2 fixes:
1. Disallow 'f' for softfloat.
2. Allow 'r' for softfloat.
Currently, 'f' is accpeted by clang, then LLVM meets an internal error.
'r' is rejected by LLVM by: couldn't allocate input reg for constraint
'r'.
Fixes: #64241, #63632
-
Co-authored-by: Fangrui Song
(cherry picked from commit c88beb4112d5bbf07d76a615ab7f13ba2ba023e6)
---
clang/lib/Basic/Targets/Mips.h| 4 +-
.../CodeGen/Mips/inline-asm-constraints.c | 11 +
clang/test/Sema/inline-asm-validate-mips.c| 9
llvm/lib/Target/Mips/MipsISelLowering.cpp | 10 ++--
.../Mips/inlineasm-constraints-softfloat.ll | 48 +++
5 files changed, 78 insertions(+), 4 deletions(-)
create mode 100644 clang/test/CodeGen/Mips/inline-asm-constraints.c
create mode 100644 clang/test/Sema/inline-asm-validate-mips.c
create mode 100644 llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index f46b95abfd75c7..23d4e1b598fa1e 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -237,12 +237,14 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
case 'r': // CPU registers.
case 'd': // Equivalent to "r" unless generating MIPS16 code.
case 'y': // Equivalent to "r", backward compatibility only.
-case 'f': // floating-point registers.
case 'c': // $25 for indirect jumps
case 'l': // lo register
case 'x': // hilo register pair
Info.setAllowsRegister();
return true;
+case 'f': // floating-point registers.
+ Info.setAllowsRegister();
+ return FloatABI != SoftFloat;
case 'I': // Signed 16-bit constant
case 'J': // Integer 0
case 'K': // Unsigned 16-bit constant
diff --git a/clang/test/CodeGen/Mips/inline-asm-constraints.c
b/clang/test/CodeGen/Mips/inline-asm-constraints.c
new file mode 100644
index 00..88afe8735083b4
--- /dev/null
+++ b/clang/test/CodeGen/Mips/inline-asm-constraints.c
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -emit-llvm -triple mips -target-feature +soft-float %s -o -
| FileCheck %s --check-prefix=SOFT_FLOAT
+
+// SOFT_FLOAT: call void asm sideeffect "", "r,~{$1}"(float %1)
+void read_float(float *p) {
+ __asm__("" ::"r"(*p));
+}
+
+// SOFT_FLOAT: call void asm sideeffect "", "r,~{$1}"(double %1)
+void read_double(double *p) {
+ __asm__("" :: "r"(*p));
+}
diff --git a/clang/test/Sema/inline-asm-validate-mips.c
b/clang/test/Sema/inline-asm-validate-mips.c
new file mode 100644
index 00..7da248fe417b5c
--- /dev/null
+++ b/clang/test/Sema/inline-asm-validate-mips.c
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -triple mips64 -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple mips64 -target-feature +soft-float -fsyntax-only
-verify=softfloat %s
+
+// expected-no-diagnostics
+
+void test_f(float p) {
+ float result = p;
+ __asm__("" :: "f"(result)); // softfloat-error{{invalid input constraint 'f'
in asm}}
+}
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp
b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index d431d3d91494f6..88b226eaaccfab 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4128,14 +4128,18 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
case 'y': // Same as 'r'. Exists for compatibility.
case 'r':
- if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 || VT == MVT::i1) {
+ if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
+ VT == MVT::i1) ||
+ (VT == MVT::f32 && Subtarget.useSoftFloat())) {
if (Subtarget.inMips16Mode())
return std::make_pair(0U, ::CPU16RegsRegClass);
return std::make_pair(0U, ::GPR32RegClass);
}
- if (VT == MVT::i64 && !Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ !Subtarget.isGP64bit())
return std::make_pair(0U, ::GPR32RegClass);
- if (VT == MVT::i64 && Subtarget.isGP64bit())
+ if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) &&
+ Subtarget.isGP64bit())
return std::make_pair(0U, ::GPR64RegClass);
// This will generate an error message
return std::make_pair(0U, nullptr);
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
b/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
new file mode 100644
index
