[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
https://github.com/ilovepi created https://github.com/llvm/llvm-project/pull/84598 This patch adds basic support for the Tag_RISCV_x3_reg_usage attribute specified in: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_x3_reg_usage-16-uleb128value It adds support for merging the x3_reg_usage attribute in the linker, and basic support for the attribute in attribute parser. Enabling this feature will allow targets to avoid challenges with mixing object files with different expectations for how x3/gp is used. Merging x3_reg_usage tags with different values is considered an error, with one exception. The value 0 can merge with 1 or 2 value. After the merge, the resulting value will be the non-zero one. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
llvmbot wrote:
@llvm/pr-subscribers-mc
Author: Paul Kirth (ilovepi)
Changes
This patch adds basic support for the Tag_RISCV_x3_reg_usage attribute
specified in:
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_x3_reg_usage-16-uleb128value
It adds support for merging the x3_reg_usage attribute in the linker,
and basic support for the attribute in attribute parser.
Enabling this feature will allow targets to avoid challenges with mixing
object files with different expectations for how x3/gp is used.
Merging x3_reg_usage tags with different values is considered an error,
with one exception. The value 0 can merge with 1 or 2 value. After the
merge, the resulting value will be the non-zero one.
---
Full diff: https://github.com/llvm/llvm-project/pull/84598.diff
9 Files Affected:
- (modified) lld/ELF/Arch/RISCV.cpp (+12)
- (modified) lld/test/ELF/riscv-attributes.s (+51)
- (modified) llvm/include/llvm/Support/RISCVAttributeParser.h (+1)
- (modified) llvm/include/llvm/Support/RISCVAttributes.h (+10)
- (modified) llvm/lib/Support/RISCVAttributeParser.cpp (+7)
- (modified) llvm/lib/Support/RISCVAttributes.cpp (+1)
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+5)
- (modified) llvm/test/MC/RISCV/attribute.s (+3)
- (modified) llvm/test/MC/RISCV/invalid-attribute.s (+3)
``diff
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index e44583fb80fd31..f3b134144b654b 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1224,6 +1224,18 @@ mergeAttributesSection(const
SmallVector §ions) {
}
}
continue;
+
+ case llvm::RISCVAttrs::AttrType::X3_REG_USAGE:
+if (auto i = parser.getAttributeValue(tag.attr)) {
+ auto r = merged.intAttr.try_emplace(tag.attr, *i);
+ if (r.second) {
+firstX3RegUse = sec;
+ } else {
+mergeX3RegUse(merged.intAttr, firstX3RegUse, sec,
+ r.first->getSecond(), *i);
+ }
+}
+continue;
}
// Fallback for deprecated priv_spec* and other unknown attributes:
retain
diff --git a/lld/test/ELF/riscv-attributes.s b/lld/test/ELF/riscv-attributes.s
index 964fec43b52847..43438b238b5d6b 100644
--- a/lld/test/ELF/riscv-attributes.s
+++ b/lld/test/ELF/riscv-attributes.s
@@ -68,6 +68,23 @@
# RUN: ld.lld atomic_abi_unknown.o atomic_abi_A7.o -o atomic_abi_A7_unknown
# RUN: llvm-readobj -A atomic_abi_A7_unknown | FileCheck %s
--check-prefix=UNKNOWN_A7
+
+# RUN: llvm-mc -filetype=obj -triple=riscv64 x3_reg_usage_unknown.s -o
x3_reg_usage_unknown.o
+# RUN: llvm-mc -filetype=obj -triple=riscv64 x3_reg_usage_gp.s -o
x3_reg_usage_gp.o
+# RUN: llvm-mc -filetype=obj -triple=riscv64 x3_reg_usage_scs.s -o
x3_reg_usage_scs.o
+# RUN: llvm-mc -filetype=obj -triple=riscv64 x3_reg_usage_tmp.s -o
x3_reg_usage_tmp.o
+
+# RUN: not ld.lld x3_reg_usage_scs.o x3_reg_usage_gp.o -o /dev/null 2>&1 |
FileCheck %s --check-prefix=X3_REG_SCS_GP --implicit-check-not=error:
+# X3_REG_SCS_GP: error: x3_reg_usage_scs.o:(.riscv.attributes) has
x3_reg_usage=2 but x3_reg_usage_gp.o:(.riscv.attributes) has x3_reg_usage=1
+
+# RUN: not ld.lld x3_reg_usage_scs.o x3_reg_usage_tmp.o -o /dev/null 2>&1 |
FileCheck %s --check-prefix=X3_REG_SCS_TMP --implicit-check-not=error:
+# X3_REG_SCS_TMP: error: x3_reg_usage_scs.o:(.riscv.attributes) has
x3_reg_usage=2 but x3_reg_usage_tmp.o:(.riscv.attributes) has x3_reg_usage=3
+
+
+# RUN: ld.lld x3_reg_usage_scs.o x3_reg_usage_unknown.o -o
x3_reg_usage_scs_unknown
+# RUN: llvm-readobj -A x3_reg_usage_scs_unknown | FileCheck %s
--check-prefix=X3_REG_SCS_UKNOWN
+
+
## The deprecated priv_spec is not handled as GNU ld does.
## Differing priv_spec attributes lead to an absent attribute.
# RUN: llvm-mc -filetype=obj -triple=riscv64 diff_priv_spec.s -o
diff_priv_spec.o
@@ -412,6 +429,40 @@
# A6S_A7: }
# A6S_A7: }
+#--- x3_reg_usage_unknown.s
+.attribute x3_reg_usage, 0
+
+#--- x3_reg_usage_gp.s
+.attribute x3_reg_usage, 1
+
+#--- x3_reg_usage_scs.s
+.attribute x3_reg_usage, 2
+
+#--- x3_reg_usage_tmp.s
+.attribute x3_reg_usage, 3
+
+
+# X3_REG_SCS_UKNOWN: BuildAttributes {
+# X3_REG_SCS_UKNOWN: FormatVersion: 0x41
+# X3_REG_SCS_UKNOWN: Section 1 {
+# X3_REG_SCS_UKNOWN: SectionLength: 17
+# X3_REG_SCS_UKNOWN: Vendor: riscv
+# X3_REG_SCS_UKNOWN: Tag: Tag_File (0x1)
+# X3_REG_SCS_UKNOWN: Size: 7
+# X3_REG_SCS_UKNOWN: FileAttributes {
+# X3_REG_SCS_UKNOWN: Attribute {
+# X3_REG_SCS_UKNOWN: Tag: 16
+# X3_REG_SCS_UKNOWN: Value: 2
+# X3_REG_SCS_UKNOWN: TagName: x3_reg_usage
+# X3_REG_SCS_UKNOWN: Description: X3 reg usage is 2
+# X3_REG_SCS_UKNOWN: }
+# X3_REG_SCS_UKNOWN: }
+# X3_REG_SCS_UKNOWN: }
+# X3_REG_SCS_UKNOWN: }
+
+
+
+
#--- unknown13.s
.attribute 13, "0"
#--- unknown13a.s
diff --git a/llvm/include/llvm/Support/RISCVAttributeParser.h
b/llvm/include/llvm/Support/
[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
llvmbot wrote:
@llvm/pr-subscribers-lld-elf
@llvm/pr-subscribers-lld
Author: Paul Kirth (ilovepi)
Changes
This patch adds basic support for the Tag_RISCV_x3_reg_usage attribute
specified in:
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_x3_reg_usage-16-uleb128value
It adds support for merging the x3_reg_usage attribute in the linker,
and basic support for the attribute in attribute parser.
Enabling this feature will allow targets to avoid challenges with mixing
object files with different expectations for how x3/gp is used.
Merging x3_reg_usage tags with different values is considered an error,
with one exception. The value 0 can merge with 1 or 2 value. After the
merge, the resulting value will be the non-zero one.
---
Full diff: https://github.com/llvm/llvm-project/pull/84598.diff
9 Files Affected:
- (modified) lld/ELF/Arch/RISCV.cpp (+12)
- (modified) lld/test/ELF/riscv-attributes.s (+51)
- (modified) llvm/include/llvm/Support/RISCVAttributeParser.h (+1)
- (modified) llvm/include/llvm/Support/RISCVAttributes.h (+10)
- (modified) llvm/lib/Support/RISCVAttributeParser.cpp (+7)
- (modified) llvm/lib/Support/RISCVAttributes.cpp (+1)
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+5)
- (modified) llvm/test/MC/RISCV/attribute.s (+3)
- (modified) llvm/test/MC/RISCV/invalid-attribute.s (+3)
``diff
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index e44583fb80fd31..f3b134144b654b 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1224,6 +1224,18 @@ mergeAttributesSection(const
SmallVector §ions) {
}
}
continue;
+
+ case llvm::RISCVAttrs::AttrType::X3_REG_USAGE:
+if (auto i = parser.getAttributeValue(tag.attr)) {
+ auto r = merged.intAttr.try_emplace(tag.attr, *i);
+ if (r.second) {
+firstX3RegUse = sec;
+ } else {
+mergeX3RegUse(merged.intAttr, firstX3RegUse, sec,
+ r.first->getSecond(), *i);
+ }
+}
+continue;
}
// Fallback for deprecated priv_spec* and other unknown attributes:
retain
diff --git a/lld/test/ELF/riscv-attributes.s b/lld/test/ELF/riscv-attributes.s
index 964fec43b52847..43438b238b5d6b 100644
--- a/lld/test/ELF/riscv-attributes.s
+++ b/lld/test/ELF/riscv-attributes.s
@@ -68,6 +68,23 @@
# RUN: ld.lld atomic_abi_unknown.o atomic_abi_A7.o -o atomic_abi_A7_unknown
# RUN: llvm-readobj -A atomic_abi_A7_unknown | FileCheck %s
--check-prefix=UNKNOWN_A7
+
+# RUN: llvm-mc -filetype=obj -triple=riscv64 x3_reg_usage_unknown.s -o
x3_reg_usage_unknown.o
+# RUN: llvm-mc -filetype=obj -triple=riscv64 x3_reg_usage_gp.s -o
x3_reg_usage_gp.o
+# RUN: llvm-mc -filetype=obj -triple=riscv64 x3_reg_usage_scs.s -o
x3_reg_usage_scs.o
+# RUN: llvm-mc -filetype=obj -triple=riscv64 x3_reg_usage_tmp.s -o
x3_reg_usage_tmp.o
+
+# RUN: not ld.lld x3_reg_usage_scs.o x3_reg_usage_gp.o -o /dev/null 2>&1 |
FileCheck %s --check-prefix=X3_REG_SCS_GP --implicit-check-not=error:
+# X3_REG_SCS_GP: error: x3_reg_usage_scs.o:(.riscv.attributes) has
x3_reg_usage=2 but x3_reg_usage_gp.o:(.riscv.attributes) has x3_reg_usage=1
+
+# RUN: not ld.lld x3_reg_usage_scs.o x3_reg_usage_tmp.o -o /dev/null 2>&1 |
FileCheck %s --check-prefix=X3_REG_SCS_TMP --implicit-check-not=error:
+# X3_REG_SCS_TMP: error: x3_reg_usage_scs.o:(.riscv.attributes) has
x3_reg_usage=2 but x3_reg_usage_tmp.o:(.riscv.attributes) has x3_reg_usage=3
+
+
+# RUN: ld.lld x3_reg_usage_scs.o x3_reg_usage_unknown.o -o
x3_reg_usage_scs_unknown
+# RUN: llvm-readobj -A x3_reg_usage_scs_unknown | FileCheck %s
--check-prefix=X3_REG_SCS_UKNOWN
+
+
## The deprecated priv_spec is not handled as GNU ld does.
## Differing priv_spec attributes lead to an absent attribute.
# RUN: llvm-mc -filetype=obj -triple=riscv64 diff_priv_spec.s -o
diff_priv_spec.o
@@ -412,6 +429,40 @@
# A6S_A7: }
# A6S_A7: }
+#--- x3_reg_usage_unknown.s
+.attribute x3_reg_usage, 0
+
+#--- x3_reg_usage_gp.s
+.attribute x3_reg_usage, 1
+
+#--- x3_reg_usage_scs.s
+.attribute x3_reg_usage, 2
+
+#--- x3_reg_usage_tmp.s
+.attribute x3_reg_usage, 3
+
+
+# X3_REG_SCS_UKNOWN: BuildAttributes {
+# X3_REG_SCS_UKNOWN: FormatVersion: 0x41
+# X3_REG_SCS_UKNOWN: Section 1 {
+# X3_REG_SCS_UKNOWN: SectionLength: 17
+# X3_REG_SCS_UKNOWN: Vendor: riscv
+# X3_REG_SCS_UKNOWN: Tag: Tag_File (0x1)
+# X3_REG_SCS_UKNOWN: Size: 7
+# X3_REG_SCS_UKNOWN: FileAttributes {
+# X3_REG_SCS_UKNOWN: Attribute {
+# X3_REG_SCS_UKNOWN: Tag: 16
+# X3_REG_SCS_UKNOWN: Value: 2
+# X3_REG_SCS_UKNOWN: TagName: x3_reg_usage
+# X3_REG_SCS_UKNOWN: Description: X3 reg usage is 2
+# X3_REG_SCS_UKNOWN: }
+# X3_REG_SCS_UKNOWN: }
+# X3_REG_SCS_UKNOWN: }
+# X3_REG_SCS_UKNOWN: }
+
+
+
+
#--- unknown13.s
.attribute 13, "0"
#--- unknown13a.s
diff --git a/llvm/include/llvm/Support/RISCVAttributeParser.h
[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/84598 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/84598 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/84598 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/84598 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/84598 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/84598 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/84598 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/84598 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
@@ -1136,11 +1136,35 @@ static void mergeAtomic(DenseMap
&intAttr,
};
}
+static void mergeX3RegUse(DenseMap &intAttr,
+ const InputSectionBase *oldSection,
+ const InputSectionBase *newSection,
+ unsigned int oldTag, unsigned int newTag) {
+ // X3/GP register usage ar incompatible and cannot be merged, with the
+ // exception of the UNKNOWN or 0 value
+ using RISCVAttrs::RISCVX3RegUse::X3RegUsage;
+ auto attr = RISCVAttrs::X3_REG_USAGE;
+ if (newTag == X3RegUsage::UNKNOWN)
+return;
+ if (oldTag == X3RegUsage::UNKNOWN) {
+intAttr[attr] = newTag;
topperc wrote:
Can we use the iterator from try_emplace instead of a second map lookup?
https://github.com/llvm/llvm-project/pull/84598
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[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
@@ -24,6 +24,9 @@ .attribute priv_spec_revision, 0 # CHECK: attribute 12, 0 + wangpc-pp wrote: This blank should be added in Atomic ABI PR I think. https://github.com/llvm/llvm-project/pull/84598 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
@@ -520,3 +520,8 @@ define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind {
; A6S: .attribute 14, 2
; A6C: .attribute 14, 1
}
+
wangpc-pp wrote:
No CHECKs for this test or I miss something here?
https://github.com/llvm/llvm-project/pull/84598
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[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
@@ -47,6 +48,15 @@ enum AtomicABI : unsigned {
};
} // namespace RISCVAtomicAbiTag
+namespace RISCVX3RegUse {
+enum X3RegUsage : unsigned {
+ UNKNOWN = 0,
+ GP = 0,
wangpc-pp wrote:
Copy paste mistakes? Why all 0s?
https://github.com/llvm/llvm-project/pull/84598
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[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
@@ -1136,11 +1136,35 @@ static void mergeAtomic(DenseMap
&intAttr,
};
}
+static void mergeX3RegUse(DenseMap &intAttr,
+ const InputSectionBase *oldSection,
+ const InputSectionBase *newSection,
+ unsigned int oldTag, unsigned int newTag) {
+ // X3/GP register usage ar incompatible and cannot be merged, with the
+ // exception of the UNKNOWN or 0 value
+ using RISCVAttrs::RISCVX3RegUse::X3RegUsage;
+ auto attr = RISCVAttrs::X3_REG_USAGE;
+ if (newTag == X3RegUsage::UNKNOWN)
+return;
+ if (oldTag == X3RegUsage::UNKNOWN) {
+intAttr[attr] = newTag;
ilovepi wrote:
yeah, I think that will work. Let me give that a try.
https://github.com/llvm/llvm-project/pull/84598
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[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
@@ -24,6 +24,9 @@ .attribute priv_spec_revision, 0 # CHECK: attribute 12, 0 + ilovepi wrote: Thank you. There is a good chance that is the case. https://github.com/llvm/llvm-project/pull/84598 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
ilovepi wrote: I forgot to mention that I'm still trying to figure out how to add the attribute. I know mechanically how, but AFAIK there isn't a target feature or anything we set when enabling SCS(except for Zcfiscs), so if there is an obvious way, a pointer would be welcome. I think that's something we need to set in STI, so I'm looking into changes to allow that. https://github.com/llvm/llvm-project/pull/84598 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
@@ -47,6 +48,15 @@ enum AtomicABI : unsigned {
};
} // namespace RISCVAtomicAbiTag
+namespace RISCVX3RegUse {
+enum X3RegUsage : unsigned {
+ UNKNOWN = 0,
+ GP = 0,
ilovepi wrote:
ugh, you are correct. I haven't tested this properly yet, since I'm not 100%
sure what the correct way to add the attribute will be. But I'll up date these
to have the proper values from the psABI.
https://github.com/llvm/llvm-project/pull/84598
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[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/84598 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/84598 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
