[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

2024-05-16 Thread Craig Topper via llvm-branch-commits 

https://github.com/topperc updated 
https://github.com/llvm/llvm-project/pull/92143

>From e18e442947da7801c915c04e34e397464eca5034 Mon Sep 17 00:00:00 2001
From: Craig Topper 
Date: Thu, 16 May 2024 12:27:05 -0700
Subject: [PATCH] [RISCV] Add a unaligned-scalar-mem feature like we had in
 clang 17.

This is ORed with the fast-unaligned-access feature which applies
to scalar and vector together.:
---
 llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp | 5 +++--
 llvm/lib/Target/RISCV/RISCVFeatures.td   | 5 +
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp  | 9 ++---
 llvm/test/CodeGen/RISCV/memcpy-inline.ll | 4 
 llvm/test/CodeGen/RISCV/memcpy.ll| 4 
 llvm/test/CodeGen/RISCV/memset-inline.ll | 4 
 llvm/test/CodeGen/RISCV/pr56110.ll   | 1 +
 llvm/test/CodeGen/RISCV/unaligned-load-store.ll  | 4 
 8 files changed, 31 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 
b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index 0a314fdd41cbe..89207640ee54a 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -317,8 +317,9 @@ bool 
RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
   .addReg(MBBI->getOperand(1).getReg())
   .add(MBBI->getOperand(2));
   if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
-// FIXME: Zdinx RV32 can not work on unaligned memory.
-assert(!STI->hasFastUnalignedAccess());
+// FIXME: Zdinx RV32 can not work on unaligned scalar memory.
+assert(!STI->hasFastUnalignedAccess() &&
+   !STI->enableUnalignedScalarMem());
 
 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
 MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 26451c80f57b4..1bb6b6a561f4a 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1025,6 +1025,11 @@ def FeatureFastUnalignedAccess
   "true", "Has reasonably performant unaligned "
   "loads and stores (both scalar and vector)">;
 
+def FeatureUnalignedScalarMem
+   : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",
+  "true", "Has reasonably performant unaligned scalar "
+  "loads and stores">;
+
 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
 "UsePostRAScheduler", "true", "Schedule again after register allocation">;
 
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp 
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d46093b9e260a..3fe7ddfdd4279 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1883,7 +1883,8 @@ bool 
RISCVTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
   // replace. If we don't support unaligned scalar mem, prefer the constant
   // pool.
   // TODO: Can the caller pass down the alignment?
-  if (!Subtarget.hasFastUnalignedAccess())
+  if (!Subtarget.hasFastUnalignedAccess() &&
+  !Subtarget.enableUnalignedScalarMem())
 return true;
 
   // Prefer to keep the load if it would require many instructions.
@@ -19772,8 +19773,10 @@ bool 
RISCVTargetLowering::allowsMisalignedMemoryAccesses(
 unsigned *Fast) const {
   if (!VT.isVector()) {
 if (Fast)
-  *Fast = Subtarget.hasFastUnalignedAccess();
-return Subtarget.hasFastUnalignedAccess();
+  *Fast = Subtarget.hasFastUnalignedAccess() ||
+  Subtarget.enableUnalignedScalarMem();
+return Subtarget.hasFastUnalignedAccess() ||
+   Subtarget.enableUnalignedScalarMem();
   }
 
   // All vector implementations must support element alignment
diff --git a/llvm/test/CodeGen/RISCV/memcpy-inline.ll 
b/llvm/test/CodeGen/RISCV/memcpy-inline.ll
index 343695ee37da8..709b8264b5833 100644
--- a/llvm/test/CodeGen/RISCV/memcpy-inline.ll
+++ b/llvm/test/CodeGen/RISCV/memcpy-inline.ll
@@ -7,6 +7,10 @@
 ; RUN:   | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+fast-unaligned-access \
 ; RUN:   | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
+; RUN: llc < %s -mtriple=riscv32 -mattr=+unaligned-scalar-mem \
+; RUN:   | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
+; RUN: llc < %s -mtriple=riscv64 -mattr=+unaligned-scalar-mem \
+; RUN:   | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
 
 ; --
 ; Fully unaligned cases
diff --git a/llvm/test/CodeGen/RISCV/memcpy.ll 
b/llvm/test/CodeGen/RISCV/memcpy.ll
index 12ec0881b20d9..f8f5d25947d7f 100644
--- a/llvm/test/CodeGen/RISCV/memcpy.ll
+++ b/llvm/test/CodeGen/RISCV/memcpy.ll
@@ -7,6 +7,10 @@
 ; RUN:   | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
 ; RUN: llc < %s -mtriple=riscv64 -mat

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

2024-05-16 Thread Craig Topper via llvm-branch-commits 

https://github.com/topperc edited 
https://github.com/llvm/llvm-project/pull/92143
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

2024-05-16 Thread Craig Topper via llvm-branch-commits 

topperc wrote:

> @topperc Can this be merged as is? There might not be time to get an updated 
> patch merged before the last release.

I just pushed a modified patch. What is the timeline for the last release?

https://github.com/llvm/llvm-project/pull/92143
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

2024-05-16 Thread Tom Stellard via llvm-branch-commits 

tstellar wrote:

@topperc The plan is to release Friday.  Do we have agreement on merging this 
updated patch?

https://github.com/llvm/llvm-project/pull/92143
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

2024-05-16 Thread Alex Bradbury via llvm-branch-commits 

asb wrote:

My thoughts:
* Thanks to @negge and others for clarifying who this is affecting and how
* It's very unfortunate we've broken some use cases here. Though as, by my 
understand, this is affecting people using internal flags as opposed to 
documented top-level flags I feel there's not a _strong_ obligation to fix the 
issue in a point release.
* That said, if we can fix it with minimal risk of introducing more problems 
then it would be nice to do so as long as the release managers are happy
* I think the solution of keeping fast-unaligned-access and adding 
+unaligned-scalar-mem is pragmatic
* Patch LGTM.

https://github.com/llvm/llvm-project/pull/92143
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

2024-05-16 Thread Alex Bradbury via llvm-branch-commits 

https://github.com/asb approved this pull request.


https://github.com/llvm/llvm-project/pull/92143
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

2024-05-17 Thread Luke Lau via llvm-branch-commits 

https://github.com/lukel97 approved this pull request.

Chiming in that this seems reasonable to me, given the performance impact of 
not having unaligned scalar accesses. And hopefully we can remove this one 
we're settled on a proper interface.

https://github.com/llvm/llvm-project/pull/92143
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

2024-05-17 Thread Nikita Popov via llvm-branch-commits 

nikic wrote:

The approach looks reasonable to me. 

https://github.com/llvm/llvm-project/pull/92143
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

2024-05-17 Thread Philip Reames via llvm-branch-commits 

preames wrote:

I'm fine with this approach.  No strong opinion either way, but definitely 
don't let me previous comments be blocking here.  

https://github.com/llvm/llvm-project/pull/92143
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

2024-05-17 Thread Tom Stellard via llvm-branch-commits 

https://github.com/tstellar updated 
https://github.com/llvm/llvm-project/pull/92143

>From a7cd0c61123889a632ceea67dc8c8e2c8753ae08 Mon Sep 17 00:00:00 2001
From: Craig Topper 
Date: Thu, 16 May 2024 12:27:05 -0700
Subject: [PATCH] [RISCV] Add a unaligned-scalar-mem feature like we had in
 clang 17.

This is ORed with the fast-unaligned-access feature which applies
to scalar and vector together.:
---
 llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp | 5 +++--
 llvm/lib/Target/RISCV/RISCVFeatures.td   | 5 +
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp  | 9 ++---
 llvm/test/CodeGen/RISCV/memcpy-inline.ll | 4 
 llvm/test/CodeGen/RISCV/memcpy.ll| 4 
 llvm/test/CodeGen/RISCV/memset-inline.ll | 4 
 llvm/test/CodeGen/RISCV/pr56110.ll   | 1 +
 llvm/test/CodeGen/RISCV/unaligned-load-store.ll  | 4 
 8 files changed, 31 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 
b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index 0a314fdd41cbe..89207640ee54a 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -317,8 +317,9 @@ bool 
RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
   .addReg(MBBI->getOperand(1).getReg())
   .add(MBBI->getOperand(2));
   if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
-// FIXME: Zdinx RV32 can not work on unaligned memory.
-assert(!STI->hasFastUnalignedAccess());
+// FIXME: Zdinx RV32 can not work on unaligned scalar memory.
+assert(!STI->hasFastUnalignedAccess() &&
+   !STI->enableUnalignedScalarMem());
 
 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
 MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 26451c80f57b4..1bb6b6a561f4a 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1025,6 +1025,11 @@ def FeatureFastUnalignedAccess
   "true", "Has reasonably performant unaligned "
   "loads and stores (both scalar and vector)">;
 
+def FeatureUnalignedScalarMem
+   : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",
+  "true", "Has reasonably performant unaligned scalar "
+  "loads and stores">;
+
 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
 "UsePostRAScheduler", "true", "Schedule again after register allocation">;
 
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp 
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d46093b9e260a..3fe7ddfdd4279 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1883,7 +1883,8 @@ bool 
RISCVTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
   // replace. If we don't support unaligned scalar mem, prefer the constant
   // pool.
   // TODO: Can the caller pass down the alignment?
-  if (!Subtarget.hasFastUnalignedAccess())
+  if (!Subtarget.hasFastUnalignedAccess() &&
+  !Subtarget.enableUnalignedScalarMem())
 return true;
 
   // Prefer to keep the load if it would require many instructions.
@@ -19772,8 +19773,10 @@ bool 
RISCVTargetLowering::allowsMisalignedMemoryAccesses(
 unsigned *Fast) const {
   if (!VT.isVector()) {
 if (Fast)
-  *Fast = Subtarget.hasFastUnalignedAccess();
-return Subtarget.hasFastUnalignedAccess();
+  *Fast = Subtarget.hasFastUnalignedAccess() ||
+  Subtarget.enableUnalignedScalarMem();
+return Subtarget.hasFastUnalignedAccess() ||
+   Subtarget.enableUnalignedScalarMem();
   }
 
   // All vector implementations must support element alignment
diff --git a/llvm/test/CodeGen/RISCV/memcpy-inline.ll 
b/llvm/test/CodeGen/RISCV/memcpy-inline.ll
index 343695ee37da8..709b8264b5833 100644
--- a/llvm/test/CodeGen/RISCV/memcpy-inline.ll
+++ b/llvm/test/CodeGen/RISCV/memcpy-inline.ll
@@ -7,6 +7,10 @@
 ; RUN:   | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+fast-unaligned-access \
 ; RUN:   | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
+; RUN: llc < %s -mtriple=riscv32 -mattr=+unaligned-scalar-mem \
+; RUN:   | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
+; RUN: llc < %s -mtriple=riscv64 -mattr=+unaligned-scalar-mem \
+; RUN:   | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
 
 ; --
 ; Fully unaligned cases
diff --git a/llvm/test/CodeGen/RISCV/memcpy.ll 
b/llvm/test/CodeGen/RISCV/memcpy.ll
index 12ec0881b20d9..f8f5d25947d7f 100644
--- a/llvm/test/CodeGen/RISCV/memcpy.ll
+++ b/llvm/test/CodeGen/RISCV/memcpy.ll
@@ -7,6 +7,10 @@
 ; RUN:   | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
 ; RUN: llc < %s -mtriple=riscv64 -ma

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

2024-05-17 Thread Tom Stellard via llvm-branch-commits 

https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/92143
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

2024-05-17 Thread Tom Stellard via llvm-branch-commits 

tstellar wrote:

@topperc (or anyone else). If you would like to add a note about this fix in 
the release notes (completely optional). Please reply to this comment with a 
one or two sentence description of the fix.  When you are done, please add the 
release:note label to this PR.

https://github.com/llvm/llvm-project/pull/92143
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

2024-05-17 Thread Craig Topper via llvm-branch-commits 

topperc wrote:

> @topperc (or anyone else). If you would like to add a note about this fix in 
> the release notes (completely optional). Please reply to this comment with a 
> one or two sentence description of the fix. When you are done, please add the 
> release:note label to this PR.

`-Xclang -target-feature -Xclang +unaligned-scalar-mem` can be used to enable 
unaligned scalar memory accesses for CPUs that do not support unaligned vector 
accesses. `-mno-strict-align` will enable unaligned scalar and vector memory 
accesses.

https://github.com/llvm/llvm-project/pull/92143
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