[llvm-branch-commits] [llvm] release/18.x: [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) (PR #81905)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/81905 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) (PR #81905)
https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/81905 >From 023925bcdfbc06941edaa64ba789dbad2bca2ce1 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 15 Feb 2024 10:48:52 -0800 Subject: [PATCH] [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) There are no checks that the type is legal so we need to handle any type. (cherry picked from commit b57ba8ec514190b38eced26d541e8e25af66c485) --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 +- llvm/test/CodeGen/RISCV/condops.ll | 51 + 2 files changed, 53 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index dba4df77663b07..37d94be5316eea 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -14654,8 +14654,8 @@ static SDValue useInversedSetcc(SDNode *N, SelectionDAG &DAG, ISD::CondCode CC = cast(Cond.getOperand(2))->get(); if (CC == ISD::SETEQ && LHS.getOpcode() == ISD::AND && isa(LHS.getOperand(1)) && isNullConstant(RHS)) { - uint64_t MaskVal = LHS.getConstantOperandVal(1); - if (isPowerOf2_64(MaskVal) && !isInt<12>(MaskVal)) + const APInt &MaskVal = LHS.getConstantOperandAPInt(1); + if (MaskVal.isPowerOf2() && !MaskVal.isSignedIntN(12)) return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CondVT, LHS, RHS, ISD::SETNE), False, True); diff --git a/llvm/test/CodeGen/RISCV/condops.ll b/llvm/test/CodeGen/RISCV/condops.ll index 8e53782b5dcd78..101cb5aeeb0940 100644 --- a/llvm/test/CodeGen/RISCV/condops.ll +++ b/llvm/test/CodeGen/RISCV/condops.ll @@ -3719,3 +3719,54 @@ entry: %cond = select i1 %tobool.not, i64 0, i64 %x ret i64 %cond } + +; Test that we don't crash on types larger than 64 bits. +define i64 @single_bit3(i80 %x, i64 %y) { +; RV32I-LABEL: single_bit3: +; RV32I: # %bb.0: # %entry +; RV32I-NEXT:lw a0, 8(a0) +; RV32I-NEXT:slli a0, a0, 31 +; RV32I-NEXT:srai a3, a0, 31 +; RV32I-NEXT:and a0, a3, a1 +; RV32I-NEXT:and a1, a3, a2 +; RV32I-NEXT:ret +; +; RV64I-LABEL: single_bit3: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT:slli a1, a1, 63 +; RV64I-NEXT:srai a0, a1, 63 +; RV64I-NEXT:and a0, a0, a2 +; RV64I-NEXT:ret +; +; RV64XVENTANACONDOPS-LABEL: single_bit3: +; RV64XVENTANACONDOPS: # %bb.0: # %entry +; RV64XVENTANACONDOPS-NEXT:andi a1, a1, 1 +; RV64XVENTANACONDOPS-NEXT:vt.maskc a0, a2, a1 +; RV64XVENTANACONDOPS-NEXT:ret +; +; RV64XTHEADCONDMOV-LABEL: single_bit3: +; RV64XTHEADCONDMOV: # %bb.0: # %entry +; RV64XTHEADCONDMOV-NEXT:slli a1, a1, 63 +; RV64XTHEADCONDMOV-NEXT:srai a0, a1, 63 +; RV64XTHEADCONDMOV-NEXT:and a0, a0, a2 +; RV64XTHEADCONDMOV-NEXT:ret +; +; RV32ZICOND-LABEL: single_bit3: +; RV32ZICOND: # %bb.0: # %entry +; RV32ZICOND-NEXT:lw a0, 8(a0) +; RV32ZICOND-NEXT:andi a3, a0, 1 +; RV32ZICOND-NEXT:czero.eqz a0, a1, a3 +; RV32ZICOND-NEXT:czero.eqz a1, a2, a3 +; RV32ZICOND-NEXT:ret +; +; RV64ZICOND-LABEL: single_bit3: +; RV64ZICOND: # %bb.0: # %entry +; RV64ZICOND-NEXT:andi a1, a1, 1 +; RV64ZICOND-NEXT:czero.eqz a0, a2, a1 +; RV64ZICOND-NEXT:ret +entry: + %and = and i80 %x, 18446744073709551616 ; 1 << 64 + %tobool.not = icmp eq i80 %and, 0 + %cond = select i1 %tobool.not, i64 0, i64 %y + ret i64 %cond +} ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) (PR #81905)
https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/81905 >From 2138f4734df035219b3071f31c08e2e46df14837 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 15 Feb 2024 10:48:52 -0800 Subject: [PATCH] [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) There are no checks that the type is legal so we need to handle any type. (cherry picked from commit b57ba8ec514190b38eced26d541e8e25af66c485) --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 +- llvm/test/CodeGen/RISCV/condops.ll | 51 + 2 files changed, 53 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index dba4df77663b07..37d94be5316eea 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -14654,8 +14654,8 @@ static SDValue useInversedSetcc(SDNode *N, SelectionDAG &DAG, ISD::CondCode CC = cast(Cond.getOperand(2))->get(); if (CC == ISD::SETEQ && LHS.getOpcode() == ISD::AND && isa(LHS.getOperand(1)) && isNullConstant(RHS)) { - uint64_t MaskVal = LHS.getConstantOperandVal(1); - if (isPowerOf2_64(MaskVal) && !isInt<12>(MaskVal)) + const APInt &MaskVal = LHS.getConstantOperandAPInt(1); + if (MaskVal.isPowerOf2() && !MaskVal.isSignedIntN(12)) return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CondVT, LHS, RHS, ISD::SETNE), False, True); diff --git a/llvm/test/CodeGen/RISCV/condops.ll b/llvm/test/CodeGen/RISCV/condops.ll index 8e53782b5dcd78..101cb5aeeb0940 100644 --- a/llvm/test/CodeGen/RISCV/condops.ll +++ b/llvm/test/CodeGen/RISCV/condops.ll @@ -3719,3 +3719,54 @@ entry: %cond = select i1 %tobool.not, i64 0, i64 %x ret i64 %cond } + +; Test that we don't crash on types larger than 64 bits. +define i64 @single_bit3(i80 %x, i64 %y) { +; RV32I-LABEL: single_bit3: +; RV32I: # %bb.0: # %entry +; RV32I-NEXT:lw a0, 8(a0) +; RV32I-NEXT:slli a0, a0, 31 +; RV32I-NEXT:srai a3, a0, 31 +; RV32I-NEXT:and a0, a3, a1 +; RV32I-NEXT:and a1, a3, a2 +; RV32I-NEXT:ret +; +; RV64I-LABEL: single_bit3: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT:slli a1, a1, 63 +; RV64I-NEXT:srai a0, a1, 63 +; RV64I-NEXT:and a0, a0, a2 +; RV64I-NEXT:ret +; +; RV64XVENTANACONDOPS-LABEL: single_bit3: +; RV64XVENTANACONDOPS: # %bb.0: # %entry +; RV64XVENTANACONDOPS-NEXT:andi a1, a1, 1 +; RV64XVENTANACONDOPS-NEXT:vt.maskc a0, a2, a1 +; RV64XVENTANACONDOPS-NEXT:ret +; +; RV64XTHEADCONDMOV-LABEL: single_bit3: +; RV64XTHEADCONDMOV: # %bb.0: # %entry +; RV64XTHEADCONDMOV-NEXT:slli a1, a1, 63 +; RV64XTHEADCONDMOV-NEXT:srai a0, a1, 63 +; RV64XTHEADCONDMOV-NEXT:and a0, a0, a2 +; RV64XTHEADCONDMOV-NEXT:ret +; +; RV32ZICOND-LABEL: single_bit3: +; RV32ZICOND: # %bb.0: # %entry +; RV32ZICOND-NEXT:lw a0, 8(a0) +; RV32ZICOND-NEXT:andi a3, a0, 1 +; RV32ZICOND-NEXT:czero.eqz a0, a1, a3 +; RV32ZICOND-NEXT:czero.eqz a1, a2, a3 +; RV32ZICOND-NEXT:ret +; +; RV64ZICOND-LABEL: single_bit3: +; RV64ZICOND: # %bb.0: # %entry +; RV64ZICOND-NEXT:andi a1, a1, 1 +; RV64ZICOND-NEXT:czero.eqz a0, a2, a1 +; RV64ZICOND-NEXT:ret +entry: + %and = and i80 %x, 18446744073709551616 ; 1 << 64 + %tobool.not = icmp eq i80 %and, 0 + %cond = select i1 %tobool.not, i64 0, i64 %y + ret i64 %cond +} ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) (PR #81905)
https://github.com/asb approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/81905 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) (PR #81905)
https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/81905 >From bdf12ae33343b8ac5561921071c27d9dd4a2182e Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 15 Feb 2024 10:48:52 -0800 Subject: [PATCH] [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) There are no checks that the type is legal so we need to handle any type. (cherry picked from commit b57ba8ec514190b38eced26d541e8e25af66c485) --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 +- llvm/test/CodeGen/RISCV/condops.ll | 51 + 2 files changed, 53 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 7895d74f06d12a..6ce7215e03ff49 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -14658,8 +14658,8 @@ static SDValue useInversedSetcc(SDNode *N, SelectionDAG &DAG, ISD::CondCode CC = cast(Cond.getOperand(2))->get(); if (CC == ISD::SETEQ && LHS.getOpcode() == ISD::AND && isa(LHS.getOperand(1)) && isNullConstant(RHS)) { - uint64_t MaskVal = LHS.getConstantOperandVal(1); - if (isPowerOf2_64(MaskVal) && !isInt<12>(MaskVal)) + const APInt &MaskVal = LHS.getConstantOperandAPInt(1); + if (MaskVal.isPowerOf2() && !MaskVal.isSignedIntN(12)) return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CondVT, LHS, RHS, ISD::SETNE), False, True); diff --git a/llvm/test/CodeGen/RISCV/condops.ll b/llvm/test/CodeGen/RISCV/condops.ll index 8e53782b5dcd78..101cb5aeeb0940 100644 --- a/llvm/test/CodeGen/RISCV/condops.ll +++ b/llvm/test/CodeGen/RISCV/condops.ll @@ -3719,3 +3719,54 @@ entry: %cond = select i1 %tobool.not, i64 0, i64 %x ret i64 %cond } + +; Test that we don't crash on types larger than 64 bits. +define i64 @single_bit3(i80 %x, i64 %y) { +; RV32I-LABEL: single_bit3: +; RV32I: # %bb.0: # %entry +; RV32I-NEXT:lw a0, 8(a0) +; RV32I-NEXT:slli a0, a0, 31 +; RV32I-NEXT:srai a3, a0, 31 +; RV32I-NEXT:and a0, a3, a1 +; RV32I-NEXT:and a1, a3, a2 +; RV32I-NEXT:ret +; +; RV64I-LABEL: single_bit3: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT:slli a1, a1, 63 +; RV64I-NEXT:srai a0, a1, 63 +; RV64I-NEXT:and a0, a0, a2 +; RV64I-NEXT:ret +; +; RV64XVENTANACONDOPS-LABEL: single_bit3: +; RV64XVENTANACONDOPS: # %bb.0: # %entry +; RV64XVENTANACONDOPS-NEXT:andi a1, a1, 1 +; RV64XVENTANACONDOPS-NEXT:vt.maskc a0, a2, a1 +; RV64XVENTANACONDOPS-NEXT:ret +; +; RV64XTHEADCONDMOV-LABEL: single_bit3: +; RV64XTHEADCONDMOV: # %bb.0: # %entry +; RV64XTHEADCONDMOV-NEXT:slli a1, a1, 63 +; RV64XTHEADCONDMOV-NEXT:srai a0, a1, 63 +; RV64XTHEADCONDMOV-NEXT:and a0, a0, a2 +; RV64XTHEADCONDMOV-NEXT:ret +; +; RV32ZICOND-LABEL: single_bit3: +; RV32ZICOND: # %bb.0: # %entry +; RV32ZICOND-NEXT:lw a0, 8(a0) +; RV32ZICOND-NEXT:andi a3, a0, 1 +; RV32ZICOND-NEXT:czero.eqz a0, a1, a3 +; RV32ZICOND-NEXT:czero.eqz a1, a2, a3 +; RV32ZICOND-NEXT:ret +; +; RV64ZICOND-LABEL: single_bit3: +; RV64ZICOND: # %bb.0: # %entry +; RV64ZICOND-NEXT:andi a1, a1, 1 +; RV64ZICOND-NEXT:czero.eqz a0, a2, a1 +; RV64ZICOND-NEXT:ret +entry: + %and = and i80 %x, 18446744073709551616 ; 1 << 64 + %tobool.not = icmp eq i80 %and, 0 + %cond = select i1 %tobool.not, i64 0, i64 %y + ret i64 %cond +} ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) (PR #81905)
llvmbot wrote: @llvm/pr-subscribers-backend-risc-v Author: None (llvmbot) Changes Backport b57ba8ec514190b38eced26d541e8e25af66c485 Requested by: @topperc --- Full diff: https://github.com/llvm/llvm-project/pull/81905.diff 2 Files Affected: - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+2-2) - (modified) llvm/test/CodeGen/RISCV/condops.ll (+51) ``diff diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 7895d74f06d12a..6ce7215e03ff49 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -14658,8 +14658,8 @@ static SDValue useInversedSetcc(SDNode *N, SelectionDAG &DAG, ISD::CondCode CC = cast(Cond.getOperand(2))->get(); if (CC == ISD::SETEQ && LHS.getOpcode() == ISD::AND && isa(LHS.getOperand(1)) && isNullConstant(RHS)) { - uint64_t MaskVal = LHS.getConstantOperandVal(1); - if (isPowerOf2_64(MaskVal) && !isInt<12>(MaskVal)) + const APInt &MaskVal = LHS.getConstantOperandAPInt(1); + if (MaskVal.isPowerOf2() && !MaskVal.isSignedIntN(12)) return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CondVT, LHS, RHS, ISD::SETNE), False, True); diff --git a/llvm/test/CodeGen/RISCV/condops.ll b/llvm/test/CodeGen/RISCV/condops.ll index 8e53782b5dcd78..101cb5aeeb0940 100644 --- a/llvm/test/CodeGen/RISCV/condops.ll +++ b/llvm/test/CodeGen/RISCV/condops.ll @@ -3719,3 +3719,54 @@ entry: %cond = select i1 %tobool.not, i64 0, i64 %x ret i64 %cond } + +; Test that we don't crash on types larger than 64 bits. +define i64 @single_bit3(i80 %x, i64 %y) { +; RV32I-LABEL: single_bit3: +; RV32I: # %bb.0: # %entry +; RV32I-NEXT:lw a0, 8(a0) +; RV32I-NEXT:slli a0, a0, 31 +; RV32I-NEXT:srai a3, a0, 31 +; RV32I-NEXT:and a0, a3, a1 +; RV32I-NEXT:and a1, a3, a2 +; RV32I-NEXT:ret +; +; RV64I-LABEL: single_bit3: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT:slli a1, a1, 63 +; RV64I-NEXT:srai a0, a1, 63 +; RV64I-NEXT:and a0, a0, a2 +; RV64I-NEXT:ret +; +; RV64XVENTANACONDOPS-LABEL: single_bit3: +; RV64XVENTANACONDOPS: # %bb.0: # %entry +; RV64XVENTANACONDOPS-NEXT:andi a1, a1, 1 +; RV64XVENTANACONDOPS-NEXT:vt.maskc a0, a2, a1 +; RV64XVENTANACONDOPS-NEXT:ret +; +; RV64XTHEADCONDMOV-LABEL: single_bit3: +; RV64XTHEADCONDMOV: # %bb.0: # %entry +; RV64XTHEADCONDMOV-NEXT:slli a1, a1, 63 +; RV64XTHEADCONDMOV-NEXT:srai a0, a1, 63 +; RV64XTHEADCONDMOV-NEXT:and a0, a0, a2 +; RV64XTHEADCONDMOV-NEXT:ret +; +; RV32ZICOND-LABEL: single_bit3: +; RV32ZICOND: # %bb.0: # %entry +; RV32ZICOND-NEXT:lw a0, 8(a0) +; RV32ZICOND-NEXT:andi a3, a0, 1 +; RV32ZICOND-NEXT:czero.eqz a0, a1, a3 +; RV32ZICOND-NEXT:czero.eqz a1, a2, a3 +; RV32ZICOND-NEXT:ret +; +; RV64ZICOND-LABEL: single_bit3: +; RV64ZICOND: # %bb.0: # %entry +; RV64ZICOND-NEXT:andi a1, a1, 1 +; RV64ZICOND-NEXT:czero.eqz a0, a2, a1 +; RV64ZICOND-NEXT:ret +entry: + %and = and i80 %x, 18446744073709551616 ; 1 << 64 + %tobool.not = icmp eq i80 %and, 0 + %cond = select i1 %tobool.not, i64 0, i64 %y + ret i64 %cond +} `` https://github.com/llvm/llvm-project/pull/81905 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) (PR #81905)
https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/81905 Backport b57ba8ec514190b38eced26d541e8e25af66c485 Requested by: @topperc >From a5e2945a3b0bb06c2c3d54cc000399a6bdb1b70f Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 15 Feb 2024 10:48:52 -0800 Subject: [PATCH] [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) There are no checks that the type is legal so we need to handle any type. (cherry picked from commit b57ba8ec514190b38eced26d541e8e25af66c485) --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 +- llvm/test/CodeGen/RISCV/condops.ll | 51 + 2 files changed, 53 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 7895d74f06d12a..6ce7215e03ff49 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -14658,8 +14658,8 @@ static SDValue useInversedSetcc(SDNode *N, SelectionDAG &DAG, ISD::CondCode CC = cast(Cond.getOperand(2))->get(); if (CC == ISD::SETEQ && LHS.getOpcode() == ISD::AND && isa(LHS.getOperand(1)) && isNullConstant(RHS)) { - uint64_t MaskVal = LHS.getConstantOperandVal(1); - if (isPowerOf2_64(MaskVal) && !isInt<12>(MaskVal)) + const APInt &MaskVal = LHS.getConstantOperandAPInt(1); + if (MaskVal.isPowerOf2() && !MaskVal.isSignedIntN(12)) return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CondVT, LHS, RHS, ISD::SETNE), False, True); diff --git a/llvm/test/CodeGen/RISCV/condops.ll b/llvm/test/CodeGen/RISCV/condops.ll index 8e53782b5dcd78..101cb5aeeb0940 100644 --- a/llvm/test/CodeGen/RISCV/condops.ll +++ b/llvm/test/CodeGen/RISCV/condops.ll @@ -3719,3 +3719,54 @@ entry: %cond = select i1 %tobool.not, i64 0, i64 %x ret i64 %cond } + +; Test that we don't crash on types larger than 64 bits. +define i64 @single_bit3(i80 %x, i64 %y) { +; RV32I-LABEL: single_bit3: +; RV32I: # %bb.0: # %entry +; RV32I-NEXT:lw a0, 8(a0) +; RV32I-NEXT:slli a0, a0, 31 +; RV32I-NEXT:srai a3, a0, 31 +; RV32I-NEXT:and a0, a3, a1 +; RV32I-NEXT:and a1, a3, a2 +; RV32I-NEXT:ret +; +; RV64I-LABEL: single_bit3: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT:slli a1, a1, 63 +; RV64I-NEXT:srai a0, a1, 63 +; RV64I-NEXT:and a0, a0, a2 +; RV64I-NEXT:ret +; +; RV64XVENTANACONDOPS-LABEL: single_bit3: +; RV64XVENTANACONDOPS: # %bb.0: # %entry +; RV64XVENTANACONDOPS-NEXT:andi a1, a1, 1 +; RV64XVENTANACONDOPS-NEXT:vt.maskc a0, a2, a1 +; RV64XVENTANACONDOPS-NEXT:ret +; +; RV64XTHEADCONDMOV-LABEL: single_bit3: +; RV64XTHEADCONDMOV: # %bb.0: # %entry +; RV64XTHEADCONDMOV-NEXT:slli a1, a1, 63 +; RV64XTHEADCONDMOV-NEXT:srai a0, a1, 63 +; RV64XTHEADCONDMOV-NEXT:and a0, a0, a2 +; RV64XTHEADCONDMOV-NEXT:ret +; +; RV32ZICOND-LABEL: single_bit3: +; RV32ZICOND: # %bb.0: # %entry +; RV32ZICOND-NEXT:lw a0, 8(a0) +; RV32ZICOND-NEXT:andi a3, a0, 1 +; RV32ZICOND-NEXT:czero.eqz a0, a1, a3 +; RV32ZICOND-NEXT:czero.eqz a1, a2, a3 +; RV32ZICOND-NEXT:ret +; +; RV64ZICOND-LABEL: single_bit3: +; RV64ZICOND: # %bb.0: # %entry +; RV64ZICOND-NEXT:andi a1, a1, 1 +; RV64ZICOND-NEXT:czero.eqz a0, a2, a1 +; RV64ZICOND-NEXT:ret +entry: + %and = and i80 %x, 18446744073709551616 ; 1 << 64 + %tobool.not = icmp eq i80 %and, 0 + %cond = select i1 %tobool.not, i64 0, i64 %y + ret i64 %cond +} ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) (PR #81905)
llvmbot wrote: @asb What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/81905 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) (PR #81905)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/81905 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits