from:"Daniel Sanders via llvm\-branch\-commits"

[llvm-branch-commits] [llvm-branch] r245037 - [mips] Drop the claim that ubsan works since r243384 and r244646 are not yet merged.

2015-08-14 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Fri Aug 14 05:18:40 2015
New Revision: 245037

URL: http://llvm.org/viewvc/llvm-project?rev=245037&view=rev
Log:
[mips] Drop the claim that ubsan works since r243384 and r244646 are not yet 
merged.

The timezone difference between myself, the code-owner, and release manager 
means
it's sensible to update the release notes on the assumption that they won't be
merged. If we do merge them, then we can revert this release notes change.


Modified:
llvm/branches/release_37/docs/ReleaseNotes.rst

Modified: llvm/branches/release_37/docs/ReleaseNotes.rst
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/docs/ReleaseNotes.rst?rev=245037&r1=245036&r2=245037&view=diff
==
--- llvm/branches/release_37/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_37/docs/ReleaseNotes.rst Fri Aug 14 05:18:40 2015
@@ -97,8 +97,7 @@ During this release the MIPS target has:
 
 * Added support for compiler-rt including:
 
-  * Support for the Address, and Undefined Behaviour Sanitizers for all MIPS
-subtargets.
+  * Support for the Address Sanitizer for all MIPS subtargets.
 
   * Support for the Data Flow, and Memory Sanitizer for 64-bit subtargets.
 


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[llvm-branch-commits] [compiler-rt-branch] r245110 - Merging r243384:

2015-08-14 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Fri Aug 14 17:33:06 2015
New Revision: 245110

URL: http://llvm.org/viewvc/llvm-project?rev=245110&view=rev
Log:
Merging r243384:

r243384 | slthakur | 2015-07-28 06:51:51 +0100 (Tue, 28 Jul 2015) | 9 lines

[UBSan][MIPS] Fix cast-overflow tests for mips big endian

This fixes the bug https://llvm.org/bugs/show_bug.cgi?id=24152
The float value resides in the first 4 bytes of ValueHandle for both mips and 
mipsel.

Reviewers: dsanders, samsonov
Subscibers: rsmith, hans, mohit.bhakkad, jaydeep, llvm-commits
Differential: http://reviews.llvm.org/D11448



Modified:
compiler-rt/branches/release_37/   (props changed)
compiler-rt/branches/release_37/lib/ubsan/ubsan_value.cc

Propchange: compiler-rt/branches/release_37/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Aug 14 17:33:06 2015
@@ -1 +1 @@
-/compiler-rt/trunk:242350,242424,242444,242449,242539-242540,242647,242651,243170,243604,243615,243686,244002
+/compiler-rt/trunk:242350,242424,242444,242449,242539-242540,242647,242651,243170,243384,243604,243615,243686,244002

Modified: compiler-rt/branches/release_37/lib/ubsan/ubsan_value.cc
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_37/lib/ubsan/ubsan_value.cc?rev=245110&r1=245109&r2=245110&view=diff
==
--- compiler-rt/branches/release_37/lib/ubsan/ubsan_value.cc (original)
+++ compiler-rt/branches/release_37/lib/ubsan/ubsan_value.cc Fri Aug 14 
17:33:06 2015
@@ -83,10 +83,11 @@ FloatMax Value::getFloatValue() const {
 #endif
   case 32: {
 float Value;
-#if defined(__BIG_ENDIAN__)
-   // For big endian the float value is in the second 4 bytes
-   //  instead of the first 4 bytes.
-   internal_memcpy(&Value, ((const char*)&Val)+4, 4);
+#if defined(__BIG_ENDIAN__) && !defined(__mips__)
+   // For big endian the float value is in the highest addressed 4 bytes
+   // (the least significant bits) but we must also consider that we might
+   // have a 32-bit type.
+   internal_memcpy(&Value, ((const char*)&Val + 1) - 4, 4);
 #else 
internal_memcpy(&Value, &Val, 4);
 #endif


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[llvm-branch-commits] [compiler-rt-branch] r245111 - Merging r244646:

2015-08-14 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Fri Aug 14 17:34:26 2015
New Revision: 245111

URL: http://llvm.org/viewvc/llvm-project?rev=245111&view=rev
Log:
Merging r244646:

r244646 | dsanders | 2015-08-11 19:40:02 +0100 (Tue, 11 Aug 2015) | 5 lines

[ubsan][mips] Revise r243384 to avoid special casing big-endian mips.

Account for the case when uptr is 32-bit instead of trying to fix this case
using the little endian path.



Modified:
compiler-rt/branches/release_37/   (props changed)
compiler-rt/branches/release_37/lib/ubsan/ubsan_value.cc

Propchange: compiler-rt/branches/release_37/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Aug 14 17:34:26 2015
@@ -1 +1 @@
-/compiler-rt/trunk:242350,242424,242444,242449,242539-242540,242647,242651,243170,243384,243604,243615,243686,244002
+/compiler-rt/trunk:242350,242424,242444,242449,242539-242540,242647,242651,243170,243384,243604,243615,243686,244002,244646

Modified: compiler-rt/branches/release_37/lib/ubsan/ubsan_value.cc
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_37/lib/ubsan/ubsan_value.cc?rev=245111&r1=245110&r2=245111&view=diff
==
--- compiler-rt/branches/release_37/lib/ubsan/ubsan_value.cc (original)
+++ compiler-rt/branches/release_37/lib/ubsan/ubsan_value.cc Fri Aug 14 
17:34:26 2015
@@ -83,11 +83,11 @@ FloatMax Value::getFloatValue() const {
 #endif
   case 32: {
 float Value;
-#if defined(__BIG_ENDIAN__) && !defined(__mips__)
-   // For big endian the float value is in the highest addressed 4 bytes
-   // (the least significant bits) but we must also consider that we might
-   // have a 32-bit type.
-   internal_memcpy(&Value, ((const char*)&Val + 1) - 4, 4);
+#if defined(__BIG_ENDIAN__)
+   // For big endian the float value is in the last 4 bytes.
+   // On some targets we may only have 4 bytes so we count backwards from
+   // the end of Val to account for both the 32-bit and 64-bit cases.
+   internal_memcpy(&Value, ((const char*)(&Val + 1)) - 4, 4);
 #else 
internal_memcpy(&Value, &Val, 4);
 #endif


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[llvm-branch-commits] [llvm-branch] r245113 - [mips] Revert release notes change in r245037 now that the ubsan patches have been merged.

2015-08-14 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Fri Aug 14 17:39:33 2015
New Revision: 245113

URL: http://llvm.org/viewvc/llvm-project?rev=245113&view=rev
Log:
[mips] Revert release notes change in r245037 now that the ubsan patches have 
been merged.


Modified:
llvm/branches/release_37/docs/ReleaseNotes.rst

Modified: llvm/branches/release_37/docs/ReleaseNotes.rst
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/docs/ReleaseNotes.rst?rev=245113&r1=245112&r2=245113&view=diff
==
--- llvm/branches/release_37/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_37/docs/ReleaseNotes.rst Fri Aug 14 17:39:33 2015
@@ -106,7 +106,8 @@ During this release the MIPS target has:
 
 * Added support for compiler-rt including:
 
-  * Support for the Address Sanitizer for all MIPS subtargets.
+  * Support for the Address, and Undefined Behaviour Sanitizers for all MIPS
+subtargets.
 
   * Support for the Data Flow, and Memory Sanitizer for 64-bit subtargets.
 


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[llvm-branch-commits] [llvm-branch] r247538 - Merging r246990:

2015-09-14 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Mon Sep 14 05:12:30 2015
New Revision: 247538

URL: http://llvm.org/viewvc/llvm-project?rev=247538&view=rev
Log:
Merging r246990:

r246990 | dsanders | 2015-09-08 10:07:03 +0100 (Tue, 08 Sep 2015) | 9 lines

[mips] Reserve address spaces 1-255 for software use.

Summary: And define them to have noop casts with address spaces 0-255.

Reviewers: pekka.jaaskelainen

Subscribers: pekka.jaaskelainen, llvm-commits

Differential Revision: http://reviews.llvm.org/D12678


Added:
llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/addrspacecast.ll
Modified:
llvm/branches/release_37/lib/Target/Mips/MipsISelLowering.h

Modified: llvm/branches/release_37/lib/Target/Mips/MipsISelLowering.h
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/Mips/MipsISelLowering.h?rev=247538&r1=247537&r2=247538&view=diff
==
--- llvm/branches/release_37/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/branches/release_37/lib/Target/Mips/MipsISelLowering.h Mon Sep 14 
05:12:30 2015
@@ -269,6 +269,14 @@ namespace llvm {
 unsigned getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const override;
 
+/// Returns true if a cast between SrcAS and DestAS is a noop.
+bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
+  // Mips doesn't have any special address spaces so we just reserve
+  // the first 256 for software use (e.g. OpenCL) and treat casts
+  // between them as noops.
+  return SrcAS < 256 && DestAS < 256;
+}
+
   protected:
 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
 

Added: llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/addrspacecast.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/addrspacecast.ll?rev=247538&view=auto
==
--- llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/addrspacecast.ll (added)
+++ llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/addrspacecast.ll Mon Sep 
14 05:12:30 2015
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL
+
+; Address spaces 1-255 are software defined.
+define i32* @cast(i32 *%arg) {
+  %1 = addrspacecast i32* %arg to i32 addrspace(1)*
+  %2 = addrspacecast i32 addrspace(1)* %1 to i32 addrspace(2)*
+  %3 = addrspacecast i32 addrspace(2)* %2 to i32 addrspace(0)*
+  ret i32* %3
+}
+
+; ALL-LABEL: cast:
+; ALL:   move   $2, $4


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[llvm-branch-commits] [llvm-branch] r247539 - Merging r247128:

2015-09-14 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Mon Sep 14 05:40:55 2015
New Revision: 247539

URL: http://llvm.org/viewvc/llvm-project?rev=247539&view=rev
Log:
Merging r247128:

r247128 | dsanders | 2015-09-09 10:53:20 +0100 (Wed, 09 Sep 2015) | 31 lines

Fix vector splitting for extract_vector_elt and vector elements of <8-bits.

Summary:
One of the vector splitting paths for extract_vector_elt tries to lower:
define i1 @via_stack_bug(i8 signext %idx) {
  %1 = extractelement <2 x i1> , i8 %idx
  ret i1 %1
}
to:
define i1 @via_stack_bug(i8 signext %idx) {
  %base = alloca <2 x i1>
  store <2 x i1> , <2 x i1>* %base
  %2 = getelementptr <2 x i1>, <2 x i1>* %base, i32 %idx
  %3 = load i1, i1* %2
  ret i1 %3
}
However, the elements of <2 x i1> are not byte-addressible. The result of this
is that the getelementptr expands to '%base + %idx * (1 / 8)' which simplifies
to '%base + %idx * 0', and then simply '%base' causing all values of %idx to
extract element zero.

This commit fixes this by promoting the vector elements of <8-bits to i8 before
splitting the vector.

This fixes a number of test failures in pocl.

Reviewers: pekka.jaaskelainen

Subscribers: pekka.jaaskelainen, llvm-commits

Differential Revision: http://reviews.llvm.org/D12591


Added:
llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/extractelement.ll
Modified:
llvm/branches/release_37/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
llvm/branches/release_37/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Modified: llvm/branches/release_37/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=247539&r1=247538&r2=247539&view=diff
==
--- llvm/branches/release_37/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp 
(original)
+++ llvm/branches/release_37/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Mon Sep 
14 05:40:55 2015
@@ -1010,6 +1010,8 @@ SDValue DAGTypeLegalizer::GetVectorEleme
 
   // Calculate the element offset and add it to the pointer.
   unsigned EltSize = EltVT.getSizeInBits() / 8; // FIXME: should be ABI size.
+  assert(EltSize * 8 == EltVT.getSizeInBits() &&
+ "Converting bits to bytes lost precision");
 
   Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
   DAG.getConstant(EltSize, dl, Index.getValueType()));

Modified: 
llvm/branches/release_37/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=247539&r1=247538&r2=247539&view=diff
==
--- llvm/branches/release_37/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 
(original)
+++ llvm/branches/release_37/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 
Mon Sep 14 05:40:55 2015
@@ -1528,9 +1528,25 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXT
   if (CustomLowerNode(N, N->getValueType(0), true))
 return SDValue();
 
-  // Store the vector to the stack.
-  EVT EltVT = VecVT.getVectorElementType();
+  // Make the vector elements byte-addressable if they aren't already.
   SDLoc dl(N);
+  EVT EltVT = VecVT.getVectorElementType();
+  if (EltVT.getSizeInBits() < 8) {
+SmallVector ElementOps;
+for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i) {
+  ElementOps.push_back(DAG.getAnyExtOrTrunc(
+  DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vec,
+  DAG.getConstant(i, dl, MVT::i8)),
+  dl, MVT::i8));
+}
+
+EltVT = MVT::i8;
+VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
+ VecVT.getVectorNumElements());
+Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, ElementOps);
+  }
+
+  // Store the vector to the stack.
   SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
   SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
MachinePointerInfo(), false, false, 0);

Added: llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/extractelement.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/extractelement.ll?rev=247539&view=auto
==
--- llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/extractelement.ll (added)
+++ llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/extractelement.ll Mon 
Sep 14 05:40:55 2015
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL
+
+; This test triggered a bug in the vector splitting where the type legalizer
+; attempted to extract the element with by storing the vector, then reading
+; an element bac

[llvm-branch-commits] [llvm-branch] r252158 - Merging r251622:

2015-11-05 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Thu Nov  5 07:30:33 2015
New Revision: 252158

URL: http://llvm.org/viewvc/llvm-project?rev=252158&view=rev
Log:
Merging r251622:

r251622 | vkalintiris | 2015-10-29 10:17:16 + (Thu, 29 Oct 2015) | 17 lines

[mips] Check the register class before replacing materializations of zero with 
$zero in microMIPS.

Summary:
The microMIPS register class GPRMM16 does not contain the $zero register.
However, MipsSEDAGToDAGISel::replaceUsesWithZeroReg() would replace uses
of the $dst register:

  [d]addiu, $dst, $zero, 0

with the $zero register, without checking for membership in the register
class of the target machine operand.

Reviewers: dsanders

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D13984


Added:
llvm/branches/release_37/test/CodeGen/Mips/micromips-zero-mat-uses.ll
  - copied unchanged from r251622, 
llvm/trunk/test/CodeGen/Mips/micromips-zero-mat-uses.ll
Modified:
llvm/branches/release_37/   (props changed)
llvm/branches/release_37/lib/Target/Mips/MipsSEISelDAGToDAG.cpp

Propchange: llvm/branches/release_37/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Nov  5 07:30:33 2015
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242372,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243057,243116,243263,243294,243361,243469,243485,243500,243519,243531,243589,243609,243636,243638-243640,243745,243891,243898,243927,243932,243934,243984,243986,243999,244058,244123,244232,244332,244418,28,244554,244644,244659,244676,244789,244889,245064,245105,245119,245256,245355,245365,245369,245394-245395,245530,245535,245902,247372,247951,249371,249718
+/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242372,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243057,243116,243263,243294,243361,243469,243485,243500,243519,243531,243589,243609,243636,243638-243640,243745,243891,243898,243927,243932,243934,243984,243986,243999,244058,244123,244232,244332,244418,28,244554,244644,244659,244676,244789,244889,245064,245105,245119,245256,245355,245365,245369,245394-245395,245530,245535,245902,247372,247951,249371,249718,251622

Modified: llvm/branches/release_37/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/Mips/MipsSEISelDAGToDAG.cpp?rev=252158&r1=252157&r2=252158&view=diff
==
--- llvm/branches/release_37/lib/Target/Mips/MipsSEISelDAGToDAG.cpp (original)
+++ llvm/branches/release_37/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Thu Nov  5 
07:30:33 2015
@@ -115,6 +115,11 @@ bool MipsSEDAGToDAGISel::replaceUsesWith
 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
   continue;
 
+// Also, we have to check that the register class of the operand
+// contains the zero register.
+if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
+  continue;
+
 MO.setReg(ZeroReg);
   }
 


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Re: [llvm-branch-commits] [llvm-branch] r257836 - Merging r257791:

2016-01-22 Thread Daniel Sanders via llvm-branch-commits

Hi Hans,

This change also stops it exporting the test-suite. Could we keep the 'svn 
export' but prevent the build by not creating the llvm.src/projects/test-suite 
symlink?
It's not a problem to export it manually but I thought I might as well ask.

> -Original Message-
> From: llvm-branch-commits [mailto:llvm-branch-commits-
> [email protected]] On Behalf Of Hans Wennborg via llvm-branch-
> commits
> Sent: 14 January 2016 23:24
> To: [email protected]
> Subject: [llvm-branch-commits] [llvm-branch] r257836 - Merging r257791:
> 
> Author: hans
> Date: Thu Jan 14 17:24:17 2016
> New Revision: 257836
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=257836&view=rev
> Log:
> Merging r257791:
> 
> r257791 | hans | 2016-01-14 11:21:14 -0800 (Thu, 14 Jan 2016) | 4 lines
> 
> Exclude test-suite from CMake builds in test-release.sh
> 
> It's broken. In 3.7 there wasn't a CMake build for test-suite at all,
> so we're not losing something we had before.
> 
> 
> Modified:
> llvm/branches/release_38/   (props changed)
> llvm/branches/release_38/utils/release/test-release.sh
> 
> Propchange: llvm/branches/release_38/
> --
> --- svn:mergeinfo (original)
> +++ svn:mergeinfo Thu Jan 14 17:24:17 2016
> @@ -1,3 +1,3 @@
>  /llvm/branches/Apple/Pertwee:110850,110961
>  /llvm/branches/type-system-rewrite:133420-134817
> -/llvm/trunk:155241,257645,257648,257730
> +/llvm/trunk:155241,257645,257648,257730,257791
> 
> Modified: llvm/branches/release_38/utils/release/test-release.sh
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/branches/release_38/utils/release/test-
> release.sh?rev=257836&r1=257835&r2=257836&view=diff
> ==
> 
> --- llvm/branches/release_38/utils/release/test-release.sh (original)
> +++ llvm/branches/release_38/utils/release/test-release.sh Thu Jan 14
> 17:24:17 2016
> @@ -159,6 +159,12 @@ while [ $# -gt 0 ]; do
>  shift
>  done
> 
> +if [ "$use_autoconf" = "no" ]; then
> +  # See llvm.org/PR26146.
> +  echo Skipping test-suite when using CMake.
> +  do_test_suite="no"
> +fi
> +
>  # Check required arguments.
>  if [ -z "$Release" ]; then
>  echo "error: no release number specified"
> 
> 
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Re: [llvm-branch-commits] [llvm-branch] r257836 - Merging r257791:

2016-01-22 Thread Daniel Sanders via llvm-branch-commits

Sure. I'll put a patch together.

> -Original Message-
> From: [email protected] [mailto:[email protected]] On Behalf
> Of Hans Wennborg
> Sent: 22 January 2016 16:37
> To: Daniel Sanders; [email protected]
> Subject: Re: [llvm-branch-commits] [llvm-branch] r257836 - Merging r257791:
> 
> Hmm, so Dimitry changed the script in r258436 to export all the
> projects in the right place and stop doing symlinks. I suppose we
> could still export test-suite on the side though. Do you want to send
> me a patch for that?
> 
> Thanks,
> Hans
> 
> On Fri, Jan 22, 2016 at 5:17 AM, Daniel Sanders via
> llvm-branch-commits  wrote:
> > Hi Hans,
> >
> > This change also stops it exporting the test-suite. Could we keep the 'svn
> export' but prevent the build by not creating the llvm.src/projects/test-suite
> symlink?
> > It's not a problem to export it manually but I thought I might as well ask.
> >
> >> -Original Message-
> >> From: llvm-branch-commits [mailto:llvm-branch-commits-
> >> [email protected]] On Behalf Of Hans Wennborg via llvm-branch-
> >> commits
> >> Sent: 14 January 2016 23:24
> >> To: [email protected]
> >> Subject: [llvm-branch-commits] [llvm-branch] r257836 - Merging r257791:
> >>
> >> Author: hans
> >> Date: Thu Jan 14 17:24:17 2016
> >> New Revision: 257836
> >>
> >> URL: http://llvm.org/viewvc/llvm-project?rev=257836&view=rev
> >> Log:
> >> Merging r257791:
> >> 
> >> r257791 | hans | 2016-01-14 11:21:14 -0800 (Thu, 14 Jan 2016) | 4 lines
> >>
> >> Exclude test-suite from CMake builds in test-release.sh
> >>
> >> It's broken. In 3.7 there wasn't a CMake build for test-suite at all,
> >> so we're not losing something we had before.
> >> 
> >>
> >> Modified:
> >> llvm/branches/release_38/   (props changed)
> >> llvm/branches/release_38/utils/release/test-release.sh
> >>
> >> Propchange: llvm/branches/release_38/
> >> --
> >> --- svn:mergeinfo (original)
> >> +++ svn:mergeinfo Thu Jan 14 17:24:17 2016
> >> @@ -1,3 +1,3 @@
> >>  /llvm/branches/Apple/Pertwee:110850,110961
> >>  /llvm/branches/type-system-rewrite:133420-134817
> >> -/llvm/trunk:155241,257645,257648,257730
> >> +/llvm/trunk:155241,257645,257648,257730,257791
> >>
> >> Modified: llvm/branches/release_38/utils/release/test-release.sh
> >> URL: http://llvm.org/viewvc/llvm-
> >> project/llvm/branches/release_38/utils/release/test-
> >> release.sh?rev=257836&r1=257835&r2=257836&view=diff
> >>
> ==
> >> 
> >> --- llvm/branches/release_38/utils/release/test-release.sh (original)
> >> +++ llvm/branches/release_38/utils/release/test-release.sh Thu Jan 14
> >> 17:24:17 2016
> >> @@ -159,6 +159,12 @@ while [ $# -gt 0 ]; do
> >>  shift
> >>  done
> >>
> >> +if [ "$use_autoconf" = "no" ]; then
> >> +  # See llvm.org/PR26146.
> >> +  echo Skipping test-suite when using CMake.
> >> +  do_test_suite="no"
> >> +fi
> >> +
> >>  # Check required arguments.
> >>  if [ -z "$Release" ]; then
> >>  echo "error: no release number specified"
> >>
> >>
> >> ___
> >> llvm-branch-commits mailing list
> >> [email protected]
> >> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
> > ___
> > llvm-branch-commits mailing list
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> > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
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[llvm-branch-commits] [llvm-branch] r259093 - Bring back the test-suite export in test-release without bringing back the build failures.

2016-01-28 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Thu Jan 28 15:05:40 2016
New Revision: 259093

URL: http://llvm.org/viewvc/llvm-project?rev=259093&view=rev
Log:
Bring back the test-suite export in test-release without bringing back the 
build failures.

Summary:
r257791 disabled the test-suite export since the addition of CMakeLists.txt was
causing build failures. This patch exports the test-suite again but does so
outside the source tree so that it isn't included in the Phase[123] builds.

Reviewers: hans

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D16679

Modified:
llvm/branches/release_38/utils/release/test-release.sh

Modified: llvm/branches/release_38/utils/release/test-release.sh
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/utils/release/test-release.sh?rev=259093&r1=259092&r2=259093&view=diff
==
--- llvm/branches/release_38/utils/release/test-release.sh (original)
+++ llvm/branches/release_38/utils/release/test-release.sh Thu Jan 28 15:05:40 
2016
@@ -155,9 +155,12 @@ while [ $# -gt 0 ]; do
 done
 
 if [ "$use_autoconf" = "no" ]; then
-  # See llvm.org/PR26146.
-  echo Skipping test-suite when using CMake.
-  do_test_suite="no"
+  if [ "$do_test_suite" = "yes" ]; then
+# See llvm.org/PR26146.
+echo Skipping test-suite build when using CMake.
+echo It will still be exported.
+do_test_suite="export-only"
+  fi
 fi
 
 # Check required arguments.
@@ -202,9 +205,11 @@ if [ $do_libs = "yes" ]; then
 projects="$projects libunwind"
   fi
 fi
-if [ $do_test_suite = "yes" ]; then
-  projects="$projects test-suite"
-fi
+case $do_test_suite in
+  yes|export-only)
+projects="$projects test-suite"
+;;
+esac
 if [ $do_openmp = "yes" ]; then
   projects="$projects openmp"
 fi
@@ -277,9 +282,16 @@ function export_sources() {
 clang-tools-extra)
 projsrc=llvm.src/tools/clang/tools/extra
 ;;
-compiler-rt|libcxx|libcxxabi|libunwind|openmp|test-suite)
+compiler-rt|libcxx|libcxxabi|libunwind|openmp)
 projsrc=llvm.src/projects/$proj
 ;;
+test-suite)
+if [ $do_test_suite = 'yes' ]; then
+  projsrc=llvm.src/projects/$proj
+else
+  projsrc=$proj.src
+fi
+;;
 *)
 echo "error: unknown project $proj"
 exit 1


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[llvm-branch-commits] [compiler-rt-branch] r259661 - Merging r259493:

2016-02-03 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Wed Feb  3 11:02:28 2016
New Revision: 259661

URL: http://llvm.org/viewvc/llvm-project?rev=259661&view=rev
Log:
Merging r259493:

r259493 | dsanders | 2016-02-02 12:55:28 + (Tue, 02 Feb 2016) | 7 lines

[compiler-rt] add_custom_libcxx should pass LLVM_PATH and a C++ compiler

Reviewers: samsonov

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D16681


Modified:
compiler-rt/branches/release_38/CMakeLists.txt
compiler-rt/branches/release_38/cmake/Modules/AddCompilerRT.cmake

Modified: compiler-rt/branches/release_38/CMakeLists.txt
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_38/CMakeLists.txt?rev=259661&r1=259660&r2=259661&view=diff
==
--- compiler-rt/branches/release_38/CMakeLists.txt (original)
+++ compiler-rt/branches/release_38/CMakeLists.txt Wed Feb  3 11:02:28 2016
@@ -66,8 +66,10 @@ if (NOT COMPILER_RT_STANDALONE_BUILD)
   # Windows where we need to use clang-cl instead.
   if(NOT MSVC)
 set(COMPILER_RT_TEST_COMPILER ${LLVM_RUNTIME_OUTPUT_INTDIR}/clang)
+set(COMPILER_RT_TEST_CXX_COMPILER ${LLVM_RUNTIME_OUTPUT_INTDIR}/clang++)
   else()
 set(COMPILER_RT_TEST_COMPILER ${LLVM_RUNTIME_OUTPUT_INTDIR}/clang.exe)
+set(COMPILER_RT_TEST_CXX_COMPILER 
${LLVM_RUNTIME_OUTPUT_INTDIR}/clang++.exe)
   endif()
 else()
   # Take output dir and install path from the user.
@@ -81,6 +83,7 @@ else()
   option(COMPILER_RT_ENABLE_WERROR "Fail and stop if warning is triggered" OFF)
   # Use a host compiler to compile/link tests.
   set(COMPILER_RT_TEST_COMPILER ${CMAKE_C_COMPILER} CACHE PATH "Compiler to 
use for testing")
+  set(COMPILER_RT_TEST_CXX_COMPILER ${CMAKE_CXX_COMPILER} CACHE PATH "C++ 
Compiler to use for testing")
 
   if (NOT LLVM_CONFIG_PATH)
 find_program(LLVM_CONFIG_PATH "llvm-config"

Modified: compiler-rt/branches/release_38/cmake/Modules/AddCompilerRT.cmake
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_38/cmake/Modules/AddCompilerRT.cmake?rev=259661&r1=259660&r2=259661&view=diff
==
--- compiler-rt/branches/release_38/cmake/Modules/AddCompilerRT.cmake (original)
+++ compiler-rt/branches/release_38/cmake/Modules/AddCompilerRT.cmake Wed Feb  
3 11:02:28 2016
@@ -290,11 +290,12 @@ macro(add_custom_libcxx name prefix)
 SOURCE_DIR ${COMPILER_RT_LIBCXX_PATH}
 CMAKE_ARGS -DCMAKE_MAKE_PROGRAM:STRING=${CMAKE_MAKE_PROGRAM}
-DCMAKE_C_COMPILER=${COMPILER_RT_TEST_COMPILER}
-   -DCMAKE_CXX_COMPILER=${COMPILER_RT_TEST_COMPILER}
+   -DCMAKE_CXX_COMPILER=${COMPILER_RT_TEST_CXX_COMPILER}
-DCMAKE_C_FLAGS=${LIBCXX_CFLAGS}
-DCMAKE_CXX_FLAGS=${LIBCXX_CFLAGS}
-DCMAKE_BUILD_TYPE=Release
-DCMAKE_INSTALL_PREFIX:PATH=
+   -DLLVM_PATH=${LLVM_MAIN_SRC_DIR}
 LOG_BUILD 1
 LOG_CONFIGURE 1
 LOG_INSTALL 1


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[llvm-branch-commits] [compiler-rt-branch] r259664 - Merging r259542:

2016-02-03 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Wed Feb  3 11:11:50 2016
New Revision: 259664

URL: http://llvm.org/viewvc/llvm-project?rev=259664&view=rev
Log:
Merging r259542:

r259542 | dsanders | 2016-02-02 18:43:53 + (Tue, 02 Feb 2016) | 24 lines

Re-commit r259512: [tsan] Add a libc++ and lit testsuite for each 
${TSAN_SUPPORTED_ARCH}.

Summary:
This is a workaround to a problem in the 3.8 release that affects MIPS and
possibly other targets where the default is not supported but a sibling is
supported.

When TSAN_SUPPORTED_ARCH is not empty, cmake currently attempts to build a
tsan'd libcxx as well as test tsan for the default target regardless of whether
the default target is supported or not. This causes problems on MIPS32 since
tsan is supported for MIPS64 but not MIPS32.

This patch causes cmake to only build the libcxx and run the lit test-suite for
archictures in ${TSAN_SUPPORTED_ARCH}

This re-commit fixes an issue where 'check-tsan' continued to look for the
tsan'd libc++ in the directory it used to be built in.

Reviewers: hans, samsonov

Subscribers: tberghammer, llvm-commits, danalbert, srhines, dvyukov

Differential Revision: http://reviews.llvm.org/D16685



Modified:
compiler-rt/branches/release_38/lib/tsan/CMakeLists.txt
compiler-rt/branches/release_38/test/tsan/CMakeLists.txt
compiler-rt/branches/release_38/test/tsan/lit.cfg
compiler-rt/branches/release_38/test/tsan/lit.site.cfg.in

Modified: compiler-rt/branches/release_38/lib/tsan/CMakeLists.txt
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_38/lib/tsan/CMakeLists.txt?rev=259664&r1=259663&r2=259664&view=diff
==
--- compiler-rt/branches/release_38/lib/tsan/CMakeLists.txt (original)
+++ compiler-rt/branches/release_38/lib/tsan/CMakeLists.txt Wed Feb  3 11:11:50 
2016
@@ -204,10 +204,17 @@ endif()
 # Build libcxx instrumented with TSan.
 if(COMPILER_RT_HAS_LIBCXX_SOURCES AND
COMPILER_RT_TEST_COMPILER_ID STREQUAL "Clang")
-  set(LIBCXX_PREFIX ${CMAKE_CURRENT_BINARY_DIR}/libcxx_tsan)
-  add_custom_libcxx(libcxx_tsan ${LIBCXX_PREFIX}
-DEPS ${TSAN_RUNTIME_LIBRARIES}
-CFLAGS -fsanitize=thread)
+  set(libcxx_tsan_deps)
+  foreach(arch ${TSAN_SUPPORTED_ARCH})
+get_target_flags_for_arch(${arch} TARGET_CFLAGS)
+set(LIBCXX_PREFIX ${CMAKE_CURRENT_BINARY_DIR}/libcxx_tsan_${arch})
+add_custom_libcxx(libcxx_tsan_${arch} ${LIBCXX_PREFIX}
+  DEPS ${TSAN_RUNTIME_LIBRARIES}
+  CFLAGS ${TARGET_CFLAGS} -fsanitize=thread)
+list(APPEND libcxx_tsan_deps libcxx_tsan_${arch})
+  endforeach()
+
+  add_custom_target(libcxx_tsan DEPENDS ${libcxx_tsan_deps})
 endif()
 
 if(COMPILER_RT_INCLUDE_TESTS)

Modified: compiler-rt/branches/release_38/test/tsan/CMakeLists.txt
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_38/test/tsan/CMakeLists.txt?rev=259664&r1=259663&r2=259664&view=diff
==
--- compiler-rt/branches/release_38/test/tsan/CMakeLists.txt (original)
+++ compiler-rt/branches/release_38/test/tsan/CMakeLists.txt Wed Feb  3 
11:11:50 2016
@@ -14,9 +14,28 @@ else()
   set(TSAN_HAS_LIBCXX False)
 endif()
 
-configure_lit_site_cfg(
-  ${CMAKE_CURRENT_SOURCE_DIR}/lit.site.cfg.in
-  ${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg)
+set(TSAN_TESTSUITES)
+
+foreach(arch ${TSAN_SUPPORTED_ARCH})
+  string(TOLOWER "-${arch}" TSAN_TEST_CONFIG_SUFFIX)
+  if(ANDROID OR ${arch} MATCHES "arm|aarch64")
+# This is only true if we are cross-compiling.
+# Build all tests with host compiler and use host tools.
+set(TSAN_TEST_TARGET_CC ${COMPILER_RT_TEST_COMPILER})
+set(TSAN_TEST_TARGET_CFLAGS ${COMPILER_RT_TEST_COMPILER_CFLAGS})
+  else()
+get_target_flags_for_arch(${arch} TSAN_TEST_TARGET_CFLAGS)
+string(REPLACE ";" " " TSAN_TEST_TARGET_CFLAGS 
"${TSAN_TEST_TARGET_CFLAGS}")
+  endif()
+
+  string(TOUPPER ${arch} ARCH_UPPER_CASE)
+  set(CONFIG_NAME ${ARCH_UPPER_CASE}Config)
+
+  configure_lit_site_cfg(
+${CMAKE_CURRENT_SOURCE_DIR}/lit.site.cfg.in
+${CMAKE_CURRENT_BINARY_DIR}/${CONFIG_NAME}/lit.site.cfg)
+  list(APPEND TSAN_TESTSUITES ${CMAKE_CURRENT_BINARY_DIR}/${CONFIG_NAME})
+endforeach()
 
 if(COMPILER_RT_INCLUDE_TESTS)
   configure_lit_site_cfg(
@@ -26,6 +45,6 @@ if(COMPILER_RT_INCLUDE_TESTS)
 endif()
 
 add_lit_testsuite(check-tsan "Running ThreadSanitizer tests"
-  ${CMAKE_CURRENT_BINARY_DIR}
+  ${TSAN_TESTSUITES}
   DEPENDS ${TSAN_TEST_DEPS})
 set_target_properties(check-tsan PROPERTIES FOLDER "TSan tests")

Modified: compiler-rt/branches/release_38/test/tsan/lit.cfg
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_38/test/tsan/lit.cfg?rev=259664&r1=259663&r2=259664&view=diff
==
--- comp

[llvm-branch-commits] [compiler-rt-branch] r259665 - Merging r259577:

2016-02-03 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Wed Feb  3 11:12:36 2016
New Revision: 259665

URL: http://llvm.org/viewvc/llvm-project?rev=259665&view=rev
Log:
Merging r259577:

r259577 | dsanders | 2016-02-02 21:41:17 + (Tue, 02 Feb 2016) | 5 lines

[tsan] Disable x86_64h build that was enabled as part of r259542.

It fails almost every test on clang-stage1-cmake-RA_check.




Modified:
compiler-rt/branches/release_38/cmake/config-ix.cmake

Modified: compiler-rt/branches/release_38/cmake/config-ix.cmake
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_38/cmake/config-ix.cmake?rev=259665&r1=259664&r2=259665&view=diff
==
--- compiler-rt/branches/release_38/cmake/config-ix.cmake (original)
+++ compiler-rt/branches/release_38/cmake/config-ix.cmake Wed Feb  3 11:12:36 
2016
@@ -299,6 +299,9 @@ set(ALL_CFI_SUPPORTED_ARCH ${X86} ${X86_
 if(APPLE)
   include(CompilerRTDarwinUtils)
 
+  # tsan fails almost everything for x86_64h
+  list(REMOVE_ITEM ALL_TSAN_SUPPORTED_ARCH x86_64h)
+
   # On Darwin if /usr/include doesn't exist, the user probably has Xcode but 
not
   # the command line tools. If this is the case, we need to find the OS X
   # sysroot to pass to clang.


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[llvm-branch-commits] [compiler-rt-branch] r259666 - Merging r259593:

2016-02-03 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Wed Feb  3 11:13:25 2016
New Revision: 259666

URL: http://llvm.org/viewvc/llvm-project?rev=259666&view=rev
Log:
Merging r259593:

r259593 | samsonov | 2016-02-02 22:42:25 + (Tue, 02 Feb 2016) | 3 lines

[TSan] Use darwin_filter_host_arch to restrict set of test arch on Mac OS.

This also reverts r259577 which was a quick-fix to fix buildbots.


Modified:
compiler-rt/branches/release_38/cmake/config-ix.cmake
compiler-rt/branches/release_38/test/tsan/CMakeLists.txt

Modified: compiler-rt/branches/release_38/cmake/config-ix.cmake
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_38/cmake/config-ix.cmake?rev=259666&r1=259665&r2=259666&view=diff
==
--- compiler-rt/branches/release_38/cmake/config-ix.cmake (original)
+++ compiler-rt/branches/release_38/cmake/config-ix.cmake Wed Feb  3 11:13:25 
2016
@@ -299,9 +299,6 @@ set(ALL_CFI_SUPPORTED_ARCH ${X86} ${X86_
 if(APPLE)
   include(CompilerRTDarwinUtils)
 
-  # tsan fails almost everything for x86_64h
-  list(REMOVE_ITEM ALL_TSAN_SUPPORTED_ARCH x86_64h)
-
   # On Darwin if /usr/include doesn't exist, the user probably has Xcode but 
not
   # the command line tools. If this is the case, we need to find the OS X
   # sysroot to pass to clang.

Modified: compiler-rt/branches/release_38/test/tsan/CMakeLists.txt
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_38/test/tsan/CMakeLists.txt?rev=259666&r1=259665&r2=259666&view=diff
==
--- compiler-rt/branches/release_38/test/tsan/CMakeLists.txt (original)
+++ compiler-rt/branches/release_38/test/tsan/CMakeLists.txt Wed Feb  3 
11:13:25 2016
@@ -16,7 +16,12 @@ endif()
 
 set(TSAN_TESTSUITES)
 
-foreach(arch ${TSAN_SUPPORTED_ARCH})
+set(TSAN_TEST_ARCH ${TSAN_SUPPORTED_ARCH})
+if(APPLE)
+  darwin_filter_host_archs(TSAN_SUPPORTED_ARCH TSAN_TEST_ARCH)
+endif()
+
+foreach(arch ${TSAN_TEST_ARCH})
   string(TOLOWER "-${arch}" TSAN_TEST_CONFIG_SUFFIX)
   if(ANDROID OR ${arch} MATCHES "arm|aarch64")
 # This is only true if we are cross-compiling.


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[llvm-branch-commits] [llvm-branch] r260095 - [mips] Add initial release notes for MIPS32.

2016-02-08 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Mon Feb  8 08:14:18 2016
New Revision: 260095

URL: http://llvm.org/viewvc/llvm-project?rev=260095&view=rev
Log:
[mips] Add initial release notes for MIPS32.

Modified:
llvm/branches/release_38/docs/ReleaseNotes.rst

Modified: llvm/branches/release_38/docs/ReleaseNotes.rst
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/docs/ReleaseNotes.rst?rev=260095&r1=260094&r2=260095&view=diff
==
--- llvm/branches/release_38/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_38/docs/ReleaseNotes.rst Mon Feb  8 08:14:18 2016
@@ -107,8 +107,63 @@ Changes to the ARM Backend
 Changes to the MIPS Target
 --
 
- During this release ...
+During this release the MIPS target has:
 
+* Significantly extended support for the Integrated Assembler. See below for
+  more information
+* Added support for the ``P5600`` processor.
+* Added support for the ``interrupt`` attribute for MIPS32R2 and later. This
+  attribute will generate a function which can be used as a interrupt handler
+  on bare metal MIPS targets using the static relocation model.
+* Added support for the ``ERETNC`` instruction found in MIPS32R5 and later.
+* Added support for OpenCL. See http://portablecl.org/.
+
+  * Address spaces 1 to 255 are now reserved for software use and conversions
+between them are no-op casts.
+
+* Removed the ``mips16`` value for the -mcpu option since it is an :abbr:`ASE
+  (Application Specific Extension)` and not a processor. If you were using 
this,
+  please specify another CPU and use ``-mips16`` to enable MIPS16.
+* Removed ``copy_u.w`` from 32-bit MSA and ``copy_u.d`` from 64-bit MSA since
+  they have been removed from the MSA specification due to forward 
compatibility
+  issues.  For example, 32-bit MSA code containing ``copy_u.w`` would behave
+  differently on a 64-bit processor supporting MSA. The corresponding 
intrinsics
+  are still available and may expand to ``copy_s.[wd]`` where this is
+  appropriate for forward compatibility purposes.
+* Relaxed the ``-mnan`` option to allow ``-mnan=2008`` on MIPS32R2/MIPS64R2 for
+  compatibility with GCC.
+* Made MIPS64R6 the default CPU for 64-bit Android triples.
+
+The MIPS target has also fixed various bugs including the following notable
+fixes:
+
+* Fixed reversed operands on ``mthi``/``mtlo`` in the DSP :abbr:`ASE
+  (Application Specific Extension)`.
+* The code generator no longer uses ``jal`` for calls to absolute immediate
+  addresses.
+* Disabled fast instruction selection on MIPS32R6 and MIPS64R6 since this is 
not
+  yet supported.
+* Corrected addend for ``R_MIPS_HI16`` and ``R_MIPS_PCHI16`` in MCJIT
+* The code generator no longer crashes when handling subregisters of an 64-bit
+  FPU register with undefined value.
+* The code generator no longer attempts to use ``$zero`` for operands that do
+  not permit ``$zero``.
+* Corrected the opcode used for ``ll``/``sc`` when using MIPS32R6/MIPS64R6 and
+  the Integrated Assembler.
+* Added support for atomic load and atomic store.
+* Corrected debug info when dynamically re-aligning the stack.
+ 
+Integrated Assembler
+
+We have made a large number of improvements to the integrated assembler for
+MIPS. In this release, the integrated assembler isn't quite production-ready
+since there are a few known issues related to bare-metal support, checking
+immediates on instructions, and the N32/N64 ABI's. However, the current support
+should be sufficient for many users of the O32 ABI, particularly those 
targeting
+MIPS32 on Linux or bare-metal MIPS32.
+
+If you would like to try the integrated assembler, please use
+``-fintegrated-as``.
 
 Changes to the PowerPC Target
 -


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[llvm-branch-commits] [compiler-rt-branch] r260371 - [mips][msan] Mark fork.cc unsupported to avoid a hang on mips64.

2016-02-10 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Wed Feb 10 04:52:36 2016
New Revision: 260371

URL: http://llvm.org/viewvc/llvm-project?rev=260371&view=rev
Log:
[mips][msan] Mark fork.cc unsupported to avoid a hang on mips64.

This also marks 32-bit mips unsupported as a side effect but 32-bit mips does
not support msan anyway.

A cleaner, more precise fix is under review for the trunk but depends on patches
we'd prefer not to merge at this time.


Modified:
compiler-rt/branches/release_38/test/msan/fork.cc

Modified: compiler-rt/branches/release_38/test/msan/fork.cc
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_38/test/msan/fork.cc?rev=260371&r1=260370&r2=260371&view=diff
==
--- compiler-rt/branches/release_38/test/msan/fork.cc (original)
+++ compiler-rt/branches/release_38/test/msan/fork.cc Wed Feb 10 04:52:36 2016
@@ -4,6 +4,11 @@
 
 // RUN: %clangxx_msan -std=c++11 -fsanitize-memory-track-origins=2 -g -O3 %s 
-o %t
 // RUN: 
MSAN_OPTIONS=store_context_size=1000,origin_history_size=0,origin_history_per_stack_limit=0
 %run %t |& FileCheck %s
+//
+// Big-endian mips64 currently hangs on this test. Mark it unsupported to allow
+// llvm-lit to finish. This also marks mips unsupported in most cases but msan
+// is already unsupported for 32-bit mips.
+// UNSUPPORTED: mips64-supported-target
 
 // Fun fact: if test output is redirected to a file (as opposed to
 // being piped directly to FileCheck), we may lose some "done"s due to


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[llvm-branch-commits] [compiler-rt-branch] r270360 - Merging r262581:

2016-05-22 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Sun May 22 09:14:59 2016
New Revision: 270360

URL: http://llvm.org/viewvc/llvm-project?rev=270360&view=rev
Log:
Merging r262581:

r262581 | mohit.bhakkad | 2016-03-03 05:05:20 + (Thu, 03 Mar 2016) | 7 lines

[LSan] Enable use_registers test for MIPS

Reviewers: samsonov

Subscribers: jaydeep, sagar, llvm-commits

Differential Revision: http://reviews.llvm.org/D17797


Modified:
compiler-rt/branches/release_38/test/lsan/TestCases/use_registers.cc

Modified: compiler-rt/branches/release_38/test/lsan/TestCases/use_registers.cc
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_38/test/lsan/TestCases/use_registers.cc?rev=270360&r1=270359&r2=270360&view=diff
==
--- compiler-rt/branches/release_38/test/lsan/TestCases/use_registers.cc 
(original)
+++ compiler-rt/branches/release_38/test/lsan/TestCases/use_registers.cc Sun 
May 22 09:14:59 2016
@@ -27,6 +27,11 @@ void *registers_thread_func(void *arg) {
   :
   : "r" (p)
   );
+#elif defined(__mips__)
+  asm ( "move $16, %0"
+  :
+  : "r" (p)
+  );
 #else
 #error "Test is not supported on this architecture."
 #endif


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[llvm-branch-commits] [compiler-rt-branch] r270361 - Merging r263000:

2016-05-22 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Sun May 22 09:17:10 2016
New Revision: 270361

URL: http://llvm.org/viewvc/llvm-project?rev=270361&view=rev
Log:
Merging r263000:

r263000 | mohit.bhakkad | 2016-03-09 07:57:20 + (Wed, 09 Mar 2016) | 7 lines

[Compiler-rt][MIPS] Defining macros for MIPS archs

Reviewers: samsonov

Subscribers: filcab, jaydeep, sagar, llvm-commits

Differential Revision: http://reviews.llvm.org/D17881


Modified:
compiler-rt/branches/release_38/lib/sanitizer_common/sanitizer_platform.h

Modified: 
compiler-rt/branches/release_38/lib/sanitizer_common/sanitizer_platform.h
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_38/lib/sanitizer_common/sanitizer_platform.h?rev=270361&r1=270360&r2=270361&view=diff
==
--- compiler-rt/branches/release_38/lib/sanitizer_common/sanitizer_platform.h 
(original)
+++ compiler-rt/branches/release_38/lib/sanitizer_common/sanitizer_platform.h 
Sun May 22 09:17:10 2016
@@ -81,6 +81,21 @@
 # define SANITIZER_X32 0
 #endif
 
+#if defined(__mips__)
+# define SANITIZER_MIPS 1
+# if defined(__mips64)
+#  define SANITIZER_MIPS32 0
+#  define SANITIZER_MIPS64 1
+# else
+#  define SANITIZER_MIPS32 1
+#  define SANITIZER_MIPS64 0
+# endif
+#else
+# define SANITIZER_MIPS 0
+# define SANITIZER_MIPS32 0
+# define SANITIZER_MIPS64 0
+#endif
+
 // By default we allow to use SizeClassAllocator64 on 64-bit platform.
 // But in some cases (e.g. AArch64's 39-bit address space) SizeClassAllocator64
 // does not work well and we need to fallback to SizeClassAllocator32.


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[llvm-branch-commits] [compiler-rt-branch] r270362 - Merging r263199:

2016-05-22 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Sun May 22 09:18:22 2016
New Revision: 270362

URL: http://llvm.org/viewvc/llvm-project?rev=270362&view=rev
Log:
Merging r263199:

r263199 | mohit.bhakkad | 2016-03-11 05:57:20 + (Fri, 11 Mar 2016) | 7 lines

[Compiler-rt] Fix ioctl codes for MIPS in sanitizer_ioctl_test

Reviewers: samsonov

Subscribers: jaydeep, sagar, llvm-commits

Differential Revision: http://reviews.llvm.org/D17985


Modified:

compiler-rt/branches/release_38/lib/sanitizer_common/tests/sanitizer_ioctl_test.cc

Modified: 
compiler-rt/branches/release_38/lib/sanitizer_common/tests/sanitizer_ioctl_test.cc
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_38/lib/sanitizer_common/tests/sanitizer_ioctl_test.cc?rev=270362&r1=270361&r2=270362&view=diff
==
--- 
compiler-rt/branches/release_38/lib/sanitizer_common/tests/sanitizer_ioctl_test.cc
 (original)
+++ 
compiler-rt/branches/release_38/lib/sanitizer_common/tests/sanitizer_ioctl_test.cc
 Sun May 22 09:18:22 2016
@@ -78,7 +78,8 @@ TEST(SanitizerIoctl, Fixup) {
 // Test decoding KVM ioctl numbers.
 TEST(SanitizerIoctl, KVM_GET_MP_STATE) {
   ioctl_desc desc;
-  bool res = ioctl_decode(0x8004ae98U, &desc);
+  unsigned int desc_value = SANITIZER_MIPS ? 0x4004ae98U : 0x8004ae98U;
+  bool res = ioctl_decode(desc_value, &desc);
   EXPECT_TRUE(res);
   EXPECT_EQ(ioctl_desc::WRITE, desc.type);
   EXPECT_EQ(4U, desc.size);
@@ -86,7 +87,8 @@ TEST(SanitizerIoctl, KVM_GET_MP_STATE) {
 
 TEST(SanitizerIoctl, KVM_GET_LAPIC) {
   ioctl_desc desc;
-  bool res = ioctl_decode(0x8400ae8eU, &desc);
+  unsigned int desc_value = SANITIZER_MIPS ? 0x4400ae8eU : 0x8400ae8eU;
+  bool res = ioctl_decode(desc_value, &desc);
   EXPECT_TRUE(res);
   EXPECT_EQ(ioctl_desc::WRITE, desc.type);
   EXPECT_EQ(1024U, desc.size);


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[llvm-branch-commits] [llvm-branch] r271119 - Merging r266833:

2016-05-28 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Sat May 28 10:56:22 2016
New Revision: 271119

URL: http://llvm.org/viewvc/llvm-project?rev=271119&view=rev
Log:
Merging r266833:

r266833 | koriakin | 2016-04-20 00:46:59 +0100 (Wed, 20 Apr 2016) | 5 lines

[Mips] [MSan] VarArgMIPS64Helper: Use target's endian, not host's.

Ugh.

Differential Revision: http://reviews.llvm.org/D19292


Modified:
llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp

Modified: 
llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp?rev=271119&r1=271118&r2=271119&view=diff
==
--- llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp 
(original)
+++ llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp 
Sat May 28 10:56:22 2016
@@ -2954,15 +2954,16 @@ struct VarArgMIPS64Helper : public VarAr
 const DataLayout &DL = F.getParent()->getDataLayout();
 for (CallSite::arg_iterator ArgIt = CS.arg_begin() + 1, End = CS.arg_end();
  ArgIt != End; ++ArgIt) {
+  llvm::Triple TargetTriple(F.getParent()->getTargetTriple());
   Value *A = *ArgIt;
   Value *Base;
   uint64_t ArgSize = DL.getTypeAllocSize(A->getType());
-#if defined(__MIPSEB__) || defined(MIPSEB)
-  // Adjusting the shadow for argument with size < 8 to match the placement
-  // of bits in big endian system
-  if (ArgSize < 8)
-VAArgOffset += (8 - ArgSize);
-#endif
+  if (TargetTriple.getArch() == llvm::Triple::mips64) {
+// Adjusting the shadow for argument with size < 8 to match the 
placement
+// of bits in big endian system
+if (ArgSize < 8)
+  VAArgOffset += (8 - ArgSize);
+  }
   Base = getShadowPtrForVAArgument(A->getType(), IRB, VAArgOffset);
   VAArgOffset += ArgSize;
   VAArgOffset = RoundUpToAlignment(VAArgOffset, 8);


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[llvm-branch-commits] [llvm-branch] r271120 - Merging r268531:

2016-05-28 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Sat May 28 10:57:13 2016
New Revision: 271120

URL: http://llvm.org/viewvc/llvm-project?rev=271120&view=rev
Log:
Merging r268531:

r268531 | koriakin | 2016-05-04 19:39:14 +0100 (Wed, 04 May 2016) | 3 lines

[MSan] [Mips64] Add tests for vararg handling.

Differential Revision: http://reviews.llvm.org/D19919


Added:
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/

llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll

llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll

Added: 
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll?rev=271120&view=auto
==
--- 
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
 (added)
+++ 
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
 Sat May 28 10:57:13 2016
@@ -0,0 +1,43 @@
+; RUN: opt < %s -msan -S | FileCheck %s
+
+target datalayout = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"
+target triple = "mips64--linux"
+
+define i32 @foo(i32 %guard, ...) {
+  %vl = alloca i8*, align 8
+  %1 = bitcast i8** %vl to i8*
+  call void @llvm.lifetime.start(i64 32, i8* %1)
+  call void @llvm.va_start(i8* %1)
+  call void @llvm.va_end(i8* %1)
+  call void @llvm.lifetime.end(i64 32, i8* %1)
+  ret i32 0
+}
+
+; First, check allocation of the save area.
+
+; CHECK-LABEL: @foo
+; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls
+; CHECK: [[B:%.*]] = add i64 0, [[A]]
+; CHECK: [[C:%.*]] = alloca {{.*}} [[B]]
+
+; CHECK: [[STACK:%.*]] = bitcast {{.*}} @__msan_va_arg_tls to i8*
+; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[C]], i8* [[STACK]], i64 
[[B]], i32 8, i1 false)
+
+declare void @llvm.lifetime.start(i64, i8* nocapture) #1
+declare void @llvm.va_start(i8*) #2
+declare void @llvm.va_end(i8*) #2
+declare void @llvm.lifetime.end(i64, i8* nocapture) #1
+
+define i32 @bar() {
+  %1 = call i32 (i32, ...) @foo(i32 0, i32 1, i64 2, double 3.00e+00)
+  ret i32 %1
+}
+
+; Save the incoming shadow value from the arguments in the __msan_va_arg_tls
+; array.  The first argument is stored at position 4, since it's right
+; justified.
+; CHECK-LABEL: @bar
+; CHECK: store i32 0, i32* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* 
@__msan_va_arg_tls to i64), i64 4) to i32*), align 8
+; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* 
@__msan_va_arg_tls to i64), i64 8) to i64*), align 8
+; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* 
@__msan_va_arg_tls to i64), i64 16) to i64*), align 8
+; CHECK: store {{.*}} 24, {{.*}} @__msan_va_arg_overflow_size_tls

Added: 
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll?rev=271120&view=auto
==
--- 
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
 (added)
+++ 
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
 Sat May 28 10:57:13 2016
@@ -0,0 +1,42 @@
+; RUN: opt < %s -msan -S | FileCheck %s
+
+target datalayout = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"
+target triple = "mips64el--linux"
+
+define i32 @foo(i32 %guard, ...) {
+  %vl = alloca i8*, align 8
+  %1 = bitcast i8** %vl to i8*
+  call void @llvm.lifetime.start(i64 32, i8* %1)
+  call void @llvm.va_start(i8* %1)
+  call void @llvm.va_end(i8* %1)
+  call void @llvm.lifetime.end(i64 32, i8* %1)
+  ret i32 0
+}
+
+; First, check allocation of the save area.
+
+; CHECK-LABEL: @foo
+; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls
+; CHECK: [[B:%.*]] = add i64 0, [[A]]
+; CHECK: [[C:%.*]] = alloca {{.*}} [[B]]
+
+; CHECK: [[STACK:%.*]] = bitcast {{.*}} @__msan_va_arg_tls to i8*
+; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[C]], i8* [[STACK]], i64 
[[B]], i32 8, i1 false)
+
+declare void @llvm.lifetime.start(i64, i8* nocapture) #1
+declare void @llvm.va_start(i8*) #2
+declare void @llvm.va_end(i8*) #2
+declare void @llvm.lifetime.end(i64, i8* nocapture) #1
+
+define i32 @bar() {
+  %1 = call i32 (i32, ...) @foo(i32 0, i32 1, i64 2, double 3.00e+00)
+  ret i32 %1
+}
+
+; Save the incoming shadow value from the arguments in the __msan_va_arg_tls
+; array.
+; CHECK-LABEL: @bar
+; CHECK: store i32 0, i32* bitcast ([100 x i64]* @__msan_va_arg_tls to i32*), 
align 8
+; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* 
@__msa

[llvm-branch-commits] [llvm-branch] r271121 - Merging r268673:

2016-05-28 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Sat May 28 10:58:03 2016
New Revision: 271121

URL: http://llvm.org/viewvc/llvm-project?rev=271121&view=rev
Log:
Merging r268673:

r268673 | koriakin | 2016-05-05 21:13:17 +0100 (Thu, 05 May 2016) | 5 lines

[MSan] [MIPS64] Fix vararg helper for >1 fixed argument.

This fixes http://llvm.org/PR27646 on Mips64.

Differential Revision: http://reviews.llvm.org/D19989


Modified:
llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp

llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll

llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll

Modified: 
llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp?rev=271121&r1=271120&r2=271121&view=diff
==
--- llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp 
(original)
+++ llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp 
Sat May 28 10:58:03 2016
@@ -2952,7 +2952,8 @@ struct VarArgMIPS64Helper : public VarAr
   void visitCallSite(CallSite &CS, IRBuilder<> &IRB) override {
 unsigned VAArgOffset = 0;
 const DataLayout &DL = F.getParent()->getDataLayout();
-for (CallSite::arg_iterator ArgIt = CS.arg_begin() + 1, End = CS.arg_end();
+for (CallSite::arg_iterator ArgIt = CS.arg_begin() +
+ CS.getFunctionType()->getNumParams(), End = CS.arg_end();
  ArgIt != End; ++ArgIt) {
   llvm::Triple TargetTriple(F.getParent()->getTargetTriple());
   Value *A = *ArgIt;

Modified: 
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll?rev=271121&r1=271120&r2=271121&view=diff
==
--- 
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
 (original)
+++ 
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
 Sat May 28 10:58:03 2016
@@ -41,3 +41,15 @@ define i32 @bar() {
 ; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* 
@__msan_va_arg_tls to i64), i64 8) to i64*), align 8
 ; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* 
@__msan_va_arg_tls to i64), i64 16) to i64*), align 8
 ; CHECK: store {{.*}} 24, {{.*}} @__msan_va_arg_overflow_size_tls
+
+; Check multiple fixed arguments.
+declare i32 @foo2(i32 %g1, i32 %g2, ...)
+define i32 @bar2() {
+  %1 = call i32 (i32, i32, ...) @foo2(i32 0, i32 1, i64 2, double 3.00e+00)
+  ret i32 %1
+}
+
+; CHECK-LABEL: @bar2
+; CHECK: store i64 0, i64* getelementptr inbounds ([100 x i64], [100 x i64]* 
@__msan_va_arg_tls, i32 0, i32 0), align 8
+; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* 
@__msan_va_arg_tls to i64), i64 8) to i64*), align 8
+; CHECK: store {{.*}} 16, {{.*}} @__msan_va_arg_overflow_size_tls

Modified: 
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll?rev=271121&r1=271120&r2=271121&view=diff
==
--- 
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
 (original)
+++ 
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
 Sat May 28 10:58:03 2016
@@ -40,3 +40,15 @@ define i32 @bar() {
 ; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* 
@__msan_va_arg_tls to i64), i64 8) to i64*), align 8
 ; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* 
@__msan_va_arg_tls to i64), i64 16) to i64*), align 8
 ; CHECK: store {{.*}} 24, {{.*}} @__msan_va_arg_overflow_size_tls
+
+; Check multiple fixed arguments.
+declare i32 @foo2(i32 %g1, i32 %g2, ...)
+define i32 @bar2() {
+  %1 = call i32 (i32, i32, ...) @foo2(i32 0, i32 1, i64 2, double 3.00e+00)
+  ret i32 %1
+}
+
+; CHECK-LABEL: @bar2
+; CHECK: store i64 0, i64* getelementptr inbounds ([100 x i64], [100 x i64]* 
@__msan_va_arg_tls, i32 0, i32 0), align 8
+; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* 
@__msan_va_arg_tls to i64), i64 8) to i64*), align 8
+; CHECK: store {{.*}} 16, {{.*}} @__msan_va_arg_overflow_size_tls


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[llvm-branch-commits] [llvm-branch] r271122 - Merging r259039:

2016-05-28 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Sat May 28 11:08:13 2016
New Revision: 271122

URL: http://llvm.org/viewvc/llvm-project?rev=271122&view=rev
Log:
Merging r259039:

r259039 | zjovanovic | 2016-01-28 11:08:03 + (Thu, 28 Jan 2016) | 9 lines

[mips][microMIPS] Disable FastISel for microMIPS

Author: milena.vujosevic.janicic
Reviewers: dsanders

FastIsel is not supported for microMIPS, thus it needs to be disabled. 
Test micromips-zero-mat-uses.ll is deleted since the tested sequence of 
instructions is not generated for microMIPS without FastISel.
Differential Revision: http://reviews.llvm.org/D15892



Removed:
llvm/branches/release_38/test/CodeGen/Mips/micromips-zero-mat-uses.ll
Modified:
llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp
llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll

Modified: llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp?rev=271122&r1=271121&r2=271122&view=diff
==
--- llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp (original)
+++ llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp Sat May 28 
11:08:13 2016
@@ -192,7 +192,8 @@ public:
 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
 MFI = funcInfo.MF->getInfo();
 Context = &funcInfo.Fn->getContext();
-bool ISASupported = !Subtarget->hasMips32r6() && Subtarget->hasMips32();
+bool ISASupported = !Subtarget->hasMips32r6() &&
+!Subtarget->inMicroMipsMode() && 
Subtarget->hasMips32();
 TargetSupported =
 ISASupported && (TM.getRelocationModel() == Reloc::PIC_) &&
 (static_cast(TM).getABI().IsO32());

Modified: 
llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll?rev=271122&r1=271121&r2=271122&view=diff
==
--- 
llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll 
(original)
+++ 
llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll 
Sat May 28 11:08:13 2016
@@ -7,6 +7,8 @@
 
 ; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
 ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -O0 
-relocation-model=pic \
+; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
 
 ; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic \
 ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s

Removed: llvm/branches/release_38/test/CodeGen/Mips/micromips-zero-mat-uses.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/micromips-zero-mat-uses.ll?rev=271121&view=auto
==
--- llvm/branches/release_38/test/CodeGen/Mips/micromips-zero-mat-uses.ll 
(original)
+++ llvm/branches/release_38/test/CodeGen/Mips/micromips-zero-mat-uses.ll 
(removed)
@@ -1,8 +0,0 @@
-; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips,+nooddspreg -O0 < %s | 
FileCheck %s
-
-; CHECK: addiu$[[R0:[0-9]+]], $zero, 0
-; CHECK: subu16   $2, $[[R0]], ${{[0-9]+}}
-define i32 @foo() {
-  %1 = sub i32 0, undef
-  ret i32 %1
-}


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[llvm-branch-commits] [llvm-branch] r271123 - Merging r268053:

2016-05-28 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Sat May 28 11:09:06 2016
New Revision: 271123

URL: http://llvm.org/viewvc/llvm-project?rev=271123&view=rev
Log:
Merging r268053:

r268053 | sdardis | 2016-04-29 17:07:47 +0100 (Fri, 29 Apr 2016) | 9 lines

[mips][FastISel] A store is not a load.

Correct trivial error. One of the failing tests from PR/27458.

Reviewers: dsanders, vkalintiris, mcrosier

Differential Review: http://reviews.llvm.org/D19726




Modified:
llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp
llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/fastalloca.ll

Modified: llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp?rev=271123&r1=271122&r2=271123&view=diff
==
--- llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp (original)
+++ llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp Sat May 28 
11:09:06 2016
@@ -803,7 +803,7 @@ bool MipsFastISel::emitStore(MVT VT, uns
 unsigned Offset = Addr.getOffset();
 MachineFrameInfo &MFI = *MF->getFrameInfo();
 MachineMemOperand *MMO = MF->getMachineMemOperand(
-MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
+MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
 MFI.getObjectSize(FI), Align);
 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
 .addReg(SrcReg)

Modified: llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/fastalloca.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/fastalloca.ll?rev=271123&r1=271122&r2=271123&view=diff
==
--- llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/fastalloca.ll 
(original)
+++ llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/fastalloca.ll Sat May 
28 11:09:06 2016
@@ -1,5 +1,5 @@
 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 
-mcpu=mips32r2 \
-; RUN: < %s | FileCheck %s
+; RUN: < %s -verify-machineinstrs | FileCheck %s
 
 %struct.x = type { i32 }
 


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[llvm-branch-commits] [llvm-branch] r271124 - Merging r268386:

2016-05-28 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Sat May 28 11:10:01 2016
New Revision: 271124

URL: http://llvm.org/viewvc/llvm-project?rev=271124&view=rev
Log:
Merging r268386:

r268386 | dsanders | 2016-05-03 15:19:26 +0100 (Tue, 03 May 2016) | 11 lines

[mips][fastisel] ADJCALLSTACKUP has a second immediate operand.

Summary:
It's always zero for SelectionDAG and is never read by the MIPS backend so
do the same for FastISel.

Reviewers: sdardis

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D19863


Modified:
llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp
llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/callabi.ll
llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/memtest1.ll

Modified: llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp?rev=271124&r1=271123&r2=271124&view=diff
==
--- llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp (original)
+++ llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp Sat May 28 
11:10:01 2016
@@ -1208,7 +1208,7 @@ bool MipsFastISel::processCallArgs(CallL
 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
   unsigned NumBytes) {
   CallingConv::ID CC = CLI.CallConv;
-  emitInst(Mips::ADJCALLSTACKUP).addImm(16);
+  emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
   if (RetVT != MVT::isVoid) {
 SmallVector RVLocs;
 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);

Modified: llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/callabi.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/callabi.ll?rev=271124&r1=271123&r2=271124&view=diff
==
--- llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/callabi.ll (original)
+++ llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/callabi.ll Sat May 28 
11:10:01 2016
@@ -1,8 +1,8 @@
-; RUN: llc -march=mipsel -mcpu=mips32 -O0 \
-; RUN: -relocation-model=pic -fast-isel-abort=1 < %s | \
+; RUN: llc -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
+; RUN: -fast-isel-abort=1 -verify-machineinstrs < %s | \
 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1
-; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 \
-; RUN: -relocation-model=pic -fast-isel-abort=1 < %s | \
+; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
+; RUN: -fast-isel-abort=1 -verify-machineinstrs < %s | \
 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2
 
 declare void @xb(i8)

Modified: llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/memtest1.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/memtest1.ll?rev=271124&r1=271123&r2=271124&view=diff
==
--- llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/memtest1.ll (original)
+++ llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/memtest1.ll Sat May 28 
11:10:01 2016
@@ -1,8 +1,8 @@
 ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
-; RUN: -fast-isel-abort=1 | FileCheck %s \
+; RUN: -fast-isel-abort=1 -verify-machineinstrs | FileCheck %s \
 ; RUN: -check-prefix=ALL -check-prefix=32R1
 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
-; RUN: -fast-isel-abort=1 | FileCheck %s \
+; RUN: -fast-isel-abort=1 -verify-machineinstrs | FileCheck %s \
 ; RUN: -check-prefix=ALL -check-prefix=32R2
 
 @str = private unnamed_addr constant [12 x i8] c"hello there\00", align 1


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[llvm-branch-commits] [llvm-branch] r271126 - Merging r262230:

2016-05-28 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Sat May 28 11:11:08 2016
New Revision: 271126

URL: http://llvm.org/viewvc/llvm-project?rev=271126&view=rev
Log:
Merging r262230:

r262230 | vkalintiris | 2016-02-29 15:58:12 + (Mon, 29 Feb 2016) | 7 lines

[mips] Do not use SLL for ANY_EXTEND nodes as the high bits are undefined.

Reviewers: dsanders

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D15420


Modified:
llvm/branches/release_38/lib/Target/Mips/Mips64InstrInfo.td
llvm/branches/release_38/test/CodeGen/Mips/cconv/return-struct.ll
llvm/branches/release_38/test/CodeGen/Mips/fcopysign-f32-f64.ll

Modified: llvm/branches/release_38/lib/Target/Mips/Mips64InstrInfo.td
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/Mips/Mips64InstrInfo.td?rev=271126&r1=271125&r2=271126&view=diff
==
--- llvm/branches/release_38/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/branches/release_38/lib/Target/Mips/Mips64InstrInfo.td Sat May 28 
11:11:08 2016
@@ -518,7 +518,8 @@ def : MipsPat<(rotr GPR64:$rt, (i32 (tru
   (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
 
 // 32-to-64-bit extension
-def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
+def : MipsPat<(i64 (anyext GPR32:$src)),
+  (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
 

Modified: llvm/branches/release_38/test/CodeGen/Mips/cconv/return-struct.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/cconv/return-struct.ll?rev=271126&r1=271125&r2=271126&view=diff
==
--- llvm/branches/release_38/test/CodeGen/Mips/cconv/return-struct.ll (original)
+++ llvm/branches/release_38/test/CodeGen/Mips/cconv/return-struct.ll Sat May 
28 11:11:08 2016
@@ -158,9 +158,6 @@ entry:
 ; sret pointer is already in $4
 ; N32-DAG:lui [[PTR_HI:\$[0-9]+]], %hi(struct_128xi16)
 ; N32-DAG:addiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(struct_128xi16)
-; FIXME: This signext isn't necessary. Like integers, pointers are
-;but unlike integers, pointers cannot have the signext attribute.
-; N32-DAG:sll $5, [[PTR]], 0
 ; N32:jal memcpy
 
 ; sret pointer is already in $4

Modified: llvm/branches/release_38/test/CodeGen/Mips/fcopysign-f32-f64.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/fcopysign-f32-f64.ll?rev=271126&r1=271125&r2=271126&view=diff
==
--- llvm/branches/release_38/test/CodeGen/Mips/fcopysign-f32-f64.ll (original)
+++ llvm/branches/release_38/test/CodeGen/Mips/fcopysign-f32-f64.ll Sat May 28 
11:11:08 2016
@@ -1,6 +1,9 @@
-; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s 
-check-prefix=64
-; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s 
-check-prefix=64
-; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s 
-check-prefix=64R2
+; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | \
+; RUN:FileCheck %s -check-prefix=ALL -check-prefix=64
+; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | \
+; RUN:FileCheck %s -check-prefix=ALL -check-prefix=64
+; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | \
+; RUN:FileCheck %s -check-prefix=ALL -check-prefix=64R2
 
 declare double @copysign(double, double) nounwind readnone
 
@@ -8,7 +11,8 @@ declare float @copysignf(float, float) n
 
 define float @func2(float %d, double %f) nounwind readnone {
 entry:
-; 64: func2
+; ALL-LABEL: func2:
+
 ; 64-DAG: lui  $[[T0:[0-9]+]], 32767
 ; 64-DAG: ori  $[[MSK0:[0-9]+]], $[[T0]], 65535
 ; 64-DAG: and  $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
@@ -30,17 +34,18 @@ entry:
 
 define double @func3(double %d, float %f) nounwind readnone {
 entry:
+; ALL-LABEL: func3:
 
-; 64: func3
-; 64-DAG: daddiu $[[T0:[0-9]+]], $zero, 1
-; 64-DAG: dsll   $[[T1:[0-9]+]], $[[T0]], 63
-; 64-DAG: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1
-; 64-DAG: and$[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
-; 64-DAG: srl$[[SRL:[0-9]+]], ${{[0-9]+}}, 31
-; 64-DAG: sll$[[SLL:[0-9]+]], $[[SRL]], 0
-; 64-DAG: dsll   $[[DSLL:[0-9]+]], $[[SLL]], 63
-; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
-; 64: dmtc1  $[[OR]], $f0
+; 64-DAG: mfc1$[[MFC:[0-9]+]], $f13
+; 64-DAG: srl $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31
+; 64: dsll$[[DSLL:[0-9]+]], $[[SRL]], 63
+; 64-DAG: daddiu  $[[R1:[0-9]+]], $zero, 1
+; 64-DAG: dsll$[[R2:[0-9]+]], $[[R1]], 63
+

[llvm-branch-commits] [llvm-branch] r271127 - Merging r263428:

2016-05-28 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Sat May 28 11:11:58 2016
New Revision: 271127

URL: http://llvm.org/viewvc/llvm-project?rev=271127&view=rev
Log:
Merging r263428:

r263428 | zbuljan | 2016-03-14 12:50:23 + (Mon, 14 Mar 2016) | 3 lines

[mips] Fix an issue with long double when function roundl is defined
Differential Revision: http://reviews.llvm.org/D17760



Added:
llvm/branches/release_38/test/CodeGen/Mips/cconv/roundl-call.ll
Modified:
llvm/branches/release_38/lib/Target/Mips/MipsCCState.cpp

Modified: llvm/branches/release_38/lib/Target/Mips/MipsCCState.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/Mips/MipsCCState.cpp?rev=271127&r1=271126&r2=271127&view=diff
==
--- llvm/branches/release_38/lib/Target/Mips/MipsCCState.cpp (original)
+++ llvm/branches/release_38/lib/Target/Mips/MipsCCState.cpp Sat May 28 
11:11:58 2016
@@ -26,8 +26,8 @@ static bool isF128SoftLibCall(const char
   "ceill", "copysignl","cosl",  "exp2l",
   "expl",  "floorl",   "fmal",  "fmodl",
   "log10l","log2l","logl",  "nearbyintl",
-  "powl",  "rintl","sinl",  "sqrtl",
-  "truncl"};
+  "powl",  "rintl","roundl","sinl",
+  "sqrtl", "truncl"};
 
   // Check that LibCalls is sorted alphabetically.
   auto Comp = [](const char *S1, const char *S2) { return strcmp(S1, S2) < 0; 
};

Added: llvm/branches/release_38/test/CodeGen/Mips/cconv/roundl-call.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/cconv/roundl-call.ll?rev=271127&view=auto
==
--- llvm/branches/release_38/test/CodeGen/Mips/cconv/roundl-call.ll (added)
+++ llvm/branches/release_38/test/CodeGen/Mips/cconv/roundl-call.ll Sat May 28 
11:11:58 2016
@@ -0,0 +1,44 @@
+; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n32 < %s | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=N32 -check-prefix=HARD-FLOAT
+; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n32 < %s | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=N32 -check-prefix=HARD-FLOAT
+
+; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 < %s | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=N64 -check-prefix=HARD-FLOAT
+; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 < %s | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=N64 -check-prefix=HARD-FLOAT
+
+; RUN: llc -march=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n32 < %s \
+; RUN: | FileCheck %s -check-prefix=ALL -check-prefix=N32 \
+; RUN:-check-prefix=SOFT-FLOAT
+; RUN: llc -march=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n32 < \
+; RUN: %s | FileCheck %s -check-prefix=ALL -check-prefix=N32 \
+; RUN:   -check-prefix=SOFT-FLOAT
+
+; RUN: llc -march=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < %s \
+; RUN: | FileCheck %s -check-prefix=ALL -check-prefix=N64 \
+; RUN:-check-prefix=SOFT-FLOAT
+; RUN: llc -march=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < \
+; RUN: %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 \
+; RUN:   -check-prefix=SOFT-FLOAT
+
+@fp128 = global fp128 zeroinitializer
+
+define void @roundl_call(fp128 %value) {
+entry:
+; ALL-LABEL: roundl_call:
+; N32:  lw  $25, %call16(roundl)($gp)
+; N64:  ld  $25, %call16(roundl)($gp)
+
+; SOFT-FLOAT:   sd  $4, 8(${{[0-9]+}})
+; SOFT-FLOAT:   sd  $2, 0(${{[0-9]+}})
+
+; HARD-FLOAT:   sdc1$f2, 8(${{[0-9]+}})
+; HARD-FLOAT:   sdc1$f0, 0(${{[0-9]+}})
+
+  %call = call fp128 @roundl(fp128 %value)
+  store fp128 %call, fp128* @fp128
+  ret void
+}
+
+declare fp128 @roundl(fp128) nounwind readnone


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[llvm-branch-commits] [llvm-branch] r276560 - Merging r275966:

2016-07-24 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Sun Jul 24 05:34:15 2016
New Revision: 276560

URL: http://llvm.org/viewvc/llvm-project?rev=276560&view=rev
Log:
Merging r275966:

r275966 | dsanders | 2016-07-19 11:22:19 +0100 (Tue, 19 Jul 2016) | 11 lines

[mips] Recognise the triple used by Debian stretch for mips64el.

Summary:
The triple used for this distribution is mips64el-linux-gnuabi64.

Reviewers: sdardis

Subscribers: sdardis, llvm-commits

Differential Revision: https://reviews.llvm.org/D22406



Modified:
llvm/branches/release_39/include/llvm/ADT/Triple.h
llvm/branches/release_39/lib/Support/Triple.cpp

Modified: llvm/branches/release_39/include/llvm/ADT/Triple.h
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/include/llvm/ADT/Triple.h?rev=276560&r1=276559&r2=276560&view=diff
==
--- llvm/branches/release_39/include/llvm/ADT/Triple.h (original)
+++ llvm/branches/release_39/include/llvm/ADT/Triple.h Sun Jul 24 05:34:15 2016
@@ -174,6 +174,7 @@ public:
 UnknownEnvironment,
 
 GNU,
+GNUABI64,
 GNUEABI,
 GNUEABIHF,
 GNUX32,
@@ -476,8 +477,9 @@ public:
 
   bool isGNUEnvironment() const {
 EnvironmentType Env = getEnvironment();
-return Env == Triple::GNU || Env == Triple::GNUEABI ||
-   Env == Triple::GNUEABIHF || Env == Triple::GNUX32;
+return Env == Triple::GNU || Env == Triple::GNUABI64 ||
+   Env == Triple::GNUEABI || Env == Triple::GNUEABIHF ||
+   Env == Triple::GNUX32;
   }
 
   /// Checks if the environment could be MSVC.

Modified: llvm/branches/release_39/lib/Support/Triple.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Support/Triple.cpp?rev=276560&r1=276559&r2=276560&view=diff
==
--- llvm/branches/release_39/lib/Support/Triple.cpp (original)
+++ llvm/branches/release_39/lib/Support/Triple.cpp Sun Jul 24 05:34:15 2016
@@ -201,6 +201,7 @@ const char *Triple::getEnvironmentTypeNa
   switch (Kind) {
   case UnknownEnvironment: return "unknown";
   case GNU: return "gnu";
+  case GNUABI64: return "gnuabi64";
   case GNUEABIHF: return "gnueabihf";
   case GNUEABI: return "gnueabi";
   case GNUX32: return "gnux32";
@@ -468,6 +469,7 @@ static Triple::EnvironmentType parseEnvi
   return StringSwitch(EnvironmentName)
 .StartsWith("eabihf", Triple::EABIHF)
 .StartsWith("eabi", Triple::EABI)
+.StartsWith("gnuabi64", Triple::GNUABI64)
 .StartsWith("gnueabihf", Triple::GNUEABIHF)
 .StartsWith("gnueabi", Triple::GNUEABI)
 .StartsWith("gnux32", Triple::GNUX32)


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[llvm-branch-commits] [llvm-branch] r276562 - Merging r275968:

2016-07-24 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Sun Jul 24 06:40:23 2016
New Revision: 276562

URL: http://llvm.org/viewvc/llvm-project?rev=276562&view=rev
Log:
Merging r275968:

r275968 | dsanders | 2016-07-19 11:58:06 +0100 (Tue, 19 Jul 2016) | 7 lines

[mips][ias] R_MIPS_GOT_(PAGE|OFST) do not need symbols

Reviewers: sdardis

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: https://reviews.llvm.org/D22458


Modified:

llvm/branches/release_39/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
llvm/branches/release_39/test/MC/Mips/relocation.s

Modified: 
llvm/branches/release_39/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp?rev=276562&r1=276561&r2=276562&view=diff
==
--- 
llvm/branches/release_39/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp 
(original)
+++ 
llvm/branches/release_39/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp 
Sun Jul 24 06:40:23 2016
@@ -518,6 +518,10 @@ bool MipsELFObjectWriter::needsRelocateW
   return true;
 return false;
 
+  case ELF::R_MIPS_GOT_PAGE:
+  case ELF::R_MICROMIPS_GOT_PAGE:
+  case ELF::R_MIPS_GOT_OFST:
+  case ELF::R_MICROMIPS_GOT_OFST:
   case ELF::R_MIPS_16:
   case ELF::R_MIPS_32:
   case ELF::R_MIPS_GPREL32:
@@ -539,8 +543,6 @@ bool MipsELFObjectWriter::needsRelocateW
   case ELF::R_MIPS_SHIFT5:
   case ELF::R_MIPS_SHIFT6:
   case ELF::R_MIPS_GOT_DISP:
-  case ELF::R_MIPS_GOT_PAGE:
-  case ELF::R_MIPS_GOT_OFST:
   case ELF::R_MIPS_GOT_HI16:
   case ELF::R_MIPS_GOT_LO16:
   case ELF::R_MIPS_INSERT_A:
@@ -589,8 +591,6 @@ bool MipsELFObjectWriter::needsRelocateW
   case ELF::R_MICROMIPS_PC16_S1:
   case ELF::R_MICROMIPS_CALL16:
   case ELF::R_MICROMIPS_GOT_DISP:
-  case ELF::R_MICROMIPS_GOT_PAGE:
-  case ELF::R_MICROMIPS_GOT_OFST:
   case ELF::R_MICROMIPS_GOT_HI16:
   case ELF::R_MICROMIPS_GOT_LO16:
   case ELF::R_MICROMIPS_SUB:

Modified: llvm/branches/release_39/test/MC/Mips/relocation.s
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/test/MC/Mips/relocation.s?rev=276562&r1=276561&r2=276562&view=diff
==
--- llvm/branches/release_39/test/MC/Mips/relocation.s (original)
+++ llvm/branches/release_39/test/MC/Mips/relocation.s Sun Jul 24 06:40:23 2016
@@ -116,7 +116,7 @@ baz:.long foo
// ?: R_MIPS_SHIFT5 foo
// ?: R_MIPS_SHIFT6 foo
 
-// DATA-NEXT:  0060: 2462 2462 2462 2462
+// DATA-NEXT:  0060: 2462 2462 24620004 2462
 addiu $2, $3, %got_disp(foo)   // RELOC: R_MIPS_GOT_DISP foo
// ENCBE: addiu $2, $3, 
%got_disp(foo) # encoding: [0x24,0x62,A,A]
// ENCLE: addiu $2, $3, 
%got_disp(foo) # encoding: [A,A,0x62,0x24]
@@ -127,17 +127,27 @@ baz:.long foo
// ENCLE: addiu $2, $3, 
%got_page(foo) # encoding: [A,A,0x62,0x24]
// FIXUP: # fixup A - offset: 0, 
value: %got_page(foo), kind: fixup_Mips_GOT_PAGE
 
+addiu $2, $3, %got_page(bar)   // RELOC: R_MIPS_GOT_PAGE .data
+   // ENCBE: addiu $2, $3, 
%got_page(bar) # encoding: [0x24,0x62,A,A]
+   // ENCLE: addiu $2, $3, 
%got_page(bar) # encoding: [A,A,0x62,0x24]
+   // FIXUP: # fixup A - offset: 0, 
value: %got_page(bar), kind: fixup_Mips_GOT_PAGE
+
 addiu $2, $3, %got_ofst(foo)   // RELOC: R_MIPS_GOT_OFST foo
// ENCBE: addiu $2, $3, 
%got_ofst(foo) # encoding: [0x24,0x62,A,A]
// ENCLE: addiu $2, $3, 
%got_ofst(foo) # encoding: [A,A,0x62,0x24]
// FIXUP: # fixup A - offset: 0, 
value: %got_ofst(foo), kind: fixup_Mips_GOT_OFST
 
+// DATA-NEXT:  0070: 24620004 2462 2462 6462
+addiu $2, $3, %got_ofst(bar)   // RELOC: R_MIPS_GOT_OFST .data
+   // ENCBE: addiu $2, $3, 
%got_ofst(bar) # encoding: [0x24,0x62,A,A]
+   // ENCLE: addiu $2, $3, 
%got_ofst(bar) # encoding: [A,A,0x62,0x24]
+   // FIXUP: # fixup A - offset: 0, 
value: %got_ofst(bar), kind: fixup_Mips_GOT_OFST
+
 addiu $2, $3, %got_hi(foo) // RELOC: R_MIPS_GOT_HI16 foo
// ENCBE: addiu $2, $3, 
%got_hi(foo) # encoding: [0x24,0x62,A

[llvm-branch-commits] [llvm-branch] r276561 - Merging r275967:

2016-07-24 Thread Daniel Sanders via llvm-branch-commits

Author: dsanders
Date: Sun Jul 24 06:39:45 2016
New Revision: 276561

URL: http://llvm.org/viewvc/llvm-project?rev=276561&view=rev
Log:
Merging r275967:

r275967 | dsanders | 2016-07-19 11:49:03 +0100 (Tue, 19 Jul 2016) | 16 lines

[mips] Correct label prefixes for N32 and N64.

Summary:
N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own
($).

This fixes the majority of object differences between -fintegrated-as and
-fno-integrated-as.

Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: https://reviews.llvm.org/D22412




Added:
llvm/branches/release_39/test/CodeGen/Mips/jumptable_labels.ll
Modified:
llvm/branches/release_39/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
llvm/branches/release_39/lib/Target/Mips/MipsTargetMachine.cpp
llvm/branches/release_39/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll
llvm/branches/release_39/test/CodeGen/Mips/2010-07-20-Switch.ll
llvm/branches/release_39/test/CodeGen/Mips/analyzebranch.ll
llvm/branches/release_39/test/CodeGen/Mips/atomic.ll
llvm/branches/release_39/test/CodeGen/Mips/blez_bgez.ll
llvm/branches/release_39/test/CodeGen/Mips/blockaddr.ll
llvm/branches/release_39/test/CodeGen/Mips/ehframe-indirect.ll
llvm/branches/release_39/test/CodeGen/Mips/fcmp.ll
llvm/branches/release_39/test/CodeGen/Mips/fpbr.ll
llvm/branches/release_39/test/CodeGen/Mips/llvm-ir/ashr.ll
llvm/branches/release_39/test/CodeGen/Mips/llvm-ir/indirectbr.ll
llvm/branches/release_39/test/CodeGen/Mips/llvm-ir/lshr.ll
llvm/branches/release_39/test/CodeGen/Mips/llvm-ir/select-dbl.ll
llvm/branches/release_39/test/CodeGen/Mips/llvm-ir/select-flt.ll
llvm/branches/release_39/test/CodeGen/Mips/llvm-ir/select-int.ll
llvm/branches/release_39/test/CodeGen/Mips/llvm-ir/shl.ll
llvm/branches/release_39/test/CodeGen/Mips/longbranch.ll
llvm/branches/release_39/test/CodeGen/Mips/msa/basic_operations.ll
llvm/branches/release_39/test/CodeGen/Mips/msa/basic_operations_float.ll
llvm/branches/release_39/test/CodeGen/Mips/octeon.ll
llvm/branches/release_39/test/MC/Mips/cpsetup.s
llvm/branches/release_39/test/MC/Mips/expansion-jal-sym-pic.s
llvm/branches/release_39/test/MC/Mips/macro-la.s
llvm/branches/release_39/test/MC/Mips/mips3/valid.s
llvm/branches/release_39/test/MC/Mips/mips4/valid.s
llvm/branches/release_39/test/MC/Mips/mips5/valid.s
llvm/branches/release_39/test/MC/Mips/mips64/valid.s
llvm/branches/release_39/test/MC/Mips/mips64r2/valid.s
llvm/branches/release_39/test/MC/Mips/mips64r3/valid.s
llvm/branches/release_39/test/MC/Mips/mips64r5/valid.s

Modified: 
llvm/branches/release_39/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp?rev=276561&r1=276560&r2=276561&view=diff
==
--- llvm/branches/release_39/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp 
(original)
+++ llvm/branches/release_39/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp Sun 
Jul 24 06:39:45 2016
@@ -28,12 +28,19 @@ MipsMCAsmInfo::MipsMCAsmInfo(const Tripl
 PointerSize = CalleeSaveStackSlotSize = 8;
   }
 
+  // FIXME: This condition isn't quite right but it's the best we can do until
+  //this object can identify the ABI. It will misbehave when using O32
+  //on a mips64*-* triple.
+  if ((TheTriple.getArch() == Triple::mipsel) ||
+  (TheTriple.getArch() == Triple::mips)) {
+PrivateGlobalPrefix = "$";
+PrivateLabelPrefix = "$";
+  }
+
   AlignmentIsInBytes  = false;
   Data16bitsDirective = "\t.2byte\t";
   Data32bitsDirective = "\t.4byte\t";
   Data64bitsDirective = "\t.8byte\t";
-  PrivateGlobalPrefix = "$";
-  PrivateLabelPrefix  = "$";
   CommentString   = "#";
   ZeroDirective   = "\t.space\t";
   GPRel32Directive= "\t.gpword\t";

Modified: llvm/branches/release_39/lib/Target/Mips/MipsTargetMachine.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/Mips/MipsTargetMachine.cpp?rev=276561&r1=276560&r2=276561&view=diff
==
--- llvm/branches/release_39/lib/Target/Mips/MipsTargetMachine.cpp (original)
+++ llvm/branches/release_39/lib/Target/Mips/MipsTargetMachine.cpp Sun Jul 24 
06:39:45 2016
@@ -57,7 +57,10 @@ static std::string computeDataLayout(con
   else
 Ret += "E";
 
-  Ret += "-m:m";
+  if (ABI.IsO32())
+Ret += "-m:m";
+  else
+Ret += "-m:e";
 
   // Pointers are 32 bit on some ABIs.
   if (!ABI.IsN64())

Modified: llvm/branches/release_39/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll
URL: 
htt

Re: [llvm-branch-commits] [llvm-branch] r276561 - Merging r275967:

2016-07-25 Thread Daniel Sanders via llvm-branch-commits

Thanks. I'm not sure why I didn't see it, presumably I must have run 'ninja 
check' instead of 'ninja check-all'.

Sorry for the breakage.

> -Original Message-
> From: [email protected] [mailto:[email protected]] On Behalf
> Of Hans Wennborg
> Sent: 25 July 2016 17:29
> To: Daniel Sanders; [email protected]
> Subject: Re: [llvm-branch-commits] [llvm-branch] r276561 - Merging r275967:
> 
> Looks like r275967 made changes to both the llvm and cfe modules, and
> this only merged the llvm ones. I've merged the cfe part in r276643.
> To fix the breakage.
> 
> Thanks,
> Hans
> 
> On Sun, Jul 24, 2016 at 4:39 AM, Daniel Sanders via
> llvm-branch-commits  wrote:
> > Author: dsanders
> > Date: Sun Jul 24 06:39:45 2016
> > New Revision: 276561
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=276561&view=rev
> > Log:
> > Merging r275967:
> > 
> > r275967 | dsanders | 2016-07-19 11:49:03 +0100 (Tue, 19 Jul 2016) | 16 lines
> >
> > [mips] Correct label prefixes for N32 and N64.
> >
> > Summary:
> > N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its
> own
> > ($).
> >
> > This fixes the majority of object differences between -fintegrated-as and
> > -fno-integrated-as.
> >
> > Reviewers: sdardis
> >
> > Subscribers: dsanders, sdardis, llvm-commits
> >
> > Differential Revision: https://reviews.llvm.org/D22412
> >
> >
> > 
> >
> > Added:
> > llvm/branches/release_39/test/CodeGen/Mips/jumptable_labels.ll
> > Modified:
> >
> llvm/branches/release_39/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.
> cpp
> > llvm/branches/release_39/lib/Target/Mips/MipsTargetMachine.cpp
> > llvm/branches/release_39/test/CodeGen/Mips/2009-11-16-
> CstPoolLoad.ll
> > llvm/branches/release_39/test/CodeGen/Mips/2010-07-20-Switch.ll
> > llvm/branches/release_39/test/CodeGen/Mips/analyzebranch.ll
> > llvm/branches/release_39/test/CodeGen/Mips/atomic.ll
> > llvm/branches/release_39/test/CodeGen/Mips/blez_bgez.ll
> > llvm/branches/release_39/test/CodeGen/Mips/blockaddr.ll
> > llvm/branches/release_39/test/CodeGen/Mips/ehframe-indirect.ll
> > llvm/branches/release_39/test/CodeGen/Mips/fcmp.ll
> > llvm/branches/release_39/test/CodeGen/Mips/fpbr.ll
> > llvm/branches/release_39/test/CodeGen/Mips/llvm-ir/ashr.ll
> > llvm/branches/release_39/test/CodeGen/Mips/llvm-ir/indirectbr.ll
> > llvm/branches/release_39/test/CodeGen/Mips/llvm-ir/lshr.ll
> > llvm/branches/release_39/test/CodeGen/Mips/llvm-ir/select-dbl.ll
> > llvm/branches/release_39/test/CodeGen/Mips/llvm-ir/select-flt.ll
> > llvm/branches/release_39/test/CodeGen/Mips/llvm-ir/select-int.ll
> > llvm/branches/release_39/test/CodeGen/Mips/llvm-ir/shl.ll
> > llvm/branches/release_39/test/CodeGen/Mips/longbranch.ll
> > llvm/branches/release_39/test/CodeGen/Mips/msa/basic_operations.ll
> >
> llvm/branches/release_39/test/CodeGen/Mips/msa/basic_operations_float
> .ll
> > llvm/branches/release_39/test/CodeGen/Mips/octeon.ll
> > llvm/branches/release_39/test/MC/Mips/cpsetup.s
> > llvm/branches/release_39/test/MC/Mips/expansion-jal-sym-pic.s
> > llvm/branches/release_39/test/MC/Mips/macro-la.s
> > llvm/branches/release_39/test/MC/Mips/mips3/valid.s
> > llvm/branches/release_39/test/MC/Mips/mips4/valid.s
> > llvm/branches/release_39/test/MC/Mips/mips5/valid.s
> > llvm/branches/release_39/test/MC/Mips/mips64/valid.s
> > llvm/branches/release_39/test/MC/Mips/mips64r2/valid.s
> > llvm/branches/release_39/test/MC/Mips/mips64r3/valid.s
> > llvm/branches/release_39/test/MC/Mips/mips64r5/valid.s
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[llvm-branch-commits] [llvm] Mips: Add frexp intrinsic test (PR #148677)

2025-07-25 Thread Daniel Sanders via llvm-branch-commits


https://github.com/dsandersllvm edited 
https://github.com/llvm/llvm-project/pull/148677
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[llvm-branch-commits] [llvm] Mips: Add frexp intrinsic test (PR #148677)

2025-07-25 Thread Daniel Sanders via llvm-branch-commits


https://github.com/dsandersllvm approved this pull request.

I don't have a means to confirm this is correct anymore but this LGTM based on 
my recollection and the function prototype

https://github.com/llvm/llvm-project/pull/148677
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[llvm-branch-commits] [llvm] Mips: Add frexp intrinsic test (PR #148677)

2025-07-25 Thread Daniel Sanders via llvm-branch-commits



@@ -0,0 +1,676 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -mtriple=mipsel < %s | FileCheck -check-prefix=MIPSEL %s
+; RUN: llc -mtriple=mips < %s | FileCheck %s -check-prefixes=SOFT-FLOAT-32
+; RUN: llc -mtriple=mips64 < %s | FileCheck %s -check-prefixes=SOFT-FLOAT-64
+
+define { half, i32 } @test_frexp_f16_i32(half %a) nounwind {
+; CHECK-LABEL: test_frexp_f16_i32:

dsandersllvm wrote:

These CHECK lines appear to be unused by the RUN lines

https://github.com/llvm/llvm-project/pull/148677
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[llvm-branch-commits] [lldb] release/21.x: [lldb] Implement DW_CFA_val_offset and DW_CFA_val_offset_sf (#150732) (PR #166611)

2025-11-10 Thread Daniel Sanders via llvm-branch-commits


dsandersllvm wrote:

My goal was just to minimize divergence in a repo three or four layers 
downstream of llvm.org's where I needed this change. I created this PR because 
when I requested it in one of the intermediate repos I was asked to do it 
upstream instead since it was early enough that that should be ok. If it's not, 
I can go back to that downstream repo and ask for it there.

https://github.com/llvm/llvm-project/pull/166611
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[llvm-branch-commits] [llvm-branch] r245037 - [mips] Drop the claim that ubsan works since r243384 and r244646 are not yet merged.

[llvm-branch-commits] [compiler-rt-branch] r245110 - Merging r243384:

[llvm-branch-commits] [compiler-rt-branch] r245111 - Merging r244646:

[llvm-branch-commits] [llvm-branch] r245113 - [mips] Revert release notes change in r245037 now that the ubsan patches have been merged.

[llvm-branch-commits] [llvm-branch] r247538 - Merging r246990:

[llvm-branch-commits] [llvm-branch] r247539 - Merging r247128:

[llvm-branch-commits] [llvm-branch] r252158 - Merging r251622:

Re: [llvm-branch-commits] [llvm-branch] r257836 - Merging r257791:

Re: [llvm-branch-commits] [llvm-branch] r257836 - Merging r257791:

[llvm-branch-commits] [llvm-branch] r259093 - Bring back the test-suite export in test-release without bringing back the build failures.

[llvm-branch-commits] [compiler-rt-branch] r259661 - Merging r259493:

[llvm-branch-commits] [compiler-rt-branch] r259664 - Merging r259542:

[llvm-branch-commits] [compiler-rt-branch] r259665 - Merging r259577:

[llvm-branch-commits] [compiler-rt-branch] r259666 - Merging r259593:

[llvm-branch-commits] [llvm-branch] r260095 - [mips] Add initial release notes for MIPS32.

[llvm-branch-commits] [compiler-rt-branch] r260371 - [mips][msan] Mark fork.cc unsupported to avoid a hang on mips64.

[llvm-branch-commits] [compiler-rt-branch] r270360 - Merging r262581:

[llvm-branch-commits] [compiler-rt-branch] r270361 - Merging r263000:

[llvm-branch-commits] [compiler-rt-branch] r270362 - Merging r263199:

[llvm-branch-commits] [llvm-branch] r271119 - Merging r266833:

[llvm-branch-commits] [llvm-branch] r271120 - Merging r268531:

[llvm-branch-commits] [llvm-branch] r271121 - Merging r268673:

[llvm-branch-commits] [llvm-branch] r271122 - Merging r259039:

[llvm-branch-commits] [llvm-branch] r271123 - Merging r268053:

[llvm-branch-commits] [llvm-branch] r271124 - Merging r268386:

[llvm-branch-commits] [llvm-branch] r271126 - Merging r262230:

[llvm-branch-commits] [llvm-branch] r271127 - Merging r263428:

[llvm-branch-commits] [llvm-branch] r276560 - Merging r275966:

[llvm-branch-commits] [llvm-branch] r276562 - Merging r275968:

[llvm-branch-commits] [llvm-branch] r276561 - Merging r275967:

Re: [llvm-branch-commits] [llvm-branch] r276561 - Merging r275967:

[llvm-branch-commits] [llvm] Mips: Add frexp intrinsic test (PR #148677)

[llvm-branch-commits] [llvm] Mips: Add frexp intrinsic test (PR #148677)

[llvm-branch-commits] [llvm] Mips: Add frexp intrinsic test (PR #148677)

[llvm-branch-commits] [lldb] release/21.x: [lldb] Implement DW_CFA_val_offset and DW_CFA_val_offset_sf (#150732) (PR #166611)

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