[llvm-branch-commits] [llvm] d8af310 - [LV] Add missed optimization fold-tail test

2021-01-02 Thread Gil Rapaport via llvm-branch-commits 

Author: Gil Rapaport
Date: 2021-01-02T14:00:15+02:00
New Revision: d8af31006351c9f441d73d4b6c5ea6d109f3d4f1

URL: 
https://github.com/llvm/llvm-project/commit/d8af31006351c9f441d73d4b6c5ea6d109f3d4f1
DIFF: 
https://github.com/llvm/llvm-project/commit/d8af31006351c9f441d73d4b6c5ea6d109f3d4f1.diff

LOG: [LV] Add missed optimization fold-tail test

The loop vectorizer avoids folding the tail for loop's whose trip-count is
known to SCEV to be divisible by VF. In this case the assumption providing this
information is not taken into account, so the tail is needlessly folded.

Added: 

llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-assumed-divisible-TC.ll

Modified: 


Removed: 




diff  --git 
a/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-assumed-divisible-TC.ll 
b/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-assumed-divisible-TC.ll
new file mode 100644
index ..e0a14db9a6d1
--- /dev/null
+++ 
b/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-assumed-divisible-TC.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -loop-vectorize -force-vector-width=4 -S | FileCheck %s
+
+target datalayout = 
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+
+; TODO: Make sure the loop is vectorized under -Os without folding its tail 
based on
+; its trip-count's lower bits assumed to be zero.
+
+define dso_local void @assumeAlignedTC(i32* noalias nocapture %A, i32* %p) 
optsize {
+; CHECK-LABEL: @assumeAlignedTC(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[N:%.*]] = load i32, i32* [[P:%.*]], align 4
+; CHECK-NEXT:[[AND:%.*]] = and i32 [[N]], 3
+; CHECK-NEXT:[[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT:tail call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; CHECK:   vector.ph:
+; CHECK-NEXT:[[N_RND_UP:%.*]] = add i32 [[N]], 3
+; CHECK-NEXT:[[N_MOD_VF:%.*]] = urem i32 [[N_RND_UP]], 4
+; CHECK-NEXT:[[N_VEC:%.*]] = sub i32 [[N_RND_UP]], [[N_MOD_VF]]
+; CHECK-NEXT:[[TRIP_COUNT_MINUS_1:%.*]] = sub i32 [[N]], 1
+; CHECK-NEXT:[[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> 
poison, i32 [[TRIP_COUNT_MINUS_1]], i32 0
+; CHECK-NEXT:[[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> 
[[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT:br label [[VECTOR_BODY:%.*]]
+; CHECK:   vector.body:
+; CHECK-NEXT:[[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ 
[[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE6:%.*]] ]
+; CHECK-NEXT:[[VEC_IND:%.*]] = phi <4 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE6]] ]
+; CHECK-NEXT:[[TMP0:%.*]] = icmp ule <4 x i32> [[VEC_IND]], 
[[BROADCAST_SPLAT]]
+; CHECK-NEXT:[[TMP1:%.*]] = extractelement <4 x i1> [[TMP0]], i32 0
+; CHECK-NEXT:br i1 [[TMP1]], label [[PRED_STORE_IF:%.*]], label 
[[PRED_STORE_CONTINUE:%.*]]
+; CHECK:   pred.store.if:
+; CHECK-NEXT:[[TMP2:%.*]] = add i32 [[INDEX]], 0
+; CHECK-NEXT:[[TMP3:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], 
i32 [[TMP2]]
+; CHECK-NEXT:store i32 13, i32* [[TMP3]], align 1
+; CHECK-NEXT:br label [[PRED_STORE_CONTINUE]]
+; CHECK:   pred.store.continue:
+; CHECK-NEXT:[[TMP4:%.*]] = extractelement <4 x i1> [[TMP0]], i32 1
+; CHECK-NEXT:br i1 [[TMP4]], label [[PRED_STORE_IF1:%.*]], label 
[[PRED_STORE_CONTINUE2:%.*]]
+; CHECK:   pred.store.if1:
+; CHECK-NEXT:[[TMP5:%.*]] = add i32 [[INDEX]], 1
+; CHECK-NEXT:[[TMP6:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 
[[TMP5]]
+; CHECK-NEXT:store i32 13, i32* [[TMP6]], align 1
+; CHECK-NEXT:br label [[PRED_STORE_CONTINUE2]]
+; CHECK:   pred.store.continue2:
+; CHECK-NEXT:[[TMP7:%.*]] = extractelement <4 x i1> [[TMP0]], i32 2
+; CHECK-NEXT:br i1 [[TMP7]], label [[PRED_STORE_IF3:%.*]], label 
[[PRED_STORE_CONTINUE4:%.*]]
+; CHECK:   pred.store.if3:
+; CHECK-NEXT:[[TMP8:%.*]] = add i32 [[INDEX]], 2
+; CHECK-NEXT:[[TMP9:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 
[[TMP8]]
+; CHECK-NEXT:store i32 13, i32* [[TMP9]], align 1
+; CHECK-NEXT:br label [[PRED_STORE_CONTINUE4]]
+; CHECK:   pred.store.continue4:
+; CHECK-NEXT:[[TMP10:%.*]] = extractelement <4 x i1> [[TMP0]], i32 3
+; CHECK-NEXT:br i1 [[TMP10]], label [[PRED_STORE_IF5:%.*]], label 
[[PRED_STORE_CONTINUE6]]
+; CHECK:   pred.store.if5:
+; CHECK-NEXT:[[TMP11:%.*]] = add i32 [[INDEX]], 3
+; CHECK-NEXT:[[TMP12:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 
[[TMP11]]
+; CHECK-NEXT:store i32 13, i32* [[TMP12]], align 1
+; CHECK-NEXT:br label [[PRED_STORE_CONTINUE6]]
+; CHECK:   pred.store.continue6:
+; CHECK-NEXT:[[INDEX_NEXT]] = add i32 [[INDEX]], 4
+; CHECK-NEXT:[[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], 
+; CHECK-NEX

[llvm-branch-commits] [llvm] d9c0b12 - [SCEV] Simplify trunc to zero based on known bits

2021-01-03 Thread Gil Rapaport via llvm-branch-commits 

Author: Gil Rapaport
Date: 2021-01-03T13:57:12+02:00
New Revision: d9c0b128e3543d5d30f43019257bfd96ce4cdcd1

URL: 
https://github.com/llvm/llvm-project/commit/d9c0b128e3543d5d30f43019257bfd96ce4cdcd1
DIFF: 
https://github.com/llvm/llvm-project/commit/d9c0b128e3543d5d30f43019257bfd96ce4cdcd1.diff

LOG: [SCEV] Simplify trunc to zero based on known bits

Let getTruncateExpr() short-circuit to zero when the value being truncated is
known to have at least as many trailing zeros as the target type.

Differential Revision: https://reviews.llvm.org/D93973

Added: 


Modified: 
llvm/lib/Analysis/ScalarEvolution.cpp
llvm/test/Analysis/ScalarEvolution/trunc-simplify.ll

llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-assumed-divisible-TC.ll

Removed: 




diff  --git a/llvm/lib/Analysis/ScalarEvolution.cpp 
b/llvm/lib/Analysis/ScalarEvolution.cpp
index 3c284007cc2d..e807db0e2ac4 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -1222,6 +1222,11 @@ const SCEV *ScalarEvolution::getTruncateExpr(const SCEV 
*Op, Type *Ty,
 return getAddRecExpr(Operands, AddRec->getLoop(), SCEV::FlagAnyWrap);
   }
 
+  // Return zero if truncating to known zeros.
+  uint32_t MinTrailingZeros = GetMinTrailingZeros(Op);
+  if (MinTrailingZeros >= getTypeSizeInBits(Ty))
+return getZero(Ty);
+
   // The cast wasn't folded; create an explicit cast node. We can reuse
   // the existing insert position since if we get here, we won't have
   // made any changes which would invalidate it.

diff  --git a/llvm/test/Analysis/ScalarEvolution/trunc-simplify.ll 
b/llvm/test/Analysis/ScalarEvolution/trunc-simplify.ll
index e4c752b02e0e..d2bc284b3b5d 100644
--- a/llvm/test/Analysis/ScalarEvolution/trunc-simplify.ll
+++ b/llvm/test/Analysis/ScalarEvolution/trunc-simplify.ll
@@ -24,3 +24,25 @@ define i8 @trunc_of_add(i32 %a) {
   %c = trunc i32 %b to i8
   ret i8 %c
 }
+
+; Check that we truncate to zero values assumed to have at least as many
+; trailing zeros as the target type.
+; CHECK-LABEL: @trunc_to_assumed_zeros
+define i8 @trunc_to_assumed_zeros(i32* %p) {
+  %a = load i32, i32* %p
+  %and = and i32 %a, 255
+  %cmp = icmp eq i32 %and, 0
+  tail call void @llvm.assume(i1 %cmp)
+  ; CHECK: %c
+  ; CHECK-NEXT: --> 0
+  %c = trunc i32 %a to i8
+  ; CHECK: %d
+  ; CHECK-NEXT: --> false
+  %d = trunc i32 %a to i1
+  ; CHECK: %e
+  ; CHECK-NEXT: --> (trunc i32 %a to i16)
+  %e = trunc i32 %a to i16
+  ret i8 %c
+}
+
+declare void @llvm.assume(i1 noundef) nofree nosync nounwind willreturn

diff  --git 
a/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-assumed-divisible-TC.ll 
b/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-assumed-divisible-TC.ll
index e0a14db9a6d1..69a856f4598f 100644
--- 
a/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-assumed-divisible-TC.ll
+++ 
b/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-assumed-divisible-TC.ll
@@ -3,7 +3,7 @@
 
 target datalayout = 
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 
-; TODO: Make sure the loop is vectorized under -Os without folding its tail 
based on
+; Make sure the loop is vectorized under -Os without folding its tail based on
 ; its trip-count's lower bits assumed to be zero.
 
 define dso_local void @assumeAlignedTC(i32* noalias nocapture %A, i32* %p) 
optsize {
@@ -13,57 +13,28 @@ define dso_local void @assumeAlignedTC(i32* noalias 
nocapture %A, i32* %p) optsi
 ; CHECK-NEXT:[[AND:%.*]] = and i32 [[N]], 3
 ; CHECK-NEXT:[[CMP:%.*]] = icmp eq i32 [[AND]], 0
 ; CHECK-NEXT:tail call void @llvm.assume(i1 [[CMP]])
-; CHECK-NEXT:br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; CHECK-NEXT:[[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
+; CHECK-NEXT:br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label 
[[VECTOR_PH:%.*]]
 ; CHECK:   vector.ph:
-; CHECK-NEXT:[[N_RND_UP:%.*]] = add i32 [[N]], 3
-; CHECK-NEXT:[[N_MOD_VF:%.*]] = urem i32 [[N_RND_UP]], 4
-; CHECK-NEXT:[[N_VEC:%.*]] = sub i32 [[N_RND_UP]], [[N_MOD_VF]]
-; CHECK-NEXT:[[TRIP_COUNT_MINUS_1:%.*]] = sub i32 [[N]], 1
-; CHECK-NEXT:[[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> 
poison, i32 [[TRIP_COUNT_MINUS_1]], i32 0
-; CHECK-NEXT:[[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> 
[[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT:[[N_MOD_VF:%.*]] = urem i32 [[N]], 4
+; CHECK-NEXT:[[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
 ; CHECK-NEXT:br label [[VECTOR_BODY:%.*]]
 ; CHECK:   vector.body:
-; CHECK-NEXT:[[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ 
[[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE6:%.*]] ]
-; CHECK-NEXT:[[VEC_IND:%.*]] = phi <4 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE6]] ]
-; CHECK-NEXT:[[TMP0:%.*]] = icmp ule <4 x i32> [[VEC_IND]], 
[[BROADCA

[llvm-branch-commits] [llvm] 7ddbe0c - [LV] Merge tests into a single file (NFC)

2021-01-06 Thread Gil Rapaport via llvm-branch-commits 

Author: Gil Rapaport
Date: 2021-01-07T09:04:07+02:00
New Revision: 7ddbe0cb905ec62d37b284a2e8daf54887a35f94

URL: 
https://github.com/llvm/llvm-project/commit/7ddbe0cb905ec62d37b284a2e8daf54887a35f94
DIFF: 
https://github.com/llvm/llvm-project/commit/7ddbe0cb905ec62d37b284a2e8daf54887a35f94.diff

LOG: [LV] Merge tests into a single file (NFC)

In response to https://reviews.llvm.org/D94088#inline-879268

Added: 


Modified: 
llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll

Removed: 

llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-assumed-divisible-TC.ll



diff  --git 
a/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-assumed-divisible-TC.ll 
b/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-assumed-divisible-TC.ll
deleted file mode 100644
index 69a856f4598f..
--- 
a/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-assumed-divisible-TC.ll
+++ /dev/null
@@ -1,70 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -loop-vectorize -force-vector-width=4 -S | FileCheck %s
-
-target datalayout = 
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
-
-; Make sure the loop is vectorized under -Os without folding its tail based on
-; its trip-count's lower bits assumed to be zero.
-
-define dso_local void @assumeAlignedTC(i32* noalias nocapture %A, i32* %p) 
optsize {
-; CHECK-LABEL: @assumeAlignedTC(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:[[N:%.*]] = load i32, i32* [[P:%.*]], align 4
-; CHECK-NEXT:[[AND:%.*]] = and i32 [[N]], 3
-; CHECK-NEXT:[[CMP:%.*]] = icmp eq i32 [[AND]], 0
-; CHECK-NEXT:tail call void @llvm.assume(i1 [[CMP]])
-; CHECK-NEXT:[[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT:br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label 
[[VECTOR_PH:%.*]]
-; CHECK:   vector.ph:
-; CHECK-NEXT:[[N_MOD_VF:%.*]] = urem i32 [[N]], 4
-; CHECK-NEXT:[[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
-; CHECK-NEXT:br label [[VECTOR_BODY:%.*]]
-; CHECK:   vector.body:
-; CHECK-NEXT:[[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ 
[[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT:[[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> 
poison, i32 [[INDEX]], i32 0
-; CHECK-NEXT:[[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> 
[[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
-; CHECK-NEXT:[[INDUCTION:%.*]] = add <4 x i32> [[BROADCAST_SPLAT]], 
-; CHECK-NEXT:[[TMP0:%.*]] = add i32 [[INDEX]], 0
-; CHECK-NEXT:[[TMP1:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], 
i32 [[TMP0]]
-; CHECK-NEXT:[[TMP2:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 0
-; CHECK-NEXT:[[TMP3:%.*]] = bitcast i32* [[TMP2]] to <4 x i32>*
-; CHECK-NEXT:store <4 x i32> , <4 x i32>* 
[[TMP3]], align 1
-; CHECK-NEXT:[[INDEX_NEXT]] = add i32 [[INDEX]], 4
-; CHECK-NEXT:[[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT:br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label 
[[VECTOR_BODY]], [[LOOP0:!llvm.loop !.*]]
-; CHECK:   middle.block:
-; CHECK-NEXT:[[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
-; CHECK-NEXT:br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
-; CHECK:   scalar.ph:
-; CHECK-NEXT:[[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] 
], [ 0, [[ENTRY:%.*]] ]
-; CHECK-NEXT:br label [[LOOP:%.*]]
-; CHECK:   loop:
-; CHECK-NEXT:[[RIV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ 
[[RIVPLUS1:%.*]], [[LOOP]] ]
-; CHECK-NEXT:[[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A]], 
i32 [[RIV]]
-; CHECK-NEXT:store i32 13, i32* [[ARRAYIDX]], align 1
-; CHECK-NEXT:[[RIVPLUS1]] = add nuw nsw i32 [[RIV]], 1
-; CHECK-NEXT:[[COND:%.*]] = icmp eq i32 [[RIVPLUS1]], [[N]]
-; CHECK-NEXT:br i1 [[COND]], label [[EXIT]], label [[LOOP]], 
[[LOOP2:!llvm.loop !.*]]
-; CHECK:   exit:
-; CHECK-NEXT:ret void
-;
-entry:
-  %n = load i32, i32* %p
-  %and = and i32 %n, 3
-  %cmp = icmp eq i32 %and, 0
-  tail call void @llvm.assume(i1 %cmp)
-  br label %loop
-
-loop:
-  %riv = phi i32 [ 0, %entry ], [ %rivPlus1, %loop ]
-  %arrayidx = getelementptr inbounds i32, i32* %A, i32 %riv
-  store i32 13, i32* %arrayidx, align 1
-  %rivPlus1 = add nuw nsw i32 %riv, 1
-  %cond = icmp eq i32 %rivPlus1, %n
-  br i1 %cond, label %exit, label %loop
-
-exit:
-  ret void
-}
-
-declare void @llvm.assume(i1 noundef) nofree nosync nounwind willreturn

diff  --git 
a/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll 
b/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
index c40742fda0d8..1f9cdbad662a 100644
--- a/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
+++ b/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
@@ -60,3 +60,69 @@ loop:
 exit:
   ret void

[llvm-branch-commits] [llvm] a562800 - [LV] Avoid needless fold tail

2020-12-22 Thread Gil Rapaport via llvm-branch-commits 

Author: Gil Rapaport
Date: 2020-12-22T10:25:20+02:00
New Revision: a56280094e08792516b035390a946ea337a27b97

URL: 
https://github.com/llvm/llvm-project/commit/a56280094e08792516b035390a946ea337a27b97
DIFF: 
https://github.com/llvm/llvm-project/commit/a56280094e08792516b035390a946ea337a27b97.diff

LOG: [LV] Avoid needless fold tail

When the trip-count is provably divisible by the maximal/chosen VF, folding the
loop's tail during vectorization is redundant. This commit extends the existing
test for constant trip-counts to any trip-count known to be divisible by
maximal/selected VF by SCEV.

Differential Revision: https://reviews.llvm.org/D93615

Added: 
llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-const-TC.ll
llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll

Modified: 
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp 
b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 25deab6d2b35..680106bcb7c6 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -5512,6 +5512,19 @@ LoopVectorizationCostModel::computeMaxVF(ElementCount 
UserVF, unsigned UserIC) {
 return MaxVF;
   }
 
+  // Avoid tail folding if the trip count is known to be a multiple of any VF 
we
+  // chose.
+  ScalarEvolution *SE = PSE.getSE();
+  const SCEV *BackedgeTakenCount = PSE.getBackedgeTakenCount();
+  const SCEV *ExitCount = SE->getAddExpr(
+  BackedgeTakenCount, SE->getOne(BackedgeTakenCount->getType()));
+  unsigned TCisMultipleOf = 1 << SE->GetMinTrailingZeros(ExitCount);
+  if (TCisMultipleOf % MaxVFtimesIC == 0) {
+// Accept MaxVF if we do not have a tail.
+LLVM_DEBUG(dbgs() << "LV: No tail will remain for any chosen VF.\n");
+return MaxVF;
+  }
+
   // If we don't know the precise trip count, or if the trip count that we
   // found modulo the vectorization factor is not zero, try to fold the tail
   // by masking.

diff  --git a/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-const-TC.ll 
b/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-const-TC.ll
new file mode 100644
index ..0dba201e73fb
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-const-TC.ll
@@ -0,0 +1,69 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -loop-vectorize -force-vector-interleave=3 
-force-vector-width=2 -S | FileCheck %s
+
+target datalayout = 
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+
+; Make sure the loop is vectorized and unrolled under -Os without folding its
+; tail based on its trip-count being provably divisible by chosen VFxIC.
+
+define dso_local void @constTC(i32* noalias nocapture %A) optsize {
+; CHECK-LABEL: @constTC(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; CHECK:   vector.ph:
+; CHECK-NEXT:br label [[VECTOR_BODY:%.*]]
+; CHECK:   vector.body:
+; CHECK-NEXT:[[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ 
[[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:[[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i32> 
undef, i32 [[INDEX]], i32 0
+; CHECK-NEXT:[[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i32> 
[[BROADCAST_SPLATINSERT]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:[[INDUCTION:%.*]] = add <2 x i32> [[BROADCAST_SPLAT]], 
+; CHECK-NEXT:[[INDUCTION1:%.*]] = add <2 x i32> [[BROADCAST_SPLAT]], 
+; CHECK-NEXT:[[INDUCTION2:%.*]] = add <2 x i32> [[BROADCAST_SPLAT]], 
+; CHECK-NEXT:[[TMP0:%.*]] = add i32 [[INDEX]], 0
+; CHECK-NEXT:[[TMP1:%.*]] = add i32 [[INDEX]], 2
+; CHECK-NEXT:[[TMP2:%.*]] = add i32 [[INDEX]], 4
+; CHECK-NEXT:[[TMP3:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], 
i32 [[TMP0]]
+; CHECK-NEXT:[[TMP4:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 
[[TMP1]]
+; CHECK-NEXT:[[TMP5:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 
[[TMP2]]
+; CHECK-NEXT:[[TMP6:%.*]] = getelementptr inbounds i32, i32* [[TMP3]], i32 0
+; CHECK-NEXT:[[TMP7:%.*]] = bitcast i32* [[TMP6]] to <2 x i32>*
+; CHECK-NEXT:store <2 x i32> , <2 x i32>* [[TMP7]], align 1
+; CHECK-NEXT:[[TMP8:%.*]] = getelementptr inbounds i32, i32* [[TMP3]], i32 
2
+; CHECK-NEXT:[[TMP9:%.*]] = bitcast i32* [[TMP8]] to <2 x i32>*
+; CHECK-NEXT:store <2 x i32> , <2 x i32>* [[TMP9]], align 1
+; CHECK-NEXT:[[TMP10:%.*]] = getelementptr inbounds i32, i32* [[TMP3]], 
i32 4
+; CHECK-NEXT:[[TMP11:%.*]] = bitcast i32* [[TMP10]] to <2 x i32>*
+; CHECK-NEXT:store <2 x i32> , <2 x i32>* [[TMP11]], align 
1
+; CHECK-NEXT:[[INDEX_NEXT]] = add i32 [[INDEX]], 6
+; CHECK-NEXT:[[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1800
+; CHECK-NEXT:br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label 
[[VECT