[llvm-branch-commits] [clang] [llvm] [AArch64] Add a check for invalid default features (PR #104752)
https://github.com/jthackray approved this pull request. LGTM. This fix should definitely be in llvm19. https://github.com/llvm/llvm-project/pull/104752 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Codegen for 16/32/64-bit floating-point atomicrmw fminimum/faximum (PR #137703)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/137703
>From c47eaad006a6310f667ac5e12589935b5e62a322 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 23 Apr 2025 21:10:31 +
Subject: [PATCH] [AArch64][llvm] Codegen for 16/32/64-bit floating-point
atomicrmw fminimum/fmaximum
Codegen for AArch64 16/32/64-bit floating-point atomic read-modify-write
operations (`atomicrmw {fmaximum,fminimum}`) using LD{B}FMAX and
LD{B}FMIN atomic instructions.
---
.../Target/AArch64/AArch64ISelLowering.cpp| 14 +-
.../lib/Target/AArch64/AArch64InstrAtomics.td | 7 +
.../AArch64/Atomics/aarch64-atomicrmw-lsfe.ll | 686 +++--
.../Atomics/aarch64_be-atomicrmw-lsfe.ll | 728 +++---
4 files changed, 244 insertions(+), 1191 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 63924dc1b30ea..0d3cd575a517e 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1001,6 +1001,16 @@ AArch64TargetLowering::AArch64TargetLowering(const
TargetMachine &TM,
setOperationAction(ISD::ATOMIC_LOAD_FMIN, MVT::f32, LibCall);
setOperationAction(ISD::ATOMIC_LOAD_FMIN, MVT::f64, LibCall);
setOperationAction(ISD::ATOMIC_LOAD_FMIN, MVT::bf16, LibCall);
+
+setOperationAction(ISD::ATOMIC_LOAD_FMAXIMUM, MVT::f16, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMAXIMUM, MVT::f32, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMAXIMUM, MVT::f64, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMAXIMUM, MVT::bf16, LibCall);
+
+setOperationAction(ISD::ATOMIC_LOAD_FMINIMUM, MVT::f16, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMINIMUM, MVT::f32, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMINIMUM, MVT::f64, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMINIMUM, MVT::bf16, LibCall);
}
if (Subtarget->hasLSE128()) {
@@ -27991,7 +28001,9 @@
AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
// If LSFE available, use atomic FP instructions in preference to expansion
if (Subtarget->hasLSFE() && (AI->getOperation() == AtomicRMWInst::FAdd ||
AI->getOperation() == AtomicRMWInst::FMax ||
- AI->getOperation() == AtomicRMWInst::FMin))
+ AI->getOperation() == AtomicRMWInst::FMin ||
+ AI->getOperation() == AtomicRMWInst::FMaximum ||
+ AI->getOperation() == AtomicRMWInst::FMinimum))
return AtomicExpansionKind::None;
// Nand is not supported in LSE.
diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
index f3734e05ae667..31fcd63b9f2c8 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
@@ -551,14 +551,21 @@ defm atomic_load_fadd :
binary_atomic_op_fp;
defm atomic_load_fmin : binary_atomic_op_fp;
defm atomic_load_fmax : binary_atomic_op_fp;
+defm atomic_load_fminimum : binary_atomic_op_fp;
+defm atomic_load_fmaximum : binary_atomic_op_fp;
+
let Predicates = [HasLSFE] in {
defm : LDFPOPregister_patterns<"LDFADD", "atomic_load_fadd">;
defm : LDFPOPregister_patterns<"LDFMAXNM", "atomic_load_fmax">;
defm : LDFPOPregister_patterns<"LDFMINNM", "atomic_load_fmin">;
+ defm : LDFPOPregister_patterns<"LDFMAX", "atomic_load_fmaximum">;
+ defm : LDFPOPregister_patterns<"LDFMIN", "atomic_load_fminimum">;
defm : LDBFPOPregister_patterns<"LDBFADD", "atomic_load_fadd">;
defm : LDBFPOPregister_patterns<"LDBFMAXNM", "atomic_load_fmax">;
defm : LDBFPOPregister_patterns<"LDBFMINNM", "atomic_load_fmin">;
+ defm : LDBFPOPregister_patterns<"LDBFMAX", "atomic_load_fmaximum">;
+ defm : LDBFPOPregister_patterns<"LDBFMIN", "atomic_load_fminimum">;
}
// v8.9a/v9.4a FEAT_LRCPC patterns
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
index 7ee2a0bb19c0e..d5ead2bff2f18 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
@@ -1600,428 +1600,197 @@ define dso_local double
@atomicrmw_fmin_double_unaligned_seq_cst(ptr %ptr, doubl
}
define dso_local half @atomicrmw_fmaximum_half_aligned_monotonic(ptr %ptr,
half %value) {
-; -O0-LABEL: atomicrmw_fmaximum_half_aligned_monotonic:
-; -O0:ldaxrh w0, [x9]
-; -O0:cmp w0, w10, uxth
-; -O0:stlxrh w8, w11, [x9]
-; -O0:subs w8, w8, w0, uxth
-;
-; -O1-LABEL: atomicrmw_fmaximum_half_aligned_monotonic:
-; -O1:ldxrh w8, [x0]
-; -O1:stxrh w9, w8, [x0]
+; CHECK-LABEL: atomicrmw_fmaximum_half_aligned_monotonic:
+; CHECK:ldfmax h0, h0, [x0]
%r = atomicrmw fmaximum ptr %ptr, half %value monotonic, align 2
ret half %r
}
[llvm-branch-commits] [llvm] [AArch64][llvm] Pre-commit tests for #137703 (NFC) (PR #137702)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/137702
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[llvm-branch-commits] [llvm] [AArch64][llvm] Pre-commit tests for #137703 (NFC) (PR #137702)
jthackray wrote: > Should I look at the ABI to understand if these tests are lowering properly? > Like in here: > https://github.com/ARM-software/abi-aa/blob/main/atomicsabi64/atomicsabi64.rst#id30 Yes, https://github.com/ARM-software/abi-aa/blob/main/atomicsabi64/atomicsabi64.rst#bit-floating-point-types shows what the instructions should be before and after. In PR #137703, you can see in the diffs that this changes to a single `ldfmax` instruction (note, not `ldfmaxnm`, as these were added in #125686). - `atomicrmw fmax` lowers to `ldfmaxnm` instruction - `atomicrmw fmaximum` lowers to `ldfmax` instruction and obviously the fmin/fminimum are similar. https://github.com/llvm/llvm-project/pull/137702 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Codegen for 16/32/64-bit floating-point atomicrmw fminimum/faximum (PR #137703)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/137703
>From b7d9ff97bc6655a38f9adc38021c6bd93f66e1fe Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 23 Apr 2025 21:10:31 +
Subject: [PATCH] [AArch64][llvm] Codegen for 16/32/64-bit floating-point
atomicrmw fminimum/fmaximum
Codegen for AArch64 16/32/64-bit floating-point atomic read-modify-write
operations (`atomicrmw {fmaximum,fminimum}`) using LD{B}FMAX and
LD{B}FMIN atomic instructions.
---
.../Target/AArch64/AArch64ISelLowering.cpp| 14 +-
.../lib/Target/AArch64/AArch64InstrAtomics.td | 7 +
.../AArch64/Atomics/aarch64-atomicrmw-lsfe.ll | 686 +++--
.../Atomics/aarch64_be-atomicrmw-lsfe.ll | 728 +++---
4 files changed, 244 insertions(+), 1191 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 63924dc1b30ea..0d3cd575a517e 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1001,6 +1001,16 @@ AArch64TargetLowering::AArch64TargetLowering(const
TargetMachine &TM,
setOperationAction(ISD::ATOMIC_LOAD_FMIN, MVT::f32, LibCall);
setOperationAction(ISD::ATOMIC_LOAD_FMIN, MVT::f64, LibCall);
setOperationAction(ISD::ATOMIC_LOAD_FMIN, MVT::bf16, LibCall);
+
+setOperationAction(ISD::ATOMIC_LOAD_FMAXIMUM, MVT::f16, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMAXIMUM, MVT::f32, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMAXIMUM, MVT::f64, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMAXIMUM, MVT::bf16, LibCall);
+
+setOperationAction(ISD::ATOMIC_LOAD_FMINIMUM, MVT::f16, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMINIMUM, MVT::f32, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMINIMUM, MVT::f64, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMINIMUM, MVT::bf16, LibCall);
}
if (Subtarget->hasLSE128()) {
@@ -27991,7 +28001,9 @@
AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
// If LSFE available, use atomic FP instructions in preference to expansion
if (Subtarget->hasLSFE() && (AI->getOperation() == AtomicRMWInst::FAdd ||
AI->getOperation() == AtomicRMWInst::FMax ||
- AI->getOperation() == AtomicRMWInst::FMin))
+ AI->getOperation() == AtomicRMWInst::FMin ||
+ AI->getOperation() == AtomicRMWInst::FMaximum ||
+ AI->getOperation() == AtomicRMWInst::FMinimum))
return AtomicExpansionKind::None;
// Nand is not supported in LSE.
diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
index f3734e05ae667..31fcd63b9f2c8 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
@@ -551,14 +551,21 @@ defm atomic_load_fadd :
binary_atomic_op_fp;
defm atomic_load_fmin : binary_atomic_op_fp;
defm atomic_load_fmax : binary_atomic_op_fp;
+defm atomic_load_fminimum : binary_atomic_op_fp;
+defm atomic_load_fmaximum : binary_atomic_op_fp;
+
let Predicates = [HasLSFE] in {
defm : LDFPOPregister_patterns<"LDFADD", "atomic_load_fadd">;
defm : LDFPOPregister_patterns<"LDFMAXNM", "atomic_load_fmax">;
defm : LDFPOPregister_patterns<"LDFMINNM", "atomic_load_fmin">;
+ defm : LDFPOPregister_patterns<"LDFMAX", "atomic_load_fmaximum">;
+ defm : LDFPOPregister_patterns<"LDFMIN", "atomic_load_fminimum">;
defm : LDBFPOPregister_patterns<"LDBFADD", "atomic_load_fadd">;
defm : LDBFPOPregister_patterns<"LDBFMAXNM", "atomic_load_fmax">;
defm : LDBFPOPregister_patterns<"LDBFMINNM", "atomic_load_fmin">;
+ defm : LDBFPOPregister_patterns<"LDBFMAX", "atomic_load_fmaximum">;
+ defm : LDBFPOPregister_patterns<"LDBFMIN", "atomic_load_fminimum">;
}
// v8.9a/v9.4a FEAT_LRCPC patterns
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
index 7ee2a0bb19c0e..d5ead2bff2f18 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
@@ -1600,428 +1600,197 @@ define dso_local double
@atomicrmw_fmin_double_unaligned_seq_cst(ptr %ptr, doubl
}
define dso_local half @atomicrmw_fmaximum_half_aligned_monotonic(ptr %ptr,
half %value) {
-; -O0-LABEL: atomicrmw_fmaximum_half_aligned_monotonic:
-; -O0:ldaxrh w0, [x9]
-; -O0:cmp w0, w10, uxth
-; -O0:stlxrh w8, w11, [x9]
-; -O0:subs w8, w8, w0, uxth
-;
-; -O1-LABEL: atomicrmw_fmaximum_half_aligned_monotonic:
-; -O1:ldxrh w8, [x0]
-; -O1:stxrh w9, w8, [x0]
+; CHECK-LABEL: atomicrmw_fmaximum_half_aligned_monotonic:
+; CHECK:ldfmax h0, h0, [x0]
%r = atomicrmw fmaximum ptr %ptr, half %value monotonic, align 2
ret half %r
}
[llvm-branch-commits] [llvm] [AArch64][llvm] Codegen for 16/32/64-bit floating-point atomicrmw fminimum/faximum (PR #137703)
https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/137703
Codegen for AArch64 16/32/64-bit floating-point atomic read-modify-write
operations (`atomicrmw {fmaximum,fminimum}`) using LD{B}FMAX and LD{B}FMIN
atomic instructions.
>From 6152e58a72cdd9f398250d4320dc513cabe4e8a4 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 23 Apr 2025 21:10:31 +
Subject: [PATCH] [AArch64][llvm] Codegen for 16/32/64-bit floating-point
atomicrmw fminimum/fmaximum
Codegen for AArch64 16/32/64-bit floating-point atomic read-modify-write
operations (`atomicrmw {fmaximum,fminimum}`) using LD{B}FMAX and
LD{B}FMIN atomic instructions.
---
.../Target/AArch64/AArch64ISelLowering.cpp| 14 +-
.../lib/Target/AArch64/AArch64InstrAtomics.td | 7 +
.../AArch64/Atomics/aarch64-atomicrmw-lsfe.ll | 686 +++--
.../Atomics/aarch64_be-atomicrmw-lsfe.ll | 728 +++---
4 files changed, 244 insertions(+), 1191 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 63924dc1b30ea..0d3cd575a517e 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1001,6 +1001,16 @@ AArch64TargetLowering::AArch64TargetLowering(const
TargetMachine &TM,
setOperationAction(ISD::ATOMIC_LOAD_FMIN, MVT::f32, LibCall);
setOperationAction(ISD::ATOMIC_LOAD_FMIN, MVT::f64, LibCall);
setOperationAction(ISD::ATOMIC_LOAD_FMIN, MVT::bf16, LibCall);
+
+setOperationAction(ISD::ATOMIC_LOAD_FMAXIMUM, MVT::f16, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMAXIMUM, MVT::f32, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMAXIMUM, MVT::f64, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMAXIMUM, MVT::bf16, LibCall);
+
+setOperationAction(ISD::ATOMIC_LOAD_FMINIMUM, MVT::f16, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMINIMUM, MVT::f32, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMINIMUM, MVT::f64, LibCall);
+setOperationAction(ISD::ATOMIC_LOAD_FMINIMUM, MVT::bf16, LibCall);
}
if (Subtarget->hasLSE128()) {
@@ -27991,7 +28001,9 @@
AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
// If LSFE available, use atomic FP instructions in preference to expansion
if (Subtarget->hasLSFE() && (AI->getOperation() == AtomicRMWInst::FAdd ||
AI->getOperation() == AtomicRMWInst::FMax ||
- AI->getOperation() == AtomicRMWInst::FMin))
+ AI->getOperation() == AtomicRMWInst::FMin ||
+ AI->getOperation() == AtomicRMWInst::FMaximum ||
+ AI->getOperation() == AtomicRMWInst::FMinimum))
return AtomicExpansionKind::None;
// Nand is not supported in LSE.
diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
index f3734e05ae667..31fcd63b9f2c8 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
@@ -551,14 +551,21 @@ defm atomic_load_fadd :
binary_atomic_op_fp;
defm atomic_load_fmin : binary_atomic_op_fp;
defm atomic_load_fmax : binary_atomic_op_fp;
+defm atomic_load_fminimum : binary_atomic_op_fp;
+defm atomic_load_fmaximum : binary_atomic_op_fp;
+
let Predicates = [HasLSFE] in {
defm : LDFPOPregister_patterns<"LDFADD", "atomic_load_fadd">;
defm : LDFPOPregister_patterns<"LDFMAXNM", "atomic_load_fmax">;
defm : LDFPOPregister_patterns<"LDFMINNM", "atomic_load_fmin">;
+ defm : LDFPOPregister_patterns<"LDFMAX", "atomic_load_fmaximum">;
+ defm : LDFPOPregister_patterns<"LDFMIN", "atomic_load_fminimum">;
defm : LDBFPOPregister_patterns<"LDBFADD", "atomic_load_fadd">;
defm : LDBFPOPregister_patterns<"LDBFMAXNM", "atomic_load_fmax">;
defm : LDBFPOPregister_patterns<"LDBFMINNM", "atomic_load_fmin">;
+ defm : LDBFPOPregister_patterns<"LDBFMAX", "atomic_load_fmaximum">;
+ defm : LDBFPOPregister_patterns<"LDBFMIN", "atomic_load_fminimum">;
}
// v8.9a/v9.4a FEAT_LRCPC patterns
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
index 7ee2a0bb19c0e..d5ead2bff2f18 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
@@ -1600,428 +1600,197 @@ define dso_local double
@atomicrmw_fmin_double_unaligned_seq_cst(ptr %ptr, doubl
}
define dso_local half @atomicrmw_fmaximum_half_aligned_monotonic(ptr %ptr,
half %value) {
-; -O0-LABEL: atomicrmw_fmaximum_half_aligned_monotonic:
-; -O0:ldaxrh w0, [x9]
-; -O0:cmp w0, w10, uxth
-; -O0:stlxrh w8, w11, [x9]
-; -O0:subs w8, w8, w0, uxth
-;
-; -O1-LABEL: atomicrmw_fmaximum_half_aligned_monotonic:
-; -O1:ldxrh w8, [x0]
-; -O1:stxrh w9, w8, [x0]
+; CHECK-LAB
[llvm-branch-commits] [llvm] [AArch64][llvm] Pre-commit tests for #137703 (NFC) (PR #137702)
https://github.com/jthackray edited https://github.com/llvm/llvm-project/pull/137702 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Pre-commit tests for #137703 (NFC) (PR #137702)
jthackray wrote: > Looks like something went wrong here? A rebase fixed it; looks like it was transient. https://github.com/llvm/llvm-project/pull/137702 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (4/4) (NFC) (PR #146331)
https://github.com/jthackray created https://github.com/llvm/llvm-project/pull/146331 This is a series of patches (4/4) to unify assembly/disassembly of recent AArch64 tests into a single file. The aim is to improve consistency, so that all instructions and system registers are thoroughly tested, and future test cases will be in a unified format. This patch: * removes .txt tests whose .s tests have functions * makes the .s tests have a roundabout run line to test both encoding and assembly >From 8c9eccdc95e465fdbfe833080afb1ad1099c224c Mon Sep 17 00:00:00 2001 From: Jonathan Thackray Date: Fri, 27 Jun 2025 20:16:06 +0100 Subject: [PATCH] [AArch64][llvm] Unify AArch64 tests into a single file (4/4) (NFC) This is a series of patches (4/4) to unify assembly/disassembly of recent AArch64 tests into a single file. The aim is to improve consistency, so that all instructions and system registers are thoroughly tested, and future test cases will be in a unified format. This patch: * removes .txt tests whose .s tests have functions * makes the .s tests have a roundabout run line to test both encoding and assembly Co-authored-by: Virginia Cangelosi --- llvm/test/MC/AArch64/armv9.6a-lsui.s | 1073 +++-- llvm/test/MC/AArch64/armv9.6a-occmo.s | 54 +- llvm/test/MC/AArch64/armv9.6a-pcdphint.s | 37 +- llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s | 46 +- .../MC/Disassembler/AArch64/armv9.6a-lsui.txt | 323 - .../Disassembler/AArch64/armv9.6a-occmo.txt | 11 - .../AArch64/armv9.6a-pcdphint.txt |8 - .../AArch64/armv9.6a-rme-gpc3.txt | 18 - 8 files changed, 805 insertions(+), 765 deletions(-) delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-occmo.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-pcdphint.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt diff --git a/llvm/test/MC/AArch64/armv9.6a-lsui.s b/llvm/test/MC/AArch64/armv9.6a-lsui.s index d4a5e1f980560..264a869b6d286 100644 --- a/llvm/test/MC/AArch64/armv9.6a-lsui.s +++ b/llvm/test/MC/AArch64/armv9.6a-lsui.s @@ -1,408 +1,751 @@ -// RUN: llvm-mc -triple aarch64 -mattr=+lsui -show-encoding %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lsui < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lsui < %s \ +// RUN: | llvm-objdump -d --mattr=+lsui --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lsui < %s \ +// RUN: | llvm-objdump -d --mattr=-lsui --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lsui < %s \ +// RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN:| llvm-mc -triple=aarch64 -mattr=+lsui -disassemble -show-encoding \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + -_func: -// CHECK: _func: //-- // Unprivileged load/store operations //-- - ldtxr x9, [sp] -// CHECK: ldtxrx9, [sp]// encoding: [0xe9,0x7f,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldtxr x9, [sp, #0] -// CHECK: ldtxrx9, [sp]// encoding: [0xe9,0x7f,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldtxr x10, [x11] -// CHECK: ldtxrx10, [x11] // encoding: [0x6a,0x7d,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldtxr x10, [x11, #0] -// CHECK: ldtxrx10, [x11] // encoding: [0x6a,0x7d,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - - ldatxr x9, [sp] -// CHECK: ldatxr x9, [sp]// encoding: [0xe9,0xff,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldatxr x10, [x11] -// CHECK: ldatxr x10, [x11] // encoding: [0x6a,0xfd,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - - sttxr wzr, w4, [sp] -// CHECK: sttxrwzr, w4, [sp] // encoding: [0xe4,0x7f,0x1f,0x89] -// ERROR: error: instruction requires: lsui - sttxr wzr, w4, [sp, #0] -// CHECK: sttxrwzr, w4, [sp] // encoding: [0xe4,0x7f,0x1f,0x89] -// ERROR: error: instruction requires: lsui - sttxr w5, x6, [x7] -// CHECK: stt
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) (PR #146329)
https://github.com/jthackray edited https://github.com/llvm/llvm-project/pull/146329 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (3/4) (NFC) (PR #146330)
https://github.com/jthackray edited https://github.com/llvm/llvm-project/pull/146330 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) (PR #146329)
https://github.com/jthackray updated https://github.com/llvm/llvm-project/pull/146329 >From 69c97078a3e7ee1592e5e5c4b2f4eba6455dd96e Mon Sep 17 00:00:00 2001 From: Jonathan Thackray Date: Wed, 25 Jun 2025 21:22:43 +0100 Subject: [PATCH 1/2] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) This is a series of patches (2/4) to unify assembly/disassembly of recent AArch64 tests into a single file. The aim is to improve consistency, so that all instructions and system registers are thoroughly tested, and future test cases will be in a unified format. This patch: * removes .txt tests which have only one feature required * makes the .s tests have a roundabout run line to test both encoding and assembly * creates diagnostic tests when needed * fixes naming convention of tests Co-authored-by: Virginia Cangelosi --- llvm/test/MC/AArch64/armv9.2a-mec.s | 172 ++- llvm/test/MC/AArch64/armv9.4-lse128.s | 98 - llvm/test/MC/AArch64/armv9.4a-gcs.s | 198 +- .../MC/AArch64/armv9.4a-lse128-diagnostics.s | 17 ++ llvm/test/MC/AArch64/armv9.4a-lse128.s| 138 llvm/test/MC/AArch64/armv9.5a-cpa.s | 89 +--- .../MC/AArch64/armv9.6a-mpam-diagnostics.s| 5 + llvm/test/MC/AArch64/armv9.6a-mpam.s | 80 +-- .../MC/Disassembler/AArch64/armv9.4a-gcs.txt | 90 .../Disassembler/AArch64/armv9.4a-lse128.txt | 98 - .../MC/Disassembler/AArch64/armv9.5a-cpa.txt | 42 .../MC/Disassembler/AArch64/armv9.6a-mpam.txt | 50 - .../MC/Disassembler/AArch64/armv9a-mec.txt| 54 - 13 files changed, 541 insertions(+), 590 deletions(-) delete mode 100644 llvm/test/MC/AArch64/armv9.4-lse128.s create mode 100644 llvm/test/MC/AArch64/armv9.4a-lse128-diagnostics.s create mode 100644 llvm/test/MC/AArch64/armv9.4a-lse128.s create mode 100644 llvm/test/MC/AArch64/armv9.6a-mpam-diagnostics.s delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.4a-gcs.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.4a-lse128.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-cpa.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-mpam.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt diff --git a/llvm/test/MC/AArch64/armv9.2a-mec.s b/llvm/test/MC/AArch64/armv9.2a-mec.s index 42e4bf732086e..c747886f7ec3b 100644 --- a/llvm/test/MC/AArch64/armv9.2a-mec.s +++ b/llvm/test/MC/AArch64/armv9.2a-mec.s @@ -1,55 +1,117 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mec < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=CHECK-NO-MEC %s - - mrs x0, MECIDR_EL2 -// CHECK: mrs x0, MECIDR_EL2 // encoding: [0xe0,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_P0_EL2 -// CHECK: mrs x0, MECID_P0_EL2 // encoding: [0x00,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_A0_EL2 -// CHECK: mrs x0, MECID_A0_EL2 // encoding: [0x20,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_P1_EL2 -// CHECK: mrs x0, MECID_P1_EL2 // encoding: [0x40,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_A1_EL2 -// CHECK: mrs x0, MECID_A1_EL2 // encoding: [0x60,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, VMECID_P_EL2 -// CHECK: mrs x0, VMECID_P_EL2 // encoding: [0x00,0xa9,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, VMECID_A_EL2 -// CHECK: mrs x0, VMECID_A_EL2 // encoding: [0x20,0xa9,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_RL_A_EL3 -// CHECK: mrs x0, MECID_RL_A_EL3 // encoding: [0x20,0xaa,0x3e,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - msr MECID_P0_EL2,x0 -// CHECK: msr MECID_P0_EL2, x0 // encoding: [0x00,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_A0_EL2,x0 -// CHECK: msr MECID_A0_EL2, x0 // encoding: [0x20,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_P1_EL2,x0 -// CHECK: msr MECID_P1_EL2, x0 // encoding: [0x40,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_A1_EL2,x0 -// CHECK: msr MECID_A1_EL2, x0 // encoding: [0x60,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - m
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) (PR #146329)
https://github.com/jthackray updated https://github.com/llvm/llvm-project/pull/146329 >From 69c97078a3e7ee1592e5e5c4b2f4eba6455dd96e Mon Sep 17 00:00:00 2001 From: Jonathan Thackray Date: Wed, 25 Jun 2025 21:22:43 +0100 Subject: [PATCH 1/2] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) This is a series of patches (2/4) to unify assembly/disassembly of recent AArch64 tests into a single file. The aim is to improve consistency, so that all instructions and system registers are thoroughly tested, and future test cases will be in a unified format. This patch: * removes .txt tests which have only one feature required * makes the .s tests have a roundabout run line to test both encoding and assembly * creates diagnostic tests when needed * fixes naming convention of tests Co-authored-by: Virginia Cangelosi --- llvm/test/MC/AArch64/armv9.2a-mec.s | 172 ++- llvm/test/MC/AArch64/armv9.4-lse128.s | 98 - llvm/test/MC/AArch64/armv9.4a-gcs.s | 198 +- .../MC/AArch64/armv9.4a-lse128-diagnostics.s | 17 ++ llvm/test/MC/AArch64/armv9.4a-lse128.s| 138 llvm/test/MC/AArch64/armv9.5a-cpa.s | 89 +--- .../MC/AArch64/armv9.6a-mpam-diagnostics.s| 5 + llvm/test/MC/AArch64/armv9.6a-mpam.s | 80 +-- .../MC/Disassembler/AArch64/armv9.4a-gcs.txt | 90 .../Disassembler/AArch64/armv9.4a-lse128.txt | 98 - .../MC/Disassembler/AArch64/armv9.5a-cpa.txt | 42 .../MC/Disassembler/AArch64/armv9.6a-mpam.txt | 50 - .../MC/Disassembler/AArch64/armv9a-mec.txt| 54 - 13 files changed, 541 insertions(+), 590 deletions(-) delete mode 100644 llvm/test/MC/AArch64/armv9.4-lse128.s create mode 100644 llvm/test/MC/AArch64/armv9.4a-lse128-diagnostics.s create mode 100644 llvm/test/MC/AArch64/armv9.4a-lse128.s create mode 100644 llvm/test/MC/AArch64/armv9.6a-mpam-diagnostics.s delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.4a-gcs.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.4a-lse128.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-cpa.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-mpam.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt diff --git a/llvm/test/MC/AArch64/armv9.2a-mec.s b/llvm/test/MC/AArch64/armv9.2a-mec.s index 42e4bf732086e..c747886f7ec3b 100644 --- a/llvm/test/MC/AArch64/armv9.2a-mec.s +++ b/llvm/test/MC/AArch64/armv9.2a-mec.s @@ -1,55 +1,117 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mec < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=CHECK-NO-MEC %s - - mrs x0, MECIDR_EL2 -// CHECK: mrs x0, MECIDR_EL2 // encoding: [0xe0,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_P0_EL2 -// CHECK: mrs x0, MECID_P0_EL2 // encoding: [0x00,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_A0_EL2 -// CHECK: mrs x0, MECID_A0_EL2 // encoding: [0x20,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_P1_EL2 -// CHECK: mrs x0, MECID_P1_EL2 // encoding: [0x40,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_A1_EL2 -// CHECK: mrs x0, MECID_A1_EL2 // encoding: [0x60,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, VMECID_P_EL2 -// CHECK: mrs x0, VMECID_P_EL2 // encoding: [0x00,0xa9,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, VMECID_A_EL2 -// CHECK: mrs x0, VMECID_A_EL2 // encoding: [0x20,0xa9,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_RL_A_EL3 -// CHECK: mrs x0, MECID_RL_A_EL3 // encoding: [0x20,0xaa,0x3e,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - msr MECID_P0_EL2,x0 -// CHECK: msr MECID_P0_EL2, x0 // encoding: [0x00,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_A0_EL2,x0 -// CHECK: msr MECID_A0_EL2, x0 // encoding: [0x20,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_P1_EL2,x0 -// CHECK: msr MECID_P1_EL2, x0 // encoding: [0x40,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_A1_EL2,x0 -// CHECK: msr MECID_A1_EL2, x0 // encoding: [0x60,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - m
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (3/4) (NFC) (PR #146330)
@@ -1,592 +1,697 @@ -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+the -mattr=+d128 < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a -mattr=+the -mattr=+d128 < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a -mattr=+the -mattr=+d128 < %s | FileCheck %s +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+the,+d128 < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+the,+d128,v8.9a < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+the,+d128,v9.4a < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+the,+d128 < %s \ +// RUN:| llvm-objdump -d --mattr=+the,+d128 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+the,+d128 < %s \ +// RUN: | llvm-objdump -d --mattr=-the,-d128 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+the,+d128 < %s \ +// RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN:| llvm-mc -triple=aarch64 -mattr=+the,+d128 -disassemble -show-encoding \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST -// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-THE %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.9a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-THE %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v9.4a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-THE %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+the < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-D128 %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.9a -mattr=+the < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-D128 %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v9.4a -mattr=+the < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-D128 %s +mrs x3, RCWMASK_EL1 +// CHECK-INST: mrs x3, RCWMASK_EL1 +// CHECK-ENCODING: encoding: [0xc3,0xd0,0x38,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d538d0c3 mrs x3, S3_0_C13_C0_6 -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+the -mattr=+d128 < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ZXR %s +msr RCWMASK_EL1, x1 +// CHECK-INST: msr RCWMASK_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0xd0,0x18,0xd5] +// CHECK-ERROR: error: expected writable system register or pstate +// CHECK-UNKNOWN: d518d0c1 msr S3_0_C13_C0_6, x1 -mrs x3, RCWMASK_EL1 -// CHECK: mrs x3, RCWMASK_EL1 // encoding: [0xc3,0xd0,0x38,0xd5] -// ERROR-NO-THE: [[@LINE-2]]:21: error: expected readable system register -msr RCWMASK_EL1, x1 -// CHECK: msr RCWMASK_EL1, x1 // encoding: [0xc1,0xd0,0x18,0xd5] -// ERROR-NO-THE: [[@LINE-2]]:17: error: expected writable system register or pstate -mrs x3, RCWSMASK_EL1 -// CHECK: mrs x3, RCWSMASK_EL1 // encoding: [0x63,0xd0,0x38,0xd5] -// ERROR-NO-THE: [[@LINE-2]]:21: error: expected readable system register -msr RCWSMASK_EL1, x1 -// CHECK: msr RCWSMASK_EL1, x1 // encoding: [0x61,0xd0,0x18,0xd5] -// ERROR-NO-THE: [[@LINE-2]]:17: error: expected writable system register or pstate +mrs x3, RCWSMASK_EL1 +// CHECK-INST: mrs x3, RCWSMASK_EL1 +// CHECK-ENCODING: encoding: [0x63,0xd0,0x38,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d538d063 mrs x3, S3_0_C13_C0_3 +msr RCWSMASK_EL1, x1 +// CHECK-INST: msr RCWSMASK_EL1, x1 +// CHECK-ENCODING: encoding: [0x61,0xd0,0x18,0xd5] +// CHECK-ERROR: error: expected writable system register or pstate +// CHECK-UNKNOWN: d518d061 msr S3_0_C13_C0_3, x1 -rcwcas x0, x1, [x4] -// CHECK: rcwcas x0, x1, [x4] // encoding: [0x81,0x08,0x20,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the -rcwcasa x0, x1, [x4] -// CHECK: rcwcasa x0, x1, [x4] // encoding: [0x81,0x08,0xa0,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the -rcwcasal x0, x1, [x4] -// CHECK: rcwcasal x0, x1, [x4] // encoding: [0x81,0x08,0xe0,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the -rcwcasl x0, x1, [x4] -// CHECK: rcwcasl x0, x1, [x4] // encoding: [0x81,0x08,0x60,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (3/4) (NFC) (PR #146330)
@@ -16,28 +16,41 @@ // RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9.3a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22 // Optional, off by default, manually enabled -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8.8a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9.3a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB +// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8.8a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9.3a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST jthackray wrote: I'm not sure (Virginia converted this file) but I suspect because it has fairly extensive version-dependent tests at the top. https://github.com/llvm/llvm-project/pull/146330 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (4/4) (NFC) (PR #146331)
https://github.com/jthackray updated https://github.com/llvm/llvm-project/pull/146331 >From 8c9eccdc95e465fdbfe833080afb1ad1099c224c Mon Sep 17 00:00:00 2001 From: Jonathan Thackray Date: Fri, 27 Jun 2025 20:16:06 +0100 Subject: [PATCH 1/2] [AArch64][llvm] Unify AArch64 tests into a single file (4/4) (NFC) This is a series of patches (4/4) to unify assembly/disassembly of recent AArch64 tests into a single file. The aim is to improve consistency, so that all instructions and system registers are thoroughly tested, and future test cases will be in a unified format. This patch: * removes .txt tests whose .s tests have functions * makes the .s tests have a roundabout run line to test both encoding and assembly Co-authored-by: Virginia Cangelosi --- llvm/test/MC/AArch64/armv9.6a-lsui.s | 1073 +++-- llvm/test/MC/AArch64/armv9.6a-occmo.s | 54 +- llvm/test/MC/AArch64/armv9.6a-pcdphint.s | 37 +- llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s | 46 +- .../MC/Disassembler/AArch64/armv9.6a-lsui.txt | 323 - .../Disassembler/AArch64/armv9.6a-occmo.txt | 11 - .../AArch64/armv9.6a-pcdphint.txt |8 - .../AArch64/armv9.6a-rme-gpc3.txt | 18 - 8 files changed, 805 insertions(+), 765 deletions(-) delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-occmo.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-pcdphint.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt diff --git a/llvm/test/MC/AArch64/armv9.6a-lsui.s b/llvm/test/MC/AArch64/armv9.6a-lsui.s index d4a5e1f980560..264a869b6d286 100644 --- a/llvm/test/MC/AArch64/armv9.6a-lsui.s +++ b/llvm/test/MC/AArch64/armv9.6a-lsui.s @@ -1,408 +1,751 @@ -// RUN: llvm-mc -triple aarch64 -mattr=+lsui -show-encoding %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lsui < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lsui < %s \ +// RUN: | llvm-objdump -d --mattr=+lsui --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lsui < %s \ +// RUN: | llvm-objdump -d --mattr=-lsui --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lsui < %s \ +// RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN:| llvm-mc -triple=aarch64 -mattr=+lsui -disassemble -show-encoding \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + -_func: -// CHECK: _func: //-- // Unprivileged load/store operations //-- - ldtxr x9, [sp] -// CHECK: ldtxrx9, [sp]// encoding: [0xe9,0x7f,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldtxr x9, [sp, #0] -// CHECK: ldtxrx9, [sp]// encoding: [0xe9,0x7f,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldtxr x10, [x11] -// CHECK: ldtxrx10, [x11] // encoding: [0x6a,0x7d,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldtxr x10, [x11, #0] -// CHECK: ldtxrx10, [x11] // encoding: [0x6a,0x7d,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - - ldatxr x9, [sp] -// CHECK: ldatxr x9, [sp]// encoding: [0xe9,0xff,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldatxr x10, [x11] -// CHECK: ldatxr x10, [x11] // encoding: [0x6a,0xfd,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - - sttxr wzr, w4, [sp] -// CHECK: sttxrwzr, w4, [sp] // encoding: [0xe4,0x7f,0x1f,0x89] -// ERROR: error: instruction requires: lsui - sttxr wzr, w4, [sp, #0] -// CHECK: sttxrwzr, w4, [sp] // encoding: [0xe4,0x7f,0x1f,0x89] -// ERROR: error: instruction requires: lsui - sttxr w5, x6, [x7] -// CHECK: sttxrw5, x6, [x7]// encoding: [0xe6,0x7c,0x05,0xc9] -// ERROR: error: instruction requires: lsui - sttxr w5, x6, [x7, #0] -// CHECK: sttxrw5, x6, [x7]// encoding: [0xe6,0x7c,0x05,0xc9] -// ERROR: error: instruction requires: lsui - - stltxr w2, w4, [sp] -// CHECK: stltxr w2, w4, [sp]// encoding: [0xe4,0xff,0x02,0x89]
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) (PR #146329)
https://github.com/jthackray updated https://github.com/llvm/llvm-project/pull/146329 >From be8bcdead883ec9bac8bebf6b3382974fc988c28 Mon Sep 17 00:00:00 2001 From: Jonathan Thackray Date: Wed, 25 Jun 2025 21:22:43 +0100 Subject: [PATCH 1/2] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) This is a series of patches (2/4) to unify assembly/disassembly of recent AArch64 tests into a single file. The aim is to improve consistency, so that all instructions and system registers are thoroughly tested, and future test cases will be in a unified format. This patch: * removes .txt tests which have only one feature required * makes the .s tests have a roundabout run line to test both encoding and assembly * creates diagnostic tests when needed * fixes naming convention of tests Co-authored-by: Virginia Cangelosi --- llvm/test/MC/AArch64/armv9.2a-mec.s | 172 ++- llvm/test/MC/AArch64/armv9.4-lse128.s | 98 - llvm/test/MC/AArch64/armv9.4a-gcs.s | 198 +- .../MC/AArch64/armv9.4a-lse128-diagnostics.s | 17 ++ llvm/test/MC/AArch64/armv9.4a-lse128.s| 138 llvm/test/MC/AArch64/armv9.5a-cpa.s | 89 +--- .../MC/AArch64/armv9.6a-mpam-diagnostics.s| 5 + llvm/test/MC/AArch64/armv9.6a-mpam.s | 80 +-- .../MC/Disassembler/AArch64/armv9.4a-gcs.txt | 90 .../Disassembler/AArch64/armv9.4a-lse128.txt | 98 - .../MC/Disassembler/AArch64/armv9.5a-cpa.txt | 42 .../MC/Disassembler/AArch64/armv9.6a-mpam.txt | 50 - .../MC/Disassembler/AArch64/armv9a-mec.txt| 54 - 13 files changed, 541 insertions(+), 590 deletions(-) delete mode 100644 llvm/test/MC/AArch64/armv9.4-lse128.s create mode 100644 llvm/test/MC/AArch64/armv9.4a-lse128-diagnostics.s create mode 100644 llvm/test/MC/AArch64/armv9.4a-lse128.s create mode 100644 llvm/test/MC/AArch64/armv9.6a-mpam-diagnostics.s delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.4a-gcs.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.4a-lse128.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-cpa.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-mpam.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt diff --git a/llvm/test/MC/AArch64/armv9.2a-mec.s b/llvm/test/MC/AArch64/armv9.2a-mec.s index 42e4bf732086e..c747886f7ec3b 100644 --- a/llvm/test/MC/AArch64/armv9.2a-mec.s +++ b/llvm/test/MC/AArch64/armv9.2a-mec.s @@ -1,55 +1,117 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mec < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=CHECK-NO-MEC %s - - mrs x0, MECIDR_EL2 -// CHECK: mrs x0, MECIDR_EL2 // encoding: [0xe0,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_P0_EL2 -// CHECK: mrs x0, MECID_P0_EL2 // encoding: [0x00,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_A0_EL2 -// CHECK: mrs x0, MECID_A0_EL2 // encoding: [0x20,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_P1_EL2 -// CHECK: mrs x0, MECID_P1_EL2 // encoding: [0x40,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_A1_EL2 -// CHECK: mrs x0, MECID_A1_EL2 // encoding: [0x60,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, VMECID_P_EL2 -// CHECK: mrs x0, VMECID_P_EL2 // encoding: [0x00,0xa9,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, VMECID_A_EL2 -// CHECK: mrs x0, VMECID_A_EL2 // encoding: [0x20,0xa9,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_RL_A_EL3 -// CHECK: mrs x0, MECID_RL_A_EL3 // encoding: [0x20,0xaa,0x3e,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - msr MECID_P0_EL2,x0 -// CHECK: msr MECID_P0_EL2, x0 // encoding: [0x00,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_A0_EL2,x0 -// CHECK: msr MECID_A0_EL2, x0 // encoding: [0x20,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_P1_EL2,x0 -// CHECK: msr MECID_P1_EL2, x0 // encoding: [0x40,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_A1_EL2,x0 -// CHECK: msr MECID_A1_EL2, x0 // encoding: [0x60,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - m
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) (PR #146329)
@@ -1,55 +1,117 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mec < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=CHECK-NO-MEC %s - - mrs x0, MECIDR_EL2 -// CHECK: mrs x0, MECIDR_EL2 // encoding: [0xe0,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_P0_EL2 -// CHECK: mrs x0, MECID_P0_EL2 // encoding: [0x00,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_A0_EL2 -// CHECK: mrs x0, MECID_A0_EL2 // encoding: [0x20,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_P1_EL2 -// CHECK: mrs x0, MECID_P1_EL2 // encoding: [0x40,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_A1_EL2 -// CHECK: mrs x0, MECID_A1_EL2 // encoding: [0x60,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, VMECID_P_EL2 -// CHECK: mrs x0, VMECID_P_EL2 // encoding: [0x00,0xa9,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, VMECID_A_EL2 -// CHECK: mrs x0, VMECID_A_EL2 // encoding: [0x20,0xa9,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_RL_A_EL3 -// CHECK: mrs x0, MECID_RL_A_EL3 // encoding: [0x20,0xaa,0x3e,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - msr MECID_P0_EL2,x0 -// CHECK: msr MECID_P0_EL2, x0 // encoding: [0x00,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_A0_EL2,x0 -// CHECK: msr MECID_A0_EL2, x0 // encoding: [0x20,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_P1_EL2,x0 -// CHECK: msr MECID_P1_EL2, x0 // encoding: [0x40,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_A1_EL2,x0 -// CHECK: msr MECID_A1_EL2, x0 // encoding: [0x60,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr VMECID_P_EL2, x0 -// CHECK: msr VMECID_P_EL2, x0 // encoding: [0x00,0xa9,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr VMECID_A_EL2, x0 -// CHECK: msr VMECID_A_EL2, x0 // encoding: [0x20,0xa9,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_RL_A_EL3, x0 -// CHECK: msr MECID_RL_A_EL3, x0 // encoding: [0x20,0xaa,0x1e,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - - dc cigdpae, x0 -// CHECK: dc cigdpae, x0 // encoding: [0xe0,0x7e,0x0c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIGDPAE requires: mec - dc cipae, x0 -// CHECK: dc cipae, x0 // encoding: [0x00,0x7e,0x0c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIPAE requires: mec +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mec < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mec < %s \ +// RUN:| llvm-objdump -d --mattr=+mec --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mec < %s \ +// RUN: | llvm-objdump -d --mattr=-mec --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mec < %s \ +// RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN:| llvm-mc -triple=aarch64 -mattr=+mec -disassemble -show-encoding \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + + +mrs x0, MECIDR_EL2 +// CHECK-INST: mrs x0, MECIDR_EL2 +// CHECK-ENCODING: encoding: [0xe0,0xa8,0x3c,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d53ca8e0 mrs x0, S3_4_C10_C8_7 + +mrs x0, MECID_P0_EL2 +// CHECK-INST: mrs x0, MECID_P0_EL2 +// CHECK-ENCODING: encoding: [0x00,0xa8,0x3c,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d53ca800 mrs x0, S3_4_C10_C8_0 + +mrs x0, MECID_A0_EL2 +// CHECK-INST: mrs x0, MECID_A0_EL2 +// CHECK-ENCODING: encoding: [0x20,0xa8,0x3c,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d53ca820 mrs
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) (PR #146329)
@@ -0,0 +1,138 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lse128 < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lse128 < %s \ +// RUN:| llvm-objdump -d --mattr=+lse128 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lse128 < %s \ +// RUN: | llvm-objdump -d --mattr=-lse128 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lse128 < %s \ +// RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN:| llvm-mc -triple=aarch64 -mattr=+lse128 -disassemble -show-encoding \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + + +ldclrp x1, x2, [x11] +// CHECK-INST: ldclrp x1, x2, [x11] +// CHECK-ENCODING: encoding: [0x61,0x11,0x22,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19221161 +ldclrp x21, x22, [sp] jthackray wrote: Thanks, now fixed. https://github.com/llvm/llvm-project/pull/146329 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) (PR #146329)
https://github.com/jthackray edited https://github.com/llvm/llvm-project/pull/146329 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) (PR #146329)
@@ -1,115 +1,203 @@ -// RUN: llvm-mc -triple aarch64 -mattr +gcs -show-encoding %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64 -show-encoding %s 2>%t | FileCheck %s --check-prefix=NO-GCS -// RUN: FileCheck --check-prefix=ERROR-NO-GCS %s < %t +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+gcs < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+gcs < %s \ +// RUN:| llvm-objdump -d --mattr=+gcs --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+gcs < %s \ +// RUN: | llvm-objdump -d --mattr=-gcs --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+gcs < %s \ +// RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN:| llvm-mc -triple=aarch64 -mattr=+gcs -disassemble -show-encoding \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + msr GCSCR_EL1, x0 +// CHECK-INST: msr GCSCR_EL1, x0 +// CHECK-ENCODING: encoding: [0x00,0x25,0x18,0xd5] +// CHECK-UNKNOWN: d5182500 msr GCSCR_EL1, x0 + mrs x1, GCSCR_EL1 -// CHECK: msr GCSCR_EL1, x0 // encoding: [0x00,0x25,0x18,0xd5] -// CHECK: mrs x1, GCSCR_EL1 // encoding: [0x01,0x25,0x38,0xd5] +// CHECK-INST: mrs x1, GCSCR_EL1 +// CHECK-ENCODING: encoding: [0x01,0x25,0x38,0xd5] +// CHECK-UNKNOWN: d5382501 mrs x1, GCSCR_EL1 msr GCSPR_EL1, x2 +// CHECK-INST: msr GCSPR_EL1, x2 +// CHECK-ENCODING: encoding: [0x22,0x25,0x18,0xd5] +// CHECK-UNKNOWN: d5182522 msr GCSPR_EL1, x2 + mrs x3, GCSPR_EL1 -// CHECK: msr GCSPR_EL1, x2 // encoding: [0x22,0x25,0x18,0xd5] -// CHECK: mrs x3, GCSPR_EL1 // encoding: [0x23,0x25,0x38,0xd5] +// CHECK-INST: mrs x3, GCSPR_EL1 +// CHECK-ENCODING: encoding: [0x23,0x25,0x38,0xd5] +// CHECK-UNKNOWN: d5382523 mrs x3, GCSPR_EL1 msr GCSCRE0_EL1, x4 +// CHECK-INST: msr GCSCRE0_EL1, x4 +// CHECK-ENCODING: encoding: [0x44,0x25,0x18,0xd5] +// CHECK-UNKNOWN: d5182544 msr GCSCRE0_EL1, x4 + mrs x5, GCSCRE0_EL1 -// CHECK: msr GCSCRE0_EL1, x4 // encoding: [0x44,0x25,0x18,0xd5] -// CHECK: mrs x5, GCSCRE0_EL1 // encoding: [0x45,0x25,0x38,0xd5] +// CHECK-INST: mrs x5, GCSCRE0_EL1 +// CHECK-ENCODING: encoding: [0x45,0x25,0x38,0xd5] +// CHECK-UNKNOWN: d5382545 mrs x5, GCSCRE0_EL1 msr GCSPR_EL0, x6 +// CHECK-INST: msr GCSPR_EL0, x6 +// CHECK-ENCODING: encoding: [0x26,0x25,0x1b,0xd5] +// CHECK-UNKNOWN: d51b2526 msr GCSPR_EL0, x6 + mrs x7, GCSPR_EL0 -// CHECK: msr GCSPR_EL0, x6 // encoding: [0x26,0x25,0x1b,0xd5] -// CHECK: mrs x7, GCSPR_EL0 // encoding: [0x27,0x25,0x3b,0xd5] +// CHECK-INST: mrs x7, GCSPR_EL0 +// CHECK-ENCODING: encoding: [0x27,0x25,0x3b,0xd5] +// CHECK-UNKNOWN: d53b2527 mrs x7, GCSPR_EL0 msr GCSCR_EL2, x10 +// CHECK-INST: msr GCSCR_EL2, x10 +// CHECK-ENCODING: encoding: [0x0a,0x25,0x1c,0xd5] +// CHECK-UNKNOWN: d51c250a msr GCSCR_EL2, x10 + mrs x11, GCSCR_EL2 -// CHECK: msr GCSCR_EL2, x10 // encoding: [0x0a,0x25,0x1c,0xd5] -// CHECK: mrs x11, GCSCR_EL2 // encoding: [0x0b,0x25,0x3c,0xd5] +// CHECK-INST: mrs x11, GCSCR_EL2 +// CHECK-ENCODING: encoding: [0x0b,0x25,0x3c,0xd5] +// CHECK-UNKNOWN: d53c250b mrs x11, GCSCR_EL2 msr GCSPR_EL2, x12 +// CHECK-INST: msr GCSPR_EL2, x12 +// CHECK-ENCODING: encoding: [0x2c,0x25,0x1c,0xd5] +// CHECK-UNKNOWN: d51c252c msr GCSPR_EL2, x12 + mrs x13, GCSPR_EL2 -// CHECK: msr GCSPR_EL2, x12 // encoding: [0x2c,0x25,0x1c,0xd5] -// CHECK: mrs x13, GCSPR_EL2 // encoding: [0x2d,0x25,0x3c,0xd5] +// CHECK-INST: mrs x13, GCSPR_EL2 +// CHECK-ENCODING: encoding: [0x2d,0x25,0x3c,0xd5] +// CHECK-UNKNOWN: d53c252d mrs x13, GCSPR_EL2 msr GCSCR_EL12, x14 +// CHECK-INST: msr GCSCR_EL12, x14 +// CHECK-ENCODING: encoding: [0x0e,0x25,0x1d,0xd5] +// CHECK-UNKNOWN: d51d250e msr GCSCR_EL12, x14 + mrs x15, GCSCR_EL12 -// CHECK: msr GCSCR_EL12, x14 // encoding: [0x0e,0x25,0x1d,0xd5] -// CHECK: mrs x15, GCSCR_EL12 // encoding: [0x0f,0x25,0x3d,0xd5] +// CHECK-INST: mrs x15, GCSCR_EL12 +// CHECK-ENCODING: encoding: [0x0f,0x25,0x3d,0xd5] +// CHECK-UNKNOWN: d53d250f mrs x15, GCSCR_EL12 msr GCSPR_EL12, x16 +// CHECK-INST: msr GCSPR_EL12, x16 +// CHECK-ENCODING: encoding: [0x30,0x25,0x1d,0xd5] +// CHECK-UNKNOWN: d51d2530 msr GCSPR_EL12, x16 + mrs x17, GCSPR_EL12 -// CHECK: msr GCSPR_EL12, x16 // encoding: [0x30,0x25,0x1d,0xd5] -// CHECK: mrs x17, GCSPR_EL12 // encoding: [0
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) (PR #146329)
https://github.com/jthackray created https://github.com/llvm/llvm-project/pull/146329 This is a series of patches (2/4) to unify assembly/disassembly of recent AArch64 tests into a single file. The aim is to improve consistency, so that all instructions and system registers are thoroughly tested, and future test cases will be in a unified format. This patch: * removes .txt tests which have only one feature required * makes the .s tests have a roundabout run line to test both encoding and assembly * creates diagnostic tests when needed * fixes naming convention of tests >From be8bcdead883ec9bac8bebf6b3382974fc988c28 Mon Sep 17 00:00:00 2001 From: Jonathan Thackray Date: Wed, 25 Jun 2025 21:22:43 +0100 Subject: [PATCH] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) This is a series of patches (2/4) to unify assembly/disassembly of recent AArch64 tests into a single file. The aim is to improve consistency, so that all instructions and system registers are thoroughly tested, and future test cases will be in a unified format. This patch: * removes .txt tests which have only one feature required * makes the .s tests have a roundabout run line to test both encoding and assembly * creates diagnostic tests when needed * fixes naming convention of tests Co-authored-by: Virginia Cangelosi --- llvm/test/MC/AArch64/armv9.2a-mec.s | 172 ++- llvm/test/MC/AArch64/armv9.4-lse128.s | 98 - llvm/test/MC/AArch64/armv9.4a-gcs.s | 198 +- .../MC/AArch64/armv9.4a-lse128-diagnostics.s | 17 ++ llvm/test/MC/AArch64/armv9.4a-lse128.s| 138 llvm/test/MC/AArch64/armv9.5a-cpa.s | 89 +--- .../MC/AArch64/armv9.6a-mpam-diagnostics.s| 5 + llvm/test/MC/AArch64/armv9.6a-mpam.s | 80 +-- .../MC/Disassembler/AArch64/armv9.4a-gcs.txt | 90 .../Disassembler/AArch64/armv9.4a-lse128.txt | 98 - .../MC/Disassembler/AArch64/armv9.5a-cpa.txt | 42 .../MC/Disassembler/AArch64/armv9.6a-mpam.txt | 50 - .../MC/Disassembler/AArch64/armv9a-mec.txt| 54 - 13 files changed, 541 insertions(+), 590 deletions(-) delete mode 100644 llvm/test/MC/AArch64/armv9.4-lse128.s create mode 100644 llvm/test/MC/AArch64/armv9.4a-lse128-diagnostics.s create mode 100644 llvm/test/MC/AArch64/armv9.4a-lse128.s create mode 100644 llvm/test/MC/AArch64/armv9.6a-mpam-diagnostics.s delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.4a-gcs.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.4a-lse128.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-cpa.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-mpam.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt diff --git a/llvm/test/MC/AArch64/armv9.2a-mec.s b/llvm/test/MC/AArch64/armv9.2a-mec.s index 42e4bf732086e..c747886f7ec3b 100644 --- a/llvm/test/MC/AArch64/armv9.2a-mec.s +++ b/llvm/test/MC/AArch64/armv9.2a-mec.s @@ -1,55 +1,117 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mec < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=CHECK-NO-MEC %s - - mrs x0, MECIDR_EL2 -// CHECK: mrs x0, MECIDR_EL2 // encoding: [0xe0,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_P0_EL2 -// CHECK: mrs x0, MECID_P0_EL2 // encoding: [0x00,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_A0_EL2 -// CHECK: mrs x0, MECID_A0_EL2 // encoding: [0x20,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_P1_EL2 -// CHECK: mrs x0, MECID_P1_EL2 // encoding: [0x40,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_A1_EL2 -// CHECK: mrs x0, MECID_A1_EL2 // encoding: [0x60,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, VMECID_P_EL2 -// CHECK: mrs x0, VMECID_P_EL2 // encoding: [0x00,0xa9,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, VMECID_A_EL2 -// CHECK: mrs x0, VMECID_A_EL2 // encoding: [0x20,0xa9,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_RL_A_EL3 -// CHECK: mrs x0, MECID_RL_A_EL3 // encoding: [0x20,0xaa,0x3e,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - msr MECID_P0_EL2,x0 -// CHECK: msr MECID_P0_EL2, x0 // encoding: [0x00,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_A0_EL2,x0 -// CHECK: msr MECID_A0_EL2, x0 // encoding: [0x20,0xa8,0x1
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) (PR #146329)
https://github.com/jthackray edited https://github.com/llvm/llvm-project/pull/146329 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (4/4) (NFC) (PR #146331)
https://github.com/jthackray edited https://github.com/llvm/llvm-project/pull/146331 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (3/4) (NFC) (PR #146330)
https://github.com/jthackray edited https://github.com/llvm/llvm-project/pull/146330 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (4/4) (NFC) (PR #146331)
@@ -1,408 +1,825 @@ -// RUN: llvm-mc -triple aarch64 -mattr=+lsui -show-encoding %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lsui < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lsui < %s \ +// RUN:| llvm-objdump -d --mattr=+lsui --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lsui < %s \ +// RUN:| llvm-objdump -d --mattr=-lsui --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lsui < %s \ +// RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN:| llvm-mc -triple=aarch64 -mattr=+lsui -disassemble -show-encoding \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + -_func: -// CHECK: _func: //-- // Unprivileged load/store operations //-- - ldtxr x9, [sp] -// CHECK: ldtxrx9, [sp]// encoding: [0xe9,0x7f,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldtxr x9, [sp, #0] -// CHECK: ldtxrx9, [sp]// encoding: [0xe9,0x7f,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldtxr x10, [x11] -// CHECK: ldtxrx10, [x11] // encoding: [0x6a,0x7d,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldtxr x10, [x11, #0] -// CHECK: ldtxrx10, [x11] // encoding: [0x6a,0x7d,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - - ldatxr x9, [sp] -// CHECK: ldatxr x9, [sp]// encoding: [0xe9,0xff,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldatxr x10, [x11] -// CHECK: ldatxr x10, [x11] // encoding: [0x6a,0xfd,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - - sttxr wzr, w4, [sp] -// CHECK: sttxrwzr, w4, [sp] // encoding: [0xe4,0x7f,0x1f,0x89] -// ERROR: error: instruction requires: lsui - sttxr wzr, w4, [sp, #0] -// CHECK: sttxrwzr, w4, [sp] // encoding: [0xe4,0x7f,0x1f,0x89] -// ERROR: error: instruction requires: lsui - sttxr w5, x6, [x7] -// CHECK: sttxrw5, x6, [x7]// encoding: [0xe6,0x7c,0x05,0xc9] -// ERROR: error: instruction requires: lsui - sttxr w5, x6, [x7, #0] -// CHECK: sttxrw5, x6, [x7]// encoding: [0xe6,0x7c,0x05,0xc9] -// ERROR: error: instruction requires: lsui - - stltxr w2, w4, [sp] -// CHECK: stltxr w2, w4, [sp]// encoding: [0xe4,0xff,0x02,0x89] -// ERROR: error: instruction requires: lsui - stltxr w5, x6, [x7] -// CHECK: stltxr w5, x6, [x7]// encoding: [0xe6,0xfc,0x05,0xc9] -// ERROR: error: instruction requires: lsui +ldtxr x9, [sp] +// CHECK-INST: ldtxr x9, [sp] +// CHECK-ENCODING: encoding: [0xe9,0x7f,0x5f,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c95f7fe9 +// ERROR: :[[@LINE-3]]:3: error: instruction requires: lsui + +ldtxr x9, [sp, #0] +// CHECK-INST: ldtxr x9, [sp] +// CHECK-ENCODING: encoding: [0xe9,0x7f,0x5f,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c95f7fe9 +// ERROR: :[[@LINE-3]]:3: error: instruction requires: lsui + +ldtxr x10, [x11] +// CHECK-INST: ldtxr x10, [x11] +// CHECK-ENCODING: encoding: [0x6a,0x7d,0x5f,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c95f7d6a +// ERROR: :[[@LINE-3]]:3: error: instruction requires: lsui + +ldtxr x10, [x11, #0] +// CHECK-INST: ldtxr x10, [x11] +// CHECK-ENCODING: encoding: [0x6a,0x7d,0x5f,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c95f7d6a +// ERROR: :[[@LINE-3]]:3: error: instruction requires: lsui + +ldatxr x9, [sp] +// CHECK-INST: ldatxr x9, [sp] +// CHECK-ENCODING: encoding: [0xe9,0xff,0x5f,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c95fffe9 +// ERROR: :[[@LINE-3]]:3: error: instruction requires: lsui + +ldatxr x10, [x11] +// CHECK-INST: ldatxr x10, [x11] +// CHECK-ENCODING: encoding: [0x6a,0xfd,0x5f,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c95ffd6a +// ERROR: :[[@LINE-3]]:3: error: instruction requires: lsui + +sttxr wzr, w4, [sp] +// CHECK-INST: sttxr wzr, w4, [sp] +// CHECK-ENCODING: encoding:
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (4/4) (NFC) (PR #146331)
@@ -1,408 +1,825 @@ -// RUN: llvm-mc -triple aarch64 -mattr=+lsui -show-encoding %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lsui < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lsui < %s \ +// RUN:| llvm-objdump -d --mattr=+lsui --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lsui < %s \ +// RUN:| llvm-objdump -d --mattr=-lsui --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lsui < %s \ +// RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN:| llvm-mc -triple=aarch64 -mattr=+lsui -disassemble -show-encoding \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + -_func: -// CHECK: _func: //-- // Unprivileged load/store operations //-- - ldtxr x9, [sp] -// CHECK: ldtxrx9, [sp]// encoding: [0xe9,0x7f,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldtxr x9, [sp, #0] -// CHECK: ldtxrx9, [sp]// encoding: [0xe9,0x7f,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldtxr x10, [x11] -// CHECK: ldtxrx10, [x11] // encoding: [0x6a,0x7d,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldtxr x10, [x11, #0] -// CHECK: ldtxrx10, [x11] // encoding: [0x6a,0x7d,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - - ldatxr x9, [sp] -// CHECK: ldatxr x9, [sp]// encoding: [0xe9,0xff,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldatxr x10, [x11] -// CHECK: ldatxr x10, [x11] // encoding: [0x6a,0xfd,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - - sttxr wzr, w4, [sp] -// CHECK: sttxrwzr, w4, [sp] // encoding: [0xe4,0x7f,0x1f,0x89] -// ERROR: error: instruction requires: lsui - sttxr wzr, w4, [sp, #0] -// CHECK: sttxrwzr, w4, [sp] // encoding: [0xe4,0x7f,0x1f,0x89] -// ERROR: error: instruction requires: lsui - sttxr w5, x6, [x7] -// CHECK: sttxrw5, x6, [x7]// encoding: [0xe6,0x7c,0x05,0xc9] -// ERROR: error: instruction requires: lsui - sttxr w5, x6, [x7, #0] -// CHECK: sttxrw5, x6, [x7]// encoding: [0xe6,0x7c,0x05,0xc9] -// ERROR: error: instruction requires: lsui - - stltxr w2, w4, [sp] -// CHECK: stltxr w2, w4, [sp]// encoding: [0xe4,0xff,0x02,0x89] -// ERROR: error: instruction requires: lsui - stltxr w5, x6, [x7] -// CHECK: stltxr w5, x6, [x7]// encoding: [0xe6,0xfc,0x05,0xc9] -// ERROR: error: instruction requires: lsui +ldtxr x9, [sp] +// CHECK-INST: ldtxr x9, [sp] +// CHECK-ENCODING: encoding: [0xe9,0x7f,0x5f,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c95f7fe9 +// ERROR: :[[@LINE-3]]:3: error: instruction requires: lsui jthackray wrote: Thanks, done. https://github.com/llvm/llvm-project/pull/146331 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (4/4) (NFC) (PR #146331)
@@ -1,17 +1,42 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+occmo -mattr=+mte %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding %s -mattr=+mte 2>&1 | FileCheck --check-prefix=ERROR %s -.func: -// CHECK: .func: - dc civaoc, x12 -// CHECK: dc civaoc, x12 // encoding: [0x0c,0x7f,0x0b,0xd5] -// ERROR: error: DC CIVAOC requires: occmo - dc cigdvaoc, x0 -// CHECK: dc cigdvaoc, x0// encoding: [0xe0,0x7f,0x0b,0xd5] -// ERROR: error: DC CIGDVAOC requires: mte, memtag, occmo - dc cvaoc, x13 -// CHECK: dc cvaoc, x13 // encoding: [0x0d,0x7b,0x0b,0xd5] -// ERROR: error: DC CVAOC requires: occmo - dc cgdvaoc, x1 -// CHECK: dc cgdvaoc, x1 // encoding: [0xe1,0x7b,0x0b,0xd5] -// ERROR: error: DC CGDVAOC requires: mte, memtag, occmo +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+occmo,+mte,+memtag < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+occmo,+mte,+memtag < %s \ +// RUN:| llvm-objdump -d --mattr=+occmo,+mte,+memtag --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+occmo,+mte,+memtag < %s \ +// RUN:| llvm-objdump -d --mattr=-occmo,-mte,-memtag --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+occmo,+mte,+memtag < %s \ +// RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN:| llvm-mc -triple=aarch64 -mattr=+occmo,+mte,+memtag -disassemble -show-encoding \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +dc civaoc, x12 +// CHECK-INST: dc civaoc, x12 +// CHECK-ENCODING: encoding: [0x0c,0x7f,0x0b,0xd5] +// CHECK-ERROR: error: DC CIVAOC requires: occmo +// CHECK-UNKNOWN: d50b7f0c sys #3, c7, c15, #0, x12 + +dc cigdvaoc, x0 +// CHECK-INST: dc cigdvaoc, x0 +// CHECK-ENCODING: encoding: [0xe0,0x7f,0x0b,0xd5] +// CHECK-ERROR: error: DC CIGDVAOC requires: mte, memtag, occmo +// CHECK-UNKNOWN: d50b7fe0 sys #3, c7, c15, #7, x0 +// ERROR: :[[@LINE-3]]:4: error: DC CIGDVAOC requires: mte, memtag, occmo jthackray wrote: Thanks, done. https://github.com/llvm/llvm-project/pull/146331 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (4/4) (NFC) (PR #146331)
@@ -1,19 +1,47 @@ -# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -// RUN: llvm-mc -triple aarch64 -show-encoding %s | FileCheck %s -.func: +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \ +// RUN:| llvm-objdump -d --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST jthackray wrote: I couldn't quite get this to work for both using `llvm-lit`, since one is checking a substring of the other, and the matching gets confused, but we don't need `CHECK-INST` since we're checking this within `CHECK-UNKNOWN`, and there is no instruction gating for the `apas` instruction. https://github.com/llvm/llvm-project/pull/146331 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Unify AArch64 tests into a single file (2/4) (NFC) (PR #146329)
https://github.com/jthackray reopened https://github.com/llvm/llvm-project/pull/146329 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
