[llvm-commits] CVS: llvm/tools/gccld/gccld.cpp
Changes in directory llvm/tools/gccld: gccld.cpp updated: 1.103 - 1.104 --- Log message: Allow users to specify -Wl,-native* multiple times if they please --- Diffs of the changes: (+2 -2) gccld.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/tools/gccld/gccld.cpp diff -u llvm/tools/gccld/gccld.cpp:1.103 llvm/tools/gccld/gccld.cpp:1.104 --- llvm/tools/gccld/gccld.cpp:1.103Tue Aug 2 17:07:38 2005 +++ llvm/tools/gccld/gccld.cpp Thu Nov 17 10:08:04 2005 @@ -78,10 +78,10 @@ cl::aliasopt(LinkAsLibrary)); cl::optbool - Native(native, + Native(native, cl::ZeroOrMore, cl::desc(Generate a native binary instead of a shell script)); cl::optbool - NativeCBE(native-cbe, + NativeCBE(native-cbe, cl::ZeroOrMore, cl::desc(Generate a native binary with the C backend and GCC)); cl::optbool ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.128 - 1.129
---
Log message:
Teach the selector to fold lo(g) into load instruction immediate fields
---
Diffs of the changes: (+8 -0)
PPCISelDAGToDAG.cpp |8
1 files changed, 8 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.128
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.129
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.128 Thu Nov 17 01:30:41 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Nov 17 12:02:16 2005
@@ -413,6 +413,14 @@
Op2 = Select(Addr.getOperand(0));
}
return false;
+} else if (Addr.getOperand(1).getOpcode() == PPCISD::Lo) {
+ // Match LOAD (ADD (X, Lo(G))).
+
assert(!castConstantSDNode(Addr.getOperand(1).getOperand(1))-getValue()
+ Cannot handle constant offsets yet!);
+ Op1 = Addr.getOperand(1).getOperand(0); // The global address.
+ assert(Op1.getOpcode() == ISD::TargetGlobalAddress);
+ Op2 = Select(Addr.getOperand(0));
+ return false; // [g+r]
} else {
Op1 = Select(Addr.getOperand(0));
Op2 = Select(Addr.getOperand(1));
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.43 - 1.44
---
Log message:
Fix a bug that resistor on IRC hit where we tried to create token factor
nodes of load results, not of their chain results.
---
Diffs of the changes: (+2 -2)
PPCISelLowering.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.43
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.44
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.43Thu Nov 17 12:26:56 2005
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Nov 17 12:30:17 2005
@@ -670,7 +670,7 @@
if (GPR_remaining 0) {
SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
DAG.getSrcValue(NULL));
- MemOps.push_back(Load);
+ MemOps.push_back(Load.getValue(1));
args_to_use.push_back(Load);
--GPR_remaining;
}
@@ -679,7 +679,7 @@
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
DAG.getSrcValue(NULL));
- MemOps.push_back(Load);
+ MemOps.push_back(Load.getValue(1));
args_to_use.push_back(Load);
--GPR_remaining;
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
Changes in directory llvm/lib/Transforms/Scalar:
IndVarSimplify.cpp updated: 1.80 - 1.81
---
Log message:
This was checking the wrong GEP expression. Fixing this fixes a gccas crash
compiling mysql reported by Ted Kremenek.
---
Diffs of the changes: (+1 -1)
IndVarSimplify.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
diff -u llvm/lib/Transforms/Scalar/IndVarSimplify.cpp:1.80
llvm/lib/Transforms/Scalar/IndVarSimplify.cpp:1.81
--- llvm/lib/Transforms/Scalar/IndVarSimplify.cpp:1.80 Tue Aug 9 20:12:06 2005
+++ llvm/lib/Transforms/Scalar/IndVarSimplify.cpp Thu Nov 17 13:35:42 2005
@@ -162,7 +162,7 @@
if (CE-getOperand(NumOps-1)-isNullValue()) {
// Check to make sure the last index really is an array index.
gep_type_iterator GTI = gep_type_begin(GEPI);
-for (unsigned i = 1, e = GEPI-getNumOperands()-1;
+for (unsigned i = 1, e = CE-getNumOperands()-1;
i != e; ++i, ++GTI)
/*empty*/;
if (isaSequentialType(*GTI)) {
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.27 - 1.28 --- Log message: Teach the type lowering code about turning packed types into vector types. Next step: generating vector dag nodes, and legalizing them into scalar code. --- Diffs of the changes: (+1 -0) TargetLowering.h |1 + 1 files changed, 1 insertion(+) Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.27 llvm/include/llvm/Target/TargetLowering.h:1.28 --- llvm/include/llvm/Target/TargetLowering.h:1.27 Thu Oct 20 19:02:42 2005 +++ llvm/include/llvm/Target/TargetLowering.h Thu Nov 17 15:44:42 2005 @@ -189,6 +189,7 @@ case Type::FloatTyID: return MVT::f32; case Type::DoubleTyID: return MVT::f64; case Type::PointerTyID: return PointerTy; +case Type::PackedTyID: return MVT::Vector; } } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/pubs/2005-11-SAFECodeTR.html 2005-11-SAFECodeTR.pdf 2003-04-29-DataStructureAnalysisTR.html
Changes in directory llvm-www/pubs: 2005-11-SAFECodeTR.html added (r1.1) 2005-11-SAFECodeTR.pdf added (r1.1) 2003-04-29-DataStructureAnalysisTR.html updated: 1.7 - 1.8 --- Log message: Added safecode tech report --- Diffs of the changes: (+73 -9) 2003-04-29-DataStructureAnalysisTR.html | 12 + 2005-11-SAFECodeTR.html | 70 2005-11-SAFECodeTR.pdf |0 3 files changed, 73 insertions(+), 9 deletions(-) Index: llvm-www/pubs/2005-11-SAFECodeTR.html diff -c /dev/null llvm-www/pubs/2005-11-SAFECodeTR.html:1.1 *** /dev/null Thu Nov 17 15:46:40 2005 --- llvm-www/pubs/2005-11-SAFECodeTR.html Thu Nov 17 15:46:30 2005 *** *** 0 --- 1,70 + !DOCTYPE HTML PUBLIC -//W3C//DTD HTML 4.01 Transitional//EN + html + head + meta http-equiv=Content-Type content=text/html; charset=UTF-8 / + link rel=stylesheet href=../llvm.css type=text/css media=screen / + titleEnforcing Alias Analysis for Weakly Typed Languages/title + /head + body + + div class=pub_title + Enforcing Alias Analysis for Weakly Typed Languages + /div + div class=pub_author + Dinakar Dhurjati, Sumant Kowshik, and Vikram Adve + /div + + + h2Abstract:/h2 + blockquote + + p + Static analysis of programs in weakly typed languages such as C and C++ is + generally not sound because of possible memory errors due to dangling + pointer references, uninitialized pointers, and array bounds overflow. + Optimizing compilers can produce unpredictable results when such errors + occur, but this is quite undesirable for many tools that aim to analyze + security and reliability properties with guarantees of soundness. We + describe a relatively simple compilation strategy for standard C programs + that guarantees sound semantics for an aggressive interprocedural pointer + analysis (or simpler ones), a call graph, and type information for a + subset of memory. These provide the foundation for sophisticated static + analyses to be applied to such programs with a guarantee of soundness. Our + work builds on a previously published transformation called Automatic Pool + Allocation to ensure that hard-to-detect memory errors (dangling pointer + references and certain array bounds errors) cannot invalidate the call + graph, points-to information or type information. The key insights behind + our approach is that pool allocation can be used to create a run-time + partitioning of memory that matches the compile-time memory partitioning + in a points-to graph, and efficient checks can be used to isolate the + run-time partitions. Furthermore, we show that the sound analysis + information enables static checking techniques that reliably eliminate + many run-time checks. We formalize our approach as a new type system with + the necessary run-time checks in operational semantics and prove the + correctness of our approach for a subset of C. Our approach requires no + source code changes, allows memory to be managed explicitly, and does not + use meta-data on pointers or individual tag bits for memory. Using several + benchmarks and system codes, we show experimentally that the run-time + overheads are low (less than 10% in nearly all cases and 30% in the worst + case we have seen). We also show the effectiveness of reliable static + analyses for eliminating run-time checks. + + /p + /blockquote + + h2Published:/h2 + blockquote + Enforcing Alias Analysis for Weakly Typed Languagesbr + By Dinakar Dhurjati, Sumant Kowshik, and Vikram Adve.br + Technical Report #UIUCDCS-R-2005-2657, Computer Science Dept., Univ. of + Illinois, Nov. 2005 + /blockquote + + h2Download:/h2 + ul + lia href=2005-11-SAFECodeTR.pdfEnforcing Alias Analysis for + Weakly Typed Languages/a (PDF)/li + /ul + + /body + /html Index: llvm-www/pubs/2005-11-SAFECodeTR.pdf Index: llvm-www/pubs/2003-04-29-DataStructureAnalysisTR.html diff -u llvm-www/pubs/2003-04-29-DataStructureAnalysisTR.html:1.7 llvm-www/pubs/2003-04-29-DataStructureAnalysisTR.html:1.8 --- llvm-www/pubs/2003-04-29-DataStructureAnalysisTR.html:1.7 Sat Apr 17 15:13:02 2004 +++ llvm-www/pubs/2003-04-29-DataStructureAnalysisTR.html Thu Nov 17 15:46:30 2005 @@ -35,19 +35,13 @@ blockquote Data Structure Analysis: An Efficient Context-Sensitive Heap Analysis, Chris Lattner amp; Vikram Advebr - Technical Report #UIUCDCS-R-2003-2340, Computer Science Dept., Univ. of - Illinois, Apr. 2003. -/blockquote - -h2Update:/h2 -blockquote - This document was updated on 15 November 2003 to reflect improvements to the - algorithm, and to be more clear and precise. + Technical Report #UIUCDCS-R-2005-2657, Computer Science Dept., Univ. of + Illinois, Nov. 2005. /blockquote h2Download:/h2 ul - lia href=2003-11-15-DataStructureAnalysisTR.psData Structure Analysis: + lia href=2005-11-DataStructureAnalysisTR.psData Structure Analysis: An Efficient Context-Sensitive Heap Analysis/a (PS)/li lia
[llvm-commits] CVS: llvm-www/safecode/index.html
Changes in directory llvm-www/safecode: index.html updated: 1.11 - 1.12 --- Log message: *** empty log message *** --- Diffs of the changes: (+1 -0) index.html |1 + 1 files changed, 1 insertion(+) Index: llvm-www/safecode/index.html diff -u llvm-www/safecode/index.html:1.11 llvm-www/safecode/index.html:1.12 --- llvm-www/safecode/index.html:1.11 Thu Nov 17 15:50:58 2005 +++ llvm-www/safecode/index.htmlThu Nov 17 15:53:31 2005 @@ -39,6 +39,7 @@ H3 Publications/H3 ul + h2 Tech Report of PLDI submission/h2 li a href=http://llvm.cs.uiuc.edu/pubs/2005-11-SAFECodeTR.html;/a Enforcing Alias Analysis for Weakly Typed Languages /a br Dinakar dhurjati, Sumant Kowshik, and Vikram Adve. UIUC TechReport/li ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/safecode/index.html
Changes in directory llvm-www/safecode: index.html updated: 1.12 - 1.13 --- Log message: *** empty log message *** --- Diffs of the changes: (+2 -2) index.html |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm-www/safecode/index.html diff -u llvm-www/safecode/index.html:1.12 llvm-www/safecode/index.html:1.13 --- llvm-www/safecode/index.html:1.12 Thu Nov 17 15:53:31 2005 +++ llvm-www/safecode/index.htmlThu Nov 17 15:55:49 2005 @@ -39,8 +39,8 @@ H3 Publications/H3 ul - h2 Tech Report of PLDI submission/h2 - li a href=http://llvm.cs.uiuc.edu/pubs/2005-11-SAFECodeTR.html;/a Enforcing Alias Analysis for Weakly Typed Languages /a + li h4 Tech Report of PLDI submission/h4 br +a href=http://llvm.cs.uiuc.edu/pubs/2005-11-SAFECodeTR.html;/a Enforcing Alias Analysis for Weakly Typed Languages /a br Dinakar dhurjati, Sumant Kowshik, and Vikram Adve. UIUC TechReport/li lia href=http://llvm.cs.uiuc.edu/pubs/2005-02-TECHREPORT-SAFECode.html;Memory Safety Without ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/safecode/index.html
Changes in directory llvm-www/safecode: index.html updated: 1.14 - 1.15 --- Log message: *** empty log message *** --- Diffs of the changes: (+1 -2) index.html |3 +-- 1 files changed, 1 insertion(+), 2 deletions(-) Index: llvm-www/safecode/index.html diff -u llvm-www/safecode/index.html:1.14 llvm-www/safecode/index.html:1.15 --- llvm-www/safecode/index.html:1.14 Thu Nov 17 15:56:06 2005 +++ llvm-www/safecode/index.htmlThu Nov 17 15:56:52 2005 @@ -39,8 +39,7 @@ H3 Publications/H3 ul - li h4 Tech Report of PLDI submission/h4 -a href=http://llvm.cs.uiuc.edu/pubs/2005-11-SAFECodeTR.html;/a Enforcing Alias Analysis for Weakly Typed Languages /a + li h4 Tech Report of PLDI submission/h4 a href=http://llvm.cs.uiuc.edu/pubs/2005-11-SAFECodeTR.html; Enforcing Alias Analysis for Weakly Typed Languages /a br Dinakar dhurjati, Sumant Kowshik, and Vikram Adve. UIUC TechReport/li lia href=http://llvm.cs.uiuc.edu/pubs/2005-02-TECHREPORT-SAFECode.html;Memory Safety Without ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/safecode/index.html
Changes in directory llvm-www/safecode: index.html updated: 1.16 - 1.17 --- Log message: *** empty log message *** --- Diffs of the changes: (+6 -1) index.html |7 ++- 1 files changed, 6 insertions(+), 1 deletion(-) Index: llvm-www/safecode/index.html diff -u llvm-www/safecode/index.html:1.16 llvm-www/safecode/index.html:1.17 --- llvm-www/safecode/index.html:1.16 Thu Nov 17 15:58:35 2005 +++ llvm-www/safecode/index.htmlThu Nov 17 16:00:25 2005 @@ -20,6 +20,11 @@ enforcement of safety, using aggressive compiler techniques developed in this project./p + +H2a href=http://llvm.cs.uiuc.edu/pubs/2005-11-SAFECodeTR.html; +Enforcing Alias Analysis for Weakly Typed Languages : Technical Report +of PLDI Submission/a/H2 + H3Project Members/H3 H4Faculty/H4 @@ -39,7 +44,7 @@ H3 Publications/H3 ul - li h4 Tech Report of PLDI submission/h4 a href=http://llvm.cs.uiuc.edu/pubs/2005-11-SAFECodeTR.html; Enforcing Alias Analysis for Weakly Typed Languages /a + li a href=http://llvm.cs.uiuc.edu/pubs/2005-11-SAFECodeTR.html; Enforcing Alias Analysis for Weakly Typed Languages /a br Dinakar dhurjati, Sumant Kowshik, and Vikram Adve. Technical Report #UIUCDCS-R-2005-2657, Computer Science Dept., University of ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/safecode/index.html
Changes in directory llvm-www/safecode: index.html updated: 1.17 - 1.18 --- Log message: *** empty log message *** --- Diffs of the changes: (+2 -2) index.html |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm-www/safecode/index.html diff -u llvm-www/safecode/index.html:1.17 llvm-www/safecode/index.html:1.18 --- llvm-www/safecode/index.html:1.17 Thu Nov 17 16:00:25 2005 +++ llvm-www/safecode/index.htmlThu Nov 17 16:01:51 2005 @@ -21,9 +21,9 @@ project./p -H2a href=http://llvm.cs.uiuc.edu/pubs/2005-11-SAFECodeTR.html; +H2a href=http://llvm.cs.uiuc.edu/pubs/2005-11-SAFECodeTR.html; Enforcing Alias Analysis for Weakly Typed Languages : Technical Report -of PLDI Submission/a/H2 +of PLDI Submission/a/H2 H3Project Members/H3 ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/safecode/index.html
Changes in directory llvm-www/safecode: index.html updated: 1.18 - 1.19 --- Log message: *** empty log message *** --- Diffs of the changes: (+2 -2) index.html |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm-www/safecode/index.html diff -u llvm-www/safecode/index.html:1.18 llvm-www/safecode/index.html:1.19 --- llvm-www/safecode/index.html:1.18 Thu Nov 17 16:01:51 2005 +++ llvm-www/safecode/index.htmlThu Nov 17 16:06:11 2005 @@ -66,9 +66,9 @@ Sumant Kowshik, Dinakar Dhurjati, Vikram Adve. CASES 2002./li /ul -H3Implementation/H3 +!H3Implementation/H3 -pimg src=impl.jpg alt=Implementation picture/p +!pimg src=impl.jpg alt=Implementation picture/p H3Download/H3 ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/safecode/index.html
Changes in directory llvm-www/safecode: index.html updated: 1.19 - 1.20 --- Log message: *** empty log message *** --- Diffs of the changes: (+0 -4) index.html |4 1 files changed, 4 deletions(-) Index: llvm-www/safecode/index.html diff -u llvm-www/safecode/index.html:1.19 llvm-www/safecode/index.html:1.20 --- llvm-www/safecode/index.html:1.19 Thu Nov 17 16:06:11 2005 +++ llvm-www/safecode/index.htmlThu Nov 17 16:06:55 2005 @@ -66,10 +66,6 @@ Sumant Kowshik, Dinakar Dhurjati, Vikram Adve. CASES 2002./li /ul -!H3Implementation/H3 - -!pimg src=impl.jpg alt=Implementation picture/p - H3Download/H3 pNot in public domain for now. Check this page later./p ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/safecode/index.html
Changes in directory llvm-www/safecode: index.html updated: 1.21 - 1.22 --- Log message: *** empty log message *** --- Diffs of the changes: (+3 -2) index.html |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) Index: llvm-www/safecode/index.html diff -u llvm-www/safecode/index.html:1.21 llvm-www/safecode/index.html:1.22 --- llvm-www/safecode/index.html:1.21 Thu Nov 17 16:07:29 2005 +++ llvm-www/safecode/index.htmlThu Nov 17 16:09:16 2005 @@ -22,8 +22,9 @@ H2a href=http://llvm.cs.uiuc.edu/pubs/2005-11-SAFECodeTR.html; -Enforcing Alias Analysis for Weakly Typed Languages : Technical Report -of PLDI Submission/a/H2 +Accompanying Technical Report +of our PLDI Submission/a/H2 Enforcing Alias Analysis for Weakly Typed Languages. + H3Project Members/H3 ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/safecode/index.html
Changes in directory llvm-www/safecode: index.html updated: 1.22 - 1.23 --- Log message: *** empty log message *** --- Diffs of the changes: (+3 -3) index.html |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm-www/safecode/index.html diff -u llvm-www/safecode/index.html:1.22 llvm-www/safecode/index.html:1.23 --- llvm-www/safecode/index.html:1.22 Thu Nov 17 16:09:16 2005 +++ llvm-www/safecode/index.htmlThu Nov 17 16:10:14 2005 @@ -21,10 +21,10 @@ project./p -H2a href=http://llvm.cs.uiuc.edu/pubs/2005-11-SAFECodeTR.html; +H3a href=http://llvm.cs.uiuc.edu/pubs/2005-11-SAFECodeTR.html; Accompanying Technical Report -of our PLDI Submission/a/H2 Enforcing Alias Analysis for Weakly Typed Languages. - +of our PLDI Submission/a: Enforcing Alias Analysis for Weakly Typed Languages. +/H3 H3Project Members/H3 ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/pubs/2005-11-SAFECodeTR.pdf
Changes in directory llvm-www/pubs: 2005-11-SAFECodeTR.pdf updated: 1.2 - 1.3 --- Log message: Fixed some inconsistencies in safecode tech report --- Diffs of the changes: (+0 -0) 2005-11-SAFECodeTR.pdf |0 1 files changed Index: llvm-www/pubs/2005-11-SAFECodeTR.pdf ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/pubs/2005-11-SAFECodeTR.pdf
Changes in directory llvm-www/pubs: 2005-11-SAFECodeTR.pdf updated: 1.3 - 1.4 --- Log message: --- Diffs of the changes: (+0 -0) 2005-11-SAFECodeTR.pdf |0 1 files changed Index: llvm-www/pubs/2005-11-SAFECodeTR.pdf ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/pubs/index.html
Changes in directory llvm-www/pubs: index.html updated: 1.32 - 1.33 --- Log message: *** empty log message *** --- Diffs of the changes: (+5 -1) index.html |6 +- 1 files changed, 5 insertions(+), 1 deletion(-) Index: llvm-www/pubs/index.html diff -u llvm-www/pubs/index.html:1.32 llvm-www/pubs/index.html:1.33 --- llvm-www/pubs/index.html:1.32 Mon Oct 24 10:16:23 2005 +++ llvm-www/pubs/index.htmlThu Nov 17 18:42:34 2005 @@ -33,7 +33,11 @@ div class=www_sectiontitlePublications using LLVM/div ol - +lia href=2005-11-SAFECodeTR.htmlEnforcing Alias Analysis for +Weakly Typed Languages/abr Dinakar Dhurjati, Sumant Kowshik, and Vikram +Advebr iTechnical Report #UIUCDCS-R-2005-2657, Computer Science Dept., Univ. of +Illinois/i, Nov. 2005.br /li + lia href=2005-10-20-LCPC-RegAlloc.htmlRevisiting Graph Coloring Register Allocation: A Study of the Chaitin-Briggs and Callahan-Koblenz Algorithms/abr ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Target.td
Changes in directory llvm/lib/Target: Target.td updated: 1.56 - 1.57 --- Log message: Also add the new vector value type here, for completeness. --- Diffs of the changes: (+1 -0) Target.td |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/Target.td diff -u llvm/lib/Target/Target.td:1.56 llvm/lib/Target/Target.td:1.57 --- llvm/lib/Target/Target.td:1.56 Wed Oct 26 12:28:23 2005 +++ llvm/lib/Target/Target.td Thu Nov 17 18:53:32 2005 @@ -38,6 +38,7 @@ def f128 : ValueType128, 10; // 128-bit floating point value def FlagVT : ValueType0 , 11; // Condition code or machine flag def isVoid : ValueType0 , 12; // Produces no value +def Vector : ValueType0 , 13; // Abstract vector type //===--===// // Register file description - These classes are used to fill in the target ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.137 - 1.138
---
Log message:
add more patterns, patch by Evan Cheng.
---
Diffs of the changes: (+156 -108)
X86InstrInfo.td | 264 +---
1 files changed, 156 insertions(+), 108 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.137
llvm/lib/Target/X86/X86InstrInfo.td:1.138
--- llvm/lib/Target/X86/X86InstrInfo.td:1.137 Wed Nov 16 20:01:55 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td Thu Nov 17 19:04:42 2005
@@ -32,6 +32,12 @@
def f64mem : X86MemOperandf64;
def f80mem : X86MemOperandf80;
+// A couple of more descriptive operand definitions.
+// 16-bits but only 8 bits are significant.
+def i16i8imm : Operandi16;
+// 32-bits but only 8 bits are significant.
+def i32i8imm : Operandi32;
+
// PCRelative calls need special operand formatting.
let PrintMethod = printCallOperand in
def calltarget : Operandi32;
@@ -127,12 +133,23 @@
//===--===//
+// Pattern fragments...
+//
+def immSExt8 : PatLeaf(imm), [{
+ // immSExt8 predicate - True if the immediate fits in a 8-bit sign extended
+ // field.
+ return (int)N-getValue() == (signed char)N-getValue();
+}];
+
+//===--===//
// Instruction templates...
class Ibits8 o, Format f, dag ops, string asm
: X86Insto, f, NoImm, ops, asm;
-class Ii8 bits8 o, Format f, dag ops, string asm
- : X86Insto, f, Imm8 , ops, asm;
+class Ii8 bits8 o, Format f, dag ops, string asm, listdag pattern
+ : X86Insto, f, Imm8 , ops, asm {
+ let Pattern = pattern;
+}
class Ii16bits8 o, Format f, dag ops, string asm, listdag pattern
: X86Insto, f, Imm16, ops, asm {
let Pattern = pattern;
@@ -324,14 +341,16 @@
def MOV32rr : I0x89, MRMDestReg, (ops R32:$dst, R32:$src),
mov{l} {$src, $dst|$dst, $src};
def MOV8ri : Ii8 0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src),
- mov{b} {$src, $dst|$dst, $src};
+ mov{b} {$src, $dst|$dst, $src},
+ [(set R8:$dst, imm:$src)];
def MOV16ri : Ii160xB8, AddRegFrm, (ops R16:$dst, i16imm:$src),
- mov{w} {$src, $dst|$dst, $src}, [(set R16:$dst,
imm:$src)],
- OpSize;
+ mov{w} {$src, $dst|$dst, $src},
+ [(set R16:$dst, imm:$src)], OpSize;
def MOV32ri : Ii320xB8, AddRegFrm, (ops R32:$dst, i32imm:$src),
- mov{l} {$src, $dst|$dst, $src}, [(set R32:$dst,
imm:$src)];
+ mov{l} {$src, $dst|$dst, $src},
+ [(set R32:$dst, imm:$src)];
def MOV8mi : Ii8 0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
- mov{b} {$src, $dst|$dst, $src};
+ mov{b} {$src, $dst|$dst, $src}, [];
def MOV16mi : Ii160xC7, MRM0m, (ops i16mem:$dst, i16imm:$src),
mov{w} {$src, $dst|$dst, $src}, [], OpSize;
def MOV32mi : Ii320xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
@@ -676,7 +695,8 @@
def AND8ri : Ii80x80, MRM4r,
(ops R8 :$dst, R8 :$src1, i8imm :$src2),
- and{b} {$src2, $dst|$dst, $src2};
+ and{b} {$src2, $dst|$dst, $src2},
+ [(set R8:$dst, (and R8:$src1, imm:$src2))];
def AND16ri : Ii160x81, MRM4r,
(ops R16:$dst, R16:$src1, i16imm:$src2),
and{w} {$src2, $dst|$dst, $src2},
@@ -686,11 +706,13 @@
and{l} {$src2, $dst|$dst, $src2},
[(set R32:$dst, (and R32:$src1, imm:$src2))];
def AND16ri8 : Ii80x83, MRM4r,
- (ops R16:$dst, R16:$src1, i8imm:$src2),
- and{w} {$src2, $dst|$dst, $src2} , OpSize;
+ (ops R16:$dst, R16:$src1, i16i8imm:$src2),
+ and{w} {$src2, $dst|$dst, $src2},
+ [(set R16:$dst, (and R16:$src1, immSExt8:$src2))], OpSize;
def AND32ri8 : Ii80x83, MRM4r,
- (ops R32:$dst, R32:$src1, i8imm:$src2),
- and{l} {$src2, $dst|$dst, $src2};
+ (ops R32:$dst, R32:$src1, i32i8imm:$src2),
+ and{l} {$src2, $dst|$dst, $src2},
+ [(set R32:$dst, (and R32:$src1, immSExt8:$src2))];
let isTwoAddress = 0 in {
def AND8mr : I0x20, MRMDestMem,
@@ -704,7 +726,7 @@
and{l} {$src, $dst|$dst, $src};
def AND8mi : Ii80x80, MRM4m,
(ops i8mem :$dst, i8imm :$src),
- and{b} {$src, $dst|$dst, $src};
+ and{b} {$src, $dst|$dst, $src}, [];
def AND16mi : Ii160x81, MRM4m,
(ops i16mem:$dst, i16imm:$src),
and{w} {$src, $dst|$dst, $src}, [], OpSize;
@@ -713,10 +735,10 @@
and{l} {$src, $dst|$dst, $src}, [];
def AND16mi8 : Ii80x83, MRM4m,
[llvm-commits] CVS: llvm/lib/VMCore/Dominators.cpp
Changes in directory llvm/lib/VMCore:
Dominators.cpp updated: 1.63 - 1.64
---
Log message:
This requires proper dominance
---
Diffs of the changes: (+1 -1)
Dominators.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/VMCore/Dominators.cpp
diff -u llvm/lib/VMCore/Dominators.cpp:1.63 llvm/lib/VMCore/Dominators.cpp:1.64
--- llvm/lib/VMCore/Dominators.cpp:1.63 Mon Apr 25 15:50:33 2005
+++ llvm/lib/VMCore/Dominators.cpp Fri Nov 18 01:27:53 2005
@@ -452,7 +452,7 @@
DomSetType::const_iterator CDFI = ChildDF.begin(), CDFE = ChildDF.end();
for (; CDFI != CDFE; ++CDFI) {
- if (!Node-dominates(DT[*CDFI]))
+ if (!Node-properlyDominates(DT[*CDFI]))
S.insert(*CDFI);
}
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
Changes in directory llvm/lib/Transforms/Utils:
PromoteMemoryToRegister.cpp updated: 1.80 - 1.81
---
Log message:
This needs proper dominance
---
Diffs of the changes: (+14 -5)
PromoteMemoryToRegister.cpp | 19 ++-
1 files changed, 14 insertions(+), 5 deletions(-)
Index: llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
diff -u llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.80
llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.81
--- llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.80 Thu Aug 4
19:57:45 2005
+++ llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp Fri Nov 18
01:29:44 2005
@@ -96,12 +96,18 @@
void run();
-/// dominates - Return true if I1 dominates I2 using the DominatorTree.
+/// properlyDominates - Return true if I1 properly dominates I2.
///
-bool dominates(Instruction *I1, Instruction *I2) const {
+bool properlyDominates(Instruction *I1, Instruction *I2) const {
if (InvokeInst *II = dyn_castInvokeInst(I1))
I1 = II-getNormalDest()-begin();
- return DT[I1-getParent()]-dominates(DT[I2-getParent()]);
+ return DT[I1-getParent()]-properlyDominates(DT[I2-getParent()]);
+}
+
+/// dominates - Return true if BB1 dominates BB2 using the DominatorTree.
+///
+bool dominates(BasicBlock *BB1, BasicBlock *BB2) const {
+ return DT[BB1]-dominates(DT[BB2]);
}
private:
@@ -168,7 +174,8 @@
// Remember the basic blocks which define new values for the alloca
DefiningBlocks.push_back(SI-getParent());
AllocaPointerVal = SI-getOperand(0);
- } else if (LoadInst *LI = dyn_castLoadInst(User)) {
+ } else {
+LoadInst *LI = castLoadInst(User);
// Otherwise it must be a load instruction, keep track of variable
reads
UsingBlocks.push_back(LI-getParent());
AllocaPointerVal = LI;
@@ -194,6 +201,7 @@
continue;
}
+
if (AST)
PointerAllocaValues[AllocaNum] = AllocaPointerVal;
@@ -348,7 +356,8 @@
for (unsigned i = 0, e = PNs.size(); i != e; ++i)
if (PNs[i]) {
if (Value *V = PNs[i]-hasConstantValue(true)) {
- if (!isaInstruction(V) || dominates(castInstruction(V), PNs[i]))
{
+ if (!isaInstruction(V) ||
+ properlyDominates(castInstruction(V), PNs[i])) {
if (AST isaPointerType(PNs[i]-getType()))
AST-deleteValue(PNs[i]);
PNs[i]-replaceAllUsesWith(V);
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
Changes in directory llvm/lib/Transforms/Utils:
PromoteMemoryToRegister.cpp updated: 1.81 - 1.82
---
Log message:
Implement a refinement to the mem2reg algorithm for cases where an alloca
has a single def. In this case, look for uses that are dominated by the def
and attempt to rewrite them to directly use the stored value.
This speeds up mem2reg on these values and reduces the number of phi nodes
inserted. This should address PR665: http://llvm.cs.uiuc.edu/PR665 .
---
Diffs of the changes: (+55 -0)
PromoteMemoryToRegister.cpp | 55
1 files changed, 55 insertions(+)
Index: llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
diff -u llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.81
llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.82
--- llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.81 Fri Nov 18
01:29:44 2005
+++ llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp Fri Nov 18
01:31:42 2005
@@ -161,6 +161,7 @@
std::vectorBasicBlock* DefiningBlocks;
std::vectorBasicBlock* UsingBlocks;
+StoreInst *OnlyStore = 0;
BasicBlock *OnlyBlock = 0;
bool OnlyUsedInOneBlock = true;
@@ -174,6 +175,7 @@
// Remember the basic blocks which define new values for the alloca
DefiningBlocks.push_back(SI-getParent());
AllocaPointerVal = SI-getOperand(0);
+OnlyStore = SI;
} else {
LoadInst *LI = castLoadInst(User);
// Otherwise it must be a load instruction, keep track of variable
reads
@@ -201,6 +203,59 @@
continue;
}
+// If there is only a single store to this value, replace any loads of
+// it that are directly dominated by the definition with the value stored.
+if (DefiningBlocks.size() == 1) {
+ // Be aware of loads before the store.
+ std::setBasicBlock* ProcessedBlocks;
+ for (unsigned i = 0, e = UsingBlocks.size(); i != e; ++i)
+// If the store dominates the block and if we haven't processed it yet,
+// do so now.
+if (dominates(OnlyStore-getParent(), UsingBlocks[i]))
+ if (ProcessedBlocks.insert(UsingBlocks[i]).second) {
+BasicBlock *UseBlock = UsingBlocks[i];
+
+// If the use and store are in the same block, do a quick scan to
+// verify that there are no uses before the store.
+if (UseBlock == OnlyStore-getParent()) {
+ BasicBlock::iterator I = UseBlock-begin();
+ for (; *I != OnlyStore; ++I) { // scan block for store.
+if (isaLoadInst(I) I-getOperand(0) == AI)
+ break;
+ }
+ if (*I != OnlyStore) break; // Do not handle this case.
+}
+
+// Otherwise, if this is a different block or if all uses happen
+// after the store, do a simple linear scan to replace loads with
+// the stored value.
+for (BasicBlock::iterator I = UseBlock-begin(),E =
UseBlock-end();
+ I != E; ) {
+ if (LoadInst *LI = dyn_castLoadInst(I++)) {
+if (LI-getOperand(0) == AI) {
+ LI-replaceAllUsesWith(OnlyStore-getOperand(0));
+ if (AST isaPointerType(LI-getType()))
+AST-deleteValue(LI);
+ LI-eraseFromParent();
+}
+ }
+}
+
+// Finally, remove this block from the UsingBlock set.
+UsingBlocks[i] = UsingBlocks.back();
+--i; --e;
+ }
+
+ // Finally, after the scan, check to see if the store is all that is
left.
+ if (UsingBlocks.empty()) {
+// The alloca has been processed, move on.
+Allocas[AllocaNum] = Allocas.back();
+Allocas.pop_back();
+--AllocaNum;
+continue;
+ }
+}
+
if (AST)
PointerAllocaValues[AllocaNum] = AllocaPointerVal;
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.100 - 1.101
---
Log message:
Split out the shift code from visitBinary.
---
Diffs of the changes: (+14 -7)
SelectionDAGISel.cpp | 21 ++---
1 files changed, 14 insertions(+), 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.100
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.101
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.100Wed Nov 16
01:22:30 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Nov 18 01:42:56 2005
@@ -347,7 +347,8 @@
void visitUnwind(UnwindInst I) { assert(0 TODO); }
//
- void visitBinary(User I, unsigned Opcode, bool isShift = false);
+ void visitBinary(User I, unsigned Opcode);
+ void visitShift(User I, unsigned Opcode);
void visitAdd(User I) {
visitBinary(I, I.getType()-isFloatingPoint() ? ISD::FADD : ISD::ADD);
}
@@ -380,9 +381,9 @@
void visitAnd(User I) { visitBinary(I, ISD::AND); }
void visitOr (User I) { visitBinary(I, ISD::OR); }
void visitXor(User I) { visitBinary(I, ISD::XOR); }
- void visitShl(User I) { visitBinary(I, ISD::SHL, true); }
- void visitShr(User I) {
-visitBinary(I, I.getType()-isUnsigned() ? ISD::SRL : ISD::SRA, true);
+ void visitShl(User I) { visitShift(I, ISD::SHL); }
+ void visitShr(User I) {
+visitShift(I, I.getType()-isUnsigned() ? ISD::SRL : ISD::SRA);
}
void visitSetCC(User I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc);
@@ -520,13 +521,19 @@
}
}
-void SelectionDAGLowering::visitBinary(User I, unsigned Opcode, bool isShift)
{
+void SelectionDAGLowering::visitBinary(User I, unsigned Opcode) {
SDOperand Op1 = getValue(I.getOperand(0));
SDOperand Op2 = getValue(I.getOperand(1));
- if (isShift)
-Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
+ setValue(I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
+}
+void SelectionDAGLowering::visitShift(User I, unsigned Opcode) {
+ SDOperand Op1 = getValue(I.getOperand(0));
+ SDOperand Op2 = getValue(I.getOperand(1));
+
+ Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
+
setValue(I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
