[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAGList.cpp updated: 1.18 - 1.19 --- Log message: update file comment --- Diffs of the changes: (+8 -3) ScheduleDAGList.cpp | 11 --- 1 files changed, 8 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.18 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.19 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.18 Mon Mar 6 01:31:44 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Mon Mar 6 11:58:04 2006 @@ -7,9 +7,14 @@ // //===--===// // -// This implements a simple two pass scheduler. The first pass attempts to push -// backward any lengthy instructions and critical paths. The second pass packs -// instructions into semi-optimal time slots. +// This implements bottom-up and top-down list schedulers, using standard +// algorithms. The basic approach uses a priority queue of available nodes to +// schedule. One at a time, nodes are taken from the priority queue (thus in +// priority order), checked for legality to schedule, and emitted if legal. +// +// Nodes may not be legal to schedule either due to structural hazards (e.g. +// pipeline or resource constraints) or because an input to the instruction has +// not completed execution. // //===--===// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/MultiSource/Applications/JM/ldecod/Makefile
Changes in directory llvm-test/MultiSource/Applications/JM/ldecod: Makefile updated: 1.1 - 1.2 --- Log message: fix objdir != srcdir testing --- Diffs of the changes: (+1 -1) Makefile |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/MultiSource/Applications/JM/ldecod/Makefile diff -u llvm-test/MultiSource/Applications/JM/ldecod/Makefile:1.1 llvm-test/MultiSource/Applications/JM/ldecod/Makefile:1.2 --- llvm-test/MultiSource/Applications/JM/ldecod/Makefile:1.1 Sat Feb 11 04:33:22 2006 +++ llvm-test/MultiSource/Applications/JM/ldecod/Makefile Mon Mar 6 12:09:38 2006 @@ -3,6 +3,6 @@ CPPFLAGS = -D __USE_LARGEFILE64 -D _FILE_OFFSET_BITS=64 LDFLAGS = -lm $(TOOLLINKOPTS) -RUN_OPTIONS = -i data/test.264 -o data/test_dec.yuv -r data/test_rec.yuv +RUN_OPTIONS = -i $(PROJ_SRC_DIR)/data/test.264 -o $(PROJ_SRC_DIR)/data/test_dec.yuv -r $(PROJ_SRC_DIR)/data/test_rec.yuv include ../../../Makefile.multisrc ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/External/SPEC/CFP2000/177.mesa/Makefile
Changes in directory llvm-test/External/SPEC/CFP2000/177.mesa: Makefile updated: 1.7 - 1.8 --- Log message: Increase default problem size to something reasonable. --- Diffs of the changes: (+1 -1) Makefile |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/External/SPEC/CFP2000/177.mesa/Makefile diff -u llvm-test/External/SPEC/CFP2000/177.mesa/Makefile:1.7 llvm-test/External/SPEC/CFP2000/177.mesa/Makefile:1.8 --- llvm-test/External/SPEC/CFP2000/177.mesa/Makefile:1.7 Mon Sep 6 22:37:34 2004 +++ llvm-test/External/SPEC/CFP2000/177.mesa/Makefile Mon Mar 6 13:53:11 2006 @@ -4,7 +4,7 @@ ifdef LARGE_PROBLEM_SIZE RUN_OPTIONS := -frames 500 else -RUN_OPTIONS := -frames 10 +RUN_OPTIONS := -frames 100 endif RUN_OPTIONS += -meshfile mesa.in -ppmfile mesa.ppm ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/External/SPEC/CFP2000/179.art/Makefile
Changes in directory llvm-test/External/SPEC/CFP2000/179.art: Makefile updated: 1.5 - 1.6 --- Log message: Bump default problem size to something that takes ~3 sec range. --- Diffs of the changes: (+1 -1) Makefile |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/External/SPEC/CFP2000/179.art/Makefile diff -u llvm-test/External/SPEC/CFP2000/179.art/Makefile:1.5 llvm-test/External/SPEC/CFP2000/179.art/Makefile:1.6 --- llvm-test/External/SPEC/CFP2000/179.art/Makefile:1.5Mon Sep 6 22:41:14 2004 +++ llvm-test/External/SPEC/CFP2000/179.art/MakefileMon Mar 6 13:59:04 2006 @@ -3,7 +3,7 @@ ifdef LARGE_PROBLEM_SIZE RUN_OPTIONS = -scanfile c756hel.in -trainfile1 a10.img -stride 2 -startx 134 -starty 220 -endx 184 -endy 240 -objects 3 else -RUN_OPTIONS = -scanfile c756hel.in -trainfile1 a10.img -stride 2 -startx 134 -starty 220 -endx 139 -endy 225 -objects 1 +RUN_OPTIONS = -scanfile c756hel.in -trainfile1 a10.img -stride 2 -startx 134 -starty 220 -endx 154 -endy 230 -objects 3 endif #STDIN_FILENAME = $(RUN_TYPE).in ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.449 - 1.450
---
Log message:
Teach instcombine to increase the alignment of memset/memcpy/memmove when
the pointer is known to come from either a global variable, alloca or
malloc. This allows us to compile this:
P = malloc(28);
memset(P, 0, 28);
into explicit stores on PPC instead of a memset call.
---
Diffs of the changes: (+74 -3)
InstructionCombining.cpp | 77 +--
1 files changed, 74 insertions(+), 3 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.449
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.450
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.449 Sat Mar 4
18:22:33 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Mon Mar 6 14:18:44 2006
@@ -5264,6 +5264,60 @@
return 0;
}
+/// GetKnownAlignment - If the specified pointer has an alignment that we can
+/// determine, return it, otherwise return 0.
+static unsigned GetKnownAlignment(Value *V, TargetData *TD) {
+ if (GlobalVariable *GV = dyn_castGlobalVariable(V)) {
+unsigned Align = GV-getAlignment();
+if (Align == 0 TD)
+ Align = TD-getTypeAlignment(GV-getType()-getElementType());
+return Align;
+ } else if (AllocationInst *AI = dyn_castAllocationInst(V)) {
+unsigned Align = AI-getAlignment();
+if (Align == 0 TD) {
+ if (isaAllocaInst(AI))
+Align = TD-getTypeAlignment(AI-getType()-getElementType());
+ else if (isaMallocInst(AI)) {
+// Malloc returns maximally aligned memory.
+Align = TD-getTypeAlignment(AI-getType()-getElementType());
+Align = std::max(Align,
(unsigned)TD-getTypeAlignment(Type::DoubleTy));
+Align = std::max(Align, (unsigned)TD-getTypeAlignment(Type::LongTy));
+ }
+}
+return Align;
+ } else if (CastInst *CI = dyn_castCastInst(V)) {
+if (isaPointerType(CI-getOperand(0)-getType()))
+ return GetKnownAlignment(CI-getOperand(0), TD);
+return 0;
+ } else if (GetElementPtrInst *GEPI = dyn_castGetElementPtrInst(V)) {
+unsigned BaseAlignment = GetKnownAlignment(GEPI-getOperand(0), TD);
+if (BaseAlignment == 0) return 0;
+
+// If all indexes are zero, it is just the alignment of the base pointer.
+bool AllZeroOperands = true;
+for (unsigned i = 1, e = GEPI-getNumOperands(); i != e; ++i)
+ if (!isaConstant(GEPI-getOperand(i)) ||
+ !castConstant(GEPI-getOperand(i))-isNullValue()) {
+AllZeroOperands = false;
+break;
+ }
+if (AllZeroOperands)
+ return BaseAlignment;
+
+// Otherwise, if the base alignment is = the alignment we expect for the
+// base pointer type, then we know that the resultant pointer is aligned at
+// least as much as its type requires.
+if (!TD) return 0;
+
+const Type *BasePtrTy = GEPI-getOperand(0)-getType();
+if (TD-getTypeAlignment(castPointerType(BasePtrTy)-getElementType())
+= BaseAlignment)
+ return TD-getTypeAlignment(GEPI-getType()-getElementType());
+return 0;
+ }
+ return 0;
+}
+
/// visitCallInst - CallInst simplification. This mostly only handles folding
/// of intrinsic instructions. For normal calls, it allows visitCallSite to do
@@ -5282,8 +5336,6 @@
if (Constant *NumBytes = dyn_castConstant(MI-getLength())) {
if (NumBytes-isNullValue()) return EraseInstFromFunction(CI);
- // FIXME: Increase alignment here.
-
if (ConstantInt *CI = dyn_castConstantInt(NumBytes))
if (CI-getRawValue() == 1) {
// Replace the instruction with just byte operations. We would
@@ -5295,7 +5347,7 @@
// If we have a memmove and the source operation is a constant global,
// then the source and dest pointers can't alias, so we can change this
// into a call to memcpy.
-if (MemMoveInst *MMI = dyn_castMemMoveInst(II))
+if (MemMoveInst *MMI = dyn_castMemMoveInst(II)) {
if (GlobalVariable *GVSrc = dyn_castGlobalVariable(MMI-getSource()))
if (GVSrc-isConstant()) {
Module *M = CI.getParent()-getParent()-getParent();
@@ -5310,7 +5362,26 @@
CI.setOperand(0, MemCpy);
Changed = true;
}
+}
+// If we can determine a pointer alignment that is bigger than currently
+// set, update the alignment.
+if (isaMemCpyInst(MI) || isaMemMoveInst(MI)) {
+ unsigned Alignment1 = GetKnownAlignment(MI-getOperand(1), TD);
+ unsigned Alignment2 = GetKnownAlignment(MI-getOperand(2), TD);
+ unsigned Align = std::min(Alignment1, Alignment2);
+ if (MI-getAlignment()-getRawValue() Align) {
+MI-setAlignment(ConstantUInt::get(Type::UIntTy, Align));
+Changed = true;
+ }
+} else if (isaMemSetInst(MI)) {
+ unsigned Alignment = GetKnownAlignment(MI-getDest(), TD);
+ if
[llvm-commits] CVS: llvm-test/MultiSource/Applications/JM/ldecod/global.h
Changes in directory llvm-test/MultiSource/Applications/JM/ldecod:
global.h updated: 1.1 - 1.2
---
Log message:
Don't overflow filename buffers. grr.
---
Diffs of the changes: (+4 -4)
global.h |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm-test/MultiSource/Applications/JM/ldecod/global.h
diff -u llvm-test/MultiSource/Applications/JM/ldecod/global.h:1.1
llvm-test/MultiSource/Applications/JM/ldecod/global.h:1.2
--- llvm-test/MultiSource/Applications/JM/ldecod/global.h:1.1 Sat Feb 11
04:33:22 2006
+++ llvm-test/MultiSource/Applications/JM/ldecod/global.h Mon Mar 6
14:41:44 2006
@@ -654,9 +654,9 @@
// input parameters from configuration file
struct inp_par
{
- char infile[100]; //! H.264 inputfile
- char outfile[100]; //! Decoded YUV 4:2:0 output
- char reffile[100]; //! Optional YUV 4:2:0 reference
file for SNR measurement
+ char infile[1000]; //! H.264 inputfile
+ char outfile[1000]; //! Decoded YUV 4:2:0 output
+ char reffile[1000]; //! Optional YUV 4:2:0 reference
file for SNR measurement
int FileFormat; //! File format of the Input file,
PAR_OF_ANNEXB or PAR_OF_RTP
int ref_offset;
int poc_scale;
@@ -666,7 +666,7 @@
unsigned long R_decoder;//! Decoder Rate in HRD Model
unsigned long B_decoder;//! Decoder Buffer size in HRD model
unsigned long F_decoder;//! Decoder Initial buffer fullness
in HRD model
- char LeakyBucketParamFile[100]; //! LeakyBucketParamFile
+ char LeakyBucketParamFile[1000]; //! LeakyBucketParamFile
#endif
// picture error concealment
___
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[llvm-commits] CVS: llvm/test/Regression/C++Frontend/2006-03-06-C++RecurseCrash.cpp
Changes in directory llvm/test/Regression/C++Frontend:
2006-03-06-C++RecurseCrash.cpp added (r1.1)
---
Log message:
new regression test
---
Diffs of the changes: (+24 -0)
2006-03-06-C++RecurseCrash.cpp | 24
1 files changed, 24 insertions(+)
Index: llvm/test/Regression/C++Frontend/2006-03-06-C++RecurseCrash.cpp
diff -c /dev/null
llvm/test/Regression/C++Frontend/2006-03-06-C++RecurseCrash.cpp:1.1
*** /dev/null Mon Mar 6 17:52:47 2006
--- llvm/test/Regression/C++Frontend/2006-03-06-C++RecurseCrash.cpp Mon Mar
6 17:52:37 2006
***
*** 0
--- 1,24
+ // %llvmgcc %s -S -o -
+ namespace std {
+ class exception { };
+
+ class type_info {
+ public:
+ virtual ~type_info();
+ };
+
+ }
+
+ namespace __cxxabiv1 {
+ class __si_class_type_info : public std::type_info {
+ ~__si_class_type_info();
+ };
+ }
+
+ class recursive_init: public std::exception {
+ public:
+ virtual ~recursive_init() throw ();
+ };
+
+ recursive_init::~recursive_init() throw() { }
+
___
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.450 - 1.451
---
Log message:
Teach the alignment handling code to look through constant expr casts and GEPs
---
Diffs of the changes: (+12 -4)
InstructionCombining.cpp | 16
1 files changed, 12 insertions(+), 4 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.450
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.451
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.450 Mon Mar 6
14:18:44 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Mon Mar 6 19:28:57 2006
@@ -5285,11 +5285,17 @@
}
}
return Align;
- } else if (CastInst *CI = dyn_castCastInst(V)) {
+ } else if (isaCastInst(V) ||
+ (isaConstantExpr(V)
+ castConstantExpr(V)-getOpcode() == Instruction::Cast)) {
+User *CI = castUser(V);
if (isaPointerType(CI-getOperand(0)-getType()))
return GetKnownAlignment(CI-getOperand(0), TD);
return 0;
- } else if (GetElementPtrInst *GEPI = dyn_castGetElementPtrInst(V)) {
+ } else if (isaGetElementPtrInst(V) ||
+ (isaConstantExpr(V)
+ castConstantExpr(V)-getOpcode()==Instruction::GetElementPtr))
{
+User *GEPI = castUser(V);
unsigned BaseAlignment = GetKnownAlignment(GEPI-getOperand(0), TD);
if (BaseAlignment == 0) return 0;
@@ -5311,8 +5317,10 @@
const Type *BasePtrTy = GEPI-getOperand(0)-getType();
if (TD-getTypeAlignment(castPointerType(BasePtrTy)-getElementType())
-= BaseAlignment)
- return TD-getTypeAlignment(GEPI-getType()-getElementType());
+= BaseAlignment) {
+ const Type *GEPTy = GEPI-getType();
+ return TD-getTypeAlignment(castPointerType(GEPTy)-getElementType());
+}
return 0;
}
return 0;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86ATTAsmPrinter.h X86AsmPrinter.cpp X86AsmPrinter.h X86ISelLowering.cpp X86InstrInfo.td X86IntelAsmPrinter.cpp X86IntelAsmPrinter.h
Changes in directory llvm/lib/Target/X86:
X86ATTAsmPrinter.cpp updated: 1.28 - 1.29
X86ATTAsmPrinter.h updated: 1.8 - 1.9
X86AsmPrinter.cpp updated: 1.167 - 1.168
X86AsmPrinter.h updated: 1.11 - 1.12
X86ISelLowering.cpp updated: 1.102 - 1.103
X86InstrInfo.td updated: 1.251 - 1.252
X86IntelAsmPrinter.cpp updated: 1.21 - 1.22
X86IntelAsmPrinter.h updated: 1.9 - 1.10
---
Log message:
Enable Dwarf debugging info.
---
Diffs of the changes: (+83 -6)
X86ATTAsmPrinter.cpp | 14 +-
X86ATTAsmPrinter.h |2 +-
X86AsmPrinter.cpp |6 ++
X86AsmPrinter.h| 38 --
X86ISelLowering.cpp|4 +++-
X86InstrInfo.td| 13 +
X86IntelAsmPrinter.cpp | 10 ++
X86IntelAsmPrinter.h |2 +-
8 files changed, 83 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.28
llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.29
--- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.28 Sun Feb 26 02:28:12 2006
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.cppMon Mar 6 20:02:57 2006
@@ -27,9 +27,16 @@
/// method to print assembly for each instruction.
///
bool X86ATTAsmPrinter::runOnMachineFunction(MachineFunction MF) {
+ // Let PassManager know we need debug information and relay
+ // the MachineDebugInfo address on to DwarfWriter.
+ DW.SetDebugInfo(getAnalysisMachineDebugInfo());
+
SetupMachineFunction(MF);
O \n\n;
+ // Emit pre-function debug information.
+ DW.BeginFunction(MF);
+
// Print out constants referenced by the function
EmitConstantPool(MF.getConstantPool());
@@ -81,6 +88,9 @@
if (HasDotTypeDotSizeDirective)
O \t.size CurrentFnName , .- CurrentFnName \n;
+ // Emit post-function debug information.
+ DW.EndFunction(MF);
+
// We didn't modify anything.
return false;
}
@@ -101,7 +111,9 @@
case MachineOperand::MO_SignExtendedImmed:
case MachineOperand::MO_UnextendedImmed:
-O '$' (int)MO.getImmedValue();
+if (!Modifier || strcmp(Modifier, debug) != 0)
+ O '$';
+O (int)MO.getImmedValue();
return;
case MachineOperand::MO_MachineBasicBlock: {
MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
Index: llvm/lib/Target/X86/X86ATTAsmPrinter.h
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.8
llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.9
--- llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.8 Tue Feb 21 20:26:30 2006
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.h Mon Mar 6 20:02:57 2006
@@ -21,7 +21,7 @@
namespace x86 {
struct X86ATTAsmPrinter : public X86SharedAsmPrinter {
- X86ATTAsmPrinter(std::ostream O, TargetMachine TM)
+ X86ATTAsmPrinter(std::ostream O, TargetMachine TM)
: X86SharedAsmPrinter(O, TM) { }
virtual const char *getPassName() const {
Index: llvm/lib/Target/X86/X86AsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.167
llvm/lib/Target/X86/X86AsmPrinter.cpp:1.168
--- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.167 Wed Feb 22 23:25:02 2006
+++ llvm/lib/Target/X86/X86AsmPrinter.cpp Mon Mar 6 20:02:57 2006
@@ -75,6 +75,9 @@
default: break;
}
+ // Emit initial debug information.
+ DW.BeginModule(M);
+
return AsmPrinter::doInitialization(M);
}
@@ -187,6 +190,9 @@
}
}
+ // Emit initial debug information.
+ DW.EndModule(M);
+
AsmPrinter::doFinalization(M);
return false; // success
}
Index: llvm/lib/Target/X86/X86AsmPrinter.h
diff -u llvm/lib/Target/X86/X86AsmPrinter.h:1.11
llvm/lib/Target/X86/X86AsmPrinter.h:1.12
--- llvm/lib/Target/X86/X86AsmPrinter.h:1.11Sat Feb 25 03:56:50 2006
+++ llvm/lib/Target/X86/X86AsmPrinter.h Mon Mar 6 20:02:57 2006
@@ -18,6 +18,8 @@
#include X86.h
#include llvm/CodeGen/AsmPrinter.h
+#include llvm/CodeGen/DwarfWriter.h
+#include llvm/CodeGen/MachineDebugInfo.h
#include llvm/ADT/Statistic.h
#include set
@@ -27,14 +29,46 @@
extern Statistic EmittedInsts;
+/// X86DwarfWriter - Dwarf debug info writer customized for Darwin/Mac OS X
+///
+struct X86DwarfWriter : public DwarfWriter {
+ // Ctor.
+X86DwarfWriter(std::ostream o, AsmPrinter *ap)
+ : DwarfWriter(o, ap)
+{
+ needsSet = true;
+ DwarfAbbrevSection = .section __DWARFA,__debug_abbrev;
+ DwarfInfoSection = .section __DWARFA,__debug_info;
+ DwarfLineSection = .section __DWARFA,__debug_line;
+ DwarfFrameSection = .section __DWARFA,__debug_frame;
+ DwarfPubNamesSection = .section __DWARFA,__debug_pubnames;
+ DwarfPubTypesSection = .section __DWARFA,__debug_pubtypes;
+ DwarfStrSection = .section __DWARFA,__debug_str;
+ DwarfLocSection = .section __DWARFA,__debug_loc;
+ DwarfARangesSection = .section __DWARFA,__debug_aranges;
+ DwarfRangesSection = .section __DWARFA,__debug_ranges;
+ DwarfMacInfoSection = .section __DWARFA,__debug_macinfo;
+ TextSection = .text;
+ DataSection = .data;
+}
+};
+
struct
[llvm-commits] CVS: llvm/win32/Support/Support.vcproj
Changes in directory llvm/win32/Support: Support.vcproj updated: 1.14 - 1.15 --- Log message: Keep VC++ building. --- Diffs of the changes: (+6 -0) Support.vcproj |6 ++ 1 files changed, 6 insertions(+) Index: llvm/win32/Support/Support.vcproj diff -u llvm/win32/Support/Support.vcproj:1.14 llvm/win32/Support/Support.vcproj:1.15 --- llvm/win32/Support/Support.vcproj:1.14 Sun Jan 29 22:07:07 2006 +++ llvm/win32/Support/Support.vcproj Mon Mar 6 20:58:13 2006 @@ -128,6 +128,9 @@ RelativePath=..\..\lib\Support\Debug.cpp /File File + RelativePath=..\..\lib\Support\Dwarf.cpp + /File + File RelativePath=..\..\lib\Support\FileUtilities.cpp /File File @@ -239,6 +242,9 @@ RelativePath=..\..\include\llvm\Support\DOTGraphTraits.h /File File + RelativePath=..\..\include\llvm\Support\Dwarf.h + /File + File RelativePath=..\..\include\llvm\Support\ELF.h /File File ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt
Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.68 - 1.69 --- Log message: add a note --- Diffs of the changes: (+14 -0) README.txt | 14 ++ 1 files changed, 14 insertions(+) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.68 llvm/lib/Target/PowerPC/README.txt:1.69 --- llvm/lib/Target/PowerPC/README.txt:1.68 Wed Mar 1 00:36:20 2006 +++ llvm/lib/Target/PowerPC/README.txt Mon Mar 6 22:42:59 2006 @@ -452,3 +452,17 @@ srwi r3, r2, 24 blr +===-=== + +On the G5, logical CR operations are more expensive in their three +address form: ops that read/write the same register are half as expensive as +those that read from two registers that are different from their destination. + +We should model this with two separate instructions. The isel should generate +the two address form of the instructions. When the register allocator +detects that it needs to insert a copy due to the two-addresness of the CR +logical op, it will invoke PPCInstrInfo::convertToThreeAddress. At this point +we can convert to the three address instruction, to save code space. + +This only matters when we start generating cr logical ops. + ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGList.cpp updated: 1.19 - 1.20
---
Log message:
Fix some formatting, when looking for hazards, prefer target nodes over
things like copyfromreg.
---
Diffs of the changes: (+15 -7)
ScheduleDAGList.cpp | 22 +++---
1 files changed, 15 insertions(+), 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.19
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.20
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.19 Mon Mar 6
11:58:04 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Mon Mar 6 23:40:43 2006
@@ -435,19 +435,27 @@
bool HasNoopHazards = false;
do {
- SUnit *CurrNode = Available.top();
+ SUnit *CurNode = Available.top();
Available.pop();
- HazardRecognizer::HazardType HT =
-HazardRec.getHazardType(CurrNode-Node);
+
+ // Get the node represented by this SUnit.
+ SDNode *N = CurNode-Node;
+ // If this is a pseudo op, like copyfromreg, look to see if there is a
+ // real target node flagged to it. If so, use the target node.
+ for (unsigned i = 0, e = CurNode-FlaggedNodes.size();
+ N-getOpcode() ISD::BUILTIN_OP_END i != e; ++i)
+N = CurNode-FlaggedNodes[i];
+
+ HazardRecognizer::HazardType HT = HazardRec.getHazardType(N);
if (HT == HazardRecognizer::NoHazard) {
-FoundNode = CurrNode;
+FoundNode = CurNode;
break;
}
// Remember if this is a noop hazard.
HasNoopHazards |= HT == HazardRecognizer::NoopHazard;
- NotReady.push_back(CurrNode);
+ NotReady.push_back(CurNode);
} while (!Available.empty());
// Add the nodes that aren't ready back onto the available list.
@@ -463,14 +471,14 @@
} else if (!HasNoopHazards) {
// Otherwise, we have a pipeline stall, but no other problem, just
advance
// the current cycle and try again.
- DEBUG(std::cerr *** Advancing cycle, no work to do);
+ DEBUG(std::cerr *** Advancing cycle, no work to do\n);
HazardRec.AdvanceCycle();
++NumStalls;
} else {
// Otherwise, we have no instructions to issue and we have instructions
// that will fault if we don't do this right. This is the case for
// processors without pipeline interlocks and other cases.
- DEBUG(std::cerr *** Emitting noop);
+ DEBUG(std::cerr *** Emitting noop\n);
HazardRec.EmitNoop();
Sequence.push_back(0); // NULL SUnit* - noop
++NumNoops;
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp PPCHazardRecognizers.h PPCISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCHazardRecognizers.cpp added (r1.1)
PPCHazardRecognizers.h added (r1.1)
PPCISelDAGToDAG.cpp updated: 1.161 - 1.162
---
Log message:
Implement a very very simple hazard recognizer for LSU rejects and ctr set/read
flushes
---
Diffs of the changes: (+292 -2)
PPCHazardRecognizers.cpp | 203 +++
PPCHazardRecognizers.h | 79 ++
PPCISelDAGToDAG.cpp | 12 ++
3 files changed, 292 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
diff -c /dev/null llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.1
*** /dev/null Tue Mar 7 00:32:58 2006
--- llvm/lib/Target/PowerPC/PPCHazardRecognizers.cppTue Mar 7 00:32:48 2006
***
*** 0
--- 1,203
+ //===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls
===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Chris Lattner and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for
details.
+ //
+
//===--===//
+ //
+ // This file implements hazard recognizers for scheduling on PowerPC
processors.
+ //
+
//===--===//
+
+ #define DEBUG_TYPE sched
+ #include PPCHazardRecognizers.h
+ #include PPC.h
+ #include llvm/Support/Debug.h
+ #include iostream
+ using namespace llvm;
+
+
+
//===--===//
+ // PowerPC 970 Hazard Recognizer
+ //
+ // FIXME: This is missing some significant cases:
+ // 0. Handling of instructions that must be the first/last in a group.
+ // 1. Modeling of microcoded instructions.
+ // 2. Handling of cracked instructions.
+ // 3. Handling of serialized operations.
+ // 4. Handling of the esoteric cases in Resource-based Instruction
Grouping,
+ // e.g. integer divides that only execute in the second slot.
+ //
+ // Note: on the PPC970, logical CR operations are more expensive in their
three
+ // address form: ops that read/write the same register are half as expensive
as
+ //
+
+ void PPCHazardRecognizer970::EndDispatchGroup() {
+ DEBUG(std::cerr === Start of dispatch group\n);
+ // Pipeline units.
+ NumFXU = NumLSU = NumFPU = 0;
+ HasCR = HasVALU = HasVPERM = false;
+ NumIssued = 0;
+
+ // Structural hazard info.
+ HasCTRSet = false;
+ StorePtr1 = StorePtr2 = SDOperand();
+ StoreSize = 0;
+ }
+
+
+ PPCHazardRecognizer970::PPC970InstrType
+ PPCHazardRecognizer970::GetInstrType(unsigned Opcode) {
+ if (Opcode ISD::BUILTIN_OP_END)
+ return PseudoInst;
+ Opcode -= ISD::BUILTIN_OP_END;
+
+ switch (Opcode) {
+ case PPC::FMRSD: return PseudoInst; // Usually coallesced away.
+ case PPC::BCTRL:
+ case PPC::BL:
+ case PPC::BLA:
+ return BR;
+ case PPC::LFS:
+ case PPC::LWZ:
+ return LSU_LD;
+ case PPC::STFD:
+ return LSU_ST;
+ case PPC::FADDS:
+ case PPC::FCTIWZ:
+ return FPU;
+ }
+
+ return FXU;
+ }
+
+
+ /// StartBasicBlock - Initiate a new dispatch group.
+ void PPCHazardRecognizer970::StartBasicBlock() {
+ EndDispatchGroup();
+ }
+
+ /// isLoadOfStoredAddress - If we have a load from the previously stored
pointer
+ /// as indicated by StorePtr1/StorePtr2/StoreSize, return true.
+ bool PPCHazardRecognizer970::
+ isLoadOfStoredAddress(unsigned LoadSize, SDOperand Ptr1, SDOperand Ptr2)
const {
+ // Handle exact and commuted addresses.
+ if (Ptr1 == StorePtr1 Ptr2 == StorePtr2)
+ return true;
+ if (Ptr2 == StorePtr1 Ptr1 == StorePtr2)
+ return true;
+
+ // Okay, we don't have an exact match, if this is an indexed offset, see if
we
+ // have overlap (which happens during fp-int conversion for example).
+ if (StorePtr2 == Ptr2) {
+ if (ConstantSDNode *StoreOffset = dyn_castConstantSDNode(StorePtr1))
+ if (ConstantSDNode *LoadOffset = dyn_castConstantSDNode(Ptr1)) {
+ // Okay the base pointers match, so we have [c1+r] vs [c2+r]. Check
to
+ // see if the load and store actually overlap.
+ int StoreOffs = StoreOffset-getValue();
+ int LoadOffs = LoadOffset-getValue();
+ if (StoreOffs LoadOffs) {
+ if (int(StoreOffs+StoreSize) LoadOffs) return true;
+ } else {
+ if (int(LoadOffs+LoadSize) StoreOffs) return true;
+ }
+ }
+ }
+ return false;
+ }
+
+ /// getHazardType - We return hazard for any non-branch instruction that would
+ /// terminate terminate the dispatch group. We turn NoopHazard for any
+ /// instructions that wouldn't terminate the dispatch group that would cause a
+ /// pipeline flush.
+ HazardRecognizer::HazardType PPCHazardRecognizer970::
+ getHazardType(SDNode *Node) {
+ PPC970InstrType InstrType = GetInstrType(Node-getOpcode());
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCHazardRecognizers.cpp updated: 1.1 - 1.2
---
Log message:
add some comments that describe what we model
---
Diffs of the changes: (+18 -3)
PPCHazardRecognizers.cpp | 21 ++---
1 files changed, 18 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
diff -u llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.1
llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.2
--- llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.1Tue Mar 7
00:32:48 2006
+++ llvm/lib/Target/PowerPC/PPCHazardRecognizers.cppTue Mar 7 00:44:19 2006
@@ -22,6 +22,24 @@
//===--===//
// PowerPC 970 Hazard Recognizer
//
+// This models the dispatch group formation of the PPC970 processor. Dispatch
+// groups are bundles of up to five instructions that can contain up to two ALU
+// (aka FXU) ops, two FPU ops, two Load/Store ops, one CR op, one VALU op, one
+// VPERM op, and one BRANCH op. If the code contains more instructions in a
+// sequence than the dispatch group can contain (e.g. three loads in a row) the
+// processor terminates the dispatch group early, wasting execution resources.
+//
+// In addition to these restrictions, there are a number of other restrictions:
+// some instructions, e.g. branches, are required to be the last instruction in
+// a group. Additionally, only branches can issue in the 5th (last) slot.
+//
+// Finally, there are a number of structural hazards on the PPC970. These
+// conditions cause large performance penalties due to misprediction, recovery,
+// and replay logic that has to happen. These cases include setting a CTR and
+// branching through it in the same dispatch group, and storing to an address,
+// then loading from the same address within a dispatch group. To avoid these
+// conditions, we insert no-op instructions when appropriate.
+//
// FIXME: This is missing some significant cases:
// 0. Handling of instructions that must be the first/last in a group.
// 1. Modeling of microcoded instructions.
@@ -30,9 +48,6 @@
// 4. Handling of the esoteric cases in Resource-based Instruction
Grouping,
// e.g. integer divides that only execute in the second slot.
//
-// Note: on the PPC970, logical CR operations are more expensive in their three
-// address form: ops that read/write the same register are half as expensive as
-//
void PPCHazardRecognizer970::EndDispatchGroup() {
DEBUG(std::cerr === Start of dispatch group\n);
___
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[llvm-commits] CVS: llvm-test/Makefile.programs
Changes in directory llvm-test: Makefile.programs updated: 1.195 - 1.196 --- Log message: Enable the td scheduler for llcbeta --- Diffs of the changes: (+1 -1) Makefile.programs |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.195 llvm-test/Makefile.programs:1.196 --- llvm-test/Makefile.programs:1.195 Sun Mar 5 03:40:01 2006 +++ llvm-test/Makefile.programs Tue Mar 7 00:47:05 2006 @@ -187,7 +187,7 @@ endif#DISABLE_DIFFS ifeq ($(ARCH),PowerPC) -LLCBETAOPTION := -sched=simple +LLCBETAOPTION := -sched=list-td endif ifeq ($(ARCH),Alpha) LLCBETAOPTION := -enable-alpha-lsmark ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCHazardRecognizers.cpp updated: 1.2 - 1.3
---
Log message:
add some new instructions to the classifier. With this, we correctly insert
a nop into Freebench/neural, which speeds it up from 136-129s (~5.4%).
---
Diffs of the changes: (+11 -0)
PPCHazardRecognizers.cpp | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
diff -u llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.2
llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.3
--- llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.2Tue Mar 7
00:44:19 2006
+++ llvm/lib/Target/PowerPC/PPCHazardRecognizers.cppTue Mar 7 01:14:55 2006
@@ -41,6 +41,7 @@
// conditions, we insert no-op instructions when appropriate.
//
// FIXME: This is missing some significant cases:
+// -1. Handle all of the instruction types in GetInstrType.
// 0. Handling of instructions that must be the first/last in a group.
// 1. Modeling of microcoded instructions.
// 2. Handling of cracked instructions.
@@ -76,12 +77,18 @@
case PPC::BLA:
return BR;
case PPC::LFS:
+ case PPC::LFD:
case PPC::LWZ:
+ case PPC::LFSX:
+ case PPC::LWZX:
return LSU_LD;
case PPC::STFD:
+ case PPC::STW:
return LSU_ST;
case PPC::FADDS:
case PPC::FCTIWZ:
+ case PPC::FRSP:
+ case PPC::FSUB:
return FPU;
}
@@ -159,8 +166,11 @@
unsigned LoadSize;
switch (Opcode) {
default: assert(0 Unknown load!);
+case PPC::LFSX:
case PPC::LFS:
+case PPC::LWZX:
case PPC::LWZ: LoadSize = 4; break;
+case PPC::LFD: LoadSize = 8; break;
}
if (isLoadOfStoredAddress(LoadSize,
@@ -186,6 +196,7 @@
switch (Opcode) {
default: assert(0 Unknown store instruction!);
case PPC::STFD: StoreSize = 8; break;
+case PPC::STW: StoreSize = 4; break;
}
}
___
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