[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.175 - 1.176
---
Log message:
Temporary hack to enable more (store (op (load ...))) folding. This makes
it possible when a TokenFactor is between the load and store. But is still
missing some cases due to ordering issue.
---
Diffs of the changes: (+74 -30)
DAGISelEmitter.cpp | 104 +
1 files changed, 74 insertions(+), 30 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.175
llvm/utils/TableGen/DAGISelEmitter.cpp:1.176
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.175Tue Mar 7 02:31:27 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Thu Mar 9 02:19:11 2006
@@ -1866,6 +1866,7 @@
std::setstd::pairbool, std::string GeneratedDecl;
std::string ChainName;
+ bool NewTF;
bool DoReplace;
unsigned TmpNo;
@@ -1888,7 +1889,8 @@
std::setstd::pairbool, std::string gd,
bool dorep)
: ISE(ise), Predicates(preds), Pattern(pattern), Instruction(instr),
-GeneratedCode(gc), GeneratedDecl(gd), DoReplace(dorep), TmpNo(0) {}
+GeneratedCode(gc), GeneratedDecl(gd),
+NewTF(false), DoReplace(dorep), TmpNo(0) {}
/// EmitMatchCode - Emit a matcher for N, going to the label for PatternNo
/// if the match fails. At this point, we already know that the opcode for N
@@ -2018,14 +2020,19 @@
}
if (NodeHasChain) {
-if (FoundChain)
- emitCheck(Chain.Val == + RootName + .Val);
-else
- FoundChain = true;
ChainName = Chain + ChainSuffix;
emitDecl(ChainName);
-emitCode(ChainName + = + RootName +
- .getOperand(0););
+if (FoundChain) {
+ // FIXME: temporary workaround for a common case where chain
+ // is a TokenFactor and the previous inner chain is an operand.
+ NewTF = true;
+ emitDecl(OldTF, true);
+ emitCheck(( + ChainName + = UpdateFoldedChain(CurDAG, +
+RootName + .Val, Chain.Val, OldTF)).Val);
+} else {
+ FoundChain = true;
+ emitCode(ChainName + = + RootName + .getOperand(0););
+}
}
}
@@ -2272,11 +2279,11 @@
emitCode(bool HasOptInFlag = false;);
// How many results is this pattern expected to produce?
- unsigned NumExpectedResults = 0;
+ unsigned PatResults = 0;
for (unsigned i = 0, e = Pattern-getExtTypes().size(); i != e; i++) {
MVT::ValueType VT = Pattern-getTypeNum(i);
if (VT != MVT::isVoid VT != MVT::Flag)
- NumExpectedResults++;
+ PatResults++;
}
// Determine operand emission order. Complex pattern first.
@@ -2405,61 +2412,64 @@
emitCode(Code + ););
}
-unsigned ValNo = 0;
-for (unsigned i = 0; i NumResults; i++) {
+if (NewTF)
+ emitCode(if (OldTF)
+ SelectionDAG::InsertISelMapEntry(CodeGenMap, OldTF, 0, +
+ ChainName + .Val, 0););
+
+for (unsigned i = 0; i NumResults; i++)
emitCode(SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, +
- utostr(ValNo) + , ResNode, + utostr(ValNo) + ););
- ValNo++;
-}
+ utostr(i) + , ResNode, + utostr(i) + ););
if (NodeHasOutFlag)
emitCode(InFlag = SDOperand(ResNode, +
- utostr(ValNo + (unsigned)HasChain) + ););
+ utostr(NumResults + (unsigned)HasChain) + ););
if (HasImpResults EmitCopyFromRegs(N, ChainEmitted)) {
- emitCode(SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, +
- utostr(ValNo) + , ResNode, + utostr(ValNo) + ););
- ValNo++;
+ emitCode(SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val,
+ 0, ResNode, 0););
+ NumResults = 1;
}
-// User does not expect the instruction would produce a chain!
-bool AddedChain = HasChain !NodeHasChain;
if (NodeHasChain) {
emitCode(SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, +
- utostr(ValNo) + , ResNode, + utostr(ValNo) + ););
+ utostr(PatResults) + , ResNode, +
+ utostr(NumResults) + ););
if (DoReplace)
-emitCode(if (N.ResNo == 0) AddHandleReplacement(N.Val,
- + utostr(ValNo) + , + ResNode, + utostr(ValNo) +
););
- ValNo++;
+emitCode(if (N.ResNo == 0) AddHandleReplacement(N.Val, +
+ utostr(PatResults) + , + ResNode, +
+ utostr(NumResults) + ););
}
-
if (FoldedChains.size() 0) {
std::string Code;
for (unsigned j = 0, e = FoldedChains.size(); j e; j++)
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp AlphaInstrInfo.td
Changes in directory llvm/lib/Target/Alpha:
AlphaISelLowering.cpp updated: 1.39 - 1.40
AlphaInstrInfo.td updated: 1.113 - 1.114
---
Log message:
fcopysign and get rid of dsnode cruft. custom PA runtimes make this better in
some senses
---
Diffs of the changes: (+15 -220)
AlphaISelLowering.cpp | 165 --
AlphaInstrInfo.td | 70 -
2 files changed, 15 insertions(+), 220 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.39
llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.40
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.39Sat Mar 4 23:08:37 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Thu Mar 9 08:58:25 2006
@@ -26,12 +26,6 @@
using namespace llvm;
-namespace llvm {
- cl::optbool EnableAlphaLSMark(enable-alpha-lsmark,
-cl::desc(Emit symbols to correlate Mem ops to LLVM Values),
-cl::Hidden);
-}
-
/// AddLiveIn - This helper function adds the specified physical register to
the
/// MachineFunction as a live in value. It also creates a corresponding
virtual
/// register for it.
@@ -71,20 +65,6 @@
setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
- if (EnableAlphaLSMark) {
-setOperationAction(ISD::LOAD, MVT::i64, Custom);
-setOperationAction(ISD::LOAD, MVT::f64, Custom);
-setOperationAction(ISD::LOAD, MVT::f32, Custom);
-
-setOperationAction(ISD::ZEXTLOAD, MVT::i8, Custom);
-setOperationAction(ISD::ZEXTLOAD, MVT::i16, Custom);
-setOperationAction(ISD::SEXTLOAD, MVT::i32, Custom);
-
-setOperationAction(ISD::EXTLOAD, MVT::i8, Custom);
-setOperationAction(ISD::EXTLOAD, MVT::i16, Custom);
-setOperationAction(ISD::EXTLOAD, MVT::i32, Custom);
- }
-
setOperationAction(ISD::FREM, MVT::f32, Expand);
setOperationAction(ISD::FREM, MVT::f64, Expand);
@@ -175,18 +155,6 @@
case AlphaISD::GlobalBaseReg: return Alpha::GlobalBaseReg;
case AlphaISD::CALL: return Alpha::CALL;
case AlphaISD::DivCall: return Alpha::DivCall;
- case AlphaISD::LDQ_: return Alpha::LDQ_;
- case AlphaISD::LDT_: return Alpha::LDT_;
- case AlphaISD::LDS_: return Alpha::LDS_;
- case AlphaISD::LDL_: return Alpha::LDL_;
- case AlphaISD::LDWU_: return Alpha::LDWU_;
- case AlphaISD::LDBU_: return Alpha::LDBU_;
- case AlphaISD::STQ_: return Alpha::STQ_;
- case AlphaISD::STT_: return Alpha::STT_;
- case AlphaISD::STS_: return Alpha::STS_;
- case AlphaISD::STL_: return Alpha::STL_;
- case AlphaISD::STW_: return Alpha::STW_;
- case AlphaISD::STB_: return Alpha::STB_;
}
}
@@ -395,48 +363,6 @@
BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
}
-
-
-static void getValueInfo(const Value* v, int type, int fun, int offset)
-{
- fun = type = offset = 0;
- if (v == NULL) {
-type = 0;
- } else if (const GlobalValue* GV = dyn_castGlobalValue(v)) {
-type = 1;
-const Module* M = GV-getParent();
-for(Module::const_global_iterator ii = M-global_begin(); *ii != GV; ++ii)
- ++offset;
- } else if (const Argument* Arg = dyn_castArgument(v)) {
-type = 2;
-const Function* F = Arg-getParent();
-const Module* M = F-getParent();
-for(Module::const_iterator ii = M-begin(); *ii != F; ++ii)
- ++fun;
-for(Function::const_arg_iterator ii = F-arg_begin(); *ii != Arg; ++ii)
- ++offset;
- } else if (const Instruction* I = dyn_castInstruction(v)) {
-assert(dyn_castPointerType(I-getType()));
-type = 3;
-const BasicBlock* bb = I-getParent();
-const Function* F = bb-getParent();
-const Module* M = F-getParent();
-for(Module::const_iterator ii = M-begin(); *ii != F; ++ii)
- ++fun;
-for(Function::const_iterator ii = F-begin(); *ii != bb; ++ii)
- offset += ii-size();
-for(BasicBlock::const_iterator ii = bb-begin(); *ii != I; ++ii)
- ++offset;
- } else if (const Constant* C = dyn_castConstant(v)) {
-//Don't know how to look these up yet
-type = 0;
- } else {
-assert(0 Error in value marking);
- }
- //type = 4: register spilling
- //type = 5: global address loading or constant loading
-}
-
static int getUID()
{
static int id = 0;
@@ -535,97 +461,6 @@
}
break;
- case ISD::LOAD:
- case ISD::SEXTLOAD:
- case ISD::ZEXTLOAD:
- case ISD::EXTLOAD:
-{
- SDOperand Chain = Op.getOperand(0);
- SDOperand Address = Op.getOperand(1);
-
- unsigned Opc;
- unsigned opcode = Op.getOpcode();
-
- if (opcode == ISD::LOAD)
-switch (Op.Val-getValueType(0)) {
-default: Op.Val-dump(); assert(0 Bad load!);
-case MVT::i64: Opc = AlphaISD::LDQ_; break;
-case MVT::f64: Opc = AlphaISD::LDT_; break;
-case MVT::f32: Opc = AlphaISD::LDS_; break;
-}
- else
-switch (castVTSDNode(Op.getOperand(3))-getVT()) {
-default: Op.Val-dump(); assert(0 Bad sign extend!);
-case MVT::i32: Opc = AlphaISD::LDL_;
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.49 - 1.50 --- Log message: fcopysign support --- Diffs of the changes: (+1 -0) TargetSelectionDAG.td |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.49 llvm/lib/Target/TargetSelectionDAG.td:1.50 --- llvm/lib/Target/TargetSelectionDAG.td:1.49 Thu Mar 2 18:19:44 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Thu Mar 9 08:57:36 2006 @@ -262,6 +262,7 @@ def fround : SDNodeISD::FP_ROUND , SDTFPRoundOp; def fextend: SDNodeISD::FP_EXTEND , SDTFPExtendOp; +def fcopysign : SDNodeISD::FCOPYSIGN , SDTFPBinOp; def sint_to_fp : SDNodeISD::SINT_TO_FP , SDTIntToFPOp; def uint_to_fp : SDNodeISD::UINT_TO_FP , SDTIntToFPOp; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/MachineDebugInfo.cpp DwarfWriter.cpp
Changes in directory llvm/lib/CodeGen:
MachineDebugInfo.cpp updated: 1.28 - 1.29
DwarfWriter.cpp updated: 1.45 - 1.46
---
Log message:
temporary hack to get the build working again, apparently a header
commit was forgotten
---
Diffs of the changes: (+4 -4)
DwarfWriter.cpp |2 +-
MachineDebugInfo.cpp |6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/MachineDebugInfo.cpp
diff -u llvm/lib/CodeGen/MachineDebugInfo.cpp:1.28
llvm/lib/CodeGen/MachineDebugInfo.cpp:1.29
--- llvm/lib/CodeGen/MachineDebugInfo.cpp:1.28 Thu Mar 9 07:28:47 2006
+++ llvm/lib/CodeGen/MachineDebugInfo.cpp Thu Mar 9 11:11:08 2006
@@ -653,7 +653,7 @@
, Name()
, File(NULL)
, Size(0)
-, Align(0)
+//, Align(0)
, Offset(0)
{}
@@ -667,7 +667,7 @@
Visitor-Apply((DebugInfoDesc *)File);
Visitor-Apply(Line);
Visitor-Apply(Size);
- Visitor-Apply(Align);
+ //Visitor-Apply(Align);
Visitor-Apply(Offset);
}
@@ -692,7 +692,7 @@
File( File ),
Line( Line ),
Size( Size ),
- Align( Align ),
+ // Align( Align ),
Offset( Offset )\n;
}
#endif
Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.45
llvm/lib/CodeGen/DwarfWriter.cpp:1.46
--- llvm/lib/CodeGen/DwarfWriter.cpp:1.45 Thu Mar 9 07:28:47 2006
+++ llvm/lib/CodeGen/DwarfWriter.cppThu Mar 9 11:11:08 2006
@@ -1323,7 +1323,7 @@
unsigned Line = MemberDesc-getLine();
TypeDesc *MemTy = MemberDesc-getFromType();
uint64_t Size = MemberDesc-getSize();
-uint64_t Align = MemberDesc-getAlign();
+uint64_t Align = 0; //MemberDesc-getAlign();
uint64_t Offset = MemberDesc-getOffset();
// Construct member die.
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaSchedule.td Alpha.td AlphaISelLowering.h AlphaInstrFormats.td AlphaInstrInfo.td AlphaSubtarget.h
Changes in directory llvm/lib/Target/Alpha: AlphaSchedule.td added (r1.1) Alpha.td updated: 1.8 - 1.9 AlphaISelLowering.h updated: 1.14 - 1.15 AlphaInstrFormats.td updated: 1.26 - 1.27 AlphaInstrInfo.td updated: 1.114 - 1.115 AlphaSubtarget.h updated: 1.4 - 1.5 --- Log message: Alpha Scheduling classes --- Diffs of the changes: (+333 -232) Alpha.td | 16 +- AlphaISelLowering.h |3 AlphaInstrFormats.td | 77 +- AlphaInstrInfo.td| 382 +-- AlphaSchedule.td | 84 +++ AlphaSubtarget.h |3 6 files changed, 333 insertions(+), 232 deletions(-) Index: llvm/lib/Target/Alpha/AlphaSchedule.td diff -c /dev/null llvm/lib/Target/Alpha/AlphaSchedule.td:1.1 *** /dev/null Thu Mar 9 11:16:55 2006 --- llvm/lib/Target/Alpha/AlphaSchedule.td Thu Mar 9 11:16:45 2006 *** *** 0 --- 1,84 + //===- AlphaSchedule.td - Alpha Scheduling Definitions -*- tablegen -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by Andrew Lenharth and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===--===// + + //This is table 2-2 from the 21264 compiler writers guide + //modified some + + //Pipelines + + def L0 : FuncUnit; + def L1 : FuncUnit; + def FST0 : FuncUnit; + def FST1 : FuncUnit; + def U0 : FuncUnit; + def U1 : FuncUnit; + def FA : FuncUnit; + def FM : FuncUnit; + + def s_ild : InstrItinClass; + def s_fld : InstrItinClass; + def s_ist : InstrItinClass; + def s_fst : InstrItinClass; + def s_lda : InstrItinClass; + def s_rpcc : InstrItinClass; + def s_rx: InstrItinClass; + def s_mxpr : InstrItinClass; + def s_icbr : InstrItinClass; + def s_ubr : InstrItinClass; + def s_jsr : InstrItinClass; + def s_iadd : InstrItinClass; + def s_ilog : InstrItinClass; + def s_ishf : InstrItinClass; + def s_cmov : InstrItinClass; + def s_imul : InstrItinClass; + def s_imisc : InstrItinClass; + def s_fbr : InstrItinClass; + def s_fadd : InstrItinClass; + def s_fmul : InstrItinClass; + def s_fcmov : InstrItinClass; + def s_fdivt : InstrItinClass; + def s_fdivs : InstrItinClass; + def s_fsqrts: InstrItinClass; + def s_fsqrtt: InstrItinClass; + def s_ftoi : InstrItinClass; + def s_itof : InstrItinClass; + def s_pseudo : InstrItinClass; + + //Table 24 Instruction Class Latency in Cycles + //modified some + + def Alpha21264Itineraries : ProcessorItineraries[ + InstrItinDatas_ild, [InstrStage3, [L0, L1]], + InstrItinDatas_fld, [InstrStage4, [L0, L1]], + InstrItinDatas_ist, [InstrStage0, [L0, L1]], + InstrItinDatas_fst, [InstrStage0, [FST0, FST1, L0, L1]], + InstrItinDatas_lda, [InstrStage1, [L0, L1, U0, U1]], + InstrItinDatas_rpcc , [InstrStage1, [L1]], + InstrItinDatas_rx , [InstrStage1, [L1]], + InstrItinDatas_mxpr , [InstrStage1, [L0, L1]], + InstrItinDatas_icbr , [InstrStage0, [U0, U1]], + InstrItinDatas_ubr, [InstrStage3, [U0, U1]], + InstrItinDatas_jsr, [InstrStage3, [L0]], + InstrItinDatas_iadd , [InstrStage1, [L0, U0, L1, U1]], + InstrItinDatas_ilog , [InstrStage1, [L0, U0, L1, U1]], + InstrItinDatas_ishf , [InstrStage1, [U0, U1]], + InstrItinDatas_cmov , [InstrStage1, [L0, U0, L1, U1]], + InstrItinDatas_imul , [InstrStage7, [U1]], + InstrItinDatas_imisc , [InstrStage3, [U0]], + InstrItinDatas_fbr, [InstrStage0, [FA]], + InstrItinDatas_fadd , [InstrStage6, [FA]], + InstrItinDatas_fmul , [InstrStage6, [FM]], + InstrItinDatas_fcmov , [InstrStage6, [FA]], + InstrItinDatas_fdivs , [InstrStage12, [FA]], + InstrItinDatas_fdivt , [InstrStage15, [FA]], + InstrItinDatas_fsqrts , [InstrStage18, [FA]], + InstrItinDatas_fsqrtt , [InstrStage33, [FA]], + InstrItinDatas_ftoi , [InstrStage3, [FST0, FST1, L0, L1]], + InstrItinDatas_itof , [InstrStage4, [L0, L1]] + ]; Index: llvm/lib/Target/Alpha/Alpha.td diff -u llvm/lib/Target/Alpha/Alpha.td:1.8 llvm/lib/Target/Alpha/Alpha.td:1.9 --- llvm/lib/Target/Alpha/Alpha.td:1.8 Fri Jan 27 02:09:42 2006 +++ llvm/lib/Target/Alpha/Alpha.td Thu Mar 9 11:16:45 2006 @@ -32,6 +32,12 @@ include AlphaRegisterInfo.td //===--===// +// Schedule Description +//===--===// + +include AlphaSchedule.td + +//===--===// // Instruction Descriptions //===--===// @@ -47,11 +53,11 @@ // Alpha Processor Definitions //===--===// -def : Processorgeneric, NoItineraries, []; -def : Processorpca56 ,
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGList.cpp updated: 1.31 - 1.32
---
Log message:
remove temporary option
---
Diffs of the changes: (+1 -3)
ScheduleDAGList.cpp |4 +---
1 files changed, 1 insertion(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.31
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.32
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.31 Thu Mar 9
01:39:25 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Thu Mar 9 11:31:22 2006
@@ -33,8 +33,6 @@
using namespace llvm;
namespace {
- // FIXME: UseLatencies is temporary.
- cl::optbool UseLatencies(use-sched-latencies);
Statistic NumNoops (scheduler, Number of noops inserted);
Statistic NumStalls(scheduler, Number of pipeline stalls);
@@ -508,7 +506,7 @@
// Compute the latency for the node. We use the sum of the latencies for
// all nodes flagged together into this SUnit.
-if (InstrItins.isEmpty() || !UseLatencies) {
+if (InstrItins.isEmpty()) {
// No latency information.
SU-Latency = 1;
} else {
___
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineDebugInfo.h
Changes in directory llvm/include/llvm/CodeGen:
MachineDebugInfo.h updated: 1.28 - 1.29
---
Log message:
Forgot this on last check in.
---
Diffs of the changes: (+3 -0)
MachineDebugInfo.h |3 +++
1 files changed, 3 insertions(+)
Index: llvm/include/llvm/CodeGen/MachineDebugInfo.h
diff -u llvm/include/llvm/CodeGen/MachineDebugInfo.h:1.28
llvm/include/llvm/CodeGen/MachineDebugInfo.h:1.29
--- llvm/include/llvm/CodeGen/MachineDebugInfo.h:1.28 Tue Mar 7 14:53:47 2006
+++ llvm/include/llvm/CodeGen/MachineDebugInfo.hThu Mar 9 11:30:53 2006
@@ -277,6 +277,7 @@
CompileUnitDesc *File;// Declared compile unit (may be NULL.)
int Line; // Declared line# (may be zero.)
uint64_t Size;// Type bit size (may be zero.)
+ uint64_t Align; // Type bit alignment (may be zero.)
uint64_t Offset; // Type bit offset (may be zero.)
public:
@@ -288,12 +289,14 @@
CompileUnitDesc *getFile() const { return File; }
int getLine() const { return Line; }
uint64_t getSize() const { return Size; }
+ uint64_t getAlign()const { return Align; }
uint64_t getOffset() const { return Offset; }
void setContext(DebugInfoDesc *C){ Context = C; }
void setName(const std::string N) { Name = N; }
void setFile(CompileUnitDesc *U) { File = U; }
void setLine(int L) { Line = L; }
void setSize(uint64_t S) { Size = S; }
+ void setAlign(uint64_t A){ Align = A; }
void setOffset(uint64_t O) { Offset = O; }
/// ApplyToFields - Target the visitor to the fields of the TypeDesc.
___
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[llvm-commits] CVS: llvm-test/Makefile.programs
Changes in directory llvm-test: Makefile.programs updated: 1.197 - 1.198 --- Log message: change alpha beta --- Diffs of the changes: (+0 -0) 0 files changed ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrInfo.td
Changes in directory llvm/lib/Target/Alpha: AlphaInstrInfo.td updated: 1.115 - 1.116 --- Log message: alpha and llvm have different oppinions on which arg is the sign bit --- Diffs of the changes: (+8 -10) AlphaInstrInfo.td | 18 -- 1 files changed, 8 insertions(+), 10 deletions(-) Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.115 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.116 --- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.115 Thu Mar 9 11:16:45 2006 +++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Thu Mar 9 11:41:50 2006 @@ -571,11 +571,10 @@ [(set F4RC:$RC, (fmul F4RC:$RA, F4RC:$RB))], s_fmul; def CPYSS : FPForm0x17, 0x020, cpys $RA,$RB,$RC, - [(set F4RC:$RC, (fcopysign F4RC:$RA, F4RC:$RB))], s_fadd; + [(set F4RC:$RC, (fcopysign F4RC:$RB, F4RC:$RA))], s_fadd; def CPYSES : FPForm0x17, 0x022, cpyse $RA,$RB,$RC,[], s_fadd; //Copy sign and exponent -//FIXME: This might be legalized in the oposite manner def CPYSNS : FPForm0x17, 0x021, cpysn $RA,$RB,$RC, - [(set F4RC:$RC, (fneg (fcopysign F4RC:$RA, F4RC:$RB)))], s_fadd; + [(set F4RC:$RC, (fneg (fcopysign F4RC:$RB, F4RC:$RA)))], s_fadd; } //Doubles @@ -595,11 +594,10 @@ [(set F8RC:$RC, (fmul F8RC:$RA, F8RC:$RB))], s_fmul; def CPYST : FPForm0x17, 0x020, cpys $RA,$RB,$RC, - [(set F8RC:$RC, (fcopysign F8RC:$RA, F8RC:$RB))], s_fadd; + [(set F8RC:$RC, (fcopysign F8RC:$RB, F8RC:$RA))], s_fadd; def CPYSET : FPForm0x17, 0x022, cpyse $RA,$RB,$RC,[], s_fadd; //Copy sign and exponent -//FIXME: This might be legalized in the oposite manner def CPYSNT : FPForm0x17, 0x021, cpysn $RA,$RB,$RC, - [(set F8RC:$RC, (fneg (fcopysign F8RC:$RA, F8RC:$RB)))], s_fadd; + [(set F8RC:$RC, (fneg (fcopysign F8RC:$RB, F8RC:$RA)))], s_fadd; def CMPTEQ : FPForm0x16, 0x5A5, cmpteq/su $RA,$RB,$RC, [], s_fadd; //[(set F8RC:$RC, (seteq F8RC:$RA, F8RC:$RB))]; @@ -850,10 +848,10 @@ (CPYSNT F8RC:$RB, F8RC:$RB); def : Pat(fneg F4RC:$RB), (CPYSNS F4RC:$RB, F4RC:$RB); -def : Pat(fcopysign (fneg F4RC:$A), F4RC:$B), - (CPYSNS F4RC:$A, F4RC:$B); -def : Pat(fcopysign (fneg F8RC:$A), F8RC:$B), - (CPYSNT F8RC:$A, F8RC:$B); +def : Pat(fcopysign F4RC:$A, (fneg F4RC:$B)), + (CPYSNS F4RC:$B, F4RC:$A); +def : Pat(fcopysign F8RC:$A, (fneg F8RC:$B)), + (CPYSNT F8RC:$B, F8RC:$A); //Yes, signed multiply high is ugly def : Pat(mulhs GPRC:$RA, GPRC:$RB), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/MachineDebugInfo.cpp DwarfWriter.cpp
Changes in directory llvm/lib/CodeGen:
MachineDebugInfo.cpp updated: 1.29 - 1.30
DwarfWriter.cpp updated: 1.46 - 1.47
---
Log message:
back out my previous hack
---
Diffs of the changes: (+4 -4)
DwarfWriter.cpp |2 +-
MachineDebugInfo.cpp |6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/MachineDebugInfo.cpp
diff -u llvm/lib/CodeGen/MachineDebugInfo.cpp:1.29
llvm/lib/CodeGen/MachineDebugInfo.cpp:1.30
--- llvm/lib/CodeGen/MachineDebugInfo.cpp:1.29 Thu Mar 9 11:11:08 2006
+++ llvm/lib/CodeGen/MachineDebugInfo.cpp Thu Mar 9 11:48:46 2006
@@ -653,7 +653,7 @@
, Name()
, File(NULL)
, Size(0)
-//, Align(0)
+, Align(0)
, Offset(0)
{}
@@ -667,7 +667,7 @@
Visitor-Apply((DebugInfoDesc *)File);
Visitor-Apply(Line);
Visitor-Apply(Size);
- //Visitor-Apply(Align);
+ Visitor-Apply(Align);
Visitor-Apply(Offset);
}
@@ -692,7 +692,7 @@
File( File ),
Line( Line ),
Size( Size ),
- // Align( Align ),
+ Align( Align ),
Offset( Offset )\n;
}
#endif
Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.46
llvm/lib/CodeGen/DwarfWriter.cpp:1.47
--- llvm/lib/CodeGen/DwarfWriter.cpp:1.46 Thu Mar 9 11:11:08 2006
+++ llvm/lib/CodeGen/DwarfWriter.cppThu Mar 9 11:48:46 2006
@@ -1323,7 +1323,7 @@
unsigned Line = MemberDesc-getLine();
TypeDesc *MemTy = MemberDesc-getFromType();
uint64_t Size = MemberDesc-getSize();
-uint64_t Align = 0; //MemberDesc-getAlign();
+uint64_t Align = MemberDesc-getAlign();
uint64_t Offset = MemberDesc-getOffset();
// Construct member die.
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[llvm-commits] CVS: llvm-test/Makefile.programs
Changes in directory llvm-test: Makefile.programs updated: 1.198 - 1.199 --- Log message: Switch PPC beta back to list-td --- Diffs of the changes: (+2 -2) Makefile.programs |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.198 llvm-test/Makefile.programs:1.199 --- llvm-test/Makefile.programs:1.198 Thu Mar 9 11:29:17 2006 +++ llvm-test/Makefile.programs Thu Mar 9 11:45:02 2006 @@ -187,10 +187,10 @@ endif#DISABLE_DIFFS ifeq ($(ARCH),PowerPC) -LLCBETAOPTION := -use-sched-latencies +LLCBETAOPTION := -sched=list-td endif ifeq ($(ARCH),Alpha) -LLCBETAOPTION := -sched=list-td -use-sched-latencies +LLCBETAOPTION := -sched=list-td # -enable-alpha-FTOI -enable-alpha-intfpdiv endif ifeq ($(ARCH),IA64) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.50 - 1.51 --- Log message: relax fcopysign --- Diffs of the changes: (+4 -1) TargetSelectionDAG.td |5 - 1 files changed, 4 insertions(+), 1 deletion(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.50 llvm/lib/Target/TargetSelectionDAG.td:1.51 --- llvm/lib/Target/TargetSelectionDAG.td:1.50 Thu Mar 9 08:57:36 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Thu Mar 9 11:47:22 2006 @@ -83,6 +83,9 @@ def SDTFPBinOp : SDTypeProfile1, 2, [ // fadd, fmul, etc. SDTCisSameAs0, 1, SDTCisSameAs0, 2, SDTCisFP0 ]; +def SDTFPSignOp : SDTypeProfile1, 2, [ // fcopysign. + SDTCisSameAs0, 1, SDTCisFP0, SDTCisFP2 +]; def SDTFPTernaryOp : SDTypeProfile1, 3, [ // fmadd, fnmsub, etc. SDTCisSameAs0, 1, SDTCisSameAs0, 2, SDTCisSameAs0, 3, SDTCisFP0 ]; @@ -262,7 +265,7 @@ def fround : SDNodeISD::FP_ROUND , SDTFPRoundOp; def fextend: SDNodeISD::FP_EXTEND , SDTFPExtendOp; -def fcopysign : SDNodeISD::FCOPYSIGN , SDTFPBinOp; +def fcopysign : SDNodeISD::FCOPYSIGN , SDTFPSignOp; def sint_to_fp : SDNodeISD::SINT_TO_FP , SDTIntToFPOp; def uint_to_fp : SDNodeISD::UINT_TO_FP , SDTIntToFPOp; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
Changes in directory llvm/lib/Target/Alpha:
AlphaRegisterInfo.cpp updated: 1.35 - 1.36
---
Log message:
remove some now-dead code
---
Diffs of the changes: (+0 -16)
AlphaRegisterInfo.cpp | 16
1 files changed, 16 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.35
llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.36
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.35Thu Feb 2 14:12:32 2006
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Thu Mar 9 12:07:49 2006
@@ -31,10 +31,6 @@
#include iostream
using namespace llvm;
-namespace llvm {
- extern cl::optbool EnableAlphaLSMark;
-}
-
//These describe LDAx
static const int IMM_LOW = -32768;
static const int IMM_HIGH = 32767;
@@ -72,9 +68,6 @@
const TargetRegisterClass *RC) const {
//std::cerr Trying to store getPrettyName(SrcReg) to
FrameIdx \n;
//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
- if (EnableAlphaLSMark)
-BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(1)
- .addImm(getUID());
if (RC == Alpha::F4RCRegisterClass)
BuildMI(MBB, MI, Alpha::STS,
3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::F8RCRegisterClass)
@@ -91,9 +84,6 @@
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const {
//std::cerr Trying to load getPrettyName(DestReg) to
FrameIdx \n;
- if (EnableAlphaLSMark)
-BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(2)
- .addImm(getUID());
if (RC == Alpha::F4RCRegisterClass)
BuildMI(MBB, MI, Alpha::LDS, 2,
DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::F8RCRegisterClass)
@@ -317,9 +307,6 @@
//now if we need to, save the old FP and set the new
if (FP)
{
-if (EnableAlphaLSMark)
- BuildMI(MBB, MBBI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(1)
-.addImm(getUID());
BuildMI(MBB, MBBI, Alpha::STQ,
3).addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
//this must be the last instr in the prolog
BuildMI(MBB, MBBI, Alpha::BIS, 2,
Alpha::R15).addReg(Alpha::R30).addReg(Alpha::R30);
@@ -346,9 +333,6 @@
BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R30).addReg(Alpha::R15)
.addReg(Alpha::R15);
//restore the FP
-if (EnableAlphaLSMark)
- BuildMI(MBB, MBBI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(2)
-.addImm(getUID());
BuildMI(MBB, MBBI, Alpha::LDQ, 2, Alpha::R15).addImm(0).addReg(Alpha::R15);
}
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrInfo.td
Changes in directory llvm/lib/Target/Alpha:
AlphaInstrInfo.td updated: 1.116 - 1.117
---
Log message:
fcopysign for mixed mode
---
Diffs of the changes: (+20 -1)
AlphaInstrInfo.td | 21 -
1 files changed, 20 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.116
llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.117
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.116 Thu Mar 9 11:41:50 2006
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Thu Mar 9 11:56:33 2006
@@ -608,7 +608,21 @@
def CMPTUN : FPForm0x16, 0x5A4, cmptun/su $RA,$RB,$RC, [], s_fadd;
//[(set F8RC:$RC, (setuo F8RC:$RA, F8RC:$RB))];
}
-//TODO: Add lots more FP patterns
+
+//More CPYS forms:
+let OperandList = (ops F8RC:$RC, F4RC:$RA, F8RC:$RB) in {
+def CPYSTs : FPForm0x17, 0x020, cpys $RA,$RB,$RC,
+ [(set F8RC:$RC, (fcopysign F8RC:$RB, F4RC:$RA))], s_fadd;
+def CPYSNTs : FPForm0x17, 0x021, cpysn $RA,$RB,$RC,
+ [(set F8RC:$RC, (fneg (fcopysign F8RC:$RB, F4RC:$RA)))],
s_fadd;
+}
+let OperandList = (ops F4RC:$RC, F8RC:$RA, F4RC:$RB) in {
+def CPYSSt : FPForm0x17, 0x020, cpys $RA,$RB,$RC,
+ [(set F4RC:$RC, (fcopysign F4RC:$RB, F8RC:$RA))], s_fadd;
+def CPYSESt : FPForm0x17, 0x022, cpyse $RA,$RB,$RC,[], s_fadd; //Copy sign
and exponent
+def CPYSNSt : FPForm0x17, 0x021, cpysn $RA,$RB,$RC,
+ [(set F4RC:$RC, (fneg (fcopysign F4RC:$RB, F8RC:$RA)))],
s_fadd;
+}
//conditional moves, floats
let OperandList = (ops F4RC:$RDEST, F4RC:$RFALSE, F4RC:$RTRUE, F8RC:$RCOND),
@@ -848,10 +862,15 @@
(CPYSNT F8RC:$RB, F8RC:$RB);
def : Pat(fneg F4RC:$RB),
(CPYSNS F4RC:$RB, F4RC:$RB);
+
def : Pat(fcopysign F4RC:$A, (fneg F4RC:$B)),
(CPYSNS F4RC:$B, F4RC:$A);
def : Pat(fcopysign F8RC:$A, (fneg F8RC:$B)),
(CPYSNT F8RC:$B, F8RC:$A);
+def : Pat(fcopysign F4RC:$A, (fneg F8RC:$B)),
+ (CPYSNSt F8RC:$B, F4RC:$A);
+def : Pat(fcopysign F8RC:$A, (fneg F4RC:$B)),
+ (CPYSNTs F4RC:$B, F8RC:$A);
//Yes, signed multiply high is ugly
def : Pat(mulhs GPRC:$RA, GPRC:$RB),
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
Changes in directory llvm/lib/Target/Alpha:
AlphaInstrInfo.cpp updated: 1.8 - 1.9
---
Log message:
these are copies too
---
Diffs of the changes: (+5 -1)
AlphaInstrInfo.cpp |6 +-
1 files changed, 5 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.cpp:1.8
llvm/lib/Target/Alpha/AlphaInstrInfo.cpp:1.9
--- llvm/lib/Target/Alpha/AlphaInstrInfo.cpp:1.8Thu Feb 2 21:07:37 2006
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.cppThu Mar 9 12:18:51 2006
@@ -26,7 +26,11 @@
unsigned sourceReg,
unsigned destReg) const {
MachineOpCode oc = MI.getOpcode();
- if (oc == Alpha::BIS || oc == Alpha::CPYSS || oc == Alpha::CPYST) {
+ if (oc == Alpha::BIS||
+ oc == Alpha::CPYSS ||
+ oc == Alpha::CPYST ||
+ oc == Alpha::CPYSSt ||
+ oc == Alpha::CPYSTs) {
// or r1, r2, r2
// cpys(s|t) r1 r2 r2
assert(MI.getNumOperands() == 3
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[llvm-commits] CVS: llvm/test/Regression/Transforms/SimplifyLibCalls/MemCpy.ll MemMove.ll
Changes in directory llvm/test/Regression/Transforms/SimplifyLibCalls: MemCpy.ll updated: 1.1 - 1.2 MemMove.ll updated: 1.1 - 1.2 --- Log message: Update these tests (which use autoupgrade) to run constprop and check that the file parses. --- Diffs of the changes: (+4 -2) MemCpy.ll |3 ++- MemMove.ll |3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) Index: llvm/test/Regression/Transforms/SimplifyLibCalls/MemCpy.ll diff -u llvm/test/Regression/Transforms/SimplifyLibCalls/MemCpy.ll:1.1 llvm/test/Regression/Transforms/SimplifyLibCalls/MemCpy.ll:1.2 --- llvm/test/Regression/Transforms/SimplifyLibCalls/MemCpy.ll:1.1 Tue Apr 26 02:40:40 2005 +++ llvm/test/Regression/Transforms/SimplifyLibCalls/MemCpy.ll Thu Mar 9 12:43:07 2006 @@ -1,5 +1,6 @@ ; Test that the StrCatOptimizer works correctly -; RUN: llvm-as %s | opt -simplify-libcalls | llvm-dis | not grep 'call.*llvm.memcpy' +; RUN: llvm-as %s | opt -constprop -simplify-libcalls -disable-output +; RUN: llvm-as %s | opt -constprop -simplify-libcalls | llvm-dis | not grep 'call.*llvm.memcpy' declare sbyte* %llvm.memcpy(sbyte*,sbyte*,int,int) %h = constant [2 x sbyte] ch\00 Index: llvm/test/Regression/Transforms/SimplifyLibCalls/MemMove.ll diff -u llvm/test/Regression/Transforms/SimplifyLibCalls/MemMove.ll:1.1 llvm/test/Regression/Transforms/SimplifyLibCalls/MemMove.ll:1.2 --- llvm/test/Regression/Transforms/SimplifyLibCalls/MemMove.ll:1.1 Tue Apr 26 14:05:51 2005 +++ llvm/test/Regression/Transforms/SimplifyLibCalls/MemMove.ll Thu Mar 9 12:43:07 2006 @@ -1,5 +1,6 @@ ; Test that the StrCatOptimizer works correctly -; RUN: llvm-as %s | opt -simplify-libcalls | llvm-dis | not grep 'call.*llvm.memmove' +; RUN: llvm-as %s | opt -constprop -simplify-libcalls -disable-output +; RUN: llvm-as %s | opt -constprop -simplify-libcalls | llvm-dis | not grep 'call.*llvm.memmove' declare sbyte* %llvm.memmove(sbyte*,sbyte*,int,int) %h = constant [2 x sbyte] ch\00 ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/VMCore/AutoUpgrade.cpp
Changes in directory llvm/lib/VMCore:
AutoUpgrade.cpp updated: 1.10 - 1.11
---
Log message:
autoupgrade memcpy/memmove/memset with signed counts.
CVS: --
---
Diffs of the changes: (+12 -4)
AutoUpgrade.cpp | 16
1 files changed, 12 insertions(+), 4 deletions(-)
Index: llvm/lib/VMCore/AutoUpgrade.cpp
diff -u llvm/lib/VMCore/AutoUpgrade.cpp:1.10
llvm/lib/VMCore/AutoUpgrade.cpp:1.11
--- llvm/lib/VMCore/AutoUpgrade.cpp:1.10Fri Mar 3 10:31:22 2006
+++ llvm/lib/VMCore/AutoUpgrade.cpp Thu Mar 9 12:42:10 2006
@@ -84,10 +84,18 @@
case 'm':
if (Name == llvm.memcpy || Name == llvm.memset ||
Name == llvm.memmove) {
- if (F-getFunctionType()-getParamType(2) == Type::UIntTy)
-return M-getOrInsertFunction(Name+.i32, F-getFunctionType());
- if (F-getFunctionType()-getParamType(2) == Type::ULongTy)
-return M-getOrInsertFunction(Name+.i64, F-getFunctionType());
+ if (F-getFunctionType()-getParamType(2) == Type::UIntTy ||
+ F-getFunctionType()-getParamType(2) == Type::IntTy)
+return M-getOrInsertFunction(Name+.i32, Type::VoidTy,
+ PointerType::get(Type::SByteTy),
+ F-getFunctionType()-getParamType(1),
+ Type::UIntTy, Type::UIntTy, NULL);
+ if (F-getFunctionType()-getParamType(2) == Type::ULongTy ||
+ F-getFunctionType()-getParamType(2) == Type::LongTy)
+return M-getOrInsertFunction(Name+.i64, Type::VoidTy,
+ PointerType::get(Type::SByteTy),
+ F-getFunctionType()-getParamType(1),
+ Type::ULongTy, Type::UIntTy, NULL);
}
break;
case 's':
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/store_op_load_fold2.ll store_op_load_fold.ll
Changes in directory llvm/test/Regression/CodeGen/X86:
store_op_load_fold2.ll added (r1.1)
store_op_load_fold.ll updated: 1.1 - 1.2
---
Log message:
Add a test case for (store (op (load ..) ..) ..) folding.
---
Diffs of the changes: (+45 -2)
store_op_load_fold.ll |2 --
store_op_load_fold2.ll | 45 +
2 files changed, 45 insertions(+), 2 deletions(-)
Index: llvm/test/Regression/CodeGen/X86/store_op_load_fold2.ll
diff -c /dev/null llvm/test/Regression/CodeGen/X86/store_op_load_fold2.ll:1.1
*** /dev/null Thu Mar 9 13:04:40 2006
--- llvm/test/Regression/CodeGen/X86/store_op_load_fold2.ll Thu Mar 9
13:04:30 2006
***
*** 0
--- 1,45
+ ; RUN: llvm-as %s | llc -march=x86 -x86-asm-syntax=intel | grep 'and DWORD
PTR' | wc -l | grep 1
+ ;
+ ; FIXME: The number of (store (and (load ..) ..) ..) really should be 2. But
the current hack
+ ; only allow one of the folding to happen.
+
+ %struct.Macroblock = type { int, int, int, int, int, [8 x int],
%struct.Macroblock*, %struct.Macroblock*, int, [2 x [4 x [4 x [2 x int, [16
x sbyte], [16 x sbyte], int, long, [4 x int], [4 x int], long, int, int, int,
int, int, int, int, int, int, int, int, int, int, int, int, short, double, int,
int, int, int, int, int, int, int, int }
+
+ implementation ; Functions:
+
+ internal fastcc int %dct_chroma(int %uv, int %cr_cbp) {
+ entry:
+ br bool false, label %bb2611, label %cond_true129
+
+ cond_true129: ; preds = %entry
+ ret int 0
+
+ bb2611: ; preds = %entry
+ br bool false, label %cond_true2732.preheader, label %cond_next2752
+
+ cond_true2732.preheader: ; preds = %bb2611
+ %tmp2666 = getelementptr %struct.Macroblock* null, int 0, uint 13
; long* [#uses=2]
+ %tmp2674 = cast int 0 to ubyte ; ubyte [#uses=1]
+ br bool false, label %cond_true2732.preheader.split.us, label
%cond_true2732.preheader.split
+
+ cond_true2732.preheader.split.us: ; preds =
%cond_true2732.preheader
+ br bool false, label %cond_true2732.outer.us.us, label
%cond_true2732.outer.us
+
+ cond_true2732.outer.us.us:; preds =
%cond_true2732.preheader.split.us
+ %tmp2667.us.us = load long* %tmp2666; long [#uses=1]
+ %tmp2670.us.us = load long* null; long [#uses=1]
+ %tmp2675.us.us = shl long %tmp2670.us.us, ubyte %tmp2674
; long [#uses=1]
+ %tmp2675not.us.us = xor long %tmp2675.us.us, -1 ; long
[#uses=1]
+ %tmp2676.us.us = and long %tmp2667.us.us, %tmp2675not.us.us
; long [#uses=1]
+ store long %tmp2676.us.us, long* %tmp2666
+ ret int 0
+
+ cond_true2732.outer.us: ; preds =
%cond_true2732.preheader.split.us
+ ret int 0
+
+ cond_true2732.preheader.split:; preds =
%cond_true2732.preheader
+ ret int 0
+
+ cond_next2752:; preds = %bb2611
+ ret int 0
+ }
Index: llvm/test/Regression/CodeGen/X86/store_op_load_fold.ll
diff -u llvm/test/Regression/CodeGen/X86/store_op_load_fold.ll:1.1
llvm/test/Regression/CodeGen/X86/store_op_load_fold.ll:1.2
--- llvm/test/Regression/CodeGen/X86/store_op_load_fold.ll:1.1 Fri Feb 3
00:46:41 2006
+++ llvm/test/Regression/CodeGen/X86/store_op_load_fold.ll Thu Mar 9
13:04:30 2006
@@ -2,8 +2,6 @@
;
; Test the add and load are folded into the store instruction.
-target triple = i686-pc-linux-gnu
-
%X = weak global short 0
void %foo() {
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[llvm-commits] CVS: llvm/lib/VMCore/Makefile
Changes in directory llvm/lib/VMCore: Makefile updated: 1.7 - 1.8 --- Log message: Build intrinsics.gen from intrinsics.td --- Diffs of the changes: (+6 -0) Makefile |6 ++ 1 files changed, 6 insertions(+) Index: llvm/lib/VMCore/Makefile diff -u llvm/lib/VMCore/Makefile:1.7 llvm/lib/VMCore/Makefile:1.8 --- llvm/lib/VMCore/Makefile:1.7Sun Aug 14 10:14:34 2005 +++ llvm/lib/VMCore/MakefileThu Mar 9 13:53:27 2006 @@ -9,6 +9,8 @@ LEVEL = ../.. LIBRARYNAME = LLVMCore +BUILT_SOURCES = $(LEVEL)/include/llvm/intrinsics.gen + include $(LEVEL)/Makefile.config ifeq ($(ARCH),Alpha) BUILD_ARCHIVE = 1 @@ -16,3 +18,7 @@ include $(LEVEL)/Makefile.common +$(LEVEL)/include/llvm/intrinsics.gen: $(LEVEL)/include/llvm/intrinsics.td + @echo Building intrinsics.gen from intrinsics.td + $(Verb) $(TableGen) $ -o $@ -gen-intrinsic + ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/IntrinsicInst.h
Changes in directory llvm/include/llvm: IntrinsicInst.h updated: 1.10 - 1.11 --- Log message: remove dbg_declare, it's not used yet. --- Diffs of the changes: (+0 -1) IntrinsicInst.h |1 - 1 files changed, 1 deletion(-) Index: llvm/include/llvm/IntrinsicInst.h diff -u llvm/include/llvm/IntrinsicInst.h:1.10 llvm/include/llvm/IntrinsicInst.h:1.11 --- llvm/include/llvm/IntrinsicInst.h:1.10 Thu Mar 2 17:57:16 2006 +++ llvm/include/llvm/IntrinsicInst.h Thu Mar 9 14:01:20 2006 @@ -76,7 +76,6 @@ case Intrinsic::dbg_region_start: case Intrinsic::dbg_region_end: case Intrinsic::dbg_func_start: - case Intrinsic::dbg_declare: return true; default: return false; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.183 - 1.184 --- Log message: remove dbg_declare, it's not used yet. --- Diffs of the changes: (+0 -4) SelectionDAGISel.cpp |4 1 files changed, 4 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.183 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.184 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.183Wed Mar 8 12:11:06 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Mar 9 14:02:42 2006 @@ -1003,10 +1003,6 @@ if (I.getType() != Type::VoidTy) setValue(I, DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType(; return 0; - case Intrinsic::dbg_declare: -if (I.getType() != Type::VoidTy) - setValue(I, DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType(; -return 0; case Intrinsic::isunordered_f32: case Intrinsic::isunordered_f64: ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/VMCore/Function.cpp Verifier.cpp
Changes in directory llvm/lib/VMCore: Function.cpp updated: 1.102 - 1.103 Verifier.cpp updated: 1.148 - 1.149 --- Log message: remove dbg_declare, it's not used yet. --- Diffs of the changes: (+0 -2) Function.cpp |1 - Verifier.cpp |1 - 2 files changed, 2 deletions(-) Index: llvm/lib/VMCore/Function.cpp diff -u llvm/lib/VMCore/Function.cpp:1.102 llvm/lib/VMCore/Function.cpp:1.103 --- llvm/lib/VMCore/Function.cpp:1.102 Thu Mar 2 18:19:44 2006 +++ llvm/lib/VMCore/Function.cppThu Mar 9 14:01:50 2006 @@ -232,7 +232,6 @@ if (Name == llvm.dbg.region.start)return Intrinsic::dbg_region_start; if (Name == llvm.dbg.region.end) return Intrinsic::dbg_region_end; if (Name == llvm.dbg.func.start) return Intrinsic::dbg_func_start; -if (Name == llvm.dbg.declare) return Intrinsic::dbg_declare; break; case 'f': if (Name == llvm.frameaddress) return Intrinsic::frameaddress; Index: llvm/lib/VMCore/Verifier.cpp diff -u llvm/lib/VMCore/Verifier.cpp:1.148 llvm/lib/VMCore/Verifier.cpp:1.149 --- llvm/lib/VMCore/Verifier.cpp:1.148 Thu Mar 2 18:19:44 2006 +++ llvm/lib/VMCore/Verifier.cppThu Mar 9 14:01:50 2006 @@ -909,7 +909,6 @@ case Intrinsic::dbg_region_start:NumArgs = 1; break; case Intrinsic::dbg_region_end: NumArgs = 1; break; case Intrinsic::dbg_func_start: NumArgs = 1; break; - case Intrinsic::dbg_declare: NumArgs = 1; break; case Intrinsic::memcpy_i32: NumArgs = 4; break; case Intrinsic::memcpy_i64: NumArgs = 4; break; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/VMCore/Makefile
Changes in directory llvm/lib/VMCore: Makefile updated: 1.8 - 1.9 --- Log message: silly case insensitive file systems... --- Diffs of the changes: (+3 -3) Makefile |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/VMCore/Makefile diff -u llvm/lib/VMCore/Makefile:1.8 llvm/lib/VMCore/Makefile:1.9 --- llvm/lib/VMCore/Makefile:1.8Thu Mar 9 13:53:27 2006 +++ llvm/lib/VMCore/MakefileThu Mar 9 13:55:06 2006 @@ -9,7 +9,7 @@ LEVEL = ../.. LIBRARYNAME = LLVMCore -BUILT_SOURCES = $(LEVEL)/include/llvm/intrinsics.gen +BUILT_SOURCES = $(LEVEL)/include/llvm/Intrinsics.gen include $(LEVEL)/Makefile.config ifeq ($(ARCH),Alpha) @@ -18,7 +18,7 @@ include $(LEVEL)/Makefile.common -$(LEVEL)/include/llvm/intrinsics.gen: $(LEVEL)/include/llvm/intrinsics.td - @echo Building intrinsics.gen from intrinsics.td +$(LEVEL)/include/llvm/Intrinsics.gen: $(LEVEL)/include/llvm/Intrinsics.td + @echo Building Intrinsics.gen from Intrinsics.td $(Verb) $(TableGen) $ -o $@ -gen-intrinsic ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/IntrinsicLowering.cpp
Changes in directory llvm/lib/CodeGen: IntrinsicLowering.cpp updated: 1.40 - 1.41 --- Log message: remove dbg_declare, it's not used yet. --- Diffs of the changes: (+0 -1) IntrinsicLowering.cpp |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/CodeGen/IntrinsicLowering.cpp diff -u llvm/lib/CodeGen/IntrinsicLowering.cpp:1.40 llvm/lib/CodeGen/IntrinsicLowering.cpp:1.41 --- llvm/lib/CodeGen/IntrinsicLowering.cpp:1.40 Thu Mar 2 18:00:25 2006 +++ llvm/lib/CodeGen/IntrinsicLowering.cpp Thu Mar 9 14:02:42 2006 @@ -402,7 +402,6 @@ case Intrinsic::dbg_stoppoint: case Intrinsic::dbg_region_start: case Intrinsic::dbg_region_end: - case Intrinsic::dbg_declare: case Intrinsic::dbg_func_start: if (CI-getType() != Type::VoidTy) CI-replaceAllUsesWith(Constant::getNullValue(CI-getType())); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/README.txt
Changes in directory llvm/lib/Target:
README.txt updated: 1.14 - 1.15
---
Log message:
add a note
---
Diffs of the changes: (+10 -0)
README.txt | 10 ++
1 files changed, 10 insertions(+)
Index: llvm/lib/Target/README.txt
diff -u llvm/lib/Target/README.txt:1.14 llvm/lib/Target/README.txt:1.15
--- llvm/lib/Target/README.txt:1.14 Mon Mar 6 20:46:26 2006
+++ llvm/lib/Target/README.txt Thu Mar 9 14:13:21 2006
@@ -117,3 +117,13 @@
//===-===//
+These two functions should generate the same code on big-endian systems:
+
+int g(int *j,int *l) { return memcmp(j,l,4); }
+int h(int *j, int *l) { return *j - *l; }
+
+this could be done in SelectionDAGISel.cpp, along with other special cases,
+for 1,2,4,8 bytes.
+
+//===-===//
+
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[llvm-commits] CVS: llvm/lib/VMCore/Function.cpp
Changes in directory llvm/lib/VMCore:
Function.cpp updated: 1.103 - 1.104
---
Log message:
Use the function name matcher autogenerated from the .td file.
---
Diffs of the changes: (+3 -76)
Function.cpp | 79 ++-
1 files changed, 3 insertions(+), 76 deletions(-)
Index: llvm/lib/VMCore/Function.cpp
diff -u llvm/lib/VMCore/Function.cpp:1.103 llvm/lib/VMCore/Function.cpp:1.104
--- llvm/lib/VMCore/Function.cpp:1.103 Thu Mar 9 14:01:50 2006
+++ llvm/lib/VMCore/Function.cppThu Mar 9 14:35:01 2006
@@ -207,82 +207,9 @@
assert(Name.size() != 5 'llvm.' is an invalid intrinsic name!);
- switch (Name[5]) {
- case 'b':
-if (Name == llvm.bswap.i16) return Intrinsic::bswap_i16;
-if (Name == llvm.bswap.i32) return Intrinsic::bswap_i32;
-if (Name == llvm.bswap.i64) return Intrinsic::bswap_i64;
-break;
- case 'c':
-if (Name == llvm.ctpop.i8) return Intrinsic::ctpop_i8;
-if (Name == llvm.ctpop.i16) return Intrinsic::ctpop_i16;
-if (Name == llvm.ctpop.i32) return Intrinsic::ctpop_i32;
-if (Name == llvm.ctpop.i64) return Intrinsic::ctpop_i64;
-if (Name == llvm.cttz.i8) return Intrinsic::cttz_i8;
-if (Name == llvm.cttz.i16) return Intrinsic::cttz_i16;
-if (Name == llvm.cttz.i32) return Intrinsic::cttz_i32;
-if (Name == llvm.cttz.i64) return Intrinsic::cttz_i64;
-if (Name == llvm.ctlz.i8) return Intrinsic::ctlz_i8;
-if (Name == llvm.ctlz.i16) return Intrinsic::ctlz_i16;
-if (Name == llvm.ctlz.i32) return Intrinsic::ctlz_i32;
-if (Name == llvm.ctlz.i64) return Intrinsic::ctlz_i64;
-break;
- case 'd':
-if (Name == llvm.dbg.stoppoint) return Intrinsic::dbg_stoppoint;
-if (Name == llvm.dbg.region.start)return Intrinsic::dbg_region_start;
-if (Name == llvm.dbg.region.end) return Intrinsic::dbg_region_end;
-if (Name == llvm.dbg.func.start) return Intrinsic::dbg_func_start;
-break;
- case 'f':
-if (Name == llvm.frameaddress) return Intrinsic::frameaddress;
-break;
- case 'g':
-if (Name == llvm.gcwrite) return Intrinsic::gcwrite;
-if (Name == llvm.gcread) return Intrinsic::gcread;
-if (Name == llvm.gcroot) return Intrinsic::gcroot;
-break;
- case 'i':
-if (Name == llvm.isunordered.f32)
- return Intrinsic::isunordered_f32;
-if (Name == llvm.isunordered.f64)
- return Intrinsic::isunordered_f64;
-break;
- case 'l':
-if (Name == llvm.longjmp) return Intrinsic::longjmp;
-break;
- case 'm':
-if (Name == llvm.memcpy.i32) return Intrinsic::memcpy_i32;
-if (Name == llvm.memcpy.i64) return Intrinsic::memcpy_i64;
-if (Name == llvm.memmove.i32) return Intrinsic::memmove_i32;
-if (Name == llvm.memmove.i64) return Intrinsic::memmove_i64;
-if (Name == llvm.memset.i32) return Intrinsic::memset_i32;
-if (Name == llvm.memset.i64) return Intrinsic::memset_i64;
-break;
- case 'p':
-if (Name == llvm.prefetch) return Intrinsic::prefetch;
-if (Name == llvm.pcmarker) return Intrinsic::pcmarker;
-break;
- case 'r':
-if (Name == llvm.returnaddress)return Intrinsic::returnaddress;
-if (Name == llvm.readcyclecounter) return Intrinsic::readcyclecounter;
-break;
- case 's':
-if (Name == llvm.setjmp) return Intrinsic::setjmp;
-if (Name == llvm.sigsetjmp)return Intrinsic::sigsetjmp;
-if (Name == llvm.siglongjmp) return Intrinsic::siglongjmp;
-if (Name == llvm.stackrestore) return Intrinsic::stackrestore;
-if (Name == llvm.stacksave)return Intrinsic::stacksave;
-if (Name == llvm.sqrt.f32) return Intrinsic::sqrt_f32;
-if (Name == llvm.sqrt.f64) return Intrinsic::sqrt_f64;
-break;
- case 'v':
-if (Name == llvm.va_copy) return Intrinsic::vacopy;
-if (Name == llvm.va_end) return Intrinsic::vaend;
-if (Name == llvm.va_start) return Intrinsic::vastart;
-break;
- }
- // The llvm. namespace is reserved!
- assert(!Unknown LLVM intrinsic function!);
+#define GET_FUNCTION_RECOGNIZER
+#include llvm/Intrinsics.gen
+#undef GET_FUNCTION_RECOGNIZER
return 0;
}
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[llvm-commits] CVS: llvm/utils/TableGen/IntrinsicEmitter.cpp IntrinsicEmitter.h
Changes in directory llvm/utils/TableGen:
IntrinsicEmitter.cpp updated: 1.1 - 1.2
IntrinsicEmitter.h updated: 1.1 - 1.2
---
Log message:
autogenerate the function name recognizer
---
Diffs of the changes: (+41 -0)
IntrinsicEmitter.cpp | 37 +
IntrinsicEmitter.h |4
2 files changed, 41 insertions(+)
Index: llvm/utils/TableGen/IntrinsicEmitter.cpp
diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.1
llvm/utils/TableGen/IntrinsicEmitter.cpp:1.2
--- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.1Thu Mar 2 20:32:46 2006
+++ llvm/utils/TableGen/IntrinsicEmitter.cppThu Mar 9 14:34:19 2006
@@ -55,10 +55,14 @@
// Emit the enum information.
EmitEnumInfo(Ints, OS);
+
+ // Emit the function name recognizer.
+ EmitFnNameRecognizer(Ints, OS);
}
void IntrinsicEmitter::EmitEnumInfo(const std::vectorCodeGenIntrinsic Ints,
std::ostream OS) {
+ OS // Enum values for Intrinsics.h\n;
OS #ifdef GET_INTRINSIC_ENUM_VALUES\n;
for (unsigned i = 0, e = Ints.size(); i != e; ++i) {
OSInts[i].EnumName;
@@ -68,3 +72,36 @@
}
OS #endif\n\n;
}
+
+void IntrinsicEmitter::
+EmitFnNameRecognizer(const std::vectorCodeGenIntrinsic Ints,
+ std::ostream OS) {
+ // Build a function name - intrinsic name mapping.
+ std::mapstd::string, std::string IntMapping;
+ for (unsigned i = 0, e = Ints.size(); i != e; ++i)
+IntMapping[Ints[i].Name] = Ints[i].EnumName;
+
+ OS // Function name - enum value recognizer code.\n;
+ OS #ifdef GET_FUNCTION_RECOGNIZER\n;
+ OSswitch (Name[5]) {\n;
+ OS// The 'llvm.' namespace is reserved!\n;
+ OSdefault: assert(0 \Unknown LLVM intrinsic function!\);\n;
+ // Emit the intrinsics in sorted order.
+ char LastChar = 0;
+ for (std::mapstd::string, std::string::iterator I = IntMapping.begin(),
+ E = IntMapping.end(); I != E; ++I) {
+assert(I-first.size() 5 std::string(I-first.begin(),
+ I-first.begin()+5) == llvm.
+ Invalid intrinsic name!);
+if (I-first[5] != LastChar) {
+ LastChar = I-first[5];
+ OScase ' LastChar ':\n;
+}
+
+OS if (Name == \ I-first \) return Intrinsic::
+I-second ;\n;
+ }
+ OS}\n;
+ OS #endif\n;
+}
+
Index: llvm/utils/TableGen/IntrinsicEmitter.h
diff -u llvm/utils/TableGen/IntrinsicEmitter.h:1.1
llvm/utils/TableGen/IntrinsicEmitter.h:1.2
--- llvm/utils/TableGen/IntrinsicEmitter.h:1.1 Thu Mar 2 20:32:46 2006
+++ llvm/utils/TableGen/IntrinsicEmitter.h Thu Mar 9 14:34:19 2006
@@ -28,6 +28,10 @@
void EmitEnumInfo(const std::vectorCodeGenIntrinsic Ints,
std::ostream OS);
+
+void EmitFnNameRecognizer(const std::vectorCodeGenIntrinsic Ints,
+ std::ostream OS);
+
};
} // End llvm namespace
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[llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.cpp
Changes in directory llvm/lib/Target/X86: X86TargetMachine.cpp updated: 1.105 - 1.106 --- Log message: Add option -enable-x86-lsr to enable x86 loop strength reduction pass. --- Diffs of the changes: (+7 -0) X86TargetMachine.cpp |7 +++ 1 files changed, 7 insertions(+) Index: llvm/lib/Target/X86/X86TargetMachine.cpp diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.105 llvm/lib/Target/X86/X86TargetMachine.cpp:1.106 --- llvm/lib/Target/X86/X86TargetMachine.cpp:1.105 Wed Feb 22 14:19:42 2006 +++ llvm/lib/Target/X86/X86TargetMachine.cppThu Mar 9 15:51:28 2006 @@ -37,6 +37,10 @@ cl::optbool DisableOutput(disable-x86-llc-output, cl::Hidden, cl::desc(Disable the X86 asm printer, for use when profiling the code generator.)); + + cl::optbool EnableX86LSR(enable-x86-lsr, cl::Hidden, + cl::desc(Enable the X86 loop strength reduction + pass.)); // Register the target. RegisterTargetX86TargetMachine X(x86, IA-32 (Pentium and above)); } @@ -92,6 +96,9 @@ if (FileType != TargetMachine::AssemblyFile FileType != TargetMachine::ObjectFile) return true; + // Run loop strength reduction before anything else. + if (EnableX86LSR) PM.add(createLoopStrengthReducePass()); + // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/TableGen/CodeGenIntrinsics.h IntrinsicEmitter.cpp IntrinsicEmitter.h
Changes in directory llvm/utils/TableGen:
CodeGenIntrinsics.h updated: 1.2 - 1.3
IntrinsicEmitter.cpp updated: 1.2 - 1.3
IntrinsicEmitter.h updated: 1.2 - 1.3
---
Log message:
parse intrinsic types
autogenerate an intrinsic verifier
---
Diffs of the changes: (+50 -4)
CodeGenIntrinsics.h |4
IntrinsicEmitter.cpp | 47 ---
IntrinsicEmitter.h |3 ++-
3 files changed, 50 insertions(+), 4 deletions(-)
Index: llvm/utils/TableGen/CodeGenIntrinsics.h
diff -u llvm/utils/TableGen/CodeGenIntrinsics.h:1.2
llvm/utils/TableGen/CodeGenIntrinsics.h:1.3
--- llvm/utils/TableGen/CodeGenIntrinsics.h:1.2 Fri Mar 3 00:13:41 2006
+++ llvm/utils/TableGen/CodeGenIntrinsics.h Thu Mar 9 16:05:04 2006
@@ -26,6 +26,10 @@
std::string Name; // The name of the LLVM function
llvm.bswap.i32
std::string EnumName; // The name of the enum bswap_i32
+/// ArgTypes - The type primitive enum value for the return value and all
+/// of the arguments. These are things like Type::UIntTyID.
+std::vectorstd::string ArgTypes;
+
// Memory mod/ref behavior of this intrinsic.
enum {
NoMem, ReadArgMem, ReadMem, WriteArgMem, WriteMem
Index: llvm/utils/TableGen/IntrinsicEmitter.cpp
diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.2
llvm/utils/TableGen/IntrinsicEmitter.cpp:1.3
--- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.2Thu Mar 9 14:34:19 2006
+++ llvm/utils/TableGen/IntrinsicEmitter.cppThu Mar 9 16:05:04 2006
@@ -42,6 +42,18 @@
else
Name += EnumName[i];
}
+
+ // Parse the list of argument types.
+ ListInit *TypeList = R-getValueAsListInit(Types);
+ for (unsigned i = 0, e = TypeList-getSize(); i != e; ++i) {
+DefInit *DI = dynamic_castDefInit*(TypeList-getElement(i));
+assert(DI Invalid list type!);
+Record *TyEl = DI-getDef();
+assert(TyEl-isSubClassOf(LLVMType) Expected a type!);
+ArgTypes.push_back(TyEl-getValueAsString(TypeVal));
+ }
+ if (ArgTypes.size() == 0)
+throw Intrinsic '+DefName+' needs at least a type for the ret value!;
}
//===--===//
@@ -58,6 +70,9 @@
// Emit the function name recognizer.
EmitFnNameRecognizer(Ints, OS);
+
+ // Emit the intrinsic verifier.
+ EmitVerifier(Ints, OS);
}
void IntrinsicEmitter::EmitEnumInfo(const std::vectorCodeGenIntrinsic Ints,
@@ -84,8 +99,7 @@
OS // Function name - enum value recognizer code.\n;
OS #ifdef GET_FUNCTION_RECOGNIZER\n;
OSswitch (Name[5]) {\n;
- OS// The 'llvm.' namespace is reserved!\n;
- OSdefault: assert(0 \Unknown LLVM intrinsic function!\);\n;
+ OSdefault: break;\n;
// Emit the intrinsics in sorted order.
char LastChar = 0;
for (std::mapstd::string, std::string::iterator I = IntMapping.begin(),
@@ -102,6 +116,33 @@
I-second ;\n;
}
OS}\n;
- OS #endif\n;
+ OS// The 'llvm.' namespace is reserved!\n;
+ OSassert(0 \Unknown LLVM intrinsic function!\);\n;
+ OS #endif\n\n;
+}
+
+void IntrinsicEmitter::EmitVerifier(const std::vectorCodeGenIntrinsic Ints,
+std::ostream OS) {
+ OS // Verifier::visitIntrinsicFunctionCall code.\n;
+ OS #ifdef GET_INTRINSIC_VERIFIER\n;
+ OSswitch (ID) {\n;
+ OSdefault: assert(0 \Invalid intrinsic!\);\n;
+ for (unsigned i = 0, e = Ints.size(); i != e; ++i) {
+OScase Intrinsic:: Ints[i].EnumName :\t\t//
+Ints[i].Name \n;
+OS Assert1(FTy-getNumParams() == Ints[i].ArgTypes.size()-1
+,\n
+\Illegal # arguments for intrinsic function!\,
IF);\n;
+OS Assert1(FTy-getReturnType()-getTypeID() ==
+Ints[i].ArgTypes[0] ,\n
+\Illegal result type!\, IF);\n;
+for (unsigned j = 1; j != Ints[i].ArgTypes.size(); ++j)
+ OS Assert1(FTy-getParamType( j-1 )-getTypeID() ==
+ Ints[i].ArgTypes[j] ,\n
+ \Illegal result type!\, IF);\n;
+OS break;\n;
+ }
+ OS}\n;
+ OS #endif\n\n;
}
Index: llvm/utils/TableGen/IntrinsicEmitter.h
diff -u llvm/utils/TableGen/IntrinsicEmitter.h:1.2
llvm/utils/TableGen/IntrinsicEmitter.h:1.3
--- llvm/utils/TableGen/IntrinsicEmitter.h:1.2 Thu Mar 9 14:34:19 2006
+++ llvm/utils/TableGen/IntrinsicEmitter.h Thu Mar 9 16:05:04 2006
@@ -31,7 +31,8 @@
void EmitFnNameRecognizer(const std::vectorCodeGenIntrinsic Ints,
std::ostream OS);
-
+void EmitVerifier(const std::vectorCodeGenIntrinsic Ints,
+ std::ostream OS);
};
} // End llvm namespace
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[llvm-commits] CVS: llvm/lib/VMCore/Verifier.cpp
Changes in directory llvm/lib/VMCore:
Verifier.cpp updated: 1.149 - 1.150
---
Log message:
Use the autogenerated intrinsic verifier
---
Diffs of the changes: (+5 -266)
Verifier.cpp | 271 +--
1 files changed, 5 insertions(+), 266 deletions(-)
Index: llvm/lib/VMCore/Verifier.cpp
diff -u llvm/lib/VMCore/Verifier.cpp:1.149 llvm/lib/VMCore/Verifier.cpp:1.150
--- llvm/lib/VMCore/Verifier.cpp:1.149 Thu Mar 9 14:01:50 2006
+++ llvm/lib/VMCore/Verifier.cppThu Mar 9 16:06:04 2006
@@ -676,273 +676,12 @@
///
void Verifier::visitIntrinsicFunctionCall(Intrinsic::ID ID, CallInst CI) {
Function *IF = CI.getCalledFunction();
- const FunctionType *FT = IF-getFunctionType();
+ const FunctionType *FTy = IF-getFunctionType();
Assert1(IF-isExternal(), Intrinsic functions should never be defined!,
IF);
- unsigned NumArgs = 0;
-
- // FIXME: this should check the return type of each intrinsic as well, also
- // arguments!
- switch (ID) {
- case Intrinsic::vastart:
-Assert1(CI.getParent()-getParent()-getFunctionType()-isVarArg(),
-llvm.va_start intrinsic may only occur in function with variable
- args!, CI);
-NumArgs = 1;
-break;
- case Intrinsic::vaend: NumArgs = 1; break;
- case Intrinsic::vacopy: NumArgs = 2; break;
-
- case Intrinsic::returnaddress:
- case Intrinsic::frameaddress:
-Assert1(isaPointerType(FT-getReturnType()),
-llvm.(frame|return)address must return pointers, IF);
-Assert1(FT-getNumParams() == 1 isaConstantInt(CI.getOperand(1)),
- llvm.(frame|return)address require a single constant integer argument,
-CI);
-NumArgs = 1;
-break;
-
- case Intrinsic::isunordered_f32:
-Assert1(FT-getNumParams() == 2,
-Illegal # arguments for intrinsic function!, IF);
-Assert1(FT-getReturnType() == Type::BoolTy,
-Return type is not bool!, IF);
-Assert1(FT-getParamType(0) == FT-getParamType(1),
-Arguments must be of the same type!, IF);
-Assert1(FT-getParamType(0) == Type::FloatTy,
-Arguments must be a 32-bit floating point type!, IF);
-NumArgs = 2;
-break;
-
- case Intrinsic::isunordered_f64:
-Assert1(FT-getNumParams() == 2,
-Illegal # arguments for intrinsic function!, IF);
-Assert1(FT-getReturnType() == Type::BoolTy,
-Return type is not bool!, IF);
-Assert1(FT-getParamType(0) == FT-getParamType(1),
-Arguments must be of the same type!, IF);
-Assert1(FT-getParamType(0) == Type::DoubleTy,
-Argument is not a 64-bit floating point type!, IF);
-NumArgs = 2;
-break;
-
- case Intrinsic::readcyclecounter:
-Assert1(FT-getNumParams() == 0,
-Illegal # arguments for intrinsic function!, IF);
-Assert1(FT-getReturnType() == Type::ULongTy,
-Return type is not ulong!, IF);
-NumArgs = 0;
-break;
-
- case Intrinsic::bswap_i16:
-Assert1(FT-getNumParams() == 1,
-Illegal # arguments for intrinsic function!, IF);
-Assert1(FT-getReturnType() == FT-getParamType(0),
-Return type does not match source type, IF);
-Assert1(FT-getReturnType() == Type::UShortTy,
-Return type is not ushort!, IF);
-NumArgs = 1;
-break;
-
- case Intrinsic::bswap_i32:
-Assert1(FT-getNumParams() == 1,
-Illegal # arguments for intrinsic function!, IF);
-Assert1(FT-getReturnType() == FT-getParamType(0),
-Return type does not match source type, IF);
-Assert1(FT-getReturnType() == Type::UIntTy,
-Return type is not uint!, IF);
-NumArgs = 1;
-break;
-
- case Intrinsic::bswap_i64:
-Assert1(FT-getNumParams() == 1,
-Illegal # arguments for intrinsic function!, IF);
-Assert1(FT-getReturnType() == FT-getParamType(0),
-Return type does not match source type, IF);
-Assert1(FT-getReturnType() == Type::ULongTy,
-Return type is not ulong!, IF);
-NumArgs = 1;
-break;
-
- case Intrinsic::ctpop_i8:
-Assert1(FT-getNumParams() == 1,
-Illegal # arguments for intrinsic function!, IF);
-Assert1(FT-getReturnType() == FT-getParamType(0),
-Return type does not match source type, IF);
-Assert1(FT-getParamType(0) == Type::UByteTy,
-Argument is not ubyte!, IF);
-NumArgs = 1;
-break;
-
- case Intrinsic::ctpop_i16:
-Assert1(FT-getNumParams() == 1,
-Illegal # arguments for intrinsic function!, IF);
-Assert1(FT-getReturnType() == FT-getParamType(0),
-Return type does not match source type, IF);
-Assert1(FT-getParamType(0) == Type::UShortTy,
-Argument is not ushort!, IF);
-NumArgs = 1;
-break;
-
- case Intrinsic::ctpop_i32:
-Assert1(FT-getNumParams() == 1,
-Illegal # arguments for intrinsic function!, IF);
-
[llvm-commits] CVS: llvm/docs/ExtendingLLVM.html
Changes in directory llvm/docs: ExtendingLLVM.html updated: 1.23 - 1.24 --- Log message: Simpler still --- Diffs of the changes: (+1 -5) ExtendingLLVM.html |6 +- 1 files changed, 1 insertion(+), 5 deletions(-) Index: llvm/docs/ExtendingLLVM.html diff -u llvm/docs/ExtendingLLVM.html:1.23 llvm/docs/ExtendingLLVM.html:1.24 --- llvm/docs/ExtendingLLVM.html:1.23 Thu Mar 9 16:07:39 2006 +++ llvm/docs/ExtendingLLVM.htmlThu Mar 9 16:32:16 2006 @@ -88,10 +88,6 @@ littllvm/include/llvm/Intrinsics.td/tt: Add an entry for your intrinsic./li -littllvm/lib/Analysis/BasicAliasAnalysis.cpp/tt: If the new intrinsic does -not access memory or does not write to memory, add it to the relevant list -of functions./li - littllvm/lib/Analysis/ConstantFolding.cpp/tt: If it is possible to constant fold your intrinsic, add support to it in the ttcanConstantFoldCallTo/tt and ttConstantFoldCall/tt functions./li @@ -398,7 +394,7 @@ a href=http://llvm.cs.uiuc.edu;The LLVM Compiler Infrastructure/a br - Last modified: $Date: 2006/03/09 22:07:39 $ + Last modified: $Date: 2006/03/09 22:32:16 $ /address /body ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/TableGen/IntrinsicEmitter.cpp IntrinsicEmitter.h
Changes in directory llvm/utils/TableGen:
IntrinsicEmitter.cpp updated: 1.3 - 1.4
IntrinsicEmitter.h updated: 1.3 - 1.4
---
Log message:
Parse mod/ref properties, autogen mod/ref information
---
Diffs of the changes: (+47 -0)
IntrinsicEmitter.cpp | 45 +
IntrinsicEmitter.h |2 ++
2 files changed, 47 insertions(+)
Index: llvm/utils/TableGen/IntrinsicEmitter.cpp
diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.3
llvm/utils/TableGen/IntrinsicEmitter.cpp:1.4
--- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.3Thu Mar 9 16:05:04 2006
+++ llvm/utils/TableGen/IntrinsicEmitter.cppThu Mar 9 16:30:49 2006
@@ -26,6 +26,7 @@
CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
std::string DefName = R-getName();
+ ModRef = WriteMem;
if (DefName.size() = 4 ||
std::string(DefName.begin(), DefName.begin()+4) != int_)
@@ -54,6 +55,29 @@
}
if (ArgTypes.size() == 0)
throw Intrinsic '+DefName+' needs at least a type for the ret value!;
+
+ // Parse the intrinsic properties.
+ ListInit *PropList = R-getValueAsListInit(Properties);
+ for (unsigned i = 0, e = PropList-getSize(); i != e; ++i) {
+DefInit *DI = dynamic_castDefInit*(PropList-getElement(i));
+assert(DI Invalid list type!);
+Record *Property = DI-getDef();
+assert(Property-isSubClassOf(IntrinsicProperty)
+ Expected a property!);
+
+if (Property-getName() == InstrNoMem)
+ ModRef = NoMem;
+else if (Property-getName() == InstrReadArgMem)
+ ModRef = ReadArgMem;
+else if (Property-getName() == IntrReadMem)
+ ModRef = ReadMem;
+else if (Property-getName() == InstrWriteArgMem)
+ ModRef = WriteArgMem;
+else if (Property-getName() == IntrWriteMem)
+ ModRef = WriteMem;
+else
+ assert(0 Unknown property!);
+ }
}
//===--===//
@@ -73,6 +97,9 @@
// Emit the intrinsic verifier.
EmitVerifier(Ints, OS);
+
+ // Emit mod/ref info for each function.
+ EmitModRefInfo(Ints, OS);
}
void IntrinsicEmitter::EmitEnumInfo(const std::vectorCodeGenIntrinsic Ints,
@@ -146,3 +173,21 @@
OS #endif\n\n;
}
+void IntrinsicEmitter::EmitModRefInfo(const std::vectorCodeGenIntrinsic
Ints,
+ std::ostream OS) {
+ OS // BasicAliasAnalysis code.\n;
+ OS #ifdef GET_MODREF_BEHAVIOR\n;
+ for (unsigned i = 0, e = Ints.size(); i != e; ++i) {
+switch (Ints[i].ModRef) {
+default: break;
+case CodeGenIntrinsic::NoMem:
+ OSNoMemoryTable.push_back(\ Ints[i].Name \);\n;
+ break;
+case CodeGenIntrinsic::ReadArgMem:
+case CodeGenIntrinsic::ReadMem:
+ OSOnlyReadsMemoryTable.push_back(\ Ints[i].Name \);\n;
+ break;
+}
+ }
+ OS #endif\n\n;
+}
Index: llvm/utils/TableGen/IntrinsicEmitter.h
diff -u llvm/utils/TableGen/IntrinsicEmitter.h:1.3
llvm/utils/TableGen/IntrinsicEmitter.h:1.4
--- llvm/utils/TableGen/IntrinsicEmitter.h:1.3 Thu Mar 9 16:05:04 2006
+++ llvm/utils/TableGen/IntrinsicEmitter.h Thu Mar 9 16:30:49 2006
@@ -33,6 +33,8 @@
std::ostream OS);
void EmitVerifier(const std::vectorCodeGenIntrinsic Ints,
std::ostream OS);
+void EmitModRefInfo(const std::vectorCodeGenIntrinsic Ints,
+std::ostream OS);
};
} // End llvm namespace
___
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[llvm-commits] CVS: llvm/utils/TableGen/IntrinsicEmitter.cpp IntrinsicEmitter.h
Changes in directory llvm/utils/TableGen:
IntrinsicEmitter.cpp updated: 1.4 - 1.5
IntrinsicEmitter.h updated: 1.4 - 1.5
---
Log message:
generate side-effect info
---
Diffs of the changes: (+27 -0)
IntrinsicEmitter.cpp | 25 +
IntrinsicEmitter.h |2 ++
2 files changed, 27 insertions(+)
Index: llvm/utils/TableGen/IntrinsicEmitter.cpp
diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.4
llvm/utils/TableGen/IntrinsicEmitter.cpp:1.5
--- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.4Thu Mar 9 16:30:49 2006
+++ llvm/utils/TableGen/IntrinsicEmitter.cppThu Mar 9 16:37:52 2006
@@ -100,6 +100,9 @@
// Emit mod/ref info for each function.
EmitModRefInfo(Ints, OS);
+
+ // Emit side effect info for each function.
+ EmitSideEffectInfo(Ints, OS);
}
void IntrinsicEmitter::EmitEnumInfo(const std::vectorCodeGenIntrinsic Ints,
@@ -191,3 +194,25 @@
}
OS #endif\n\n;
}
+
+void IntrinsicEmitter::
+EmitSideEffectInfo(const std::vectorCodeGenIntrinsic Ints, std::ostream
OS){
+ OS // isInstructionTriviallyDead code.\n;
+ OS #ifdef GET_SIDE_EFFECT_INFO\n;
+ OSswitch (F-getIntrinsicID()) {\n;
+ OSdefault: break;\n;
+ for (unsigned i = 0, e = Ints.size(); i != e; ++i) {
+switch (Ints[i].ModRef) {
+ default: break;
+ case CodeGenIntrinsic::NoMem:
+ case CodeGenIntrinsic::ReadArgMem:
+ case CodeGenIntrinsic::ReadMem:
+OScase Intrinsic:: Ints[i].EnumName :\n;
+break;
+}
+ }
+ OS return true; // These intrinsics have no side effects.\n;
+ OS}\n;
+ OS #endif\n\n;
+
+}
Index: llvm/utils/TableGen/IntrinsicEmitter.h
diff -u llvm/utils/TableGen/IntrinsicEmitter.h:1.4
llvm/utils/TableGen/IntrinsicEmitter.h:1.5
--- llvm/utils/TableGen/IntrinsicEmitter.h:1.4 Thu Mar 9 16:30:49 2006
+++ llvm/utils/TableGen/IntrinsicEmitter.h Thu Mar 9 16:37:52 2006
@@ -35,6 +35,8 @@
std::ostream OS);
void EmitModRefInfo(const std::vectorCodeGenIntrinsic Ints,
std::ostream OS);
+void EmitSideEffectInfo(const std::vectorCodeGenIntrinsic Ints,
+std::ostream OS);
};
} // End llvm namespace
___
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[llvm-commits] CVS: llvm/docs/ExtendingLLVM.html
Changes in directory llvm/docs: ExtendingLLVM.html updated: 1.24 - 1.25 --- Log message: Adding an intrinsic is simpler still. --- Diffs of the changes: (+1 -5) ExtendingLLVM.html |6 +- 1 files changed, 1 insertion(+), 5 deletions(-) Index: llvm/docs/ExtendingLLVM.html diff -u llvm/docs/ExtendingLLVM.html:1.24 llvm/docs/ExtendingLLVM.html:1.25 --- llvm/docs/ExtendingLLVM.html:1.24 Thu Mar 9 16:32:16 2006 +++ llvm/docs/ExtendingLLVM.htmlThu Mar 9 16:38:42 2006 @@ -92,10 +92,6 @@ constant fold your intrinsic, add support to it in the ttcanConstantFoldCallTo/tt and ttConstantFoldCall/tt functions./li -littllvm/lib/Transforms/Utils/Local.cpp/tt: If your intrinsic has no side- -effects, add it to the list of intrinsics in the -ttisInstructionTriviallyDead/tt function./li - littllvm/test/Regression/*/tt: Add test cases for your test cases to the test suite/li /ol @@ -394,7 +390,7 @@ a href=http://llvm.cs.uiuc.edu;The LLVM Compiler Infrastructure/a br - Last modified: $Date: 2006/03/09 22:32:16 $ + Last modified: $Date: 2006/03/09 22:38:42 $ /address /body ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Utils/Local.cpp
Changes in directory llvm/lib/Transforms/Utils:
Local.cpp updated: 1.52 - 1.53
---
Log message:
use autogenerated side-effect information
---
Diffs of the changes: (+5 -27)
Local.cpp | 32 +---
1 files changed, 5 insertions(+), 27 deletions(-)
Index: llvm/lib/Transforms/Utils/Local.cpp
diff -u llvm/lib/Transforms/Utils/Local.cpp:1.52
llvm/lib/Transforms/Utils/Local.cpp:1.53
--- llvm/lib/Transforms/Utils/Local.cpp:1.52Thu Jan 19 17:53:23 2006
+++ llvm/lib/Transforms/Utils/Local.cpp Thu Mar 9 16:38:10 2006
@@ -307,33 +307,11 @@
if (!I-mayWriteToMemory()) return true;
if (CallInst *CI = dyn_castCallInst(I))
-if (Function *F = CI-getCalledFunction())
- switch (F-getIntrinsicID()) {
- default: break;
- case Intrinsic::returnaddress:
- case Intrinsic::frameaddress:
- case Intrinsic::stacksave:
- case Intrinsic::isunordered_f32:
- case Intrinsic::isunordered_f64:
- case Intrinsic::bswap_i16:
- case Intrinsic::bswap_i32:
- case Intrinsic::bswap_i64:
- case Intrinsic::ctpop_i8:
- case Intrinsic::ctpop_i16:
- case Intrinsic::ctpop_i32:
- case Intrinsic::ctpop_i64:
- case Intrinsic::ctlz_i8:
- case Intrinsic::ctlz_i16:
- case Intrinsic::ctlz_i32:
- case Intrinsic::ctlz_i64:
- case Intrinsic::cttz_i8:
- case Intrinsic::cttz_i16:
- case Intrinsic::cttz_i32:
- case Intrinsic::cttz_i64:
- case Intrinsic::sqrt_f32:
- case Intrinsic::sqrt_f64:
-return true; // These intrinsics have no side effects.
- }
+if (Function *F = CI-getCalledFunction()) {
+#define GET_SIDE_EFFECT_INFO
+#include llvm/Intrinsics.gen
+#undef GET_SIDE_EFFECT_INFO
+}
return false;
}
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[llvm-commits] CVS: llvm-test/Makefile.programs
Changes in directory llvm-test: Makefile.programs updated: 1.199 - 1.200 --- Log message: x86 llc-beta sets -enable-x86-lsr to turn on loop strength reduction. --- Diffs of the changes: (+1 -1) Makefile.programs |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.199 llvm-test/Makefile.programs:1.200 --- llvm-test/Makefile.programs:1.199 Thu Mar 9 11:45:02 2006 +++ llvm-test/Makefile.programs Thu Mar 9 20:18:30 2006 @@ -197,7 +197,7 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) -LLCBETAOPTION := -enable-x86-fastcc +LLCBETAOPTION := -enable-x86-lsr endif ifeq ($(ARCH),Sparc) LLCBETAOPTION := -enable-sparc-v9-insts ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGList.cpp updated: 1.32 - 1.33
---
Log message:
Fix VC++ build breakage.
---
Diffs of the changes: (+3 -3)
ScheduleDAGList.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.32
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.33
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.32 Thu Mar 9
11:31:22 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Thu Mar 9 21:57:45 2006
@@ -761,7 +761,7 @@
SethiUllmanNumber = 1;
} else {
int Extra = 0;
-for (std::setSUnit*::iterator I = SU-Preds.begin(),
+for (std::setSUnit*::const_iterator I = SU-Preds.begin(),
E = SU-Preds.end(); I != E; ++I) {
SUnit *PredSU = *I;
int PredSethiUllman = CalcNodePriority(PredSU);
@@ -870,11 +870,11 @@
return Latency;
int MaxSuccLatency = 0;
- for (std::setSUnit*::iterator I = SU.Succs.begin(),
+ for (std::setSUnit*::const_iterator I = SU.Succs.begin(),
E = SU.Succs.end(); I != E; ++I)
MaxSuccLatency = std::max(MaxSuccLatency, CalcLatency(**I));
- for (std::setSUnit*::iterator I = SU.ChainSuccs.begin(),
+ for (std::setSUnit*::const_iterator I = SU.ChainSuccs.begin(),
E = SU.ChainSuccs.end(); I != E; ++I)
MaxSuccLatency = std::max(MaxSuccLatency, CalcLatency(**I));
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[llvm-commits] CVS: llvm/include/llvm/Intrinsics.td
Changes in directory llvm/include/llvm: Intrinsics.td updated: 1.1 - 1.2 --- Log message: Fix an incorrect intrinsic description --- Diffs of the changes: (+3 -2) Intrinsics.td |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) Index: llvm/include/llvm/Intrinsics.td diff -u llvm/include/llvm/Intrinsics.td:1.1 llvm/include/llvm/Intrinsics.td:1.2 --- llvm/include/llvm/Intrinsics.td:1.1 Thu Mar 2 20:33:15 2006 +++ llvm/include/llvm/Intrinsics.td Thu Mar 9 22:17:06 2006 @@ -179,8 +179,9 @@ //=== Debugger Intrinsics -===// // -def int_dbg_stoppoint: Intrinsic[llvm_anchor_ty, llvm_uint_ty, - llvm_uint_ty, llvm_descriptor_ty]; +def int_dbg_stoppoint: Intrinsic[llvm_anchor_ty, llvm_anchor_ty, + llvm_uint_ty, llvm_uint_ty, + llvm_descriptor_ty]; def int_dbg_region_start : Intrinsic[llvm_anchor_ty, llvm_anchor_ty]; def int_dbg_region_end : Intrinsic[llvm_anchor_ty, llvm_anchor_ty]; def int_dbg_func_start : Intrinsic[llvm_anchor_ty, llvm_descriptor_ty]; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGList.cpp updated: 1.34 - 1.35
---
Log message:
Teach the latency scheduler some new tricks. In particular, to break ties,
keep track of a sense of mobility, i.e. how many other nodes scheduling one
node will free up. For something like this:
float testadd(float *X, float *Y, float *Z, float *W, float *V) {
return (*X+*Y)*(*Z+*W)+*V;
}
For example, this makes us schedule *X then *Y, not *X then *Z. The former
allows us to issue the add, the later only lets us issue other loads.
This turns the above code from this:
_testadd:
lfs f0, 0(r3)
lfs f1, 0(r6)
lfs f2, 0(r4)
lfs f3, 0(r5)
fadds f0, f0, f2
fadds f1, f3, f1
lfs f2, 0(r7)
fmadds f1, f0, f1, f2
blr
into this:
_testadd:
lfs f0, 0(r6)
lfs f1, 0(r5)
fadds f0, f1, f0
lfs f1, 0(r4)
lfs f2, 0(r3)
fadds f1, f2, f1
lfs f2, 0(r7)
fmadds f1, f1, f0, f2
blr
---
Diffs of the changes: (+157 -10)
ScheduleDAGList.cpp | 167
1 files changed, 157 insertions(+), 10 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.34
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.35
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.34 Thu Mar 9
22:32:49 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Thu Mar 9 23:51:05 2006
@@ -51,6 +51,8 @@
short NumChainSuccsLeft;// # of chain succs not scheduled.
bool isTwoAddress : 1; // Is a two-address instruction.
bool isDefNUseOperand : 1; // Is a defuse operand.
+bool isAvailable : 1; // True once available.
+bool isScheduled : 1; // True once scheduled.
unsigned short Latency; // Node latency.
unsigned CycleBound;// Upper/lower cycle to be scheduled
at.
unsigned NodeNum; // Entry # of node in the node vector.
@@ -59,6 +61,7 @@
: Node(node), NumPredsLeft(0), NumSuccsLeft(0),
NumChainPredsLeft(0), NumChainSuccsLeft(0),
isTwoAddress(false), isDefNUseOperand(false),
+ isAvailable(false), isScheduled(false),
Latency(0), CycleBound(0), NodeNum(nodenum) {}
void dump(const SelectionDAG *G) const;
@@ -247,8 +250,10 @@
if ((PredSU-NumSuccsLeft + PredSU-NumChainSuccsLeft) == 0) {
// EntryToken has to go last! Special case it here.
-if (PredSU-Node-getOpcode() != ISD::EntryToken)
+if (PredSU-Node-getOpcode() != ISD::EntryToken) {
+ PredSU-isAvailable = true;
PriorityQueue-push(PredSU);
+}
}
}
@@ -275,8 +280,10 @@
}
#endif
- if ((SuccSU-NumPredsLeft + SuccSU-NumChainPredsLeft) == 0)
+ if ((SuccSU-NumPredsLeft + SuccSU-NumChainPredsLeft) == 0) {
+SuccSU-isAvailable = true;
PriorityQueue-push(SuccSU);
+ }
}
/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
@@ -350,8 +357,9 @@
PriorityQueue-push_all(NotReady);
NotReady.clear();
-PriorityQueue-ScheduledNode(CurrNode);
ScheduleNodeBottomUp(CurrNode);
+CurrNode-isScheduled = true;
+PriorityQueue-ScheduledNode(CurrNode);
}
// Add entry node last
@@ -432,9 +440,10 @@
// If we found a node to schedule, do it now.
if (FoundNode) {
- PriorityQueue-ScheduledNode(FoundNode);
ScheduleNodeTopDown(FoundNode);
HazardRec-EmitInstruction(FoundNode-Node);
+ FoundNode-isScheduled = true;
+ PriorityQueue-ScheduledNode(FoundNode);
} else if (!HasNoopHazards) {
// Otherwise, we have a pipeline stall, but no other problem, just
advance
// the current cycle and try again.
@@ -827,7 +836,13 @@
// Latencies - The latency (max of latency from this node to the bb exit)
// for each node.
std::vectorint Latencies;
-
+
+/// NumNodesSolelyBlocking - This vector contains, for every node in the
+/// Queue, the number of nodes that the node is the sole unscheduled
+/// predecessor for. This is used as a tie-breaker heuristic for better
+/// mobility.
+std::vectorunsigned NumNodesSolelyBlocking;
+
std::priority_queueSUnit*, std::vectorSUnit*, latency_sort Queue;
public:
LatencyPriorityQueue() : Queue(latency_sort(this)) {
@@ -848,14 +863,21 @@
return Latencies[NodeNum];
}
+unsigned getNumSolelyBlockNodes(unsigned NodeNum) const {
+ assert(NodeNum NumNodesSolelyBlocking.size());
+ return NumNodesSolelyBlocking[NodeNum];
+}
+
bool empty() const { return Queue.empty(); }
-void push(SUnit *U) {
- Queue.push(U);
+virtual void push(SUnit *U) {
+ push_impl(U);
}
+void push_impl(SUnit *U);
+
void push_all(const std::vectorSUnit * Nodes) {
[llvm-commits] CVS: llvm/include/llvm/CodeGen/ScheduleDAG.h
Changes in directory llvm/include/llvm/CodeGen: ScheduleDAG.h updated: 1.15 - 1.16 --- Log message: make some methods protected instead of private --- Diffs of the changes: (+4 -4) ScheduleDAG.h |8 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/include/llvm/CodeGen/ScheduleDAG.h diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.15 llvm/include/llvm/CodeGen/ScheduleDAG.h:1.16 --- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.15Tue Mar 7 22:24:56 2006 +++ llvm/include/llvm/CodeGen/ScheduleDAG.h Fri Mar 10 00:30:11 2006 @@ -382,16 +382,16 @@ private: void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum, const TargetInstrDescriptor *II); - + +void AddToGroup(NodeInfo *D, NodeInfo *U); +protected: /// PrepareNodeInfo - Set up the basic minimum node info for scheduling. /// void PrepareNodeInfo(); - + /// IdentifyGroups - Put flagged nodes into groups. /// void IdentifyGroups(); - -void AddToGroup(NodeInfo *D, NodeInfo *U); }; /// createSimpleDAGScheduler - This creates a simple two pass instruction ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/ScheduleDAG.h
Changes in directory llvm/include/llvm/CodeGen:
ScheduleDAG.h updated: 1.16 - 1.17
---
Log message:
Store VRBase in a map, not in NodeInfo.
---
Diffs of the changes: (+5 -12)
ScheduleDAG.h | 17 +
1 files changed, 5 insertions(+), 12 deletions(-)
Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.16
llvm/include/llvm/CodeGen/ScheduleDAG.h:1.17
--- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.16Fri Mar 10 00:30:11 2006
+++ llvm/include/llvm/CodeGen/ScheduleDAG.h Fri Mar 10 01:24:45 2006
@@ -151,7 +151,6 @@
bool IsStore : 1;// Is memory store
unsigned Slot; // Node's time slot
NodeGroup *Group; // Grouping information
-unsigned VRBase; // Virtual register base
#ifndef NDEBUG
unsigned Preorder; // Index before scheduling
#endif
@@ -166,7 +165,6 @@
, IsCall(false)
, Slot(0)
, Group(NULL)
- , VRBase(0)
#ifndef NDEBUG
, Preorder(0)
#endif
@@ -326,14 +324,6 @@
///
NodeInfo *getNI(SDNode *Node) { return Map[Node]; }
-/// getVR - Returns the virtual register number of the node.
-///
-unsigned getVR(SDOperand Op) {
- NodeInfo *NI = getNI(Op.Val);
- assert(NI-VRBase != 0 Node emitted out of order - late);
- return NI-VRBase + Op.ResNo;
-}
-
/// isPassiveNode - Return true if the node is a non-scheduled leaf.
///
static bool isPassiveNode(SDNode *Node) {
@@ -348,8 +338,10 @@
}
/// EmitNode - Generate machine code for an node and needed dependencies.
+/// VRBaseMap contains, for each already emitted node, the first virtual
+/// register number for the results of the node.
///
-void EmitNode(NodeInfo *NI);
+void EmitNode(NodeInfo *NI, std::mapSDNode*, unsigned VRBaseMap);
/// EmitNoop - Emit a noop instruction.
///
@@ -381,7 +373,8 @@
private:
void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
-const TargetInstrDescriptor *II);
+const TargetInstrDescriptor *II,
+std::mapSDNode*, unsigned VRBaseMap);
void AddToGroup(NodeInfo *D, NodeInfo *U);
protected:
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.74 - 1.75
ScheduleDAGList.cpp updated: 1.38 - 1.39
---
Log message:
Move the VRBase field from NodeInfo to being a separate, explicit, map.
---
Diffs of the changes: (+27 -13)
ScheduleDAG.cpp | 35 ---
ScheduleDAGList.cpp |5 +++--
2 files changed, 27 insertions(+), 13 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.74
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.75
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.74 Fri Mar 10 00:34:51 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Fri Mar 10 01:25:12 2006
@@ -110,13 +110,23 @@
return ResultReg;
}
+/// getVR - Return the virtual register corresponding to the specified result
+/// of the specified node.
+static unsigned getVR(SDOperand Op, std::mapSDNode*, unsigned VRBaseMap) {
+ std::mapSDNode*, unsigned::iterator I = VRBaseMap.find(Op.Val);
+ assert(I != VRBaseMap.end() Node emitted out of order - late);
+ return I-second + Op.ResNo;
+}
+
+
/// AddOperand - Add the specified operand to the specified machine instr. II
/// specifies the instruction information for the node, and IIOpNum is the
/// operand number (in the II) that we are adding. IIOpNum and II are used for
/// assertions only.
void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
unsigned IIOpNum,
- const TargetInstrDescriptor *II) {
+ const TargetInstrDescriptor *II,
+ std::mapSDNode*, unsigned VRBaseMap) {
if (Op.isTargetOpcode()) {
// Note that this case is redundant with the final else block, but we
// include it because it is the most common and it makes the logic
@@ -126,7 +136,7 @@
Chain and flag operands should occur at end of operand list!);
// Get/emit the operand.
-unsigned VReg = getVR(Op);
+unsigned VReg = getVR(Op, VRBaseMap);
MI-addRegOperand(VReg, MachineOperand::Use);
// Verify that it is right.
@@ -174,7 +184,7 @@
assert(Op.getValueType() != MVT::Other
Op.getValueType() != MVT::Flag
Chain and flag operands should occur at end of operand list!);
-unsigned VReg = getVR(Op);
+unsigned VReg = getVR(Op, VRBaseMap);
MI-addRegOperand(VReg, MachineOperand::Use);
// Verify that it is right.
@@ -192,7 +202,8 @@
/// EmitNode - Generate machine code for an node and needed dependencies.
///
-void ScheduleDAG::EmitNode(NodeInfo *NI) {
+void ScheduleDAG::EmitNode(NodeInfo *NI,
+ std::mapSDNode*, unsigned VRBaseMap) {
unsigned VRBase = 0; // First virtual register for node
SDNode *Node = NI-Node;
@@ -240,7 +251,7 @@
// Emit all of the actual operands of this instruction, adding them to the
// instruction as appropriate.
for (unsigned i = 0; i != NodeOperands; ++i)
- AddOperand(MI, Node-getOperand(i), i+NumResults, II);
+ AddOperand(MI, Node-getOperand(i), i+NumResults, II, VRBaseMap);
// Now that we have emitted all operands, emit this instruction itself.
if ((II.Flags M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
@@ -259,7 +270,7 @@
case ISD::TokenFactor:
break;
case ISD::CopyToReg: {
- unsigned InReg = getVR(Node-getOperand(2));
+ unsigned InReg = getVR(Node-getOperand(2), VRBaseMap);
unsigned DestReg = castRegisterSDNode(Node-getOperand(1))-getReg();
if (InReg != DestReg) // Coallesced away the copy?
MRI-copyRegToReg(*BB, BB-end(), DestReg, InReg,
@@ -357,7 +368,7 @@
// The addressing mode has been selected, just add all of the
// operands to the machine instruction.
for (; NumVals; --NumVals, ++i)
-AddOperand(MI, Node-getOperand(i), 0, 0);
+AddOperand(MI, Node-getOperand(i), 0, 0, VRBaseMap);
break;
}
}
@@ -366,8 +377,8 @@
}
}
- assert(NI-VRBase == 0 Node emitted out of order - early);
- NI-VRBase = VRBase;
+ assert(!VRBaseMap.count(Node) Node emitted out of order - early);
+ VRBaseMap[Node] = VRBase;
}
void ScheduleDAG::EmitNoop() {
@@ -377,15 +388,17 @@
/// EmitAll - Emit all nodes in schedule sorted order.
///
void ScheduleDAG::EmitAll() {
+ std::mapSDNode*, unsigned VRBaseMap;
+
// For each node in the ordering
for (unsigned i = 0, N = Ordering.size(); i N; i++) {
// Get the scheduling info
NodeInfo *NI = Ordering[i];
if (NI-isInGroup()) {
NodeGroupIterator NGI(Ordering[i]);
- while (NodeInfo *NI = NGI.next()) EmitNode(NI);
+ while (NodeInfo *NI = NGI.next()) EmitNode(NI, VRBaseMap);
} else {
- EmitNode(NI);
+ EmitNode(NI, VRBaseMap);
}
}
}
Index:
[llvm-commits] CVS: llvm/include/llvm/CodeGen/ScheduleDAG.h
Changes in directory llvm/include/llvm/CodeGen: ScheduleDAG.h updated: 1.17 - 1.18 --- Log message: Make EmitNode take a SDNode instead of a NodeInfo* --- Diffs of the changes: (+1 -1) ScheduleDAG.h |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/CodeGen/ScheduleDAG.h diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.17 llvm/include/llvm/CodeGen/ScheduleDAG.h:1.18 --- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.17Fri Mar 10 01:24:45 2006 +++ llvm/include/llvm/CodeGen/ScheduleDAG.h Fri Mar 10 01:28:21 2006 @@ -341,7 +341,7 @@ /// VRBaseMap contains, for each already emitted node, the first virtual /// register number for the results of the node. /// -void EmitNode(NodeInfo *NI, std::mapSDNode*, unsigned VRBaseMap); +void EmitNode(SDNode *Node, std::mapSDNode*, unsigned VRBaseMap); /// EmitNoop - Emit a noop instruction. /// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.75 - 1.76
ScheduleDAGList.cpp updated: 1.39 - 1.40
---
Log message:
Make EmitNode take a SDNode instead of a NodeInfo*
---
Diffs of the changes: (+6 -12)
ScheduleDAG.cpp |7 +++
ScheduleDAGList.cpp | 11 +++
2 files changed, 6 insertions(+), 12 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.75
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.76
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.75 Fri Mar 10 01:25:12 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Fri Mar 10 01:28:36 2006
@@ -202,10 +202,9 @@
/// EmitNode - Generate machine code for an node and needed dependencies.
///
-void ScheduleDAG::EmitNode(NodeInfo *NI,
+void ScheduleDAG::EmitNode(SDNode *Node,
std::mapSDNode*, unsigned VRBaseMap) {
unsigned VRBase = 0; // First virtual register for node
- SDNode *Node = NI-Node;
// If machine instruction
if (Node-isTargetOpcode()) {
@@ -396,9 +395,9 @@
NodeInfo *NI = Ordering[i];
if (NI-isInGroup()) {
NodeGroupIterator NGI(Ordering[i]);
- while (NodeInfo *NI = NGI.next()) EmitNode(NI, VRBaseMap);
+ while (NodeInfo *NI = NGI.next()) EmitNode(NI-Node, VRBaseMap);
} else {
- EmitNode(NI, VRBaseMap);
+ EmitNode(NI-Node, VRBaseMap);
}
}
}
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.39
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.40
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.39 Fri Mar 10
01:25:12 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Fri Mar 10 01:28:36 2006
@@ -613,11 +613,9 @@
std::mapSDNode*, unsigned VRBaseMap;
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
if (SUnit *SU = Sequence[i]) {
- for (unsigned j = 0, ee = SU-FlaggedNodes.size(); j != ee; j++) {
-SDNode *N = SU-FlaggedNodes[j];
-EmitNode(getNI(N), VRBaseMap);
- }
- EmitNode(getNI(SU-Node), VRBaseMap);
+ for (unsigned j = 0, ee = SU-FlaggedNodes.size(); j != ee; j++)
+EmitNode(SU-FlaggedNodes[j], VRBaseMap);
+ EmitNode(SU-Node, VRBaseMap);
} else {
// Null SUnit* is a noop.
EmitNoop();
@@ -641,9 +639,6 @@
void ScheduleDAGList::Schedule() {
DEBUG(std::cerr ** List Scheduling **\n);
- // Set up minimum info for scheduling
- PrepareNodeInfo();
-
// Build scheduling units.
BuildSchedUnits();
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp ScheduleDAGSimple.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.76 - 1.77
ScheduleDAGSimple.cpp updated: 1.7 - 1.8
---
Log message:
move some simple scheduler methods into the simple scheduler
---
Diffs of the changes: (+266 -235)
ScheduleDAG.cpp | 235
ScheduleDAGSimple.cpp | 266 ++
2 files changed, 266 insertions(+), 235 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.76
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.77
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.76 Fri Mar 10 01:28:36 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Fri Mar 10 01:35:21 2006
@@ -52,47 +52,6 @@
return N;
}
-/// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
-///
-void ScheduleDAG::PrepareNodeInfo() {
- // Allocate node information
- Info = new NodeInfo[NodeCount];
-
- unsigned i = 0;
- for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
- E = DAG.allnodes_end(); I != E; ++I, ++i) {
-// Fast reference to node schedule info
-NodeInfo* NI = Info[i];
-// Set up map
-Map[I] = NI;
-// Set node
-NI-Node = I;
-// Set pending visit count
-NI-setPending(I-use_size());
- }
-}
-
-/// IdentifyGroups - Put flagged nodes into groups.
-///
-void ScheduleDAG::IdentifyGroups() {
- for (unsigned i = 0, N = NodeCount; i N; i++) {
-NodeInfo* NI = Info[i];
-SDNode *Node = NI-Node;
-
-// For each operand (in reverse to only look at flags)
-for (unsigned N = Node-getNumOperands(); 0 N--;) {
- // Get operand
- SDOperand Op = Node-getOperand(N);
- // No more flags to walk
- if (Op.getValueType() != MVT::Flag) break;
- // Add to node group
- AddToGroup(getNI(Op.Val), NI);
- // Let everyone else know
- HasGroups = true;
-}
- }
-}
-
static unsigned CreateVirtualRegisters(MachineInstr *MI,
unsigned NumResults,
SSARegMap *RegMap,
@@ -384,122 +343,6 @@
TII-insertNoop(*BB, BB-end());
}
-/// EmitAll - Emit all nodes in schedule sorted order.
-///
-void ScheduleDAG::EmitAll() {
- std::mapSDNode*, unsigned VRBaseMap;
-
- // For each node in the ordering
- for (unsigned i = 0, N = Ordering.size(); i N; i++) {
-// Get the scheduling info
-NodeInfo *NI = Ordering[i];
-if (NI-isInGroup()) {
- NodeGroupIterator NGI(Ordering[i]);
- while (NodeInfo *NI = NGI.next()) EmitNode(NI-Node, VRBaseMap);
-} else {
- EmitNode(NI-Node, VRBaseMap);
-}
- }
-}
-
-/// isFlagDefiner - Returns true if the node defines a flag result.
-static bool isFlagDefiner(SDNode *A) {
- unsigned N = A-getNumValues();
- return N A-getValueType(N - 1) == MVT::Flag;
-}
-
-/// isFlagUser - Returns true if the node uses a flag result.
-///
-static bool isFlagUser(SDNode *A) {
- unsigned N = A-getNumOperands();
- return N A-getOperand(N - 1).getValueType() == MVT::Flag;
-}
-
-/// printNI - Print node info.
-///
-void ScheduleDAG::printNI(std::ostream O, NodeInfo *NI) const {
-#ifndef NDEBUG
- SDNode *Node = NI-Node;
- O
- std::hex Node std::dec
- , Lat= NI-Latency
- , Slot= NI-Slot
- , ARITY=( Node-getNumOperands() ,
-Node-getNumValues() )
-Node-getOperationName(DAG);
- if (isFlagDefiner(Node)) O #;
- if (isFlagUser(Node)) O #;
-#endif
-}
-
-/// printChanges - Hilight changes in order caused by scheduling.
-///
-void ScheduleDAG::printChanges(unsigned Index) const {
-#ifndef NDEBUG
- // Get the ordered node count
- unsigned N = Ordering.size();
- // Determine if any changes
- unsigned i = 0;
- for (; i N; i++) {
-NodeInfo *NI = Ordering[i];
-if (NI-Preorder != i) break;
- }
-
- if (i N) {
-std::cerr Index . New Ordering\n;
-
-for (i = 0; i N; i++) {
- NodeInfo *NI = Ordering[i];
- std::cerr NI-Preorder . ;
- printNI(std::cerr, NI);
- std::cerr \n;
- if (NI-isGroupDominator()) {
-NodeGroup *Group = NI-Group;
-for (NIIterator NII = Group-group_begin(), E = Group-group_end();
- NII != E; NII++) {
- std::cerr;
- printNI(std::cerr, *NII);
- std::cerr \n;
-}
- }
-}
- } else {
-std::cerr Index . No Changes\n;
- }
-#endif
-}
-
-/// print - Print ordering to specified output stream.
-///
-void ScheduleDAG::print(std::ostream O) const {
-#ifndef NDEBUG
- using namespace std;
- O Ordering\n;
- for (unsigned i = 0, N = Ordering.size(); i N; i++) {
-NodeInfo *NI = Ordering[i];
-printNI(O, NI);
-O \n;
-if (NI-isGroupDominator()) {
- NodeGroup *Group = NI-Group;
- for (NIIterator NII = Group-group_begin(), E = Group-group_end();
- NII != E; NII++) {
-O
[llvm-commits] CVS: llvm/include/llvm/CodeGen/ScheduleDAG.h
Changes in directory llvm/include/llvm/CodeGen:
ScheduleDAG.h updated: 1.19 - 1.20
---
Log message:
Move some simple-sched-specific instance vars to the simple scheduler.
---
Diffs of the changes: (+2 -23)
ScheduleDAG.h | 25 ++---
1 files changed, 2 insertions(+), 23 deletions(-)
Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.19
llvm/include/llvm/CodeGen/ScheduleDAG.h:1.20
--- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.19Fri Mar 10 01:35:10 2006
+++ llvm/include/llvm/CodeGen/ScheduleDAG.h Fri Mar 10 01:41:52 2006
@@ -284,7 +284,6 @@
class ScheduleDAG {
public:
-SchedHeuristics Heuristic;// Scheduling heuristic
SelectionDAG DAG;// DAG of the current basic block
MachineBasicBlock *BB;// Current basic block
const TargetMachine TM; // Target processor
@@ -292,38 +291,18 @@
const MRegisterInfo *MRI; // Target processor register info
SSARegMap *RegMap;// Virtual/real register map
MachineConstantPool *ConstPool; // Target constant pool
-std::mapSDNode *, NodeInfo * Map; // Map nodes to info
-unsigned NodeCount; // Number of nodes in DAG
-bool HasGroups; // True if there are any groups
-NodeInfo *Info; // Info for nodes being scheduled
-NIVector Ordering;// Emit ordering of nodes
-NodeGroup *HeadNG, *TailNG; // Keep track of allocated NodeGroups
-ScheduleDAG(SchedHeuristics hstc, SelectionDAG dag, MachineBasicBlock *bb,
+ScheduleDAG(SelectionDAG dag, MachineBasicBlock *bb,
const TargetMachine tm)
- : Heuristic(hstc), DAG(dag), BB(bb), TM(tm), NodeCount(0),
-HasGroups(false), Info(NULL), HeadNG(NULL), TailNG(NULL) {}
+ : DAG(dag), BB(bb), TM(tm) {}
virtual ~ScheduleDAG() {
- if (Info)
-delete[] Info;
-
- NodeGroup *NG = HeadNG;
- while (NG) {
-NodeGroup *NextSU = NG-Next;
-delete NG;
-NG = NextSU;
- }
};
/// Run - perform scheduling.
///
MachineBasicBlock *Run();
-/// getNI - Returns the node info for the specified node.
-///
-NodeInfo *getNI(SDNode *Node) { return Map[Node]; }
-
/// isPassiveNode - Return true if the node is a non-scheduled leaf.
///
static bool isPassiveNode(SDNode *Node) {
___
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/ScheduleDAG.h
Changes in directory llvm/include/llvm/CodeGen:
ScheduleDAG.h updated: 1.20 - 1.21
---
Log message:
Simplify the interface to the schedulers, to not pass the selected heuristic
in.
---
Diffs of the changes: (+4 -14)
ScheduleDAG.h | 18 --
1 files changed, 4 insertions(+), 14 deletions(-)
Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.20
llvm/include/llvm/CodeGen/ScheduleDAG.h:1.21
--- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.20Fri Mar 10 01:41:52 2006
+++ llvm/include/llvm/CodeGen/ScheduleDAG.h Fri Mar 10 01:48:52 2006
@@ -34,16 +34,6 @@
typedef std::vectorNodeInfoPtr NIVector;
typedef std::vectorNodeInfoPtr::iterator NIIterator;
- // Scheduling heuristics
- enum SchedHeuristics {
-defaultScheduling, // Let the target specify its preference.
-noScheduling, // No scheduling, emit breadth first sequence.
-simpleScheduling, // Two pass, min. critical path, max. utilization.
-simpleNoItinScheduling, // Same as above exact using generic latency.
-listSchedulingBURR, // Bottom up reg reduction list scheduling.
-listSchedulingTD// Top-down list scheduler.
- };
-
/// HazardRecognizer - This determines whether or not an instruction can be
/// issued this cycle, and whether or not a noop needs to be inserted to
handle
/// the hazard.
@@ -296,8 +286,7 @@
const TargetMachine tm)
: DAG(dag), BB(bb), TM(tm) {}
-virtual ~ScheduleDAG() {
-};
+virtual ~ScheduleDAG() {}
/// Run - perform scheduling.
///
@@ -337,10 +326,11 @@
std::mapSDNode*, unsigned VRBaseMap);
};
+ ScheduleDAG *createBFS_DAGScheduler(SelectionDAG DAG, MachineBasicBlock
*BB);
+
/// createSimpleDAGScheduler - This creates a simple two pass instruction
/// scheduler.
- ScheduleDAG* createSimpleDAGScheduler(SchedHeuristics Heuristic,
-SelectionDAG DAG,
+ ScheduleDAG* createSimpleDAGScheduler(bool NoItins, SelectionDAG DAG,
MachineBasicBlock *BB);
/// createBURRListDAGScheduler - This creates a bottom up register usage
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGSimple.cpp updated: 1.10 - 1.11
---
Log message:
Move simple-selector-specific types to the simple selector.
---
Diffs of the changes: (+202 -0)
ScheduleDAGSimple.cpp | 202 ++
1 files changed, 202 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.10
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.11
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.10Fri Mar 10
01:49:12 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp Fri Mar 10 01:51:18 2006
@@ -24,6 +24,208 @@
using namespace llvm;
namespace {
+class NodeInfo;
+typedef NodeInfo *NodeInfoPtr;
+typedef std::vectorNodeInfoPtr NIVector;
+typedef std::vectorNodeInfoPtr::iterator NIIterator;
+
+//======//
+///
+/// Node group - This struct is used to manage flagged node groups.
+///
+class NodeGroup {
+public:
+ NodeGroup *Next;
+private:
+ NIVector Members;// Group member nodes
+ NodeInfo *Dominator; // Node with highest latency
+ unsigned Latency;// Total latency of the group
+ int Pending;// Number of visits pending before
+// adding to order
+
+public:
+ // Ctor.
+ NodeGroup() : Next(NULL), Dominator(NULL), Pending(0) {}
+
+ // Accessors
+ inline void setDominator(NodeInfo *D) { Dominator = D; }
+ inline NodeInfo *getTop() { return Members.front(); }
+ inline NodeInfo *getBottom() { return Members.back(); }
+ inline NodeInfo *getDominator() { return Dominator; }
+ inline void setLatency(unsigned L) { Latency = L; }
+ inline unsigned getLatency() { return Latency; }
+ inline int getPending() const { return Pending; }
+ inline void setPending(int P) { Pending = P; }
+ inline int addPending(int I) { return Pending += I; }
+
+ // Pass thru
+ inline bool group_empty() { return Members.empty(); }
+ inline NIIterator group_begin() { return Members.begin(); }
+ inline NIIterator group_end() { return Members.end(); }
+ inline void group_push_back(const NodeInfoPtr NI) {
+Members.push_back(NI);
+ }
+ inline NIIterator group_insert(NIIterator Pos, const NodeInfoPtr NI) {
+return Members.insert(Pos, NI);
+ }
+ inline void group_insert(NIIterator Pos, NIIterator First,
+ NIIterator Last) {
+Members.insert(Pos, First, Last);
+ }
+
+ static void Add(NodeInfo *D, NodeInfo *U);
+};
+
+//======//
+///
+/// NodeInfo - This struct tracks information used to schedule the a node.
+///
+class NodeInfo {
+private:
+ int Pending;// Number of visits pending before
+// adding to order
+public:
+ SDNode*Node; // DAG node
+ InstrStage*StageBegin;// First stage in itinerary
+ InstrStage*StageEnd; // Last+1 stage in itinerary
+ unsigned Latency;// Total cycles to complete instr
+ bool IsCall : 1; // Is function call
+ bool IsLoad : 1; // Is memory load
+ bool IsStore : 1;// Is memory store
+ unsigned Slot; // Node's time slot
+ NodeGroup *Group; // Grouping information
+#ifndef NDEBUG
+ unsigned Preorder; // Index before scheduling
+#endif
+
+ // Ctor.
+ NodeInfo(SDNode *N = NULL)
+: Pending(0)
+, Node(N)
+, StageBegin(NULL)
+, StageEnd(NULL)
+, Latency(0)
+, IsCall(false)
+, Slot(0)
+, Group(NULL)
+#ifndef NDEBUG
+, Preorder(0)
+#endif
+ {}
+
+ // Accessors
+ inline bool isInGroup() const {
+assert(!Group || !Group-group_empty() Group with no members);
+return Group != NULL;
+ }
+ inline bool isGroupDominator() const {
+return isInGroup() Group-getDominator() == this;
+ }
+ inline int getPending() const {
+return Group ? Group-getPending() : Pending;
+ }
+ inline void setPending(int P) {
+if (Group) Group-setPending(P);
+else Pending = P;
+ }
+ inline int addPending(int I) {
+if (Group) return Group-addPending(I);
+else return Pending += I;
+ }
+};
+
+//======//
+///
+/// NodeGroupIterator - Iterates over all the nodes indicated by the node
+/// info. If the node is in a group then iterate over the members of the
+/// group, otherwise just the node info.
+///
+class NodeGroupIterator {
+private:
+ NodeInfo *NI; // Node info
+ NIIterator NGI; // Node group iterator
+ NIIterator NGE; // Node group
[llvm-commits] CVS: llvm/include/llvm/CodeGen/ScheduleDAG.h
Changes in directory llvm/include/llvm/CodeGen:
ScheduleDAG.h updated: 1.21 - 1.22
---
Log message:
Move simple-selector-specific types to the simple selector.
---
Diffs of the changes: (+0 -201)
ScheduleDAG.h | 201 --
1 files changed, 201 deletions(-)
Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.21
llvm/include/llvm/CodeGen/ScheduleDAG.h:1.22
--- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.21Fri Mar 10 01:48:52 2006
+++ llvm/include/llvm/CodeGen/ScheduleDAG.h Fri Mar 10 01:51:12 2006
@@ -29,11 +29,6 @@
class TargetInstrDescriptor;
class TargetMachine;
- class NodeInfo;
- typedef NodeInfo *NodeInfoPtr;
- typedef std::vectorNodeInfoPtr NIVector;
- typedef std::vectorNodeInfoPtr::iterator NIIterator;
-
/// HazardRecognizer - This determines whether or not an instruction can be
/// issued this cycle, and whether or not a noop needs to be inserted to
handle
/// the hazard.
@@ -75,203 +70,7 @@
virtual void EmitNoop() {
}
};
-
-
//======//
- ///
- /// Node group - This struct is used to manage flagged node groups.
- ///
- class NodeGroup {
- public:
-NodeGroup *Next;
- private:
-NIVector Members;// Group member nodes
-NodeInfo *Dominator; // Node with highest latency
-unsigned Latency;// Total latency of the group
-int Pending;// Number of visits pending before
- // adding to order
-
- public:
-// Ctor.
-NodeGroup() : Next(NULL), Dominator(NULL), Pending(0) {}
-
-// Accessors
-inline void setDominator(NodeInfo *D) { Dominator = D; }
-inline NodeInfo *getTop() { return Members.front(); }
-inline NodeInfo *getBottom() { return Members.back(); }
-inline NodeInfo *getDominator() { return Dominator; }
-inline void setLatency(unsigned L) { Latency = L; }
-inline unsigned getLatency() { return Latency; }
-inline int getPending() const { return Pending; }
-inline void setPending(int P) { Pending = P; }
-inline int addPending(int I) { return Pending += I; }
-
-// Pass thru
-inline bool group_empty() { return Members.empty(); }
-inline NIIterator group_begin() { return Members.begin(); }
-inline NIIterator group_end() { return Members.end(); }
-inline void group_push_back(const NodeInfoPtr NI) {
- Members.push_back(NI);
-}
-inline NIIterator group_insert(NIIterator Pos, const NodeInfoPtr NI) {
- return Members.insert(Pos, NI);
-}
-inline void group_insert(NIIterator Pos, NIIterator First,
- NIIterator Last) {
- Members.insert(Pos, First, Last);
-}
-
-static void Add(NodeInfo *D, NodeInfo *U);
- };
-
-
//======//
- ///
- /// NodeInfo - This struct tracks information used to schedule the a node.
- ///
- class NodeInfo {
- private:
-int Pending;// Number of visits pending before
- // adding to order
- public:
-SDNode*Node; // DAG node
-InstrStage*StageBegin;// First stage in itinerary
-InstrStage*StageEnd; // Last+1 stage in itinerary
-unsigned Latency;// Total cycles to complete instr
-bool IsCall : 1; // Is function call
-bool IsLoad : 1; // Is memory load
-bool IsStore : 1;// Is memory store
-unsigned Slot; // Node's time slot
-NodeGroup *Group; // Grouping information
-#ifndef NDEBUG
-unsigned Preorder; // Index before scheduling
-#endif
-
-// Ctor.
-NodeInfo(SDNode *N = NULL)
- : Pending(0)
- , Node(N)
- , StageBegin(NULL)
- , StageEnd(NULL)
- , Latency(0)
- , IsCall(false)
- , Slot(0)
- , Group(NULL)
-#ifndef NDEBUG
- , Preorder(0)
-#endif
-{}
-
-// Accessors
-inline bool isInGroup() const {
- assert(!Group || !Group-group_empty() Group with no members);
- return Group != NULL;
-}
-inline bool isGroupDominator() const {
- return isInGroup() Group-getDominator() == this;
-}
-inline int getPending() const {
- return Group ? Group-getPending() : Pending;
-}
-inline void setPending(int P) {
- if (Group) Group-setPending(P);
- else Pending = P;
-}
-inline int addPending(int I) {
- if (Group) return Group-addPending(I);
- else return Pending += I;
-}
- };
-
-
//======//
- ///
-
