[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td

2006-03-28 Thread Evan Cheng 


Changes in directory llvm/include/llvm:

IntrinsicsX86.td updated: 1.2 -> 1.3
---
Log message:

Add more SSE intrinsics

---
Diffs of the changes:  (+118 -94)

 IntrinsicsX86.td |  212 ++-
 1 files changed, 118 insertions(+), 94 deletions(-)


Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.2 
llvm/include/llvm/IntrinsicsX86.td:1.3
--- llvm/include/llvm/IntrinsicsX86.td:1.2  Mon Mar 27 02:23:12 2006
+++ llvm/include/llvm/IntrinsicsX86.td  Wed Mar 29 00:07:16 2006
@@ -18,73 +18,45 @@
 // Arithmetic ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse_add_ss : GCCBuiltin<"__builtin_ia32_addss">,
-  Intrinsic<[llvm_float_ty, llvm_float_ty,
- llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_add_ps : GCCBuiltin<"__builtin_ia32_addps">,
   Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
  llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_sub_ss : GCCBuiltin<"__builtin_ia32_subss">,
-  Intrinsic<[llvm_float_ty, llvm_float_ty,
- llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_sub_ps : GCCBuiltin<"__builtin_ia32_subps">,
   Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
  llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_mul_ss : GCCBuiltin<"__builtin_ia32_mulss">,
-  Intrinsic<[llvm_float_ty, llvm_float_ty,
- llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_mul_ps : GCCBuiltin<"__builtin_ia32_mulps">,
   Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
  llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_div_ss : GCCBuiltin<"__builtin_ia32_divss">,
-  Intrinsic<[llvm_float_ty, llvm_float_ty,
- llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_div_ps : GCCBuiltin<"__builtin_ia32_divps">,
   Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
  llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_sqrt_ss : GCCBuiltin<"__builtin_ia32_sqrtss">,
-  Intrinsic<[llvm_float_ty, llvm_float_ty,
- llvm_float_ty], [InstrNoMem]>;
+  Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
+[InstrNoMem]>;
   def int_x86_sse_sqrt_ps : GCCBuiltin<"__builtin_ia32_sqrtps">,
-  Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
- llvm_v4f32_ty], [InstrNoMem]>;
+  Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
+[InstrNoMem]>;
   def int_x86_sse_rcp_ss : GCCBuiltin<"__builtin_ia32_rcpss">,
-  Intrinsic<[llvm_float_ty, llvm_float_ty,
- llvm_float_ty], [InstrNoMem]>;
+  Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
+[InstrNoMem]>;
   def int_x86_sse_rcp_ps : GCCBuiltin<"__builtin_ia32_rcpps">,
-  Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
- llvm_v4f32_ty], [InstrNoMem]>;
+  Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
+[InstrNoMem]>;
   def int_x86_sse_rsqrt_ss : GCCBuiltin<"__builtin_ia32_rsqrtss">,
-  Intrinsic<[llvm_float_ty, llvm_float_ty,
- llvm_float_ty], [InstrNoMem]>;
+  Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
+[InstrNoMem]>;
   def int_x86_sse_rsqrt_ps : GCCBuiltin<"__builtin_ia32_rsqrtps">,
+  Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
+[InstrNoMem]>;
+  def int_x86_sse_min_ss : GCCBuiltin<"__builtin_ia32_minss">,
   Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
  llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_min_ss : GCCBuiltin<"__builtin_ia32_minss">,
-  Intrinsic<[llvm_float_ty, llvm_float_ty,
- llvm_float_ty], [InstrNoMem]>;
   def int_x86_sse_min_ps : GCCBuiltin<"__builtin_ia32_minps">,
   Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
  llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_max_ss : GCCBuiltin<"__builtin_ia32_maxss">,
-  Intrinsic<[llvm_float_ty, llvm_float_ty,
- llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_max_ps : GCCBuiltin<"__builtin_ia32_maxps">,
   Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
  llvm_v4f32_ty], [InstrNoMem]>;
-}
-
-// Logical ops
-let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
-  def int_x86_sse_and_ps : GCCBuiltin<"__builtin_ia32_andps">,
-  Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
- llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_andnot_ps : GCCBuiltin<"__builtin_ia32_andnotps">,
-  Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
- llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_or_

[llvm-commits] CVS: llvm/lib/Target/X86/README.txt

2006-03-28 Thread Evan Cheng 


Changes in directory llvm/lib/Target/X86:

README.txt updated: 1.77 -> 1.78
---
Log message:

Another entry about shuffles.


---
Diffs of the changes:  (+6 -0)

 README.txt |6 ++
 1 files changed, 6 insertions(+)


Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.77 llvm/lib/Target/X86/README.txt:1.78
--- llvm/lib/Target/X86/README.txt:1.77 Tue Mar 28 00:55:45 2006
+++ llvm/lib/Target/X86/README.txt  Tue Mar 28 21:03:46 2006
@@ -667,3 +667,9 @@
 
 Use movhps to update upper 64-bits of a v4sf value. Also movlps on lower half
 of a v4sf value.
+
+//===-===//
+
+Better codegen for vector_shuffles like this { x, 0, 0, 0 } or { x, 0, x, 0}.
+Perhaps use pxor / xorp* to clear a XMM register first?
+



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrSSE.td

2006-03-28 Thread Evan Cheng 


Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.142 -> 1.143
X86InstrSSE.td updated: 1.41 -> 1.42
---
Log message:

- More shuffle related bug fixes.
- Whenever possible use ops of the right packed types for vector shuffles /
  splats.


---
Diffs of the changes:  (+30 -47)

 X86ISelLowering.cpp |   35 +--
 X86InstrSSE.td  |   42 +-
 2 files changed, 30 insertions(+), 47 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.142 
llvm/lib/Target/X86/X86ISelLowering.cpp:1.143
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.142   Tue Mar 28 19:30:51 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 28 21:04:49 2006
@@ -2403,43 +2403,18 @@
   return SDOperand();
 
 // PSHUFD's 2nd vector must be undef.
-if (MVT::isInteger(VT) && X86::isPSHUFDMask(PermMask.Val))
-  if (V2.getOpcode() == ISD::UNDEF)
-return SDOperand();
-  else
+if (MVT::isInteger(VT) && X86::isPSHUFDMask(PermMask.Val)) {
+  if (V2.getOpcode() != ISD::UNDEF)
 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
-   DAG.getNode(ISD::UNDEF, V1.getValueType()),
-   PermMask);
+   DAG.getNode(ISD::UNDEF, 
V1.getValueType()),PermMask);
+  return SDOperand();
+}
 
 if (NumElems == 2 ||
 X86::isSplatMask(PermMask.Val) ||
 X86::isSHUFPMask(PermMask.Val)) {
   return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG);
 }
-#if 0
-else if (X86::isSplatMask(PermMask.Val)) {
-  // Handle splat cases.
-  if (V2.getOpcode() == ISD::UNDEF)
-// Leave the VECTOR_SHUFFLE alone. It matches SHUFP*.
-return SDOperand();
-  else
-// Make it match SHUFP* or UNPCKLPD. Second vector is undef since it's
-// not needed.
-return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
-   DAG.getNode(ISD::UNDEF, V1.getValueType()),
-   PermMask);
-} else if (X86::isPSHUFDMask(PermMask.Val)) {
-  if (V2.getOpcode() == ISD::UNDEF)
-// Leave the VECTOR_SHUFFLE alone. It matches PSHUFD.
-return SDOperand();
-  else
-// Make it match PSHUFD. Second vector is undef since it's not needed.
-return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
-   DAG.getNode(ISD::UNDEF, V1.getValueType()),
-   PermMask);
-} else if (X86::isSHUFPMask(PermMask.Val))
-  return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG);
-#endif
 
 assert(0 && "Unexpected VECTOR_SHUFFLE to lower");
 abort();


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.41 
llvm/lib/Target/X86/X86InstrSSE.td:1.42
--- llvm/lib/Target/X86/X86InstrSSE.td:1.41 Tue Mar 28 19:30:51 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td  Tue Mar 28 21:04:49 2006
@@ -55,11 +55,7 @@
   return getI8Imm(X86::getShuffleSHUFImmediate(N));
 }]>;
 
-def SHUFP_splat_mask : PatLeaf<(build_vector), [{
-  return X86::isSplatMask(N);
-}], SHUFFLE_get_shuf_imm>;
-
-def MOVLHPS_splat_mask : PatLeaf<(build_vector), [{
+def v2f64_v2i64_splat_mask : PatLeaf<(build_vector), [{
   return X86::isSplatMask(N);
 }]>;
 
@@ -87,6 +83,12 @@
   return X86::isSHUFPMask(N);
 }], SHUFFLE_get_shuf_imm>;
 
+// Only use SHUFP for v4i32 if no other options are available.
+// FIXME: add tblgen hook to reduce the complexity of pattern.
+def SHUFP_v4i32_shuffle_mask : PatLeaf<(build_vector), [{
+  return !X86::isUNPCKHMask(N) && !X86::isPSHUFDMask(N) && X86::isSHUFPMask(N);
+}], SHUFFLE_get_shuf_imm>;
+
 
//===--===//
 // SSE scalar FP Instructions
 
//===--===//
@@ -1327,6 +1329,8 @@
   Requires<[HasSSE2]>;
 
 // bit_convert
+def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>,
+  Requires<[HasSSE2]>;
 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>,
   Requires<[HasSSE2]>;
 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>,
@@ -1346,16 +1350,20 @@
 def : Pat<(v16i8 (X86zexts2vec R8:$src)),
   (MOVZD128rr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>;
 
-// Splat v4f32 / v4i32
-def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SHUFP_splat_mask:$sm),
-  (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SHUFP_splat_mask:$sm))>,
-  Requires<[HasSSE1]>;
-def : Pat<(vector_shuffle (v4i32 VR128:$src), (undef), SHUFP_splat_mask:$sm),
-  (v4i32 (SHUFPSrr VR128:$src, VR128:$src, SHUFP_splat_mask:$sm))>,
-  Requires<[HasSSE2]>;
-
 // Splat v2f64 / v2i64
-def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), MOVLHPS_splat_mask:$sm),
-  (v2f64 (MOVLHPSrr VR128:$src, VR128:$src))>, Requires<[

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrSSE.td

2006-03-28 Thread Evan Cheng 


Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.141 -> 1.142
X86InstrSSE.td updated: 1.40 -> 1.41
---
Log message:

- Only use pshufd for v4i32 vector shuffles.
- Other shuffle related fixes.


---
Diffs of the changes:  (+83 -61)

 X86ISelLowering.cpp |   51 +---
 X86InstrSSE.td  |   93 +---
 2 files changed, 83 insertions(+), 61 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.141 
llvm/lib/Target/X86/X86ISelLowering.cpp:1.142
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.141   Tue Mar 28 17:41:33 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 28 19:30:51 2006
@@ -1583,15 +1583,21 @@
   return Mask;
 }
 
-/// CommuteVectorShuffleIfNeeded - Swap vector_shuffle operands (as well as
-/// values in ther permute mask if needed. Return an empty SDOperand is it is
-/// already well formed.
-static SDOperand CommuteVectorShuffleIfNeeded(SDOperand V1, SDOperand V2,
-  SDOperand Mask, MVT::ValueType 
VT,
-  SelectionDAG &DAG) {
+/// NormalizeVectorShuffle - Swap vector_shuffle operands (as well as
+/// values in ther permute mask if needed. Use V1 as second vector if it is
+/// undef. Return an empty SDOperand is it is already well formed.
+static SDOperand NormalizeVectorShuffle(SDOperand V1, SDOperand V2,
+SDOperand Mask, MVT::ValueType VT,
+SelectionDAG &DAG) {
   unsigned NumElems = Mask.getNumOperands();
   SDOperand Half1 = Mask.getOperand(0);
   SDOperand Half2 = Mask.getOperand(NumElems/2);
+  bool V2Undef = false;
+  if (V2.getOpcode() == ISD::UNDEF) {
+V2Undef = true;
+V2 = V1;
+  }
+
   if (cast(Half1)->getValue() >= NumElems &&
   cast(Half2)->getValue() <  NumElems) {
 // Swap the operands and change mask.
@@ -1604,6 +1610,10 @@
   DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), MaskVec);
 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1, Mask);
   }
+
+  if (V2Undef)
+return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
+
   return SDOperand();
 }
 
@@ -2387,8 +2397,26 @@
 MVT::ValueType VT = Op.getValueType();
 unsigned NumElems = PermMask.getNumOperands();
 
-if (NumElems == 2)
-  return CommuteVectorShuffleIfNeeded(V1, V2, PermMask, VT, DAG);
+if (X86::isUNPCKLMask(PermMask.Val) ||
+X86::isUNPCKHMask(PermMask.Val))
+  // Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*.
+  return SDOperand();
+
+// PSHUFD's 2nd vector must be undef.
+if (MVT::isInteger(VT) && X86::isPSHUFDMask(PermMask.Val))
+  if (V2.getOpcode() == ISD::UNDEF)
+return SDOperand();
+  else
+return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
+   DAG.getNode(ISD::UNDEF, V1.getValueType()),
+   PermMask);
+
+if (NumElems == 2 ||
+X86::isSplatMask(PermMask.Val) ||
+X86::isSHUFPMask(PermMask.Val)) {
+  return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG);
+}
+#if 0
 else if (X86::isSplatMask(PermMask.Val)) {
   // Handle splat cases.
   if (V2.getOpcode() == ISD::UNDEF)
@@ -2400,10 +2428,6 @@
 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
DAG.getNode(ISD::UNDEF, V1.getValueType()),
PermMask);
-} else if (X86::isUNPCKLMask(PermMask.Val) ||
-   X86::isUNPCKHMask(PermMask.Val)) {
-  // Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*.
-  return SDOperand();
 } else if (X86::isPSHUFDMask(PermMask.Val)) {
   if (V2.getOpcode() == ISD::UNDEF)
 // Leave the VECTOR_SHUFFLE alone. It matches PSHUFD.
@@ -2414,7 +2438,8 @@
DAG.getNode(ISD::UNDEF, V1.getValueType()),
PermMask);
 } else if (X86::isSHUFPMask(PermMask.Val))
-  return CommuteVectorShuffleIfNeeded(V1, V2, PermMask, VT, DAG);
+  return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG);
+#endif
 
 assert(0 && "Unexpected VECTOR_SHUFFLE to lower");
 abort();


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.40 
llvm/lib/Target/X86/X86InstrSSE.td:1.41
--- llvm/lib/Target/X86/X86InstrSSE.td:1.40 Tue Mar 28 17:51:43 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td  Tue Mar 28 19:30:51 2006
@@ -79,9 +79,8 @@
   return X86::isUNPCKHMask(N);
 }]>;
 
-// Only use PSHUF if it is not a splat.
 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
-  return !X86::isSplatMask(N) && X86::isPSHUFDMask(N);
+  return X86::isPSHUFDMask(N);
 }], SHUFFLE_get_shuf_imm>;
 
 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
@@ -918,86 +917,92 @@
  "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
 def PSHUFDrr : PDIi8<

[llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt

2006-03-28 Thread Chris Lattner 


Changes in directory llvm/lib/Target/PowerPC:

README_ALTIVEC.txt updated: 1.5 -> 1.6
---
Log message:

add a note


---
Diffs of the changes:  (+4 -0)

 README_ALTIVEC.txt |4 
 1 files changed, 4 insertions(+)


Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.5 
llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.6
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.5  Tue Mar 28 12:56:23 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt  Tue Mar 28 18:24:13 2006
@@ -145,3 +145,7 @@
 
 
//===--===//
 
+Instcombine llvm.ppc.altivec.vperm with an immediate into a shuffle operation.
+
+//===--===//
+



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector-constantexpr.ll

2006-03-28 Thread Chris Lattner 


Changes in directory llvm/test/Regression/CodeGen/Generic:

vector-constantexpr.ll added (r1.1)
---
Log message:

new testcase


---
Diffs of the changes:  (+10 -0)

 vector-constantexpr.ll |   10 ++
 1 files changed, 10 insertions(+)


Index: llvm/test/Regression/CodeGen/Generic/vector-constantexpr.ll
diff -c /dev/null 
llvm/test/Regression/CodeGen/Generic/vector-constantexpr.ll:1.1
*** /dev/null   Tue Mar 28 18:12:18 2006
--- llvm/test/Regression/CodeGen/Generic/vector-constantexpr.ll Tue Mar 28 
18:12:08 2006
***
*** 0 
--- 1,10 
+ ; RUN: llvm-as < %s | llc
+   
+ void ""(float* %inregs, float* %outregs) {
+ %a_addr.i = alloca <4 x float>  ; <<4 x float>*> [#uses=1]
+ store <4 x float> < float extractelement (<4 x float> undef, uint 3), 
float extractelement (<4 x float> undef, uint 0), float extractelement (<4 x 
float> undef, uint 1), float extractelement (<4 x float> undef, uint 2) >, <4 x 
float>* %a_addr.i
+ ret void
+ }
+ 
+ 
+ 



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

2006-03-28 Thread Chris Lattner 


Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.211 -> 1.212
---
Log message:

Bug fixes: handle constantexpr insert/extract element operations
Handle constantpacked vectors with constantexpr elements.

This fixes CodeGen/Generic/vector-constantexpr.ll




---
Diffs of the changes:  (+6 -16)

 SelectionDAGISel.cpp |   22 ++
 1 files changed, 6 insertions(+), 16 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.211 
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.212
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.211Tue Mar 28 
07:45:20 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp  Tue Mar 28 18:11:43 2006
@@ -507,8 +507,8 @@
   void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT); }
   void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT); }
 
-  void visitExtractElement(ExtractElementInst &I);
-  void visitInsertElement(InsertElementInst &I);
+  void visitExtractElement(User &I);
+  void visitInsertElement(User &I);
 
   void visitGetElementPtr(User &I);
   void visitCast(User &I);
@@ -586,18 +586,8 @@
   // the packed constant.
   std::vector Ops;
   if (ConstantPacked *CP = dyn_cast(C)) {
-if (MVT::isFloatingPoint(PVT)) {
-  for (unsigned i = 0; i != NumElements; ++i) {
-const ConstantFP *El = cast(CP->getOperand(i));
-Ops.push_back(DAG.getConstantFP(El->getValue(), PVT));
-  }
-} else {
-  for (unsigned i = 0; i != NumElements; ++i) {
-const ConstantIntegral *El = 
-cast(CP->getOperand(i));
-Ops.push_back(DAG.getConstant(El->getRawValue(), PVT));
-  }
-}
+for (unsigned i = 0; i != NumElements; ++i)
+  Ops.push_back(getValue(CP->getOperand(i)));
   } else {
 assert(isa(C) && "Unknown packed constant!");
 SDOperand Op;
@@ -1020,7 +1010,7 @@
   }
 }
 
-void SelectionDAGLowering::visitInsertElement(InsertElementInst &I) {
+void SelectionDAGLowering::visitInsertElement(User &I) {
   SDOperand InVec = getValue(I.getOperand(0));
   SDOperand InVal = getValue(I.getOperand(1));
   SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
@@ -1032,7 +1022,7 @@
InVec, InVal, InIdx, Num, Typ));
 }
 
-void SelectionDAGLowering::visitExtractElement(ExtractElementInst &I) {
+void SelectionDAGLowering::visitExtractElement(User &I) {
   SDOperand InVec = getValue(I.getOperand(0));
   SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
 getValue(I.getOperand(1)));



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td

2006-03-28 Thread Evan Cheng 


Changes in directory llvm/lib/Target/X86:

X86InstrSSE.td updated: 1.39 -> 1.40
---
Log message:

Added aliases to scalar SSE instructions, e.g. addss, to match x86 intrinsics.
The source operands type are v4sf with upper bits passes through.
Added matching code for these.


---
Diffs of the changes:  (+201 -47)

 X86InstrSSE.td |  248 ++---
 1 files changed, 201 insertions(+), 47 deletions(-)


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.39 
llvm/lib/Target/X86/X86InstrSSE.td:1.40
--- llvm/lib/Target/X86/X86InstrSSE.td:1.39 Tue Mar 28 01:01:28 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td  Tue Mar 28 17:51:43 2006
@@ -174,53 +174,6 @@
  [(set VR128:$dst, 
(v2f64 (scalar_to_vector (loadf64 addr:$src]>;
 
-
-// Conversion instructions
-def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops R32:$dst, FR32:$src),
-   "cvtss2si {$src, $dst|$dst, $src}", []>;
-def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src),
-   "cvtss2si {$src, $dst|$dst, $src}", []>;
-
-def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src),
-   "cvttss2si {$src, $dst|$dst, $src}",
-   [(set R32:$dst, (fp_to_sint FR32:$src))]>;
-def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
-   "cvttss2si {$src, $dst|$dst, $src}",
-   [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
-def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src),
-   "cvttsd2si {$src, $dst|$dst, $src}",
-   [(set R32:$dst, (fp_to_sint FR64:$src))]>;
-def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
-   "cvttsd2si {$src, $dst|$dst, $src}",
-   [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
-def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
-  "cvtsd2ss {$src, $dst|$dst, $src}",
-  [(set FR32:$dst, (fround FR64:$src))]>;
-def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src), 
-  "cvtsd2ss {$src, $dst|$dst, $src}",
-  [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
-def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src),
-  "cvtsi2ss {$src, $dst|$dst, $src}",
-  [(set FR32:$dst, (sint_to_fp R32:$src))]>;
-def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
-  "cvtsi2ss {$src, $dst|$dst, $src}",
-  [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
-def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src),
-  "cvtsi2sd {$src, $dst|$dst, $src}",
-  [(set FR64:$dst, (sint_to_fp R32:$src))]>;
-def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
-  "cvtsi2sd {$src, $dst|$dst, $src}",
-  [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
-// SSE2 instructions with XS prefix
-def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
-  "cvtss2sd {$src, $dst|$dst, $src}",
-  [(set FR64:$dst, (fextend FR32:$src))]>, XS,
-Requires<[HasSSE2]>;
-def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
-  "cvtss2sd {$src, $dst|$dst, $src}",
-  [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS,
-Requires<[HasSSE2]>;
-
 // Arithmetic instructions
 let isTwoAddress = 1 in {
 let isCommutable = 1 in {
@@ -317,6 +270,207 @@
 def MINSDrm : SDI<0x5D, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
   "minsd {$src, $dst|$dst, $src}", []>;
 
+
+// Aliases to match intrinsics which expect XMM operand(s).
+let isTwoAddress = 1 in {
+let isCommutable = 1 in {
+def Int_ADDSSrr : SSI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+VR128:$src2),
+"addss {$src2, $dst|$dst, $src2}",
+[(set VR128:$dst, (int_x86_sse_add_ss VR128:$src1,
+   VR128:$src2))]>;
+def Int_ADDSDrr : SDI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+VR128:$src2),
+"addsd {$src2, $dst|$dst, $src2}",
+[(set VR128:$dst, (int_x86_sse2_add_sd VR128:$src1,
+   VR128:$src2))]>;
+def Int_MULSSrr : SSI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+VR128:$src2),
+"mulss {$src2, $dst|$dst, $src2}",
+[(set VR128:$dst, (int_x86_sse_mul_ss VR128:$src1,
+   VR128:$src2))]>;
+def Int_MULSDrr : SDI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+VR128:$src2),
+"mulsd {$src2, $dst|$dst, $src2}",
+[(set VR128:$dst, (int_x86_

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

2006-03-28 Thread Evan Cheng 


Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.140 -> 1.141
---
Log message:

Fixing buggy code.


---
Diffs of the changes:  (+6 -6)

 X86ISelLowering.cpp |   12 ++--
 1 files changed, 6 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.140 
llvm/lib/Target/X86/X86ISelLowering.cpp:1.141
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.140   Tue Mar 28 04:17:11 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 28 17:41:33 2006
@@ -1571,14 +1571,14 @@
   unsigned NumOperands = N->getNumOperands();
   unsigned Shift = (NumOperands == 4) ? 2 : 1;
   unsigned Mask = 0;
-  unsigned i = NumOperands - 1;
-  do {
-unsigned Val = cast(N->getOperand(i))->getValue();
+  for (unsigned i = 0; i < NumOperands; ++i) {
+unsigned Val
+  = cast(N->getOperand(NumOperands-i-1))->getValue();
 if (Val >= NumOperands) Val -= NumOperands;
 Mask |= Val;
-Mask <<= Shift;
---i;
-  } while (i != 0);
+if (i != NumOperands - 1)
+  Mask <<= Shift;
+  }
 
   return Mask;
 }



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/utils/TableGen/IntrinsicEmitter.cpp

2006-03-28 Thread Evan Cheng 


Changes in directory llvm/utils/TableGen:

IntrinsicEmitter.cpp updated: 1.16 -> 1.17
---
Log message:

Don't sort the names before outputing the intrinsic name table. It causes a
mismatch against the enum table.
This is a part of Sabre's master plan to drive me nuts with subtle bugs that
happens to only affect x86 be. :-)


---
Diffs of the changes:  (+2 -7)

 IntrinsicEmitter.cpp |9 ++---
 1 files changed, 2 insertions(+), 7 deletions(-)


Index: llvm/utils/TableGen/IntrinsicEmitter.cpp
diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.16 
llvm/utils/TableGen/IntrinsicEmitter.cpp:1.17
--- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.16   Fri Mar 24 13:49:31 2006
+++ llvm/utils/TableGen/IntrinsicEmitter.cppTue Mar 28 16:25:56 2006
@@ -100,16 +100,11 @@
 void IntrinsicEmitter::
 EmitIntrinsicToNameTable(const std::vector &Ints, 
  std::ostream &OS) {
-  std::vector Names;
-  for (unsigned i = 0, e = Ints.size(); i != e; ++i)
-Names.push_back(Ints[i].Name);
-  std::sort(Names.begin(), Names.end());
-  
   OS << "// Intrinsic ID to name table\n";
   OS << "#ifdef GET_INTRINSIC_NAME_TABLE\n";
   OS << "  // Note that entry #0 is the invalid intrinsic!\n";
-  for (unsigned i = 0, e = Names.size(); i != e; ++i)
-OS << "  \"" << Names[i] << "\",\n";
+  for (unsigned i = 0, e = Ints.size(); i != e; ++i)
+OS << "  \"" << Ints[i].Name << "\",\n";
   OS << "#endif\n\n";
 }
 



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2006-03-28 Thread Chris Lattner 


Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.132 -> 1.133
---
Log message:

When building a VVECTOR_SHUFFLE node from extract_element operations, make
sure to build it as SHUFFLE(X, undef, mask), not SHUFFLE(X, X, mask).

The later is not canonical form, and prevents the PPC splat pattern from 
matching.  For a particular splat, we go from generating this:

li r10, lo16(LCPI1_0)
lis r11, ha16(LCPI1_0)
lvx v3, r11, r10
vperm v3, v2, v2, v3

to generating:

vspltw v3, v2, 3



---
Diffs of the changes:  (+11 -1)

 DAGCombiner.cpp |   12 +++-
 1 files changed, 11 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.132 
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.133
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.132 Tue Mar 28 16:11:53 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp   Tue Mar 28 16:19:47 2006
@@ -2419,7 +2419,17 @@
 // Return the new VVECTOR_SHUFFLE node.
 std::vector Ops;
 Ops.push_back(VecIn1);
-Ops.push_back(VecIn2.Val ? VecIn2 : VecIn1); // Use V1 twice if no V2.
+if (VecIn2.Val) {
+  Ops.push_back(VecIn2);
+} else {
+   // Use an undef vbuild_vector as input for the second operand.
+  std::vector UnOps(NumInScalars,
+   DAG.getNode(ISD::UNDEF, 
+   cast(EltType)->getVT()));
+  UnOps.push_back(NumElts);
+  UnOps.push_back(EltType);
+  Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps));
+}
 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, 
BuildVecIndices));
 Ops.push_back(NumElts);
 Ops.push_back(EltType);



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/Altivec/casts.c

2006-03-28 Thread Chris Lattner 


Changes in directory llvm-test/SingleSource/UnitTests/Vector/Altivec:

casts.c added (r1.1)
---
Log message:

Random testcase from my collection


---
Diffs of the changes:  (+30 -0)

 casts.c |   30 ++
 1 files changed, 30 insertions(+)


Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/casts.c
diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/Altivec/casts.c:1.1
*** /dev/null   Tue Mar 28 16:28:47 2006
--- llvm-test/SingleSource/UnitTests/Vector/Altivec/casts.c Tue Mar 28 
16:28:37 2006
***
*** 0 
--- 1,30 
+ #include 
+ #include 
+ 
+ typedef union {
+  float f[4];
+  vector float v;
+ } floatToVector;
+ 
+ 
+ void test(float F, vector float *R) {
+floatToVector FTV;
+FTV.f[0] = F;
+*R = (vector float) vec_splat((vector unsigned int)FTV.v, 0);
+ }
+ 
+ void test2(float F, vector float *R) {
+*R = (vector float)(F);
+ }
+ void test2a(float F, vector float *X, vector float *R) {
+*R = (vector float)(F) + *X;
+ }
+ 
+ 
+ int main() {
+   floatToVector X;
+   int i;
+   test(12.34, &X.v);
+ 
+   printf("%f %f %f %f\n", X.f[0], X.f[1], X.f[2], X.f[3]);
+ }



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2006-03-28 Thread Chris Lattner 


Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.131 -> 1.132
---
Log message:

Canonicalize VECTOR_SHUFFLE(X, X, Y) -> VECTOR_SHUFFLE(X,undef,Y')


---
Diffs of the changes:  (+30 -0)

 DAGCombiner.cpp |   30 ++
 1 files changed, 30 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.131 
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.132
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.131 Tue Mar 28 14:28:38 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp   Tue Mar 28 16:11:53 2006
@@ -212,6 +212,7 @@
 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
 SDOperand visitVBUILD_VECTOR(SDNode *N);
+SDOperand visitVECTOR_SHUFFLE(SDNode *N);
 
 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
 
@@ -646,6 +647,7 @@
   case ISD::INSERT_VECTOR_ELT:  return visitINSERT_VECTOR_ELT(N);
   case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
   case ISD::VBUILD_VECTOR:  return visitVBUILD_VECTOR(N);
+  case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
   }
   return SDOperand();
 }
@@ -2427,6 +2429,34 @@
   return SDOperand();
 }
 
+SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
+  // If the LHS and the RHS are the same node, turn the RHS into an undef.
+  if (N->getOperand(0) == N->getOperand(1)) {
+// Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
+// first operand.
+std::vector MappedOps;
+SDOperand ShufMask = N->getOperand(2);
+unsigned NumElts = ShufMask.getNumOperands();
+for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
+  if (cast(ShufMask.getOperand(i))->getValue() >= NumElts) 
{
+unsigned NewIdx = 
+   cast(ShufMask.getOperand(i))->getValue() - NumElts;
+MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
+  } else {
+MappedOps.push_back(ShufMask.getOperand(i));
+  }
+}
+ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
+   MappedOps);
+return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
+   N->getOperand(0), 
+   DAG.getNode(ISD::UNDEF, N->getValueType(0)),
+   ShufMask);
+  }
+ 
+  return SDOperand();
+}
+
 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand 
N2){
   assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC 
node!");
   



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/unpcklps.ll

2006-03-28 Thread Chris Lattner 


Changes in directory llvm/test/Regression/CodeGen/X86:

unpcklps.ll added (r1.1)
---
Log message:

new testcase


---
Diffs of the changes:  (+18 -0)

 unpcklps.ll |   18 ++
 1 files changed, 18 insertions(+)


Index: llvm/test/Regression/CodeGen/X86/unpcklps.ll
diff -c /dev/null llvm/test/Regression/CodeGen/X86/unpcklps.ll:1.1
*** /dev/null   Tue Mar 28 14:32:22 2006
--- llvm/test/Regression/CodeGen/X86/unpcklps.llTue Mar 28 14:32:12 2006
***
*** 0 
--- 1,18 
+ ; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | grep unpcklps &&
+ ; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | not grep 'sub.*esp'
+ 
+ void %test(<4 x float>* %res, <4 x float>* %A, <4 x float>* %B) {
+ %tmp = load <4 x float>* %B ; <<4 x float>> [#uses=2]
+ %tmp3 = load <4 x float>* %A; <<4 x float>> [#uses=2]
+ %tmp = extractelement <4 x float> %tmp3, uint 0 ;  
[#uses=1]
+ %tmp7 = extractelement <4 x float> %tmp, uint 0 ;  
[#uses=1]
+ %tmp8 = extractelement <4 x float> %tmp3, uint 1; 
 [#uses=1]
+ %tmp9 = extractelement <4 x float> %tmp, uint 1 ;  
[#uses=1]
+ %tmp10 = insertelement <4 x float> undef, float %tmp, uint 0  
  ; <<4 x float>> [#uses=1]
+ %tmp11 = insertelement <4 x float> %tmp10, float %tmp7, uint 1
  ; <<4 x float>> [#uses=1]
+ %tmp12 = insertelement <4 x float> %tmp11, float %tmp8, uint 2
  ; <<4 x float>> [#uses=1]
+ %tmp13 = insertelement <4 x float> %tmp12, float %tmp9, uint 3
  ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp13, <4 x float>* %res
+ ret void
+ }
+ 



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2006-03-28 Thread Chris Lattner 


Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.130 -> 1.131
---
Log message:

Turn a series of extract_element's feeding a build_vector into a
vector_shuffle node.  For this:

void test(__m128 *res, __m128 *A, __m128 *B) {
  *res = _mm_unpacklo_ps(*A, *B);
}

we now produce this code:

_test:
movl 8(%esp), %eax
movaps (%eax), %xmm0
movl 12(%esp), %eax
unpcklps (%eax), %xmm0
movl 4(%esp), %eax
movaps %xmm0, (%eax)
ret

instead of this:

_test:
subl $76, %esp
movl 88(%esp), %eax
movaps (%eax), %xmm0
movaps %xmm0, (%esp)
movaps %xmm0, 32(%esp)
movss 4(%esp), %xmm0
movss 32(%esp), %xmm1
unpcklps %xmm0, %xmm1
movl 84(%esp), %eax
movaps (%eax), %xmm0
movaps %xmm0, 16(%esp)
movaps %xmm0, 48(%esp)
movss 20(%esp), %xmm0
movss 48(%esp), %xmm2
unpcklps %xmm0, %xmm2
unpcklps %xmm1, %xmm2
movl 80(%esp), %eax
movaps %xmm2, (%eax)
addl $76, %esp
ret

GCC produces this (with -fomit-frame-pointer):

_test:
subl$12, %esp
movl20(%esp), %eax
movaps  (%eax), %xmm0
movl24(%esp), %eax
unpcklps(%eax), %xmm0
movl16(%esp), %eax
movaps  %xmm0, (%eax)
addl$12, %esp
ret



---
Diffs of the changes:  (+86 -0)

 DAGCombiner.cpp |   86 
 1 files changed, 86 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.130 
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.131
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.130 Tue Mar 28 13:11:05 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp   Tue Mar 28 14:28:38 2006
@@ -211,6 +211,7 @@
 SDOperand visitSTORE(SDNode *N);
 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
+SDOperand visitVBUILD_VECTOR(SDNode *N);
 
 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
 
@@ -644,6 +645,7 @@
   case ISD::STORE:  return visitSTORE(N);
   case ISD::INSERT_VECTOR_ELT:  return visitINSERT_VECTOR_ELT(N);
   case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
+  case ISD::VBUILD_VECTOR:  return visitVBUILD_VECTOR(N);
   }
   return SDOperand();
 }
@@ -2341,6 +2343,90 @@
   return SDOperand();
 }
 
+SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
+  unsigned NumInScalars = N->getNumOperands()-2;
+  SDOperand NumElts = N->getOperand(NumInScalars);
+  SDOperand EltType = N->getOperand(NumInScalars+1);
+
+  // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
+  // operations.  If so, and if the EXTRACT_ELT vector inputs come from at most
+  // two distinct vectors, turn this into a shuffle node.
+  SDOperand VecIn1, VecIn2;
+  for (unsigned i = 0; i != NumInScalars; ++i) {
+// Ignore undef inputs.
+if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
+
+// If this input is something other than a VEXTRACT_VECTOR_ELT with a
+// constant index, bail out.
+if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
+!isa(N->getOperand(i).getOperand(1))) {
+  VecIn1 = VecIn2 = SDOperand(0, 0);
+  break;
+}
+
+// If the input vector type disagrees with the result of the vbuild_vector,
+// we can't make a shuffle.
+SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
+if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
+*(ExtractedFromVec.Val->op_end()-1) != EltType) {
+  VecIn1 = VecIn2 = SDOperand(0, 0);
+  break;
+}
+
+// Otherwise, remember this.  We allow up to two distinct input vectors.
+if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
+  continue;
+
+if (VecIn1.Val == 0) {
+  VecIn1 = ExtractedFromVec;
+} else if (VecIn2.Val == 0) {
+  VecIn2 = ExtractedFromVec;
+} else {
+  // Too many inputs.
+  VecIn1 = VecIn2 = SDOperand(0, 0);
+  break;
+}
+  }
+  
+  // If everything is good, we can make a shuffle operation.
+  if (VecIn1.Val) {
+std::vector BuildVecIndices;
+for (unsigned i = 0; i != NumInScalars; ++i) {
+  if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
+BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
+continue;
+  }
+  
+  SDOperand Extract = N->getOperand(i);
+  
+  // If extracting from the first vector, just use the index directly.
+  if (Extract.getOperand(0) == VecIn1) {
+BuildVecIndices.push_back(Extract.getOperand(1));
+continue;
+  }
+
+  // Otherwise, use InIdx + VecSize
+  unsigned Idx = cast(Extract.getOperand(1))->getValue();
+  BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i3

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

2006-03-28 Thread Chris Lattner 


Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.341 -> 1.342
---
Log message:

Teach Legalize how to pack VVECTOR_SHUFFLE nodes into VECTOR_SHUFFLE nodes.


---
Diffs of the changes:  (+21 -0)

 LegalizeDAG.cpp |   21 +
 1 files changed, 21 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.341 
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.342
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.341 Mon Mar 27 18:40:09 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp   Tue Mar 28 14:24:43 2006
@@ -4532,6 +4532,27 @@
Node->getOperand(1), Node->getOperand(2));
 }
 break;
+  case ISD::VVECTOR_SHUFFLE:
+if (!MVT::isVector(NewVT)) {
+  // Returning a scalar?  Figure out if it is the LHS or RHS and return it.
+  SDOperand EltNum = Node->getOperand(2).getOperand(0);
+  if (cast(EltNum)->getValue())
+Result = PackVectorOp(Node->getOperand(1), NewVT);
+  else
+Result = PackVectorOp(Node->getOperand(0), NewVT);
+} else {
+  // Otherwise, return a VECTOR_SHUFFLE node.  First convert the index
+  // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
+  std::vector BuildVecIdx(Node->getOperand(2).Val->op_begin(),
+ Node->getOperand(2).Val->op_end()-2);
+  MVT::ValueType BVT = 
MVT::getIntVectorWithNumElements(BuildVecIdx.size());
+  SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, BuildVecIdx);
+  
+  Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
+   PackVectorOp(Node->getOperand(0), NewVT),
+   PackVectorOp(Node->getOperand(1), NewVT), BV);
+}
+break;
   case ISD::VBIT_CONVERT:
 if (Op.getOperand(0).getValueType() != MVT::Vector)
   Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

2006-03-28 Thread Chris Lattner 


Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.291 -> 1.292
---
Log message:

new node


---
Diffs of the changes:  (+1 -0)

 SelectionDAG.cpp |1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.291 
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.292
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.291Tue Mar 28 
13:04:49 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp  Tue Mar 28 13:54:42 2006
@@ -2761,6 +2761,7 @@
   case ISD::SCALAR_TO_VECTOR:   return "scalar_to_vector";
   case ISD::VBUILD_VECTOR: return "vbuild_vector";
   case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
+  case ISD::VVECTOR_SHUFFLE: return "vvector_shuffle";
   case ISD::VBIT_CONVERT: return "vbit_convert";
   case ISD::ADDC:return "addc";
   case ISD::ADDE:return "adde";



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h

2006-03-28 Thread Chris Lattner 


Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGNodes.h updated: 1.124 -> 1.125
---
Log message:

Add a new node


---
Diffs of the changes:  (+9 -0)

 SelectionDAGNodes.h |9 +
 1 files changed, 9 insertions(+)


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.124 
llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.125
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.124 Mon Mar 27 18:39:06 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h   Tue Mar 28 13:54:11 2006
@@ -189,6 +189,15 @@
 /// element number IDX.
 EXTRACT_VECTOR_ELT,
 
+/// VVECTOR_SHUFFLE(VEC1, VEC2, SHUFFLEVEC, COUNT,TYPE) - Returns a vector,
+/// of the same type as VEC1/VEC2.  SHUFFLEVEC is a VBUILD_VECTOR of
+/// constant int values that indicate which value each result element will
+/// get.  The elements of VEC1/VEC2 are enumerated in order.  This is quite
+/// similar to the Altivec 'vperm' instruction, except that the indices 
must
+/// be constants and are in terms of the element size of VEC1/VEC2, not in
+/// terms of bytes.
+VVECTOR_SHUFFLE,
+
 /// VECTOR_SHUFFLE(VEC1, VEC2, SHUFFLEVEC) - Returns a vector, of the same
 /// type as VEC1/VEC2.  SHUFFLEVEC is a BUILD_VECTOR of constant int values
 /// (regardless of whether its datatype is legal or not) that indicate



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2006-03-28 Thread Chris Lattner 


Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.129 -> 1.130
---
Log message:

Don't crash on X^X if X is a vector.  Instead, produce a vector of zeros.


---
Diffs of the changes:  (+10 -2)

 DAGCombiner.cpp |   12 ++--
 1 files changed, 10 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.129 
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.130
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.129 Sat Mar 25 16:19:00 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp   Tue Mar 28 13:11:05 2006
@@ -1396,8 +1396,16 @@
  DAG.getConstant(N1C->getValue()^N01C->getValue(), 
VT));
   }
   // fold (xor x, x) -> 0
-  if (N0 == N1)
-return DAG.getConstant(0, VT);
+  if (N0 == N1) {
+if (!MVT::isVector(VT)) {
+  return DAG.getConstant(0, VT);
+} else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
+  // Produce a vector of zeros.
+  SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
+  std::vector Ops(MVT::getVectorNumElements(VT), El);
+  return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
+}
+  }
   // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
   if (N0.getOpcode() == ISD::ZERO_EXTEND && 
   N1.getOpcode() == ISD::ZERO_EXTEND &&



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

2006-03-28 Thread Chris Lattner 


Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.290 -> 1.291
---
Log message:

Add an assertion


---
Diffs of the changes:  (+2 -0)

 SelectionDAG.cpp |2 ++
 1 files changed, 2 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.290 
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.291
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.290Mon Mar 27 
18:40:09 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp  Tue Mar 28 13:04:49 2006
@@ -634,6 +634,8 @@
 
 SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT) {
   assert(MVT::isInteger(VT) && "Cannot create FP integer constant!");
+  assert(!MVT::isVector(VT) && "Cannot create Vector ConstantSDNodes!");
+  
   // Mask out any bits that are not valid for this constant.
   if (VT != MVT::i64)
 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1;



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt

2006-03-28 Thread Chris Lattner 


Changes in directory llvm/lib/Target/PowerPC:

README_ALTIVEC.txt updated: 1.4 -> 1.5
---
Log message:

add a note


---
Diffs of the changes:  (+10 -0)

 README_ALTIVEC.txt |   10 ++
 1 files changed, 10 insertions(+)


Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.4 
llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.5
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.4  Mon Mar 27 22:15:58 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt  Tue Mar 28 12:56:23 2006
@@ -134,4 +134,14 @@
 2. Identical operations in different types are not getting CSE'd (e.g. 
{ 0U, 0U, 0U, 0U } and {0.0, 0.0, 0.0, 0.0}.
 
+//===--===//
+
+Two identical comparisons in predicate and nonpredicate form like this:
+
+a = vec_cmpb(x, y);
+b = vec_any_out(x, y);
+
+Should turn into one "." compare instruction, not a dot and "nondot" form.
+
+//===--===//
 



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp

2006-03-28 Thread Jim Laskey 


Changes in directory llvm/lib/CodeGen:

DwarfWriter.cpp updated: 1.52 -> 1.53
---
Log message:

Refactor address attributes.  Add base register to frame info.


---
Diffs of the changes:  (+19 -13)

 DwarfWriter.cpp |   32 +++-
 1 files changed, 19 insertions(+), 13 deletions(-)


Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.52 
llvm/lib/CodeGen/DwarfWriter.cpp:1.53
--- llvm/lib/CodeGen/DwarfWriter.cpp:1.52   Fri Mar 24 15:10:36 2006
+++ llvm/lib/CodeGen/DwarfWriter.cppTue Mar 28 08:58:32 2006
@@ -1213,6 +1213,21 @@
   }
 }
 
+/// AddAddress - Add an address attribute to a die based on the location
+/// provided.
+void DwarfWriter::AddAddress(DIE *Die, unsigned Attribute,
+ MachineLocation &Location) {
+  DIEBlock *Block = new DIEBlock();
+  if (Location.isRegister()) {
+Block->AddUInt(DW_FORM_data1, DW_OP_reg0 + Location.getRegister());
+  } else {
+Block->AddUInt(DW_FORM_data1, DW_OP_breg0 + Location.getRegister());
+Block->AddUInt(DW_FORM_sdata, Location.getOffset());
+  }
+  Block->ComputeSize(*this);
+  Die->AddBlock(Attribute, 0, Block);
+}
+
 /// getDieMapSlotFor - Returns the debug information entry map slot for the
 /// specified debug descriptor.
 DIE *&DwarfWriter::getDieMapSlotFor(DebugInfoDesc *DD) {
@@ -1518,7 +1533,6 @@
   return SubprogramDie;
 }
 
-
 /// NewScopeVariable - Create a new scope variable.
 ///
 DIE *DwarfWriter::NewScopeVariable(DebugVariable *DV, CompileUnit *Unit) {
@@ -1545,20 +1559,10 @@
   DIE *Type = NewType(Unit->getDie(), VD->getType(), Unit); 
   VariableDie->AddDIEntry(DW_AT_type, DW_FORM_ref4, Type);
   
-  // Get variable address.
+  // Add variable address.
   MachineLocation Location;
   Asm->TM.getRegisterInfo()->getLocation(*MF, DV->getFrameIndex(), Location);
-  
-  // Add computation for variable.
-  DIEBlock *Block = new DIEBlock();
-  if (Location.isRegister()) {
-Block->AddUInt(DW_FORM_data1, DW_OP_reg0 + Location.getRegister());
-  } else {
-Block->AddUInt(DW_FORM_data1, DW_OP_breg0 + Location.getRegister());
-Block->AddUInt(DW_FORM_sdata, Location.getOffset());
-  }
-  Block->ComputeSize(*this);
-  VariableDie->AddBlock(DW_AT_location, 0, Block);
+  AddAddress(VariableDie, DW_AT_location, Location);
   
   return VariableDie;
 }
@@ -1628,6 +1632,8 @@
   DWLabel("func_begin", SubprogramCount));
   SPDie->AddLabel(DW_AT_high_pc, DW_FORM_addr,
   DWLabel("func_end", SubprogramCount));
+  MachineLocation Location(Asm->TM.getRegisterInfo()->getFrameRegister(*MF));
+  AddAddress(SPDie, DW_AT_frame_base, Location);
   
   ConstructScope(RootScope, SPDie, Unit);
 }



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/include/llvm/CodeGen/DwarfWriter.h

2006-03-28 Thread Jim Laskey 


Changes in directory llvm/include/llvm/CodeGen:

DwarfWriter.h updated: 1.31 -> 1.32
---
Log message:

Refactor address attributes.  Add base register to frame info.


---
Diffs of the changes:  (+5 -0)

 DwarfWriter.h |5 +
 1 files changed, 5 insertions(+)


Index: llvm/include/llvm/CodeGen/DwarfWriter.h
diff -u llvm/include/llvm/CodeGen/DwarfWriter.h:1.31 
llvm/include/llvm/CodeGen/DwarfWriter.h:1.32
--- llvm/include/llvm/CodeGen/DwarfWriter.h:1.31Thu Mar 23 17:02:34 2006
+++ llvm/include/llvm/CodeGen/DwarfWriter.h Tue Mar 28 08:58:32 2006
@@ -41,6 +41,7 @@
 class DIEAbbrev;
 class GlobalVariableDesc;
 class MachineDebugInfo;
+class MachineLocation;
 class MachineFunction;
 class Module;
 class SubprogramDesc;
@@ -321,6 +322,10 @@
   /// entry. 
   void AddSourceLine(DIE *Die, CompileUnitDesc *File, unsigned Line);
 
+  /// AddAddress - Add an address attribute to a die based on the location
+  /// provided.
+  void AddAddress(DIE *Die, unsigned Attribute, MachineLocation &Location);
+
   /// NewType - Create a new type DIE.
   ///
   DIE *NewType(DIE *Context, TypeDesc *TyDesc, CompileUnit *Unit);



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp SparcV9RegisterInfo.h

2006-03-28 Thread Jim Laskey 


Changes in directory llvm/lib/Target/SparcV9:

SparcV9RegisterInfo.cpp updated: 1.11 -> 1.12
SparcV9RegisterInfo.h updated: 1.10 -> 1.11
---
Log message:

Expose base register for DwarfWriter.  Refactor code accordingly.


---
Diffs of the changes:  (+5 -4)

 SparcV9RegisterInfo.cpp |4 ++--
 SparcV9RegisterInfo.h   |5 +++--
 2 files changed, 5 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.11 
llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.12
--- llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.11Thu Mar 23 
12:12:57 2006
+++ llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp Tue Mar 28 07:48:33 2006
@@ -318,7 +318,7 @@
 }
 
 
-void SparcV9RegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
-  MachineLocation &ML) const {
+unsigned SparcV9RegisterInfo::getFrameRegister(MachineFunction &MF) const {
   abort ();
+  return 0;
 }


Index: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h:1.10 
llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h:1.11
--- llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h:1.10  Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h   Tue Mar 28 07:48:33 2006
@@ -44,8 +44,9 @@
   void eliminateFrameIndex (MachineBasicBlock::iterator MI) const;
   void emitPrologue (MachineFunction &MF) const;
   void emitEpilogue (MachineFunction &MF, MachineBasicBlock &MBB) const;
-  void getLocation(MachineFunction &MF, unsigned Index,
-   MachineLocation &ML) const;
+  
+  // Debug information queries.
+  unsigned getFrameRegister(MachineFunction &MF) const;
 };
 
 } // End llvm namespace



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp AlphaRegisterInfo.h

2006-03-28 Thread Jim Laskey 


Changes in directory llvm/lib/Target/Alpha:

AlphaRegisterInfo.cpp updated: 1.38 -> 1.39
AlphaRegisterInfo.h updated: 1.10 -> 1.11
---
Log message:

Expose base register for DwarfWriter.  Refactor code accordingly.


---
Diffs of the changes:  (+4 -12)

 AlphaRegisterInfo.cpp |   12 ++--
 AlphaRegisterInfo.h   |4 ++--
 2 files changed, 4 insertions(+), 12 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.38 
llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.39
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.38Mon Mar 27 14:18:45 2006
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Tue Mar 28 07:48:33 2006
@@ -354,16 +354,8 @@
  }
 }
 
-void AlphaRegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
-MachineLocation &ML) const {
-  assert(0 && "Needs to be defined for target");
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  bool FP = hasFP(MF);
-  
-  // FIXME - Needs to handle register variables.
-  // FIXME - Faking that llvm number is same as gcc numbering.
-  ML.set(getDwarfRegNum(FP ? Alpha::R15 : Alpha::R30),
- MFI->getObjectOffset(Index) + MFI->getStackSize());
+unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const {
+  return getDwarfRegNum(hasFP(MF) ? Alpha::R15 : Alpha::R30);
 }
 
 #include "AlphaGenRegisterInfo.inc"


Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.h
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.10 
llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.11
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.10  Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.h   Tue Mar 28 07:48:33 2006
@@ -53,8 +53,8 @@
   void emitPrologue(MachineFunction &MF) const;
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
 
-  void getLocation(MachineFunction &MF, unsigned Index, MachineLocation &ML) 
const;
-
+   // Debug information queries.
+  unsigned getFrameRegister(MachineFunction &MF) const;
 
   static std::string getPrettyName(unsigned reg);
 };



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h

2006-03-28 Thread Jim Laskey 


Changes in directory llvm/lib/Target/PowerPC:

PPCRegisterInfo.cpp updated: 1.51 -> 1.52
PPCRegisterInfo.h updated: 1.11 -> 1.12
---
Log message:

Expose base register for DwarfWriter.  Refactor code accordingly.


---
Diffs of the changes:  (+4 -11)

 PPCRegisterInfo.cpp |   11 ++-
 PPCRegisterInfo.h   |4 ++--
 2 files changed, 4 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.51 
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.52
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.51Mon Mar 27 14:18:45 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Mar 28 07:48:33 2006
@@ -447,15 +447,8 @@
   }
 }
 
-void PPCRegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
-  MachineLocation &ML) const {
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  bool FP = hasFP(MF);
-  
-  // FIXME - Needs to handle register variables.
-  // FIXME - Faking that llvm number is same as gcc numbering.
-  ML.set(getDwarfRegNum(FP ? PPC::R31 : PPC::R1),
- MFI->getObjectOffset(Index) + MFI->getStackSize());
+unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
+  return getDwarfRegNum(hasFP(MF) ? PPC::R31 : PPC::R1);
 }
 
 #include "PPCGenRegisterInfo.inc"


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.11 
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.12
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.11  Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h   Tue Mar 28 07:48:33 2006
@@ -56,8 +56,8 @@
   void emitPrologue(MachineFunction &MF) const;
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
 
-  void getLocation(MachineFunction &MF, unsigned Index,
-   MachineLocation &ML) const;
+  // Debug information queries.
+  unsigned getFrameRegister(MachineFunction &MF) const;
 };
 
 } // end namespace llvm



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp SparcRegisterInfo.h

2006-03-28 Thread Jim Laskey 


Changes in directory llvm/lib/Target/Sparc:

SparcRegisterInfo.cpp updated: 1.39 -> 1.40
SparcRegisterInfo.h updated: 1.10 -> 1.11
---
Log message:

Expose base register for DwarfWriter.  Refactor code accordingly.


---
Diffs of the changes:  (+4 -11)

 SparcRegisterInfo.cpp |   11 ++-
 SparcRegisterInfo.h   |4 ++--
 2 files changed, 4 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.39 
llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.40
--- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.39Mon Mar 27 14:18:45 2006
+++ llvm/lib/Target/Sparc/SparcRegisterInfo.cpp Tue Mar 28 07:48:33 2006
@@ -200,15 +200,8 @@
   BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0);
 }
 
-void SparcRegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
-  MachineLocation &ML) const {
-  assert(0 && "Needs to be defined for target");
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  
-  // FIXME - Needs to handle register variables.
-  // FIXME - Faking that llvm number is same as gcc numbering.
-  ML.set(getDwarfRegNum(SP::G1),
- MFI->getObjectOffset(Index) + MFI->getStackSize());
+unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
+  return getDwarfRegNum(SP::G1);
 }
 
 #include "SparcGenRegisterInfo.inc"


Index: llvm/lib/Target/Sparc/SparcRegisterInfo.h
diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.10 
llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.11
--- llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.10  Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/Sparc/SparcRegisterInfo.h   Tue Mar 28 07:48:33 2006
@@ -57,8 +57,8 @@
   void emitPrologue(MachineFunction &MF) const;
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
   
-  void getLocation(MachineFunction &MF, unsigned Index,
-   MachineLocation &ML) const;
+  // Debug information queries.
+  unsigned getFrameRegister(MachineFunction &MF) const;
 };
 
 } // end namespace llvm



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/Target/MRegisterInfo.cpp

2006-03-28 Thread Jim Laskey 


Changes in directory llvm/lib/Target:

MRegisterInfo.cpp updated: 1.12 -> 1.13
---
Log message:

Expose base register for DwarfWriter.  Refactor code accordingly.


---
Diffs of the changes:  (+16 -0)

 MRegisterInfo.cpp |   16 
 1 files changed, 16 insertions(+)


Index: llvm/lib/Target/MRegisterInfo.cpp
diff -u llvm/lib/Target/MRegisterInfo.cpp:1.12 
llvm/lib/Target/MRegisterInfo.cpp:1.13
--- llvm/lib/Target/MRegisterInfo.cpp:1.12  Wed Feb  1 12:10:56 2006
+++ llvm/lib/Target/MRegisterInfo.cpp   Tue Mar 28 07:48:33 2006
@@ -12,6 +12,11 @@
 
//===--===//
 
 #include "llvm/Target/MRegisterInfo.h"
+
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineLocation.h"
+
 using namespace llvm;
 
 MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
@@ -38,3 +43,14 @@
   }
   return Allocatable;
 }
+
+/// getLocation - This method should return the actual location of a frame
+/// variable given the frame index.  The location is returned in ML.
+/// Subclasses should override this method for special handling of frame
+/// variables and then call MRegisterInfo::getLocation for the default action.
+void MRegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
+MachineLocation &ML) const {
+  MachineFrameInfo *MFI = MF.getFrameInfo();
+  ML.set(getFrameRegister(MF),
+ MFI->getObjectOffset(Index) + MFI->getStackSize());
+}



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86RegisterInfo.h

2006-03-28 Thread Jim Laskey 


Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.132 -> 1.133
X86RegisterInfo.h updated: 1.35 -> 1.36
---
Log message:

Expose base register for DwarfWriter.  Refactor code accordingly.


---
Diffs of the changes:  (+4 -11)

 X86RegisterInfo.cpp |   11 ++-
 X86RegisterInfo.h   |4 ++--
 2 files changed, 4 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.132 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.133
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.132   Mon Mar 27 14:18:45 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Mar 28 07:48:33 2006
@@ -686,15 +686,8 @@
   }
 }
 
-void X86RegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
-  MachineLocation &ML) const {
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  bool FP = hasFP(MF);
-  
-  // FIXME - Needs to handle register variables.
-  // FIXME - Hardcoding gcc numbering.
-  ML.set(getDwarfRegNum(FP ? X86::EBP : X86::ESP),
- MFI->getObjectOffset(Index) + MFI->getStackSize());
+unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
+  return getDwarfRegNum(hasFP(MF) ? X86::EBP : X86::ESP);
 }
 
 #include "X86GenRegisterInfo.inc"


Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.35 
llvm/lib/Target/X86/X86RegisterInfo.h:1.36
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.35  Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.h   Tue Mar 28 07:48:33 2006
@@ -63,8 +63,8 @@
   void emitPrologue(MachineFunction &MF) const;
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
 
-  void getLocation(MachineFunction &MF, unsigned Index,
-   MachineLocation &ML) const;
+  // Debug information queries.
+  unsigned getFrameRegister(MachineFunction &MF) const;
 };
 
 } // End llvm namespace



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h

2006-03-28 Thread Jim Laskey 


Changes in directory llvm/include/llvm/Target:

MRegisterInfo.h updated: 1.72 -> 1.73
---
Log message:

Expose base register for DwarfWriter.  Refactor code accordingly.


---
Diffs of the changes:  (+11 -1)

 MRegisterInfo.h |   12 +++-
 1 files changed, 11 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.72 
llvm/include/llvm/Target/MRegisterInfo.h:1.73
--- llvm/include/llvm/Target/MRegisterInfo.h:1.72   Fri Mar 24 10:18:42 2006
+++ llvm/include/llvm/Target/MRegisterInfo.hTue Mar 28 07:48:33 2006
@@ -343,10 +343,20 @@
   virtual void emitEpilogue(MachineFunction &MF,
 MachineBasicBlock &MBB) const = 0;
 
+  
//======//
+  /// Debug information queries.
+
+  /// getFrameRegister - This method should return the register used as a base
+  /// for values allocated in the current stack frame.  This value should be
+  /// returned as a dwarf register number (getDwarfRegNum.)
+  virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
+
   /// getLocation - This method should return the actual location of a frame
   /// variable given the frame index.  The location is returned in ML.
+  /// Subclasses should override this method for special handling of frame
+  /// variables and call MRegisterInfo::getLocation for the default action.
   virtual void getLocation(MachineFunction &MF, unsigned Index,
-  MachineLocation &ML) const = 0;
+   MachineLocation &ML) const;
 };
 
 // This is useful when building DenseMaps keyed on virtual registers



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.cpp IA64RegisterInfo.h

2006-03-28 Thread Jim Laskey 


Changes in directory llvm/lib/Target/IA64:

IA64RegisterInfo.cpp updated: 1.15 -> 1.16
IA64RegisterInfo.h updated: 1.5 -> 1.6
---
Log message:

Expose base register for DwarfWriter.  Refactor code accordingly.


---
Diffs of the changes:  (+4 -12)

 IA64RegisterInfo.cpp |   13 ++---
 IA64RegisterInfo.h   |3 ++-
 2 files changed, 4 insertions(+), 12 deletions(-)


Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.15 
llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.16
--- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.15  Mon Mar 27 14:18:45 2006
+++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp   Tue Mar 28 07:48:33 2006
@@ -329,18 +329,9 @@
 
 }
 
-void IA64RegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
-   MachineLocation &ML) const {
-  assert(0 && "Needs to be defined for target");
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  bool FP = hasFP(MF);
-  
-  // FIXME - Needs to handle register variables.
-  // FIXME - Faking that llvm number is same as gcc numbering.
-  ML.set(getDwarfRegNum(FP ? IA64::r5 : IA64::r12),
- MFI->getObjectOffset(Index) + MFI->getStackSize());
+unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const {
+  return getDwarfRegNum(hasFP(MF) ? IA64::r5 : IA64::r12);
 }
 
-
 #include "IA64GenRegisterInfo.inc"
 


Index: llvm/lib/Target/IA64/IA64RegisterInfo.h
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.h:1.5 
llvm/lib/Target/IA64/IA64RegisterInfo.h:1.6
--- llvm/lib/Target/IA64/IA64RegisterInfo.h:1.5 Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/IA64/IA64RegisterInfo.h Tue Mar 28 07:48:33 2006
@@ -49,7 +49,8 @@
   void emitPrologue(MachineFunction &MF) const;
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
 
-  void getLocation(MachineFunction &MF, unsigned Index, MachineLocation &ML) 
const;
+  // Debug information queries.
+  unsigned getFrameRegister(MachineFunction &MF) const;
 };
 
 } // End llvm namespace



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

2006-03-28 Thread Jim Laskey 


Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.210 -> 1.211
---
Log message:

More bulletproofing of llvm.dbg.declare.


---
Diffs of the changes:  (+1 -1)

 SelectionDAGISel.cpp |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.210 
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.211
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.210Mon Mar 27 
18:40:09 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp  Tue Mar 28 07:45:20 2006
@@ -1390,7 +1390,7 @@
   case Intrinsic::dbg_declare: {
 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
 DbgDeclareInst &DI = cast(I);
-if (DebugInfo && DebugInfo->Verify(DI.getVariable())) {
+if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
   std::vector Ops;
 
   SDOperand AddressOp  = getValue(DI.getAddress());



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

2006-03-28 Thread Jim Laskey 


Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.139 -> 1.140
---
Log message:

Added missing paren on behalf of Ramana Radhakrishnan.


---
Diffs of the changes:  (+1 -1)

 X86ISelLowering.cpp |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.139 
llvm/lib/Target/X86/X86ISelLowering.cpp:1.140
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.139   Tue Mar 28 02:27:15 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 28 04:17:11 2006
@@ -2609,5 +2609,5 @@
   X86::isPSHUFDMask(Mask.Val) ||
   X86::isSHUFPMask(Mask.Val) ||
   X86::isUNPCKLMask(Mask.Val) ||
-  X86::isUNPCKHMask(Mask.Val);
+  X86::isUNPCKHMask(Mask.Val));
 }



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

2006-03-28 Thread Evan Cheng 


Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.138 -> 1.139
---
Log message:

Missed X86::isUNPCKHMask

---
Diffs of the changes:  (+2 -1)

 X86ISelLowering.cpp |3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.138 
llvm/lib/Target/X86/X86ISelLowering.cpp:1.139
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.138   Tue Mar 28 00:50:32 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 28 02:27:15 2006
@@ -2608,5 +2608,6 @@
   X86::isSplatMask(Mask.Val) ||
   X86::isPSHUFDMask(Mask.Val) ||
   X86::isSHUFPMask(Mask.Val) ||
-  X86::isUNPCKLMask(Mask.Val));
+  X86::isUNPCKLMask(Mask.Val) ||
+  X86::isUNPCKHMask(Mask.Val);
 }



___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits