[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.15 - 1.16
---
Log message:
movnt* and maskmovdqu intrinsics
---
Diffs of the changes: (+19 -4)
IntrinsicsX86.td | 23 +++
1 files changed, 19 insertions(+), 4 deletions(-)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.15
llvm/include/llvm/IntrinsicsX86.td:1.16
--- llvm/include/llvm/IntrinsicsX86.td:1.15 Mon Apr 10 17:02:38 2006
+++ llvm/include/llvm/IntrinsicsX86.td Tue Apr 11 01:56:27 2006
@@ -141,10 +141,9 @@
let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
def int_x86_sse_prefetch : GCCBuiltin__builtin_ia32_prefetch,
Intrinsic[llvm_ptr_ty, llvm_int_ty], [IntrWriteMem];
- def int_x86_sse_movntq : GCCBuiltin__builtin_ia32_movntq,
- Intrinsic[llvm_ptr_ty, llvm_v2i32_ty], [IntrWriteMem];
- def int_x86_sse_movntps : GCCBuiltin__builtin_ia32_movntps,
- Intrinsic[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem];
+ def int_x86_sse_movnt_ps : GCCBuiltin__builtin_ia32_movntps,
+ Intrinsic[llvm_void_ty, llvm_ptr_ty,
+ llvm_v4f32_ty], [IntrWriteMem];
def int_x86_sse_sfence : GCCBuiltin__builtin_ia32_sfence,
Intrinsic[llvm_void_ty], [IntrWriteMem];
}
@@ -281,6 +280,19 @@
llvm_v2f64_ty], [IntrWriteMem];
}
+// Cacheability support ops
+let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
+ def int_x86_sse2_movnt_dq : GCCBuiltin__builtin_ia32_movntdq,
+ Intrinsic[llvm_void_ty, llvm_ptr_ty,
+ llvm_v2i64_ty], [IntrWriteMem];
+ def int_x86_sse2_movnt_pd : GCCBuiltin__builtin_ia32_movntpd,
+ Intrinsic[llvm_void_ty, llvm_ptr_ty,
+ llvm_v2f64_ty], [IntrWriteMem];
+ def int_x86_sse2_movnt_i : GCCBuiltin__builtin_ia32_movnti,
+ Intrinsic[llvm_void_ty, llvm_ptr_ty,
+ llvm_int_ty], [IntrWriteMem];
+}
+
// Misc.
let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
def int_x86_sse2_packsswb_128 : GCCBuiltin__builtin_ia32_packsswb128,
@@ -296,6 +308,9 @@
Intrinsic[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem];
def int_x86_sse2_pmovmskb_128 : GCCBuiltin__builtin_ia32_pmovmskb128,
Intrinsic[llvm_int_ty, llvm_v16i8_ty], [IntrNoMem];
+ def int_x86_sse2_maskmov_dqu : GCCBuiltin__builtin_ia32_maskmovdqu,
+ Intrinsic[llvm_void_ty, llvm_v16i8_ty,
+ llvm_v16i8_ty, llvm_ptr_ty], [IntrWriteMem];
}
//===--===//
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrMMX.td X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrMMX.td updated: 1.9 - 1.10
X86InstrSSE.td updated: 1.73 - 1.74
---
Log message:
movnt* and maskmovdqu intrinsics
---
Diffs of the changes: (+44 -16)
X86InstrMMX.td | 25 +
X86InstrSSE.td | 35 +++
2 files changed, 44 insertions(+), 16 deletions(-)
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.9
llvm/lib/Target/X86/X86InstrMMX.td:1.10
--- llvm/lib/Target/X86/X86InstrMMX.td:1.9 Sat Mar 25 00:00:03 2006
+++ llvm/lib/Target/X86/X86InstrMMX.td Tue Apr 11 01:57:30 2006
@@ -13,6 +13,13 @@
//
//===--===//
+// Instruction templates
+// MMXi8 - MMX instructions with ImmT == Imm8 and TB prefix.
+class MMXIi8bits8 o, Format F, dag ops, string asm, listdag pattern
+ : X86Insto, F, Imm8, ops, asm, TB, Requires[HasMMX] {
+ let Pattern = pattern;
+}
+
// Some 'special' instructions
def IMPLICIT_DEF_VR64 : I0, Pseudo, (ops VR64:$dst),
#IMPLICIT_DEF $dst,
@@ -50,3 +57,21 @@
def CVTTPS2PIrm: I0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
cvttps2pi {$src, $dst|$dst, $src}, [], TB,
Requires[HasMMX];
+
+// Shuffle and unpack instructions
+def PSHUFWri : MMXIi80x70, MRMSrcReg,
+ (ops VR64:$dst, VR64:$src1, i8imm:$src2),
+ pshufw {$src2, $src1, $dst|$dst, $src1, $src2}, [];
+def PSHUFWmi : MMXIi80x70, MRMSrcMem,
+ (ops VR64:$dst, i64mem:$src1, i8imm:$src2),
+ pshufw {$src2, $src1, $dst|$dst, $src1, $src2}, [];
+
+// Misc.
+def MOVNTQ : I0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
+ movntq {$src, $dst|$dst, $src}, [], TB,
+ Requires[HasMMX];
+
+def MASKMOVQ : I0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask),
+ maskmovq {$mask, $src|$src, $mask}, [], TB,
+ Requires[HasMMX];
+
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.73
llvm/lib/Target/X86/X86InstrSSE.td:1.74
--- llvm/lib/Target/X86/X86InstrSSE.td:1.73 Mon Apr 10 19:19:04 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 11 01:57:30 2006
@@ -1321,13 +1321,6 @@
}
// Shuffle and unpack instructions
-def PSHUFWri : PSIi80x70, MRMSrcReg,
- (ops VR64:$dst, VR64:$src1, i8imm:$src2),
- pshufw {$src2, $src1, $dst|$dst, $src1, $src2}, [];
-def PSHUFWmi : PSIi80x70, MRMSrcMem,
- (ops VR64:$dst, i64mem:$src1, i8imm:$src2),
- pshufw {$src2, $src1, $dst|$dst, $src1, $src2}, [];
-
def PSHUFDri : PDIi80x70, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, i8imm:$src2),
pshufd {$src2, $src1, $dst|$dst, $src1, $src2},
@@ -1516,6 +1509,12 @@
pmovmskb {$src, $dst|$dst, $src},
[(set R32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))];
+// Conditional store
+def MASKMOVDQU : PDI0xF7, RawFrm, (ops VR128:$src, VR128:$mask),
+ maskmovdqu {$mask, $src|$src, $mask},
+ [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask,
EDI)],
+ Imp[EDI],[];
+
// Prefetching loads
def PREFETCHT0 : I0x18, MRM1m, (ops i8mem:$src),
prefetcht0 $src, [], TB,
@@ -1531,15 +1530,19 @@
Requires[HasSSE1];
// Non-temporal stores
-def MOVNTQ : I0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
- movntq {$src, $dst|$dst, $src}, [], TB,
- Requires[HasSSE1];
-def MOVNTPS : I0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
-movntps {$src, $dst|$dst, $src}, [], TB,
- Requires[HasSSE1];
-def MASKMOVQ : I0xF7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
- maskmovq {$src, $dst|$dst, $src}, [], TB,
- Requires[HasSSE1];
+def MOVNTPSmr : PSI0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
+movntps {$src, $dst|$dst, $src},
+[(int_x86_sse_movnt_ps addr:$dst, VR128:$src)];
+def MOVNTPDmr : PDI0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
+movntpd {$src, $dst|$dst, $src},
+[(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)];
+def MOVNTDQmr : PDI0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
+movntdq {$src, $dst|$dst, $src},
+[(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)];
+def MOVNTImr : I0xC3, MRMDestMem, (ops i32mem:$dst, R32:$src),
+movnti {$src, $dst|$dst, $src},
+[(int_x86_sse2_movnt_i addr:$dst, R32:$src)],
+ TB, Requires[HasSSE2];
// Store fence
def SFENCE : I0xAE, MRM7m, (ops),
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.54 - 1.55
---
Log message:
Suppress debug label when not debug.
---
Diffs of the changes: (+1 -1)
PPCRegisterInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.54
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.55
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.54Fri Apr 7 11:34:45 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Apr 11 03:11:53 2006
@@ -407,7 +407,7 @@
.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
}
- if (DebugInfo) {
+ if (DebugInfo DebugInfo-hasInfo()) {
std::vectorMachineMove * Moves = DebugInfo-getFrameMoves();
unsigned LabelID = DebugInfo-NextLabelID();
___
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[llvm-commits] CVS: llvm/CREDITS.TXT
Changes in directory llvm: CREDITS.TXT updated: 1.48 - 1.49 --- Log message: Update credibility. --- Diffs of the changes: (+1 -0) CREDITS.TXT |1 + 1 files changed, 1 insertion(+) Index: llvm/CREDITS.TXT diff -u llvm/CREDITS.TXT:1.48 llvm/CREDITS.TXT:1.49 --- llvm/CREDITS.TXT:1.48 Tue Apr 11 00:48:40 2006 +++ llvm/CREDITS.TXTTue Apr 11 03:16:45 2006 @@ -89,6 +89,7 @@ N: Jim Laskey E: [EMAIL PROTECTED] D: Improvements to the PPC backend, instruction scheduling +D: Debug implementation, Dwarf implementation N: Chris Lattner E: [EMAIL PROTECTED] ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.16 - 1.17
---
Log message:
Misc. intrinsics.
---
Diffs of the changes: (+2 -1)
IntrinsicsX86.td |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.16
llvm/include/llvm/IntrinsicsX86.td:1.17
--- llvm/include/llvm/IntrinsicsX86.td:1.16 Tue Apr 11 01:56:27 2006
+++ llvm/include/llvm/IntrinsicsX86.td Tue Apr 11 12:35:57 2006
@@ -140,7 +140,8 @@
// Cacheability support ops
let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
def int_x86_sse_prefetch : GCCBuiltin__builtin_ia32_prefetch,
- Intrinsic[llvm_ptr_ty, llvm_int_ty], [IntrWriteMem];
+ Intrinsic[llvm_void_ty, llvm_ptr_ty,
+ llvm_int_ty], [IntrWriteMem];
def int_x86_sse_movnt_ps : GCCBuiltin__builtin_ia32_movntps,
Intrinsic[llvm_void_ty, llvm_ptr_ty,
llvm_v4f32_ty], [IntrWriteMem];
___
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[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.17 - 1.18
---
Log message:
gcc lower SSE prefetch into generic prefetch intrinsic. Need to add support
later.
---
Diffs of the changes: (+0 -3)
IntrinsicsX86.td |3 ---
1 files changed, 3 deletions(-)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.17
llvm/include/llvm/IntrinsicsX86.td:1.18
--- llvm/include/llvm/IntrinsicsX86.td:1.17 Tue Apr 11 12:35:57 2006
+++ llvm/include/llvm/IntrinsicsX86.td Tue Apr 11 13:04:57 2006
@@ -139,9 +139,6 @@
// Cacheability support ops
let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
- def int_x86_sse_prefetch : GCCBuiltin__builtin_ia32_prefetch,
- Intrinsic[llvm_void_ty, llvm_ptr_ty,
- llvm_int_ty], [IntrWriteMem];
def int_x86_sse_movnt_ps : GCCBuiltin__builtin_ia32_movntps,
Intrinsic[llvm_void_ty, llvm_ptr_ty,
llvm_v4f32_ty], [IntrWriteMem];
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.75 - 1.76 --- Log message: gcc lower SSE prefetch into generic prefetch intrinsic. Need to add support later. --- Diffs of the changes: (+4 -8) X86InstrSSE.td | 12 1 files changed, 4 insertions(+), 8 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.75 llvm/lib/Target/X86/X86InstrSSE.td:1.76 --- llvm/lib/Target/X86/X86InstrSSE.td:1.75 Tue Apr 11 12:35:57 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 11 13:04:57 2006 @@ -1517,17 +1517,13 @@ // Prefetching loads def PREFETCHT0 : PSI0x18, MRM1m, (ops i8mem:$src), - prefetcht0 $src, - [(int_x86_sse_prefetch addr:$src, 1)]; + prefetcht0 $src, []; def PREFETCHT1 : PSI0x18, MRM2m, (ops i8mem:$src), - prefetcht1 $src, - [(int_x86_sse_prefetch addr:$src, 2)]; + prefetcht1 $src, []; def PREFETCHT2 : PSI0x18, MRM3m, (ops i8mem:$src), - prefetcht2 $src, - [(int_x86_sse_prefetch addr:$src, 3)]; + prefetcht2 $src, []; def PREFETCHTNTA : PSI0x18, MRM0m, (ops i8mem:$src), - prefetchtnta $src, - [(int_x86_sse_prefetch addr:$src, 0)]; + prefetchtnta $src, []; // Non-temporal stores def MOVNTPSmr : PSI0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.55 - 1.56
---
Log message:
Fix PR727: http://llvm.cs.uiuc.edu/PR727 , correctly handling large stack
aligments on ppc
---
Diffs of the changes: (+28 -32)
PPCRegisterInfo.cpp | 60
1 files changed, 28 insertions(+), 32 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.55
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.56
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.55Tue Apr 11 03:11:53 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Apr 11 14:29:21 2006
@@ -202,12 +202,10 @@
const MachineFrameInfo *MFI = MF.getFrameInfo();
unsigned TargetAlign = MF.getTarget().getFrameInfo()-getStackAlignment();
- // If frame pointers are forced, if there are variable sized stack objects,
- // or if there is an object on the stack that requires more alignment than is
- // normally provided, use a frame pointer.
+ // If frame pointers are forced, or if there are variable sized stack
objects,
+ // use a frame pointer.
//
- return NoFramePointerElim || MFI-hasVarSizedObjects() ||
- MFI-getMaxAlignment() TargetAlign;
+ return NoFramePointerElim || MFI-hasVarSizedObjects();
}
void PPCRegisterInfo::
@@ -396,15 +394,26 @@
int NegNumbytes = -NumBytes;
// Adjust stack pointer: r1 -= numbytes.
- if (NumBytes = 32768) {
-BuildMI(MBB, MBBI, PPC::STWU, 3)
- .addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
+ // If there is a preferred stack alignment, align R1 now
+ if (MaxAlign TargetAlign) {
+assert(isPowerOf2_32(MaxAlign) MaxAlign 32767 Invalid
alignment!);
+assert(NumBytes = 32768 Unhandled stack size and alignment combo!);
+BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
+ .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
+BuildMI(MBB, MBBI,
PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0).addSImm(MaxAlign);
+BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R0).addReg(PPC::R0)
+ .addSImm(NegNumbytes);
+BuildMI(MBB, MBBI, PPC::STWUX, 3)
+ .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
+ } else if (NumBytes = 32768) {
+BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addSImm(NegNumbytes)
+ .addReg(PPC::R1);
} else {
BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes 16);
-BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0)
-.addReg(PPC::R0).addImm(NegNumbytes 0x);
-BuildMI(MBB, MBBI, PPC::STWUX, 3)
-.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
+BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
+ .addImm(NegNumbytes 0x);
+BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
+ .addReg(PPC::R0);
}
if (DebugInfo DebugInfo-hasInfo()) {
@@ -419,19 +428,6 @@
BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addSImm(LabelID);
}
- // If there is a preferred stack alignment, align R1 now
- // FIXME: If this ever matters, this could be made more efficient by folding
- // this into the code above, so that we don't issue two store+update
- // instructions.
- if (MaxAlign TargetAlign) {
-assert(isPowerOf2_32(MaxAlign) MaxAlign 32767 Invalid
alignment!);
-BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
- .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
-BuildMI(MBB, MBBI, PPC::SUBFIC,
2,PPC::R0).addReg(PPC::R0).addImm(MaxAlign);
-BuildMI(MBB, MBBI, PPC::STWUX, 3)
- .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
- }
-
// If there is a frame pointer, copy R1 (SP) into R31 (FP)
if (HasFP) {
BuildMI(MBB, MBBI, PPC::STW, 3)
@@ -446,8 +442,12 @@
assert(MBBI-getOpcode() == PPC::BLR
Can only insert epilog into returning blocks);
+ // Get alignment info so we know how to restore r1
+ const MachineFrameInfo *MFI = MF.getFrameInfo();
+ unsigned TargetAlign = MF.getTarget().getFrameInfo()-getStackAlignment();
+
// Get the number of bytes allocated from the FrameInfo.
- unsigned NumBytes = MF.getFrameInfo()-getStackSize();
+ unsigned NumBytes = MFI-getStackSize();
unsigned GPRSize = 4;
if (NumBytes != 0) {
@@ -460,15 +460,11 @@
// The loaded (or persistent) stack pointer value is offseted by the 'stwu'
// on entry to the function. Add this offset back now.
-if (NumBytes 32768) {
+if (NumBytes 32768 TargetAlign = MFI-getMaxAlignment()) {
BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
.addReg(PPC::R1).addSImm(NumBytes);
} else {
- BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NumBytes 16);
- BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0)
- .addReg(PPC::R0).addImm(NumBytes 0x);
- BuildMI(MBB, MBBI, PPC::ADD4, 2, PPC::R1)
-.addReg(PPC::R0).addReg(PPC::R1);
+ BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
}
}
}
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.56 - 1.57
---
Log message:
Fix SingleSource/UnitTests/Vector/sumarray-dbl
---
Diffs of the changes: (+3 -4)
PPCRegisterInfo.cpp |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.56
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.57
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.56Tue Apr 11 14:29:21 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Apr 11 14:44:43 2006
@@ -397,12 +397,11 @@
// If there is a preferred stack alignment, align R1 now
if (MaxAlign TargetAlign) {
assert(isPowerOf2_32(MaxAlign) MaxAlign 32767 Invalid
alignment!);
-assert(NumBytes = 32768 Unhandled stack size and alignment combo!);
+assert(isInt16(MaxAlign-NumBytes) Unhandled stack size and
alignment!);
BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
.addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
-BuildMI(MBB, MBBI,
PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0).addSImm(MaxAlign);
-BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R0).addReg(PPC::R0)
- .addSImm(NegNumbytes);
+BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
+ .addSImm(MaxAlign-NumBytes);
BuildMI(MBB, MBBI, PPC::STWUX, 3)
.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
} else if (NumBytes = 32768) {
___
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[llvm-commits] CVS: llvm/docs/HowToReleaseLLVM.html
Changes in directory llvm/docs: HowToReleaseLLVM.html updated: 1.5 - 1.6 --- Log message: First pass over Reid's document. Changed the order of operations so that more of the fine tuning is performed in the release branch. This should free up mainline sooner to resume development. Removed information on the special release Makefile targets as I've never used them for a release; Tanya is investigating their integration, and they can be re-added if she uses them. Added an outline for building the LLVM GCC binary distributions. I will be filling that section out later (but before the 1.7 release). --- Diffs of the changes: (+186 -42) HowToReleaseLLVM.html | 228 -- 1 files changed, 186 insertions(+), 42 deletions(-) Index: llvm/docs/HowToReleaseLLVM.html diff -u llvm/docs/HowToReleaseLLVM.html:1.5 llvm/docs/HowToReleaseLLVM.html:1.6 --- llvm/docs/HowToReleaseLLVM.html:1.5 Tue Apr 11 01:22:15 2006 +++ llvm/docs/HowToReleaseLLVM.html Tue Apr 11 15:24:28 2006 @@ -24,9 +24,21 @@ div class=doc_text pThis document collects information about successfully releasing LLVM to the public. It is the release manager's guide to ensuring that a high quality build -of LLVM is released. Mostly, its just a bunch of reminders of things to do at +of LLVM is released. Mostly, it's just a bunch of reminders of things to do at release time so we don't inadvertently ship something that is utility deficient./p + +p +There are three main tasks for building a release of LLVM: +ol + liCreate the LLVM source distribution./li + liCreate the LLVM GCC source distribtuion./li + liCreate a set of LLVM GCC binary distribtuions for each supported + platform. These binary distributions must include compiled versions + of the libraries found in ttllvm/runtime/tt from the LLVM + source distribution created in Step 1./li +/ol +/p /div !-- *** -- @@ -37,46 +49,143 @@ div class=doc_subsectiona name=overviewProcess Overview/a/div div class=doc_text ol +lia href=#updocsUpdate Documentation/a/li lia href=#mergeMerge Branches/a/li +lia href=#depsMake LibDeps.txt/a/li lia href=#settleSettle LLVM HEAD/a/li +lia href=#tagTag LLVM and Create the Release Branch/a/li lia href=#buildBuild LLVM/a/li lia href=#checkRun 'make check'/a/li lia href=#testRun LLVM Test Suite/a/li -lia href=#depsmake LibDeps.txt/a/li -lia href=#tagcvs tag/a/li -lia href=#distmake dist/a/li -lia href=#releaserelease/a/li +lia href=#distBuild the LLVM Source Distributions/a/li +lia href=#llvmgccbinBuild the LLVM GCC Binary Distribution/a/li /ol /div !-- === -- +div class=doc_subsectiona name=updocsUpdate Documentation/a/div +div class=doc_text + p + Review the documentation and ensure that it is up to date. The Release Notes + must be updated to reflect bug fixes, new known issues, and changes in the + list of supported platforms. The Getting Started Guide should be updated to + reflect the new release version number tag avaiable from CVS and changes in + basic system requirements. + /p +/div + +!-- === -- div class=doc_subsectiona name=mergeMerge Branches/a/div div class=doc_text -pMerge any work done on branches intended for release into mainline. Work that -is not to be incorporated into the release should not be merged from the branch. +p +Merge any work done on branches intended for release into mainline. Finish and +commit all new features or bug fixes that are scheduled to go into the release. +Work that is not to be incorporated into the release should not be merged from +branchs or commited from developer's working directories. +/p + +p +From this point until the release branch is created, developers should +emnot/em +commit changes to the llvm and llvm-gcc CVS repositories unless it is a bug +fix emfor the release/em. /p /div !-- === -- +div class=doc_subsectiona name=depsMake LibDeps.txt/a/div +div class=doc_text + pRebuild the ttLibDeps.txt/tt target in ttutils/llvm-config/tt. This + makes sure that the ttllvm-config/tt utility remains relevant for the + release, reflecting any changes in the library dependencies./p +/div + + +!-- === -- div class=doc_subsectiona name=settleSettle CVS HEAD/a/div div class=doc_text - pUse the nightly test reports, and 'make check' (deja-gnu based tests) to - increase the quality of LLVM and ensure that merged branches have not - destabilized LLVM./p + p + Use the nightly test reports and 'make check' (deja-gnu based tests) to + ensure that recent changes and merged branches have not destabilized LLVM. +
[llvm-commits] CVS: llvm/docs/HowToReleaseLLVM.html
Changes in directory llvm/docs: HowToReleaseLLVM.html updated: 1.6 - 1.7 --- Log message: Add the contents of my email about distribution targets as a new section. Attribute John as an author. --- Diffs of the changes: (+170 -3) HowToReleaseLLVM.html | 173 +- 1 files changed, 170 insertions(+), 3 deletions(-) Index: llvm/docs/HowToReleaseLLVM.html diff -u llvm/docs/HowToReleaseLLVM.html:1.6 llvm/docs/HowToReleaseLLVM.html:1.7 --- llvm/docs/HowToReleaseLLVM.html:1.6 Tue Apr 11 15:24:28 2006 +++ llvm/docs/HowToReleaseLLVM.html Tue Apr 11 16:59:37 2006 @@ -12,9 +12,11 @@ ol lia href=#introductionIntroduction/a/li lia href=#processRelease Process/a/li + lia href=#distDistribution Make Targets/a/li /ol div class=doc_author - pWritten by a href=mailto:[EMAIL PROTECTED]Reid Spencer/a/p + pWritten by a href=mailto:[EMAIL PROTECTED]Reid Spencer/a, + a href=mailto:[EMAIL PROTECTED]John Criswell/a/p /div !-- *** -- @@ -273,7 +275,6 @@ /div !-- -!-- === -- div class=doc_subsectiona name=releaseRelease/a/div div class=doc_text pRelease the distribution tarball to the public. This consists of generating @@ -291,6 +292,172 @@ -- !-- *** -- +div class=doc_sectiona name=distDistribution Make Targets/a/div +!-- *** -- +!-- === -- +div class=doc_subsectionOverview/div +div class=doc_text +pThe first thing you need to understand is that there are multiple make +targets to support this feature. Here's an overview, we'll delve into the +details later./p +ul + libdistdir/b - builds the distribution directory from which the + distribution will be packaged/li + libdist/b - builds each of the distribution tarballs (tar.gz, + tar.bzip2, .zip). These can be built individually as well, with separate + targets./li + libdist-check/b - this is identical to ttdist/tt but includes a + check on the distribution that ensures the tarball can: unpack successfully, + compile correctly, pass 'make check', and pass 'make clean'./li + libdist-clean/b- this just does a normal clean but also cleans up the + stuff generated by the other three ttdist/tt targets (above)./li +/ul +pOkay, that's the basic functionality. When making a release, we want to +ensure that the tree you build the distribution from passes +ttdist-check/tt. Beyond fixing the usual bugs, there is generally one +impediment to making the release in this fashion: missing files. The +ttdist-check/tt process guards against that possibility. It will either +fail and that failure will indicate what's missing, or it will succeed +meaning that it has proved that the tarballs can actually succeed in +building LLVM correctly and that it passes ttmake check/tt./p +!-- === -- +div class=doc_subsectiondistdir/div +pThis target builds the distribution directory which is the directory from +which the tarballs are generated. The distribution directory has the same +name as the release, e.g. LLVM-1.7). This target goes through the following +process: +ol + liFirst, if there was an old distribution directory (for the current + release), it is removed in its entirety and you see ttRemoving old + LLVM-1.7/tt/li + liSecond, it issues a ttmake all ENABLE_OPTIMIZED=3D1/tt to ensure + that the everything in your tree can be built in release mode. Often times + there are discrepancies in building between debug and release modes so it + enforces release mode first. If that fails, the ttdistdir/tt target + fails too. This is preceded by the message ttMaking 'all' to verify + build/tt./li + liNext, it traverses your source tree and copies it to a new directory + that has the name of the release (ttLLVM-M.m/tt in our current case). + This is the directory that will get tar'd. It contains all the software + that needs to be in the distribution. During the copying process, it omits + generated files, CVS directories, and any other cruft that's in your + build tree. This is done to eliminate the possibility of huge distribution + tarballs that include useless or irrelevant stuff in them. This is the + trickiest part of making the distribution. Done manually you will either + include stuff that shouldn't be in the distribution or exclude stuff that + should. This step is preceded by the message ttBuilding Distribution + Directory LLVM-1.7/tt/li + liThe distribution directory is then traversed and all ttCVS/tt or + tt.svn/tt directories are removed. You see: ttEliminating CVS/.svn + directories from distribution/tt/li + liThe recursive
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.18 - 1.19
---
Log message:
Added __builtin_ia32_storelv4si, __builtin_ia32_movqv4si,
__builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu.
---
Diffs of the changes: (+11 -0)
IntrinsicsX86.td | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.18
llvm/include/llvm/IntrinsicsX86.td:1.19
--- llvm/include/llvm/IntrinsicsX86.td:1.18 Tue Apr 11 13:04:57 2006
+++ llvm/include/llvm/IntrinsicsX86.td Tue Apr 11 17:28:25 2006
@@ -269,6 +269,8 @@
let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
def int_x86_sse2_loadu_pd : GCCBuiltin__builtin_ia32_loadupd,
Intrinsic[llvm_v2f64_ty, llvm_ptr_ty], [IntrReadMem];
+ def int_x86_sse2_loadu_dq : GCCBuiltin__builtin_ia32_loaddqu,
+ Intrinsic[llvm_v16i8_ty, llvm_ptr_ty], [IntrReadMem];
}
// SIMD store ops
@@ -276,6 +278,12 @@
def int_x86_sse2_storeu_pd : GCCBuiltin__builtin_ia32_storeupd,
Intrinsic[llvm_void_ty, llvm_ptr_ty,
llvm_v2f64_ty], [IntrWriteMem];
+ def int_x86_sse2_storeu_dq : GCCBuiltin__builtin_ia32_storedqu,
+ Intrinsic[llvm_void_ty, llvm_ptr_ty,
+ llvm_v16i8_ty], [IntrWriteMem];
+ def int_x86_sse2_storel_dq : GCCBuiltin__builtin_ia32_storelv4si,
+ Intrinsic[llvm_void_ty, llvm_ptr_ty,
+ llvm_v4i32_ty], [IntrWriteMem];
}
// Cacheability support ops
@@ -302,6 +310,9 @@
def int_x86_sse2_packuswb_128 : GCCBuiltin__builtin_ia32_packuswb128,
Intrinsic[llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v8i16_ty], [IntrNoMem];
+ // FIXME: Temporary workaround since 2-wide shuffle is broken.
+ def int_x86_sse2_movl_dq : GCCBuiltin__builtin_ia32_movqv4si,
+ Intrinsic[llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem];
def int_x86_sse2_movmskpd : GCCBuiltin__builtin_ia32_movmskpd,
Intrinsic[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem];
def int_x86_sse2_pmovmskb_128 : GCCBuiltin__builtin_ia32_pmovmskb128,
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.76 - 1.77
---
Log message:
Added __builtin_ia32_storelv4si, __builtin_ia32_movqv4si,
__builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu.
---
Diffs of the changes: (+21 -2)
X86InstrSSE.td | 23 +--
1 files changed, 21 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.76
llvm/lib/Target/X86/X86InstrSSE.td:1.77
--- llvm/lib/Target/X86/X86InstrSSE.td:1.76 Tue Apr 11 13:04:57 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 11 17:28:25 2006
@@ -724,6 +724,14 @@
def MOVUPDmr : PDI0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
movupd {$src, $dst|$dst, $src},
[(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)];
+def MOVDQUrm : I0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
+ movdqu {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))],
+ XS, Requires[HasSSE2];
+def MOVDQUmr : I0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
+ movdqu {$src, $dst|$dst, $src},
+ [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
+ XS, Requires[HasSSE2];
let isTwoAddress = 1 in {
def MOVLPSrm : PSI0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
@@ -1657,6 +1665,16 @@
MOVS_shuffle_mask)))];
}
+// Store / copy lower 64-bits of a XMM register.
+def MOVLQ128mr : PDI0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
+ movq {$src, $dst|$dst, $src},
+ [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)];
+
+// FIXME: Temporary workaround since 2-wide shuffle is broken.
+def MOVLQ128rr : PDI0xD6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ movq {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))];
+
// Move to lower bits of a VR128 and zeroing upper bits.
// Loading from memory automatically zeroing upper bits.
def MOVZSS2PSrm : SSI0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
@@ -1672,9 +1690,10 @@
[(set VR128:$dst,
(v4i32 (X86zexts2vec (loadi32 addr:$src];
def MOVZQI2PQIrm : PDI0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
- movd {$src, $dst|$dst, $src},
+ movq {$src, $dst|$dst, $src},
[(set VR128:$dst,
- (v2i64 (X86zexts2vec (loadi64 addr:$src];
+ (bc_v2i64 (v2f64 (X86zexts2vec
+ (loadf64 addr:$src)];
//===--===//
// Non-Instruction Patterns
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[llvm-commits] CVS: llvm/Makefile.rules
Changes in directory llvm: Makefile.rules updated: 1.360 - 1.361 --- Log message: Remove extraneous building in target dist-check. There is no reason that a distribution should need to be able to make a distribution so eliminate the make dist from the list of targets attempted. --- Diffs of the changes: (+0 -2) Makefile.rules |2 -- 1 files changed, 2 deletions(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.360 llvm/Makefile.rules:1.361 --- llvm/Makefile.rules:1.360 Mon Apr 10 11:46:04 2006 +++ llvm/Makefile.rules Tue Apr 11 22:07:02 2006 @@ -1502,8 +1502,6 @@ $(MAKE) check \ $(MAKE) install \ $(MAKE) uninstall \ - $(MAKE) dist \ - $(MAKE) clean \ $(MAKE) dist-clean \ $(EchoCmd) = $(DistTarGZip) Ready For Distribution = ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll
Changes in directory llvm/test/Regression/CodeGen/Generic:
2006-04-11-vecload.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+12 -0)
2006-04-11-vecload.ll | 12
1 files changed, 12 insertions(+)
Index: llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll
diff -c /dev/null llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll:1.1
*** /dev/null Tue Apr 11 22:24:56 2006
--- llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll Tue Apr 11
22:24:46 2006
***
*** 0
--- 1,12
+ ; RUN: llvm-as %s | llc
+
+ ; The vload was getting memoized to the previous scalar load!
+
+ void %VertexProgram2() {
+ %xFloat0.688 = load float* null ; float [#uses=0]
+ %loadVector37.712 = load 4 x float* null ; 4 x
float [#uses=1]
+ %inFloat3.713 = insertelement 4 x float %loadVector37.712, float
0.00e+00, uint 3 ; 4 x float [#uses=1]
+ store 4 x float %inFloat3.713, 4 x float* null
+ unreachable
+ }
+
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.297 - 1.298
---
Log message:
Don't memoize vloads in the load map! Don't memoize them anywhere here, let
getNode do it. This fixes CodeGen/Generic/2006-04-11-vecload.ll
---
Diffs of the changes: (+0 -2)
SelectionDAG.cpp |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.297
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.298
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.297Sat Apr 8
17:22:57 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Apr 11 22:25:41 2006
@@ -1508,8 +1508,6 @@
SDOperand SelectionDAG::getVecLoad(unsigned Count, MVT::ValueType EVT,
SDOperand Chain, SDOperand Ptr,
SDOperand SV) {
- SDNode *N = Loads[std::make_pair(Ptr, std::make_pair(Chain, EVT))];
- if (N) return SDOperand(N, 0);
std::vectorSDOperand Ops;
Ops.reserve(5);
Ops.push_back(Chain);
___
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[llvm-commits] CVS: llvm-www/OpenProjects.html
Changes in directory llvm-www: OpenProjects.html updated: 1.12 - 1.13 --- Log message: Nate went and did one of the projects, so remove it. The skeleton backend is no more. --- Diffs of the changes: (+1 -17) OpenProjects.html | 18 +- 1 files changed, 1 insertion(+), 17 deletions(-) Index: llvm-www/OpenProjects.html diff -u llvm-www/OpenProjects.html:1.12 llvm-www/OpenProjects.html:1.13 --- llvm-www/OpenProjects.html:1.12 Thu Mar 16 13:02:22 2006 +++ llvm-www/OpenProjects.html Tue Apr 11 23:18:36 2006 @@ -304,8 +304,6 @@ ol liImprove the instruction selectors./li -liImplement support for the switch instruction without requiring the -lower-switches pass./li liImplement interprocedural register allocation. The CallGraphSCCPass can be used to implement a bottom-up analysis that will determine the *actual* registers clobbered by a function. Use the pass to fine tune register usage @@ -314,20 +312,6 @@ (a href=docs/CompilerWriterInfo.html#armARM/a? a href=docs/CompilerWriterInfo.html#mipsMIPS/a? a href=http://www-cs-faculty.stanford.edu/~knuth/mmix.html;MMIX/a?)/li -liImprove the usefulness and utility of the Skeleton target backend: -ul - liConvert the non-functional Skeleton target to become an abstract machine - target (choose some simple instructions, a register set, etc). This will - become a much more useful example of a backend since it would be a simple - but emfunctional/em backend. Examples of such architectures include MIX, - MMIX, a - href=http://www.cs.cinvestav.mx/SC/prof_personal/adiaz/vhdl/DLX/;DLX/a, - or come up with your own!/li - liUse the new Skeleton backend in the Interpreter: compile LLVM to Skeleton - target, and then interpret that code instead of LLVM. Performance win would - be the primary goal, as the number of registers would be a small constant - instead of unbounded, for example./li -/ul/li /ol /div @@ -381,7 +365,7 @@ src=http://www.w3.org/Icons/valid-html401; alt=Valid HTML 4.01!/a a href=http://llvm.org;LLVM Compiler Infrastructure/abr - Last modified: $Date: 2006/03/16 19:02:22 $ + Last modified: $Date: 2006/04/12 04:18:36 $ /address !--#include virtual=footer.incl -- ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td
Changes in directory llvm/include/llvm:
IntrinsicsX86.td updated: 1.19 - 1.20
---
Log message:
Various SSE2 conversion intrinsics
---
Diffs of the changes: (+24 -0)
IntrinsicsX86.td | 24
1 files changed, 24 insertions(+)
Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.19
llvm/include/llvm/IntrinsicsX86.td:1.20
--- llvm/include/llvm/IntrinsicsX86.td:1.19 Tue Apr 11 17:28:25 2006
+++ llvm/include/llvm/IntrinsicsX86.td Wed Apr 12 00:20:24 2006
@@ -265,6 +265,30 @@
llvm_int_ty], [IntrNoMem];
}
+// Conversion ops
+let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
+ def int_x86_sse2_cvtdq2pd : GCCBuiltin__builtin_ia32_cvtdq2pd,
+ Intrinsic[llvm_v2f64_ty, llvm_v4i32_ty], [IntrNoMem];
+ def int_x86_sse2_cvtdq2ps : GCCBuiltin__builtin_ia32_cvtdq2ps,
+ Intrinsic[llvm_v4f32_ty, llvm_v4i32_ty], [IntrNoMem];
+ def int_x86_sse2_cvtpd2dq : GCCBuiltin__builtin_ia32_cvtpd2dq,
+ Intrinsic[llvm_v4i32_ty, llvm_v2f64_ty], [IntrNoMem];
+ def int_x86_sse2_cvttpd2dq : GCCBuiltin__builtin_ia32_cvttpd2dq,
+ Intrinsic[llvm_v4i32_ty, llvm_v2f64_ty], [IntrNoMem];
+ def int_x86_sse2_cvtpd2ps : GCCBuiltin__builtin_ia32_cvtpd2ps,
+ Intrinsic[llvm_v4f32_ty, llvm_v2f64_ty], [IntrNoMem];
+ def int_x86_sse2_cvtps2dq : GCCBuiltin__builtin_ia32_cvtps2dq,
+ Intrinsic[llvm_v4i32_ty, llvm_v4f32_ty], [IntrNoMem];
+ def int_x86_sse2_cvttps2dq : GCCBuiltin__builtin_ia32_cvttps2dq,
+ Intrinsic[llvm_v4i32_ty, llvm_v4f32_ty], [IntrNoMem];
+ def int_x86_sse2_cvtps2pd : GCCBuiltin__builtin_ia32_cvtps2pd,
+ Intrinsic[llvm_v2f64_ty, llvm_v4f32_ty], [IntrNoMem];
+ def int_x86_sse2_cvtsd2si : GCCBuiltin__builtin_ia32_cvtsd2si,
+ Intrinsic[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem];
+ def int_x86_sse2_cvttsd2si : GCCBuiltin__builtin_ia32_cvttsd2si,
+ Intrinsic[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem];
+}
+
// SIMD load ops
let TargetPrefix = x86 in { // All intrinsics start with llvm.x86..
def int_x86_sse2_loadu_pd : GCCBuiltin__builtin_ia32_loadupd,
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.77 - 1.78
---
Log message:
Various SSE2 conversion intrinsics
---
Diffs of the changes: (+94 -39)
X86InstrSSE.td | 133 -
1 files changed, 94 insertions(+), 39 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.77
llvm/lib/Target/X86/X86InstrSSE.td:1.78
--- llvm/lib/Target/X86/X86InstrSSE.td:1.77 Tue Apr 11 17:28:25 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 12 00:20:24 2006
@@ -524,6 +524,23 @@
[(set FR64:$dst, (fextend (loadf32 addr:$src)))], XS,
Requires[HasSSE2];
+// Aliases to match intrinsics which expect XMM operand(s).
+def Int_CVTTSD2SIrr: SDI0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
+ cvttsd2si {$src, $dst|$dst, $src},
+ [(set R32:$dst, (int_x86_sse2_cvttsd2si
VR128:$src))];
+def Int_CVTTSD2SIrm: SDI0x2C, MRMSrcMem, (ops R32:$dst, f128mem:$src),
+ cvttsd2si {$src, $dst|$dst, $src},
+ [(set R32:$dst, (int_x86_sse2_cvttsd2si
+ (load addr:$src)))];
+
+def CVTSD2SIrr: SDI0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
+cvtsd2si {$src, $dst|$dst, $src},
+[(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))];
+def CVTSD2SIrm: SDI0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src),
+cvtsd2si {$src, $dst|$dst, $src},
+[(set R32:$dst, (int_x86_sse2_cvtsd2si
+ (load addr:$src)))];
+
// Comparison instructions
let isTwoAddress = 1 in {
def CMPSSrr : SSI0xC2, MRMSrcReg,
@@ -800,62 +817,100 @@
}
// Conversion instructions
-def CVTPI2PSr : PSI0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
+def CVTPI2PSrr : PSI0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
cvtpi2ps {$src, $dst|$dst, $src}, [];
-def CVTPI2PSm : PSI0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
+def CVTPI2PSrm : PSI0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
cvtpi2ps {$src, $dst|$dst, $src}, [];
-def CVTPI2PDr : PDI0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
+def CVTPI2PDrr : PDI0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
cvtpi2pd {$src, $dst|$dst, $src}, [];
-def CVTPI2PDm : PDI0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
+def CVTPI2PDrm : PDI0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
cvtpi2pd {$src, $dst|$dst, $src}, [];
// SSE2 instructions without OpSize prefix
-def CVTDQ2PSr : I0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
- cvtdq2ps {$src, $dst|$dst, $src}, [], TB,
-Requires[HasSSE2];
-def CVTDQ2PSm : I0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
- cvtdq2ps {$src, $dst|$dst, $src}, [], TB,
-Requires[HasSSE2];
+def CVTDQ2PSrr : I0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ cvtdq2ps {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))],
+ TB, Requires[HasSSE2];
+def CVTDQ2PSrm : I0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
+ cvtdq2ps {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
+ (load addr:$src)))],
+ TB, Requires[HasSSE2];
// SSE2 instructions with XS prefix
-def CVTDQ2PDr : I0xE6, MRMSrcReg, (ops VR128:$dst, VR64:$src),
- cvtdq2pd {$src, $dst|$dst, $src}, [],
-XS, Requires[HasSSE2];
-def CVTDQ2PDm : I0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
- cvtdq2pd {$src, $dst|$dst, $src}, [],
-XS, Requires[HasSSE2];
+def CVTDQ2PDrr : I0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ cvtdq2pd {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
+ XS, Requires[HasSSE2];
+def CVTDQ2PDrm : I0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
+ cvtdq2pd {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
+ (load addr:$src)))],
+ XS, Requires[HasSSE2];
-def CVTPS2PIr : PSI0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
+def CVTPS2PIrr : PSI0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
cvtps2pi {$src, $dst|$dst, $src}, [];
-def CVTPS2PIm : PSI0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
+def CVTPS2PIrm : PSI0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
cvtps2pi {$src, $dst|$dst, $src}, [];
-def CVTPD2PIr : PDI0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
+def CVTPD2PIrr : PDI0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
cvtpd2pi {$src, $dst|$dst, $src}, [];
-def CVTPD2PIm : PDI0x2D, MRMSrcMem,
