[llvm-commits] CVS: llvm/Makefile.rules
Changes in directory llvm: Makefile.rules updated: 1.365 -> 1.366 --- Log message: Fix some problems linking stuff in libTarget. --- Diffs of the changes: (+1 -1) Makefile.rules |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.365 llvm/Makefile.rules:1.366 --- llvm/Makefile.rules:1.365 Thu Apr 20 13:42:24 2006 +++ llvm/Makefile.rules Wed May 10 22:10:15 2006 @@ -629,7 +629,7 @@ endif LLVMLIBS := $(JIT_LIBS) LLVMScalarOpts.a LLVMTransformUtils.a LLVMAnalysis.a \ -LLVMBCReader LLVMCore LLVMSupport.a LLVMTarget.a LLVMbzip2 \ +LLVMBCReader LLVMTarget.a LLVMCore LLVMSupport.a LLVMbzip2 \ LLVMSystem.a $(PLATFORMLIBDL) endif ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocLinearScan.cpp
Changes in directory llvm/lib/CodeGen:
RegAllocLinearScan.cpp updated: 1.120 -> 1.121
---
Log message:
If the live interval legnth is essentially zero, i.e. in every live range
the use follows def immediately, it doesn't make sense to spill it and
hope it will be easier to allocate for this LI.
---
Diffs of the changes: (+15 -1)
RegAllocLinearScan.cpp | 16 +++-
1 files changed, 15 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/RegAllocLinearScan.cpp
diff -u llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.120
llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.121
--- llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.120 Sat Mar 25 17:00:56 2006
+++ llvm/lib/CodeGen/RegAllocLinearScan.cpp Wed May 10 17:30:41 2006
@@ -406,6 +406,14 @@
}
}
+static bool isZeroLengthInterval(LiveInterval *li) {
+ for (LiveInterval::Ranges::const_iterator
+ i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
+if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
+ return false;
+ return true;
+}
+
/// assignRegOrStackSlotAtInterval - assign a register if one is available, or
/// spill.
@@ -557,10 +565,16 @@
DEBUG(std::cerr << "\t\tregister with min weight: "
<< mri_->getName(minReg) << " (" << minWeight << ")\n");
+ // If the live interval legnth is essentially zero, i.e. in every live range
+ // the use follows def immediately, it doesn't make sense to spill it and
+ // hope it will be easier to allocate for this li.
+ if (isZeroLengthInterval(cur))
+DEBUG(std::cerr << "\t\tavoid spilling zero length live interval: "
+ << *cur << '\n';);
// if the current has the minimum weight, we need to spill it and
// add any added intervals back to unhandled, and restart
// linearscan.
- if (cur->weight <= minWeight) {
+ else if (cur->weight <= minWeight) {
DEBUG(std::cerr << "\t\t\tspilling(c): " << *cur << '\n';);
int slot = vrm_->assignVirt2StackSlot(cur->reg);
std::vector added =
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/2006-05-08-InstrSched.ll
Changes in directory llvm/test/Regression/CodeGen/X86: 2006-05-08-InstrSched.ll updated: 1.1 -> 1.2 --- Log message: Update test case --- Diffs of the changes: (+1 -0) 2006-05-08-InstrSched.ll |1 + 1 files changed, 1 insertion(+) Index: llvm/test/Regression/CodeGen/X86/2006-05-08-InstrSched.ll diff -u llvm/test/Regression/CodeGen/X86/2006-05-08-InstrSched.ll:1.1 llvm/test/Regression/CodeGen/X86/2006-05-08-InstrSched.ll:1.2 --- llvm/test/Regression/CodeGen/X86/2006-05-08-InstrSched.ll:1.1 Tue May 9 02:20:24 2006 +++ llvm/test/Regression/CodeGen/X86/2006-05-08-InstrSched.ll Wed May 10 14:53:05 2006 @@ -1,3 +1,4 @@ +; RUN: llvm-as < %s | llc -march=x86 -relocation-model=static -sched-lower-defnuse && ; RUN: llvm-as < %s | llc -march=x86 -relocation-model=static -sched-lower-defnuse | not grep 'xorb $16, %cl' %A = external global ushort* ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.477 -> 1.478
---
Log message:
Two changes:
1. Implement InstCombine/deadcode.ll by not adding instructions in unreachable
blocks (due to constants in conditional branches/switches) to the worklist.
This causes them to be deleted before instcombine starts up, leading to
better optimization.
2. In the prepass over instructions, do trivial constprop/dce as we go. This
has the effect of improving the effectiveness of #1. In addition, it
*significantly* speeds up instcombine on test cases with large amounts of
constant folding code (for example, that produced by code specialization
or partial evaluation). In one example, it speeds up instcombine from
0.0589s to 0.0224s with a release build (a 2.6x speedup).
---
Diffs of the changes: (+72 -7)
InstructionCombining.cpp | 79 ++-
1 files changed, 72 insertions(+), 7 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.477
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.478
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.477 Sat May 6
04:00:16 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Wed May 10 14:00:36 2006
@@ -48,7 +48,6 @@
#include "llvm/Support/InstVisitor.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/PatternMatch.h"
-#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include
@@ -7318,17 +7317,83 @@
return true;
}
+
+/// AddReachableCodeToWorklist - Walk the function in depth-first order, adding
+/// all reachable code to the worklist.
+///
+/// This has a couple of tricks to make the code faster and more powerful. In
+/// particular, we constant fold and DCE instructions as we go, to avoid adding
+/// them to the worklist (this significantly speeds up instcombine on code
where
+/// many instructions are dead or constant). Additionally, if we find a branch
+/// whose condition is a known constant, we only visit the reachable
successors.
+///
+static void AddReachableCodeToWorklist(BasicBlock *BB,
+ std::set &Visited,
+ std::vector &WorkList) {
+ // We have now visited this block! If we've already been here, bail out.
+ if (!Visited.insert(BB).second) return;
+
+ for (BasicBlock::iterator BBI = BB->begin(), E = BB->end(); BBI != E; ) {
+Instruction *Inst = BBI++;
+
+// DCE instruction if trivially dead.
+if (isInstructionTriviallyDead(Inst)) {
+ ++NumDeadInst;
+ DEBUG(std::cerr << "IC: DCE: " << *Inst);
+ Inst->eraseFromParent();
+ continue;
+}
+
+// ConstantProp instruction if trivially constant.
+if (Constant *C = ConstantFoldInstruction(Inst)) {
+ DEBUG(std::cerr << "IC: ConstFold to: " << *C << " from: " << *Inst);
+ Inst->replaceAllUsesWith(C);
+ ++NumConstProp;
+ Inst->eraseFromParent();
+ continue;
+}
+
+WorkList.push_back(Inst);
+ }
+
+ // Recursively visit successors. If this is a branch or switch on a
constant,
+ // only visit the reachable successor.
+ TerminatorInst *TI = BB->getTerminator();
+ if (BranchInst *BI = dyn_cast(TI)) {
+if (BI->isConditional() && isa(BI->getCondition())) {
+ bool CondVal = cast(BI->getCondition())->getValue();
+ AddReachableCodeToWorklist(BI->getSuccessor(!CondVal), Visited,
WorkList);
+ return;
+}
+ } else if (SwitchInst *SI = dyn_cast(TI)) {
+if (ConstantInt *Cond = dyn_cast(SI->getCondition())) {
+ // See if this is an explicit destination.
+ for (unsigned i = 1, e = SI->getNumSuccessors(); i != e; ++i)
+if (SI->getCaseValue(i) == Cond) {
+ AddReachableCodeToWorklist(SI->getSuccessor(i), Visited, WorkList);
+ return;
+}
+
+ // Otherwise it is the default destination.
+ AddReachableCodeToWorklist(SI->getSuccessor(0), Visited, WorkList);
+ return;
+}
+ }
+
+ for (unsigned i = 0, e = TI->getNumSuccessors(); i != e; ++i)
+AddReachableCodeToWorklist(TI->getSuccessor(i), Visited, WorkList);
+}
+
bool InstCombiner::runOnFunction(Function &F) {
bool Changed = false;
TD = &getAnalysis();
{
-// Populate the worklist with the reachable instructions.
+// Do a depth-first traversal of the function, populate the worklist with
+// the reachable instructions. Ignore blocks that are not reachable. Keep
+// track of which blocks we visit.
std::set Visited;
-for (df_ext_iterator BB = df_ext_begin(&F.front(), Visited),
- E = df_ext_end(&F.front(), Visited); BB != E; ++BB)
- for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
-WorkList.push_back(I);
+AddReachableCodeToWorklist(F.begin(), Visited, Wor
[llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/deadcode.ll
Changes in directory llvm/test/Regression/Transforms/InstCombine:
deadcode.ll added (r1.1)
---
Log message:
New testcase, check that dead code doesn't pessimize instcombine
---
Diffs of the changes: (+12 -0)
deadcode.ll | 12
1 files changed, 12 insertions(+)
Index: llvm/test/Regression/Transforms/InstCombine/deadcode.ll
diff -c /dev/null llvm/test/Regression/Transforms/InstCombine/deadcode.ll:1.1
*** /dev/null Wed May 10 13:56:14 2006
--- llvm/test/Regression/Transforms/InstCombine/deadcode.ll Wed May 10
13:56:04 2006
***
*** 0
--- 1,12
+ ; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep 'ret int %A'
+
+ int %test(int %A) {
+ %X = or bool false, false
+ br bool %X, label %T, label %C
+ T:
+ %B = add int %A, 1
+ br label %C
+ C:
+ %C = phi int [%B, %T], [%A, %0]
+ ret int %C
+ }
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.65 -> 1.66
---
Log message:
Fix the PowerPC JIT-only failure on UnitTests/Vector/sumarray-dbl, which is
really a bad codegen bug that LLC happens to get lucky with. I must chat with
Nate for the proper fix.
---
Diffs of the changes: (+2 -2)
PPCRegisterInfo.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.65
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.66
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.65Thu May 4 12:52:23 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed May 10 01:38:32 2006
@@ -506,11 +506,11 @@
// If there is a preferred stack alignment, align R1 now
if (MaxAlign > TargetAlign) {
assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid
alignment!");
-assert(isInt16(MaxAlign-NumBytes) && "Unhandled stack size and
alignment!");
+assert(isInt16(0-NumBytes) && "Unhandled stack size and alignment!");
BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
.addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
- .addImm(MaxAlign-NumBytes);
+ .addImm(0-NumBytes);
BuildMI(MBB, MBBI, PPC::STWUX, 3)
.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
} else if (NumBytes <= 32768) {
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