[llvm-commits] CVS: llvm-www/Features.html
Changes in directory llvm-www: Features.html updated: 1.17 -> 1.18 --- Log message: Update --- Diffs of the changes: (+3 -3) Features.html |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm-www/Features.html diff -u llvm-www/Features.html:1.17 llvm-www/Features.html:1.18 --- llvm-www/Features.html:1.17 Sat Sep 2 19:03:59 2006 +++ llvm-www/Features.html Wed Nov 15 00:56:55 2006 @@ -5,7 +5,7 @@ following: - Front-ends for C and C++ based on the GCC 3.4 and 4.0.01 parsers. + Front-ends for C and C++ based on the GCC 3.4 and 4.0.1 parsers. They support the full ANSI-standard C and C++ languages, plus many GCC extensions. LLVM also includes a front-end for "Stacker", a @@ -27,9 +27,9 @@ optimizations. An easily retargettable code generator, which currently supports X86, - Sparc, PowerPC, Alpha, and IA-64. + X86-64, PowerPC, PowerPC-64, SPARC, Alpha, and IA-64. - A Just-In-Time (JIT) code generation system for X86, Sparc, + A Just-In-Time (JIT) code generation system for X86, X86-64, PowerPC and PowerPC-64. A C back-end useful for testing and for generating native code on targets ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.544 -> 1.545
---
Log message:
Fix a gcc 4.2 warning.
---
Diffs of the changes: (+2 -0)
InstructionCombining.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.544
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.545
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.544 Tue Nov 14
01:46:50 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Tue Nov 14 22:53:24 2006
@@ -2760,6 +2760,7 @@
}
// FoldSetCCLogical - Implements (setcc1 A, B) & (setcc2 A, B) --> (setcc3 A,
B)
+namespace {
struct FoldSetCCLogical {
InstCombiner ⁣
Value *LHS, *RHS;
@@ -2795,6 +2796,7 @@
return IC.ReplaceInstUsesWith(Log, RV);
}
};
+} // end anonymous namespace
// OptAndOp - This handles expressions of the form ((val OP C1) & C2). Where
// the Op parameter is 'OP', OpRHS is 'C1', and AndRHS is 'C2'. Op is
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[llvm-commits] CVS: llvm/include/llvm/DerivedTypes.h
Changes in directory llvm/include/llvm:
DerivedTypes.h updated: 1.71 -> 1.72
---
Log message:
Add a method to get the bit width of a packed type.
---
Diffs of the changes: (+6 -0)
DerivedTypes.h |6 ++
1 files changed, 6 insertions(+)
Index: llvm/include/llvm/DerivedTypes.h
diff -u llvm/include/llvm/DerivedTypes.h:1.71
llvm/include/llvm/DerivedTypes.h:1.72
--- llvm/include/llvm/DerivedTypes.h:1.71 Tue Feb 7 00:17:10 2006
+++ llvm/include/llvm/DerivedTypes.hTue Nov 14 21:02:41 2006
@@ -299,8 +299,14 @@
///
static PackedType *get(const Type *ElementType, unsigned NumElements);
+ /// @brief Return the number of elements in the Packed type.
inline unsigned getNumElements() const { return NumElements; }
+ /// @brief Return the number of bits in the Packed type.
+ inline unsigned getBitWidth() const {
+return NumElements *getElementType()->getPrimitiveSizeInBits();
+ }
+
// Implement the AbstractTypeUser interface.
virtual void refineAbstractType(const DerivedType *OldTy, const Type *NewTy);
virtual void typeBecameConcrete(const DerivedType *AbsTy);
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[llvm-commits] CVS: llvm/utils/TableGen/CodeGenInstruction.h CodeGenTarget.cpp InstrInfoEmitter.cpp
Changes in directory llvm/utils/TableGen:
CodeGenInstruction.h updated: 1.23 -> 1.24
CodeGenTarget.cpp updated: 1.77 -> 1.78
InstrInfoEmitter.cpp updated: 1.52 -> 1.53
---
Log message:
ADd support for adding constraints to suboperands
---
Diffs of the changes: (+111 -32)
CodeGenInstruction.h | 20 +++-
CodeGenTarget.cpp| 121 ++-
InstrInfoEmitter.cpp |2
3 files changed, 111 insertions(+), 32 deletions(-)
Index: llvm/utils/TableGen/CodeGenInstruction.h
diff -u llvm/utils/TableGen/CodeGenInstruction.h:1.23
llvm/utils/TableGen/CodeGenInstruction.h:1.24
--- llvm/utils/TableGen/CodeGenInstruction.h:1.23 Mon Nov 6 17:49:51 2006
+++ llvm/utils/TableGen/CodeGenInstruction.hTue Nov 14 20:38:17 2006
@@ -61,8 +61,9 @@
/// up of multiple MI operands.
DagInit *MIOperandInfo;
- /// Constraint info for this operand.
- std::string Constraint;
+ /// Constraint info for this operand. This operand can have pieces, so
we
+ /// track constraint info for each.
+ std::vector Constraints;
OperandInfo(Record *R, const std::string &N, const std::string &PMN,
unsigned MION, unsigned MINO, DagInit *MIOI)
@@ -91,6 +92,21 @@
bool hasVariableNumberOfOperands;
bool hasCtrlDep;
bool noResults;
+
+/// ParseOperandName - Parse an operand name like "$foo" or "$foo.bar",
+/// where $foo is a whole operand and $foo.bar refers to a suboperand.
+/// This throws an exception if the name is invalid. If AllowWholeOp is
+/// true, references to operands with suboperands are allowed, otherwise
+/// not.
+std::pair ParseOperandName(const std::string &Op,
+ bool AllowWholeOp = true);
+
+/// getFlattenedOperandNumber - Flatten a operand/suboperand pair into a
+/// flat machineinstr operand #.
+unsigned getFlattenedOperandNumber(std::pair Op) const {
+ return OperandList[Op.first].MIOperandNo + Op.second;
+}
+
CodeGenInstruction(Record *R, const std::string &AsmStr);
Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.77
llvm/utils/TableGen/CodeGenTarget.cpp:1.78
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.77 Thu Nov 9 20:01:40 2006
+++ llvm/utils/TableGen/CodeGenTarget.cpp Tue Nov 14 20:38:17 2006
@@ -273,34 +273,49 @@
return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
}
-static std::string ParseConstraint(const std::string &CStr,
- CodeGenInstruction *I, unsigned &DestOp) {
- const std::string ops("="); // FIXME: Only supports TIED_TO for now.
- std::string::size_type pos = CStr.find_first_of(ops);
+
+
+static void ParseConstraint(const std::string &CStr, CodeGenInstruction *I) {
+ // FIXME: Only supports TIED_TO for now.
+ std::string::size_type pos = CStr.find_first_of('=');
assert(pos != std::string::npos && "Unrecognized constraint");
- std::string Name = CStr.substr(1, pos); // Skip '$'
+ std::string Name = CStr.substr(0, pos);
// TIED_TO: $src1 = $dst
- const std::string delims(" \t");
- std::string::size_type wpos = Name.find_first_of(delims);
- if (wpos != std::string::npos)
-Name = Name.substr(0, wpos);
- DestOp = I->getOperandNamed(Name);
+ std::string::size_type wpos = Name.find_first_of(" \t");
+ if (wpos == std::string::npos)
+throw "Illegal format for tied-to constraint: '" + CStr + "'";
+ std::string DestOpName = Name.substr(0, wpos);
+ std::pair DestOp = I->ParseOperandName(DestOpName, false);
Name = CStr.substr(pos+1);
- wpos = Name.find_first_not_of(delims);
- if (wpos != std::string::npos)
-Name = Name.substr(wpos+1);
-
- unsigned TIdx = I->getOperandNamed(Name);
- if (TIdx >= DestOp)
+ wpos = Name.find_first_not_of(" \t");
+ if (wpos == std::string::npos)
+throw "Illegal format for tied-to constraint: '" + CStr + "'";
+
+ std::pair SrcOp =
+I->ParseOperandName(Name.substr(wpos), false);
+ if (SrcOp > DestOp)
throw "Illegal tied-to operand constraint '" + CStr + "'";
- // Build the string.
- return "((" + utostr(TIdx) + " << 16) | (1 << TargetInstrInfo::TIED_TO))";
+
+ unsigned FlatOpNo = I->getFlattenedOperandNumber(SrcOp);
+ // Build the string for the operand.
+ std::string OpConstraint =
+"((" + utostr(FlatOpNo) + " << 16) | (1 << TargetInstrInfo::TIED_TO))";
+
+
+ if (!I->OperandList[DestOp.first].Constraints[DestOp.second].empty())
+throw "Operand '" + DestOpName + "' cannot have multiple constraints!";
+ I->OperandList[DestOp.first].Constraints[DestOp.second] = OpConstraint;
}
static void ParseConstraints(const std::string &CStr, CodeGenInstruction *I) {
+ // Make sure the constraints list for each operand is large enough to hold
+ // constraint info, even if none is present.
+ for (unsigned i = 0, e = I->OperandList.size(); i != e; +
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCHazardRecognizers.cpp updated: 1.15 -> 1.16
PPCInstrInfo.td updated: 1.259 -> 1.260
---
Log message:
Switch loads over to use memri as the operand instead of a reg/imm operand
pair for cleanliness. Add instructions for PPC32 preinc-stores with commented
out patterns. More improvement is needed to enable the patterns, but we're
getting close.
---
Diffs of the changes: (+60 -43)
PPCHazardRecognizers.cpp | 11 ++---
PPCInstrInfo.td | 92 ---
2 files changed, 60 insertions(+), 43 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
diff -u llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.15
llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.16
--- llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.15 Mon Nov 13
14:11:06 2006
+++ llvm/lib/Target/PowerPC/PPCHazardRecognizers.cppTue Nov 14 20:43:19 2006
@@ -234,14 +234,14 @@
unsigned ThisStoreSize;
switch (Opcode) {
default: assert(0 && "Unknown store instruction!");
-case PPC::STB:
+case PPC::STB: case PPC::STBU:
case PPC::STBX:
case PPC::STB8:
case PPC::STBX8:
case PPC::STVEBX:
ThisStoreSize = 1;
break;
-case PPC::STH:
+case PPC::STH: case PPC::STHU:
case PPC::STHX:
case PPC::STH8:
case PPC::STHX8:
@@ -249,12 +249,11 @@
case PPC::STHBRX:
ThisStoreSize = 2;
break;
-case PPC::STFS:
+case PPC::STFS: case PPC::STFSU:
case PPC::STFSX:
-case PPC::STWU:
case PPC::STWX:
case PPC::STWUX:
-case PPC::STW:
+case PPC::STW:case PPC::STWU:
case PPC::STW8:
case PPC::STWX8:
case PPC::STVEWX:
@@ -264,7 +263,7 @@
break;
case PPC::STD_32:
case PPC::STDX_32:
-case PPC::STD:
+case PPC::STD: case PPC::STDU:
case PPC::STFD:
case PPC::STFDX:
case PPC::STDX:
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.259
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.260
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.259 Tue Nov 14 13:19:53 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Nov 14 20:43:19 2006
@@ -247,7 +247,7 @@
// Address operands
def memri : Operand {
let PrintMethod = "printMemRegImm";
- let MIOperandInfo = (ops i32imm, ptr_rc);
+ let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
}
def memrr : Operand {
let PrintMethod = "printMemRegReg";
@@ -270,6 +270,7 @@
def xoaddr : ComplexPattern;
def ixaddr : ComplexPattern; // "std"
+
//===--===//
// PowerPC Instruction Predicate Definitions.
def FPContractions : Predicate<"!NoExcessFPPrecision">;
@@ -410,7 +411,7 @@
// PPC32 Load Instructions.
//
-// Unindexed (r+i) Loads.
+// Unindexed (r+i) Loads.
let isLoad = 1, PPC970_Unit = 2 in {
def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
"lbz $rD, $src", LdStGeneral,
@@ -434,38 +435,32 @@
[(set F8RC:$rD, (load iaddr:$src))]>;
-// 'Update' load forms.
-def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
-ptr_rc:$rA),
- "lbzu $rD, $disp($rA)", LdStGeneral,
- []>, RegConstraint<"$rA = $rA_result">;
-
-def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
-ptr_rc:$rA),
- "lhau $rD, $disp($rA)", LdStGeneral,
- []>, RegConstraint<"$rA = $rA_result">;
-
-def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
-ptr_rc:$rA),
- "lhzu $rD, $disp($rA)", LdStGeneral,
- []>, RegConstraint<"$rA = $rA_result">;
-
-def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
-ptr_rc:$rA),
- "lwzu $rD, $disp($rA)", LdStGeneral,
- []>, RegConstraint<"$rA = $rA_result">;
-
-def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
-ptr_rc:$rA),
- "lfs $rD, $disp($rA)", LdStLFDU,
- []>, RegConstraint<"$rA = $rA_result">;
-def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
-ptr_rc:$rA),
- "lfd $rD, $disp($rA)", LdStLFD,
- []>, RegConstraint<"$rA = $rA_result">;
+// Unindexed (r+i) Loads with Update (preinc).
+def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
+ "lbzu $rD, $addr", LdStGeneral,
+ []>, RegConstraint<"$addr.reg = $ea_result">;
+
+def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
+ "lhau $rD, $addr", LdStGeneral,
+ []>, RegConstraint<"$addr.re
[llvm-commits] CVS: llvm/include/llvm/PassManager.h
Changes in directory llvm/include/llvm: PassManager.h updated: 1.30 -> 1.31 --- Log message: Add doInitialization and doFinalization support in FunctionManager_New. --- Diffs of the changes: (+8 -1) PassManager.h |9 - 1 files changed, 8 insertions(+), 1 deletion(-) Index: llvm/include/llvm/PassManager.h diff -u llvm/include/llvm/PassManager.h:1.30 llvm/include/llvm/PassManager.h:1.31 --- llvm/include/llvm/PassManager.h:1.30Fri Nov 10 19:31:05 2006 +++ llvm/include/llvm/PassManager.h Tue Nov 14 20:07:25 2006 @@ -135,10 +135,17 @@ /// so, return true. bool runOnModule(Module &M); + /// doInitialization - Run all of the initializers for the function passes. + /// + bool doInitialization(); + + /// doFinalization - Run all of the initializers for the function passes. + /// + bool doFinalization(); private: FunctionPassManagerImpl_New *FPM; - + ModuleProvider *MP; }; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/VMCore/PassManager.cpp
Changes in directory llvm/lib/VMCore:
PassManager.cpp updated: 1.30 -> 1.31
---
Log message:
Tidy up marking of last analysis user pass.
---
Diffs of the changes: (+11 -15)
PassManager.cpp | 26 +++---
1 files changed, 11 insertions(+), 15 deletions(-)
Index: llvm/lib/VMCore/PassManager.cpp
diff -u llvm/lib/VMCore/PassManager.cpp:1.30
llvm/lib/VMCore/PassManager.cpp:1.31
--- llvm/lib/VMCore/PassManager.cpp:1.30Tue Nov 14 19:27:05 2006
+++ llvm/lib/VMCore/PassManager.cpp Tue Nov 14 19:48:14 2006
@@ -83,22 +83,9 @@
return PassVector.end();
}
- inline void setLastUser(Pass *P, Pass *LU) {
+ inline void setLastUser(Pass *P, Pass *LU) {
LastUser[P] = LU;
// TODO : Check if pass P is available.
-
-// Prolong live range of analyses that are needed after an analysis pass
-// is destroyed, for querying by subsequent passes
-AnalysisUsage AnUsage;
-P->getAnalysisUsage(AnUsage);
-const std::vector &IDs = AnUsage.getRequiredTransitiveSet();
-for (std::vector::const_iterator I = IDs.begin(),
- E = IDs.end(); I != E; ++I) {
- Pass *AnalysisPass = getAnalysisPass(*I); //
getAnalysisPassFromManager(*I);
- assert (AnalysisPass && "Analysis pass is not available");
- setLastUser(AnalysisPass, LU);
-}
-
}
private:
@@ -671,8 +658,17 @@
schedulePass(AnalysisPass);
}
setLastUser (AnalysisPass, P);
+
+// Prolong live range of analyses that are needed after an analysis pass
+// is destroyed, for querying by subsequent passes
+const std::vector &IDs = AnUsage.getRequiredTransitiveSet();
+for (std::vector::const_iterator I = IDs.begin(),
+ E = IDs.end(); I != E; ++I) {
+ Pass *AP = getAnalysisPassFromManager(*I);
+ assert (AP && "Analysis pass is not available");
+ setLastUser(AP, P);
+}
}
-
addPass(P);
}
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[llvm-commits] CVS: llvm/lib/VMCore/PassManager.cpp
Changes in directory llvm/lib/VMCore:
PassManager.cpp updated: 1.29 -> 1.30
---
Log message:
Add doInitialization and doFinalization support in FunctionManager_New.
---
Diffs of the changes: (+52 -2)
PassManager.cpp | 54 --
1 files changed, 52 insertions(+), 2 deletions(-)
Index: llvm/lib/VMCore/PassManager.cpp
diff -u llvm/lib/VMCore/PassManager.cpp:1.29
llvm/lib/VMCore/PassManager.cpp:1.30
--- llvm/lib/VMCore/PassManager.cpp:1.29Tue Nov 14 19:11:27 2006
+++ llvm/lib/VMCore/PassManager.cpp Tue Nov 14 19:27:05 2006
@@ -14,6 +14,7 @@
#include "llvm/PassManager.h"
#include "llvm/Module.h"
+#include "llvm/ModuleProvider.h"
#include
#include
@@ -174,6 +175,13 @@
/// Return true IFF AnalysisID AID is currently available.
Pass *getAnalysisPassFromManager(AnalysisID AID);
+ /// doInitialization - Run all of the initializers for the function passes.
+ ///
+ bool doInitialization(Module &M);
+
+ /// doFinalization - Run all of the initializers for the function passes.
+ ///
+ bool doFinalization(Module &M);
private:
// Active Pass Managers
BasicBlockPassManager_New *activeBBPassManager;
@@ -355,8 +363,8 @@
// implementations it needs.
//
void CommonPassManagerImpl::initializeAnalysisImpl(Pass *P) {
-AnalysisUsage AnUsage;
-P->getAnalysisUsage(AnUsage);
+ AnalysisUsage AnUsage;
+ P->getAnalysisUsage(AnUsage);
for (std::vector::const_iterator
I = AnUsage.getRequiredSet().begin(),
@@ -441,6 +449,18 @@
return FPM->runOnModule(M);
}
+/// doInitialization - Run all of the initializers for the function passes.
+///
+bool FunctionPassManager_New::doInitialization() {
+ return FPM->doInitialization(*MP->getModule());
+}
+
+/// doFinalization - Run all of the initializers for the function passes.
+///
+bool FunctionPassManager_New::doFinalization() {
+ return FPM->doFinalization(*MP->getModule());
+}
+
// FunctionPassManagerImpl_New implementation
// FunctionPassManager
@@ -517,6 +537,36 @@
return NULL;
}
+inline bool FunctionPassManagerImpl_New::doInitialization(Module &M) {
+ bool Changed = false;
+
+ for (std::vector::iterator itr = passVectorBegin(),
+ e = passVectorEnd(); itr != e; ++itr) {
+Pass *P = *itr;
+
+FunctionPass *FP = dynamic_cast(P);
+Changed |= FP->doInitialization(M);
+ }
+
+ return Changed;
+}
+
+inline bool FunctionPassManagerImpl_New::doFinalization(Module &M) {
+ bool Changed = false;
+
+ for (std::vector::iterator itr = passVectorBegin(),
+ e = passVectorEnd(); itr != e; ++itr) {
+Pass *P = *itr;
+
+FunctionPass *FP = dynamic_cast(P);
+Changed |= FP->doFinalization(M);
+ }
+
+
+ return Changed;
+}
+
+
// ModulePassManager implementation
/// Add P into pass vector if it is manageble. If P is a FunctionPass
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[llvm-commits] CVS: llvm/lib/VMCore/PassManager.cpp
Changes in directory llvm/lib/VMCore:
PassManager.cpp updated: 1.28 -> 1.29
---
Log message:
Do not derive CommonPassManagerImpl from Pass.
Now BasicBlockPassManager_New is a FunctionPass,
FunctionPassManager_New is a ModulePass
---
Diffs of the changes: (+7 -5)
PassManager.cpp | 12 +++-
1 files changed, 7 insertions(+), 5 deletions(-)
Index: llvm/lib/VMCore/PassManager.cpp
diff -u llvm/lib/VMCore/PassManager.cpp:1.28
llvm/lib/VMCore/PassManager.cpp:1.29
--- llvm/lib/VMCore/PassManager.cpp:1.28Tue Nov 14 15:49:36 2006
+++ llvm/lib/VMCore/PassManager.cpp Tue Nov 14 19:11:27 2006
@@ -24,7 +24,7 @@
/// CommonPassManagerImpl helps pass manager analysis required by
/// the managed passes. It provides methods to add/remove analysis
/// available and query if certain analysis is available or not.
-class CommonPassManagerImpl : public Pass {
+class CommonPassManagerImpl {
public:
@@ -124,7 +124,8 @@
/// BasicBlockPassManager_New manages BasicBlockPass. It batches all the
/// pass together and sequence them to process one basic block before
/// processing next basic block.
-class BasicBlockPassManager_New : public CommonPassManagerImpl {
+class BasicBlockPassManager_New : public CommonPassManagerImpl,
+ public FunctionPass {
public:
BasicBlockPassManager_New() { }
@@ -146,7 +147,8 @@
/// It batches all function passes and basic block pass managers together and
/// sequence them to process one function at a time before processing next
/// function.
-class FunctionPassManagerImpl_New : public CommonPassManagerImpl {
+class FunctionPassManagerImpl_New : public CommonPassManagerImpl,
+public ModulePass {
public:
FunctionPassManagerImpl_New(ModuleProvider *P) { /* TODO */ }
FunctionPassManagerImpl_New() {
@@ -353,8 +355,8 @@
// implementations it needs.
//
void CommonPassManagerImpl::initializeAnalysisImpl(Pass *P) {
- AnalysisUsage AnUsage;
- P->getAnalysisUsage(AnUsage);
+AnalysisUsage AnUsage;
+P->getAnalysisUsage(AnUsage);
for (std::vector::const_iterator
I = AnUsage.getRequiredSet().begin(),
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[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.286 -> 1.287
---
Log message:
restore some 'magic' code that I removed: it is needed. Add comments explaining
why.
---
Diffs of the changes: (+22 -10)
DAGISelEmitter.cpp | 32 ++--
1 files changed, 22 insertions(+), 10 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.286
llvm/utils/TableGen/DAGISelEmitter.cpp:1.287
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.286Tue Nov 14 15:50:27 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Tue Nov 14 16:17:10 2006
@@ -3602,10 +3602,15 @@
// Print function.
std::string OpVTStr;
- if (OpVT == MVT::iPTR)
-OpVTStr = "iPTR";
- else
-OpVTStr = getEnumName(OpVT).substr(5); // Skip 'MVT::'
+ if (OpVT == MVT::iPTR) {
+OpVTStr = "_iPTR";
+ } else if (OpVT == MVT::isVoid) {
+// Nodes with a void result actually have a first result type of either
+// Other (a chain) or Flag. Since there is no one-to-one mapping from
+// void to this case, we handle it specially here.
+ } else {
+OpVTStr = "_" + getEnumName(OpVT).substr(5); // Skip 'MVT::'
+ }
std::map >::iterator OpVTI =
OpcodeVTMap.find(OpName);
if (OpVTI == OpcodeVTMap.end()) {
@@ -3616,7 +3621,7 @@
OpVTI->second.push_back(OpVTStr);
OS << "SDNode *Select_" << getLegalCName(OpName)
- << "_" << OpVTStr << "(const SDOperand &N) {\n";
+ << OpVTStr << "(const SDOperand &N) {\n";
// Loop through and reverse all of the CodeList vectors, as we will be
// accessing them from their logical front, but accessing the end of a
@@ -3723,25 +3728,29 @@
if (OpVTs.size() == 1) {
std::string &VTStr = OpVTs[0];
OS << "return Select_" << getLegalCName(OpName)
- << (VTStr != "" ? "_" : "") << VTStr << "(N);\n";
+ << VTStr << "(N);\n";
} else {
// Keep track of whether we see a pattern that has an iPtr result.
bool HasPtrPattern = false;
+ bool HasDefaultPattern = false;
OS << "switch (NVT) {\n";
for (unsigned i = 0, e = OpVTs.size(); i < e; ++i) {
std::string &VTStr = OpVTs[i];
-assert(!VTStr.empty() && "Unset vtstr?");
+if (VTStr.empty()) {
+ HasDefaultPattern = true;
+ continue;
+}
// If this is a match on iPTR: don't emit it directly, we need special
// code.
-if (VTStr == "iPTR") {
+if (VTStr == "_iPTR") {
HasPtrPattern = true;
continue;
}
-OS << "case MVT::" << VTStr << ":\n"
+OS << "case MVT::" << VTStr.substr(1) << ":\n"
<< " return Select_" << getLegalCName(OpName)
- << "_" << VTStr << "(N);\n";
+ << VTStr << "(N);\n";
}
OS << "default:\n";
@@ -3750,6 +3759,9 @@
OS << " if (NVT == TLI.getPointerTy())\n";
OS << "return Select_" << getLegalCName(OpName)
<<"_iPTR(N);\n";
}
+ if (HasDefaultPattern) {
+OS << " return Select_" << getLegalCName(OpName) << "(N);\n";
+ }
OS << " break;\n";
OS << "}\n";
OS << "break;\n";
___
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[llvm-commits] CVS: llvm/lib/VMCore/PassManager.cpp
Changes in directory llvm/lib/VMCore:
PassManager.cpp updated: 1.27 -> 1.28
---
Log message:
Copy initializeAnalysisImpl() implementation from PassManagerT.
Update LastUser to recursively walk required transitive set.
---
Diffs of the changes: (+39 -2)
PassManager.cpp | 41 +++--
1 files changed, 39 insertions(+), 2 deletions(-)
Index: llvm/lib/VMCore/PassManager.cpp
diff -u llvm/lib/VMCore/PassManager.cpp:1.27
llvm/lib/VMCore/PassManager.cpp:1.28
--- llvm/lib/VMCore/PassManager.cpp:1.27Mon Nov 13 21:05:08 2006
+++ llvm/lib/VMCore/PassManager.cpp Tue Nov 14 15:49:36 2006
@@ -72,7 +72,7 @@
// successfully use the getAnalysis() method to retrieve the
// implementations it needs.
//
- inline void initializeAnalysisImpl(Pass *P) { /* TODO : Implement */ }
+ void initializeAnalysisImpl(Pass *P);
inline std::vector::iterator passVectorBegin() {
return PassVector.begin();
@@ -82,7 +82,23 @@
return PassVector.end();
}
- inline void setLastUser(Pass *P, Pass *LU) { LastUser[P] = LU; }
+ inline void setLastUser(Pass *P, Pass *LU) {
+LastUser[P] = LU;
+// TODO : Check if pass P is available.
+
+// Prolong live range of analyses that are needed after an analysis pass
+// is destroyed, for querying by subsequent passes
+AnalysisUsage AnUsage;
+P->getAnalysisUsage(AnUsage);
+const std::vector &IDs = AnUsage.getRequiredTransitiveSet();
+for (std::vector::const_iterator I = IDs.begin(),
+ E = IDs.end(); I != E; ++I) {
+ Pass *AnalysisPass = getAnalysisPass(*I); //
getAnalysisPassFromManager(*I);
+ assert (AnalysisPass && "Analysis pass is not available");
+ setLastUser(AnalysisPass, LU);
+}
+
+ }
private:
// Analysis required by the passes managed by this manager. This information
@@ -258,6 +274,8 @@
// FIXME: What about duplicates ?
RequiredAnalysis.insert(RequiredAnalysis.end(), RequiredSet.begin(),
RequiredSet.end());
+
+ initializeAnalysisImpl(P);
}
/// Augement AvailableAnalysis by adding analysis made available by pass P.
@@ -329,6 +347,25 @@
PassVector.push_back(P);
}
+// All Required analyses should be available to the pass as it runs! Here
+// we fill in the AnalysisImpls member of the pass so that it can
+// successfully use the getAnalysis() method to retrieve the
+// implementations it needs.
+//
+void CommonPassManagerImpl::initializeAnalysisImpl(Pass *P) {
+ AnalysisUsage AnUsage;
+ P->getAnalysisUsage(AnUsage);
+
+ for (std::vector::const_iterator
+ I = AnUsage.getRequiredSet().begin(),
+ E = AnUsage.getRequiredSet().end(); I != E; ++I) {
+Pass *Impl = getAnalysisPass(*I);
+if (Impl == 0)
+ assert(0 && "Analysis used but not available!");
+// TODO: P->AnalysisImpls.push_back(std::make_pair(*I, Impl));
+ }
+}
+
/// BasicBlockPassManager implementation
/// Add pass P into PassVector and return true. If this pass is not
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[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.285 -> 1.286
---
Log message:
minimal hack to get patterns whose result type is iPTR to be selected.
---
Diffs of the changes: (+16 -0)
DAGISelEmitter.cpp | 16
1 files changed, 16 insertions(+)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.285
llvm/utils/TableGen/DAGISelEmitter.cpp:1.286
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.285Tue Nov 14 15:41:35 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Tue Nov 14 15:50:27 2006
@@ -3725,15 +3725,31 @@
OS << "return Select_" << getLegalCName(OpName)
<< (VTStr != "" ? "_" : "") << VTStr << "(N);\n";
} else {
+ // Keep track of whether we see a pattern that has an iPtr result.
+ bool HasPtrPattern = false;
+
OS << "switch (NVT) {\n";
for (unsigned i = 0, e = OpVTs.size(); i < e; ++i) {
std::string &VTStr = OpVTs[i];
assert(!VTStr.empty() && "Unset vtstr?");
+
+// If this is a match on iPTR: don't emit it directly, we need special
+// code.
+if (VTStr == "iPTR") {
+ HasPtrPattern = true;
+ continue;
+}
OS << "case MVT::" << VTStr << ":\n"
<< " return Select_" << getLegalCName(OpName)
<< "_" << VTStr << "(N);\n";
}
OS << "default:\n";
+
+ // If there is an iPTR result version of this pattern, emit it here.
+ if (HasPtrPattern) {
+OS << " if (NVT == TLI.getPointerTy())\n";
+OS << "return Select_" << getLegalCName(OpName)
<<"_iPTR(N);\n";
+ }
OS << " break;\n";
OS << "}\n";
OS << "break;\n";
___
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[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.284 -> 1.285
---
Log message:
remove some dead code
---
Diffs of the changes: (+2 -9)
DAGISelEmitter.cpp | 11 ++-
1 files changed, 2 insertions(+), 9 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.284
llvm/utils/TableGen/DAGISelEmitter.cpp:1.285
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.284Tue Nov 14 15:32:01 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Tue Nov 14 15:41:35 2006
@@ -3725,23 +3725,16 @@
OS << "return Select_" << getLegalCName(OpName)
<< (VTStr != "" ? "_" : "") << VTStr << "(N);\n";
} else {
- int Default = -1;
OS << "switch (NVT) {\n";
for (unsigned i = 0, e = OpVTs.size(); i < e; ++i) {
std::string &VTStr = OpVTs[i];
-if (VTStr == "") {
- Default = i;
- continue;
-}
+assert(!VTStr.empty() && "Unset vtstr?");
OS << "case MVT::" << VTStr << ":\n"
<< " return Select_" << getLegalCName(OpName)
<< "_" << VTStr << "(N);\n";
}
OS << "default:\n";
- if (Default != -1)
-OS << " return Select_" << getLegalCName(OpName) << "(N);\n";
- else
- OS << " break;\n";
+ OS << " break;\n";
OS << "}\n";
OS << "break;\n";
}
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[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.283 -> 1.284
---
Log message:
Add support for nodes that return iPTR.
---
Diffs of the changes: (+6 -4)
DAGISelEmitter.cpp | 10 ++
1 files changed, 6 insertions(+), 4 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.283
llvm/utils/TableGen/DAGISelEmitter.cpp:1.284
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.283Tue Nov 14 15:18:40 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Tue Nov 14 15:32:01 2006
@@ -3601,8 +3601,11 @@
}
// Print function.
- std::string OpVTStr = (OpVT != MVT::isVoid && OpVT != MVT::iPTR)
-? getEnumName(OpVT).substr(5) : "" ;
+ std::string OpVTStr;
+ if (OpVT == MVT::iPTR)
+OpVTStr = "iPTR";
+ else
+OpVTStr = getEnumName(OpVT).substr(5); // Skip 'MVT::'
std::map >::iterator OpVTI =
OpcodeVTMap.find(OpName);
if (OpVTI == OpcodeVTMap.end()) {
@@ -3613,8 +3616,7 @@
OpVTI->second.push_back(OpVTStr);
OS << "SDNode *Select_" << getLegalCName(OpName)
- << (OpVTStr != "" ? "_" : "")
- << OpVTStr << "(const SDOperand &N) {\n";
+ << "_" << OpVTStr << "(const SDOperand &N) {\n";
// Loop through and reverse all of the CodeList vectors, as we will be
// accessing them from their logical front, but accessing the end of a
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[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.282 -> 1.283
---
Log message:
changes to get ptr_rc to be accepted in patterns. This is needed for ppc preinc
stores.
---
Diffs of the changes: (+22 -8)
DAGISelEmitter.cpp | 30 ++
1 files changed, 22 insertions(+), 8 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.282
llvm/utils/TableGen/DAGISelEmitter.cpp:1.283
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.282Tue Nov 14 12:41:38 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Tue Nov 14 15:18:40 2006
@@ -618,6 +618,9 @@
std::vector
ComplexPat(1, TP.getDAGISelEmitter().getComplexPattern(R).getValueType());
return ComplexPat;
+ } else if (R->getName() == "ptr_rc") {
+Other[0] = MVT::iPTR;
+return Other;
} else if (R->getName() == "node" || R->getName() == "srcvalue") {
// Placeholder.
return Unknown;
@@ -747,16 +750,23 @@
CodeGenInstruction &InstInfo =
ISE.getTargetInfo().getInstruction(getOperator()->getName());
// Apply the result type to the node
-if (NumResults == 0 || InstInfo.noResults) { // FIXME: temporary hack...
+if (NumResults == 0 || InstInfo.noResults) { // FIXME: temporary hack.
MadeChange = UpdateNodeType(MVT::isVoid, TP);
} else {
Record *ResultNode = Inst.getResult(0);
- assert(ResultNode->isSubClassOf("RegisterClass") &&
- "Operands should be register classes!");
+
+ if (ResultNode->getName() == "ptr_rc") {
+std::vector VT;
+VT.push_back(MVT::iPTR);
+MadeChange = UpdateNodeType(VT, TP);
+ } else {
+assert(ResultNode->isSubClassOf("RegisterClass") &&
+ "Operands should be register classes!");
- const CodeGenRegisterClass &RC =
-ISE.getTargetInfo().getRegisterClass(ResultNode);
- MadeChange = UpdateNodeType(ConvertVTs(RC.getValueTypes()), TP);
+const CodeGenRegisterClass &RC =
+ ISE.getTargetInfo().getRegisterClass(ResultNode);
+MadeChange = UpdateNodeType(ConvertVTs(RC.getValueTypes()), TP);
+ }
}
unsigned ChildNo = 0;
@@ -782,6 +792,8 @@
} else if (OperandNode->isSubClassOf("Operand")) {
VT = getValueType(OperandNode->getValueAsDef("Type"));
MadeChange |= Child->UpdateNodeType(VT, TP);
+ } else if (OperandNode->getName() == "ptr_rc") {
+MadeChange |= Child->UpdateNodeType(MVT::iPTR, TP);
} else {
assert(0 && "Unknown operand type!");
abort();
@@ -1381,7 +1393,8 @@
if (!Val)
I->error("set destination should be a register!");
-if (Val->getDef()->isSubClassOf("RegisterClass")) {
+if (Val->getDef()->isSubClassOf("RegisterClass") ||
+Val->getDef()->getName() == "ptr_rc") {
if (Dest->getName().empty())
I->error("set destination must have a name!");
if (InstResults.count(Dest->getName()))
@@ -2507,7 +2520,8 @@
// Handle leaves of various types.
if (DefInit *DI = dynamic_cast(Child->getLeafValue())) {
Record *LeafRec = DI->getDef();
-if (LeafRec->isSubClassOf("RegisterClass")) {
+if (LeafRec->isSubClassOf("RegisterClass") ||
+LeafRec->getName() == "ptr_rc") {
// Handle register references. Nothing to do here.
} else if (LeafRec->isSubClassOf("Register")) {
// Handle register references.
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[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.58 -> 1.59
---
Log message:
Revert. This wasn't meant to be checked in.
---
Diffs of the changes: (+18 -11)
X86FloatingPoint.cpp | 29 ++---
1 files changed, 18 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.58
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.59
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.58 Mon Nov 13 17:36:35 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cppTue Nov 14 13:20:33 2006
@@ -40,7 +40,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
#include "llvm/ADT/DepthFirstIterator.h"
-#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include
@@ -214,12 +213,20 @@
// Get dead variables list now because the MI pointer may be deleted as
part
// of processing!
-SmallVector DeadRegs;
-for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDead())
-DeadRegs.push_back(MO.getReg());
-}
+LiveVariables::killed_iterator IB, IE;
+tie(IB, IE) = LV->dead_range(MI);
+
+DEBUG(
+ const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo();
+ LiveVariables::killed_iterator I = LV->killed_begin(MI);
+ LiveVariables::killed_iterator E = LV->killed_end(MI);
+ if (I != E) {
+std::cerr << "Killed Operands:";
+for (; I != E; ++I)
+ std::cerr << " %" << MRI->getName(*I);
+std::cerr << "\n";
+ }
+);
switch (Flags & X86II::FPTypeMask) {
case X86II::ZeroArgFP: handleZeroArgFP(I); break;
@@ -234,8 +241,8 @@
// Check to see if any of the values defined by this instruction are dead
// after definition. If so, pop them.
-for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
- unsigned Reg = DeadRegs[i];
+for (; IB != IE; ++IB) {
+ unsigned Reg = *IB;
if (Reg >= X86::FP0 && Reg <= X86::FP6) {
DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
freeStackSlotAfter(I, Reg-X86::FP0);
@@ -755,7 +762,6 @@
unsigned Op0 = getFPReg(MI->getOperand(0));
unsigned Op1 = getFPReg(MI->getOperand(2));
- bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
// The first operand *must* be on the top of the stack.
moveToTop(Op0, I);
@@ -767,8 +773,9 @@
MI->getOperand(0).setReg(getSTReg(Op1));
MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
+
// If we kill the second operand, make sure to pop it from the stack.
- if (Op0 != Op1 && KillsOp1) {
+ if (Op0 != Op1 && LV->KillsRegister(MI, X86::FP0+Op1)) {
// Get this value off of the register stack.
freeStackSlotAfter(I, Op1);
}
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.td updated: 1.258 -> 1.259
---
Log message:
group load and store instructions together. No functionality change.
---
Diffs of the changes: (+110 -99)
PPCInstrInfo.td | 209 +---
1 files changed, 110 insertions(+), 99 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.258
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.259
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.258 Tue Nov 14 12:44:47 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Nov 14 13:19:53 2006
@@ -405,10 +405,12 @@
def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
"dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
PPC970_DGroup_Single;
-
-// D-Form instructions. Most instructions that perform an operation on a
-// register and an immediate are of this type.
+
+//===--===//
+// PPC32 Load Instructions.
//
+
+// Unindexed (r+i) Loads.
let isLoad = 1, PPC970_Unit = 2 in {
def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
"lbz $rD, $src", LdStGeneral,
@@ -431,7 +433,6 @@
"lfd $rD, $src", LdStLFD,
[(set F8RC:$rD, (load iaddr:$src))]>;
-// FIXME: PTRRC for Pointer regs for ppc64.
// 'Update' load forms.
def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
@@ -464,6 +465,108 @@
[]>, RegConstraint<"$rA = $rA_result">;
}
+// Indexed (r+r) loads.
+//
+let isLoad = 1, PPC970_Unit = 2 in {
+def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
+ "lbzx $rD, $src", LdStGeneral,
+ [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
+def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
+ "lhax $rD, $src", LdStLHA,
+ [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
+ PPC970_DGroup_Cracked;
+def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
+ "lhzx $rD, $src", LdStGeneral,
+ [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
+def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
+ "lwzx $rD, $src", LdStGeneral,
+ [(set GPRC:$rD, (load xaddr:$src))]>;
+
+
+def LHBRX : XForm_1<31, 790, (ops GPRC:$rD, memrr:$src),
+ "lhbrx $rD, $src", LdStGeneral,
+ [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
+def LWBRX : XForm_1<31, 534, (ops GPRC:$rD, memrr:$src),
+ "lwbrx $rD, $src", LdStGeneral,
+ [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
+
+def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
+ "lfsx $frD, $src", LdStLFDU,
+ [(set F4RC:$frD, (load xaddr:$src))]>;
+def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
+ "lfdx $frD, $src", LdStLFDU,
+ [(set F8RC:$frD, (load xaddr:$src))]>;
+}
+
+//===--===//
+// PPC32 Store Instructions.
+//
+
+// Unindexed (r+i) Stores.
+let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
+def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
+ "stb $rS, $src", LdStGeneral,
+ [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
+def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
+ "sth $rS, $src", LdStGeneral,
+ [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
+def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
+ "stw $rS, $src", LdStGeneral,
+ [(store GPRC:$rS, iaddr:$src)]>;
+def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
+ "stwu $rS, $disp($rA)", LdStGeneral,
+ []>;
+
+def STFS : DForm_1<52, (ops F4RC:$rS, memri:$dst),
+ "stfs $rS, $dst", LdStUX,
+ [(store F4RC:$rS, iaddr:$dst)]>;
+def STFD : DForm_1<54, (ops F8RC:$rS, memri:$dst),
+ "stfd $rS, $dst", LdStUX,
+ [(store F8RC:$rS, iaddr:$dst)]>;
+}
+
+// Indexed (r+r) Stores.
+//
+let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
+def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
+ "stbx $rS, $dst", LdStGeneral,
+ [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
+ PPC970_DGroup_Cracked;
+def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
+ "sthx $rS, $dst", LdStGeneral,
+ [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
+ PPC970_DGroup_Cracked;
+def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
+
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.76 -> 1.77
---
Log message:
Fix predicates for unindexed stores so they don't accidentally match indexed
stores.
---
Diffs of the changes: (+39 -33)
TargetSelectionDAG.td | 72 +++---
1 files changed, 39 insertions(+), 33 deletions(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.76
llvm/lib/Target/TargetSelectionDAG.td:1.77
--- llvm/lib/Target/TargetSelectionDAG.td:1.76 Thu Nov 9 12:44:21 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Tue Nov 14 13:13:39 2006
@@ -408,7 +408,7 @@
def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::NON_EXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED;
+ LD->getAddressingMode() == ISD::UNINDEXED;
return false;
}]>;
@@ -416,94 +416,94 @@
def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::EXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i1;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i1;
return false;
}]>;
def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::EXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i8;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i8;
return false;
}]>;
def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::EXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i16;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i16;
return false;
}]>;
def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::EXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i32;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i32;
return false;
}]>;
def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::EXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::f32;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::f32;
return false;
}]>;
def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::SEXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i1;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i1;
return false;
}]>;
def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::SEXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i8;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i8;
return false;
}]>;
def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::SEXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i16;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i16;
return false;
}]>;
def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::SEXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i32;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i32;
return false;
}]>;
def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::ZEXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i1;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i1;
return false;
}]>;
def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::ZEXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i8;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i8;
return false;
}]
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp PPCInstr64Bit.td PPCInstrInfo.td PPCRegisterInfo.cpp PPCRegisterInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCCodeEmitter.cpp updated: 1.68 -> 1.69
PPCInstr64Bit.td updated: 1.25 -> 1.26
PPCInstrInfo.td updated: 1.257 -> 1.258
PPCRegisterInfo.cpp updated: 1.81 -> 1.82
PPCRegisterInfo.td updated: 1.38 -> 1.39
---
Log message:
Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 calls
clobber. This allows LR8 to be save/restored correctly as a 64-bit quantity,
instead of handling it as a 32-bit quantity. This unbreaks ppc64 codegen when
the code is actually located above the 4G boundary.
---
Diffs of the changes: (+107 -38)
PPCCodeEmitter.cpp |1
PPCInstr64Bit.td| 43 ++-
PPCInstrInfo.td |6 ++-
PPCRegisterInfo.cpp | 82
PPCRegisterInfo.td | 13 +---
5 files changed, 107 insertions(+), 38 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp
diff -u llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.68
llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.69
--- llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.68 Thu Nov 2 14:25:49 2006
+++ llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp Tue Nov 14 12:44:47 2006
@@ -102,6 +102,7 @@
case PPC::IMPLICIT_DEF_VRRC:
break; // pseudo opcode, no side effects
case PPC::MovePCtoLR:
+case PPC::MovePCtoLR8:
assert(0 && "CodeEmitter does not support MovePCtoLR instruction");
break;
}
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.25
llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.26
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.25 Sat Nov 11 13:05:28 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdTue Nov 14 12:44:47 2006
@@ -60,11 +60,52 @@
def IMPLICIT_DEF_G8RC : Pseudo<(ops G8RC:$rD), "; IMPLICIT_DEF_G8RC $rD",
[(set G8RC:$rD, (undef))]>;
+
+//===--===//
+// Calls.
+//
+
+let Defs = [LR8] in
+ def MovePCtoLR8 : Pseudo<(ops piclabel:$label), "bl $label", []>,
+PPC970_Unit_BRU;
+
+let isCall = 1, noResults = 1, PPC970_Unit = 7,
+ // All calls clobber the PPC64 non-callee saved registers.
+ Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
+ F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
+
V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
+ LR8,CTR8,
+ CR0,CR1,CR5,CR6,CR7] in {
+ // Convenient aliases for call instructions
+ def BL8 : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
+"bl $func", BrB, []>; // See Pat patterns below.
+
+ def BLA8 : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
+ "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
+}
+
+// Calls
+def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
+ (BL8 tglobaladdr:$dst)>;
+def : Pat<(PPCcall (i64 texternalsym:$dst)),
+ (BL8 texternalsym:$dst)>;
+
+//===--===//
+// 64-bit SPR manipulation instrs.
+
+def MFCTR8 : XFXForm_1_ext<31, 339, 9, (ops G8RC:$rT), "mfctr $rT", SprMFSPR>,
+ PPC970_DGroup_First, PPC970_Unit_FXU;
let Pattern = [(PPCmtctr G8RC:$rS)] in {
def MTCTR8 : XFXForm_7_ext<31, 467, 9, (ops G8RC:$rS), "mtctr $rS", SprMTSPR>,
-PPC970_DGroup_First, PPC970_Unit_FXU;
+ PPC970_DGroup_First, PPC970_Unit_FXU;
}
+def MTLR8 : XFXForm_7_ext<31, 467, 8, (ops G8RC:$rS), "mtlr $rS", SprMTSPR>,
+ PPC970_DGroup_First, PPC970_Unit_FXU;
+def MFLR8 : XFXForm_1_ext<31, 339, 8, (ops G8RC:$rT), "mflr $rT", SprMFSPR>,
+ PPC970_DGroup_First, PPC970_Unit_FXU;
+
+
//===--===//
// Fixed point instructions.
//
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.257
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.258
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.257 Fri Nov 10 22:51:36 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Nov 14 12:44:47 2006
@@ -274,6 +274,7 @@
// PowerPC Instruction Predicate Definitions.
def FPContractions : Predicate<"!NoExcessFPPrecision">;
+
//===--===//
// PowerPC Instruction Definitions.
@@ -328,6 +329,7 @@
}
+
let Defs = [LR] in
def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
PPC970_Unit_BRU;
@@ -1014,9 +1016,9 @@
(RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME
maskimm32:$imm))>;
// Calls
-def : Pat<(PPCcall tglobaladdr:$dst),
+def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
(BL tglobaladdr:$dst)>;
-def : Pat<(PPCcall texternalsym:$dst),
+def : Pat<(PPCcall (i32 texternalsym:$dst)),
(BL texternalsym:$dst)>;
// Hi and Lo for Darwin Gl
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.218 -> 1.219
---
Log message:
remove a ton of custom selection logic no longer needed
---
Diffs of the changes: (+7 -145)
PPCISelDAGToDAG.cpp | 152 ++--
1 files changed, 7 insertions(+), 145 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.218
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.219
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.218 Fri Nov 10 22:53:30 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Nov 14 12:43:11 2006
@@ -190,8 +190,6 @@
private:
SDNode *SelectSETCC(SDOperand Op);
-SDNode *MySelect_PPCbctrl(SDOperand N);
-SDNode *MySelect_PPCcall(SDOperand N);
};
}
@@ -282,13 +280,15 @@
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
SSARegMap *RegMap = BB->getParent()->getSSARegMap();
-if (PPCLowering.getPointerTy() == MVT::i32)
+if (PPCLowering.getPointerTy() == MVT::i32) {
GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
-else
+ BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
+ BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
+} else {
GlobalBaseReg = RegMap->createVirtualRegister(PPC::G8RCRegisterClass);
-
-BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
-BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
+ BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR8, 0, PPC::LR8);
+ BuildMI(FirstMBB, MBBI, PPC::MFLR8, 1, GlobalBaseReg);
+}
}
return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()).Val;
}
@@ -1013,150 +1013,12 @@
Chain), 0);
return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
}
- // FIXME: These are manually selected because tblgen isn't handling varargs
- // nodes correctly.
- case PPCISD::BCTRL:return MySelect_PPCbctrl(Op);
- case PPCISD::CALL: return MySelect_PPCcall(Op);
}
return SelectCode(Op);
}
-// FIXME: This is manually selected because tblgen isn't handling varargs nodes
-// correctly.
-SDNode *PPCDAGToDAGISel::MySelect_PPCbctrl(SDOperand N) {
- SDOperand Chain(0, 0);
-
- bool hasFlag =
-N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag;
-
- SmallVector Ops;
- // Push varargs arguments, including optional flag.
- for (unsigned i = 1, e = N.getNumOperands()-hasFlag; i != e; ++i) {
-Chain = N.getOperand(i);
-AddToISelQueue(Chain);
-Ops.push_back(Chain);
- }
-
- Chain = N.getOperand(0);
- AddToISelQueue(Chain);
- Ops.push_back(Chain);
-
- if (hasFlag) {
-Chain = N.getOperand(N.getNumOperands()-1);
-AddToISelQueue(Chain);
-Ops.push_back(Chain);
- }
-
- return CurDAG->getTargetNode(PPC::BCTRL, MVT::Other, MVT::Flag,
- &Ops[0], Ops.size());
-}
-
-// FIXME: This is manually selected because tblgen isn't handling varargs nodes
-// correctly.
-SDNode *PPCDAGToDAGISel::MySelect_PPCcall(SDOperand N) {
- SDOperand Chain(0, 0);
- SDOperand N1(0, 0);
- SDOperand Tmp0(0, 0);
- Chain = N.getOperand(0);
- N1 = N.getOperand(1);
-
- // Pattern: (PPCcall:void (imm:i32):$func)
- // Emits: (BLA:void (imm:i32):$func)
- // Pattern complexity = 4 cost = 1
- if (N1.getOpcode() == ISD::Constant) {
-unsigned Tmp0C = (unsigned)cast(N1)->getValue();
-
-SmallVector Ops;
-Ops.push_back(CurDAG->getTargetConstant(Tmp0C, MVT::i32));
-
-bool hasFlag =
- N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag;
-
-// Push varargs arguments, not including optional flag.
-for (unsigned i = 2, e = N.getNumOperands()-hasFlag; i != e; ++i) {
- Chain = N.getOperand(i);
- AddToISelQueue(Chain);
- Ops.push_back(Chain);
-}
-Chain = N.getOperand(0);
-AddToISelQueue(Chain);
-Ops.push_back(Chain);
-if (hasFlag) {
- Chain = N.getOperand(N.getNumOperands()-1);
- AddToISelQueue(Chain);
- Ops.push_back(Chain);
-}
-return CurDAG->getTargetNode(PPC::BLA, MVT::Other, MVT::Flag,
- &Ops[0], Ops.size());
- }
-
- // Pattern: (PPCcall:void (tglobaladdr:i32):$dst)
- // Emits: (BL:void (tglobaladdr:i32):$dst)
- // Pattern complexity = 4 cost = 1
- if (N1.getOpcode() == ISD::TargetGlobalAddress) {
-SmallVector Ops;
-Ops.push_back(N1);
-
-bool hasFlag =
- N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag;
-
-// Push varargs arguments, not including optional flag.
-for (unsigned i = 2, e = N.getNumOperands()-hasFlag; i != e; ++i) {
- Chain = N.getOperand(i);
- AddToISelQueue(Chain);
- Ops.push_back(Chain);
-}
-Chain = N.getOperand(0);
-AddToISelQueue(Chain);
-Ops.push_back(Chain);
-if (hasFlag) {
- Chain = N.getOperand(N.getNumOperands()-1);
[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.281 -> 1.282
---
Log message:
Fix a bug handling nodes with variable arguments. The code was fixed to assume
that there were two input operands before the variable operand portion. This
*happened* to be true for all call instructions, which took a chain and a
destination, but was not true for the PPC BCTRL instruction, whose destination
is implicit.
Making this code more general allows elimination of the custom selection logic
for BCTRL.
---
Diffs of the changes: (+15 -8)
DAGISelEmitter.cpp | 23 +++
1 files changed, 15 insertions(+), 8 deletions(-)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.281
llvm/utils/TableGen/DAGISelEmitter.cpp:1.282
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.281Wed Nov 8 17:01:03 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Tue Nov 14 12:41:38 2006
@@ -2852,6 +2852,11 @@
if (NodeHasOutFlag)
Code += ", MVT::Flag";
+// Figure out how many fixed inputs the node has. This is important to
+// know which inputs are the variable ones if present.
+unsigned NumInputs = AllOps.size();
+NumInputs += NodeHasChain;
+
// Inputs.
if (HasVarOps) {
for (unsigned i = 0, e = AllOps.size(); i != e; ++i)
@@ -2860,15 +2865,17 @@
}
if (HasVarOps) {
+ // Figure out whether any operands at the end of the op list are not
+ // part of the variable section.
+ std::string EndAdjust;
if (NodeHasInFlag || HasImpInputs)
-emitCode("for (unsigned i = 2, e = N.getNumOperands()-1; "
- "i != e; ++i) {");
- else if (NodeHasOptInFlag)
-emitCode("for (unsigned i = 2, e = N.getNumOperands()-"
- "(HasInFlag?1:0); i != e; ++i) {");
- else
-emitCode("for (unsigned i = 2, e = N.getNumOperands(); "
- "i != e; ++i) {");
+EndAdjust = "-1"; // Always has one flag.
+ else if (NodeHasOptInFlag)
+EndAdjust = "-(HasInFlag?1:0)"; // May have a flag.
+
+ emitCode("for (unsigned i = " + utostr(NumInputs) +
+ ", e = N.getNumOperands()" + EndAdjust + "; i != e; ++i)
{");
+
emitCode(" AddToISelQueue(N.getOperand(i));");
emitCode(" Ops" + utostr(OpsNo) + ".push_back(N.getOperand(i));");
emitCode("}");
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[llvm-commits] CVS: llvm-test/SingleSource/Benchmarks/McGill/exptree.c
Changes in directory llvm-test/SingleSource/Benchmarks/McGill:
exptree.c updated: 1.1 -> 1.2
---
Log message:
Shut gcc up about main not returning int.
---
Diffs of the changes: (+2 -1)
exptree.c |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm-test/SingleSource/Benchmarks/McGill/exptree.c
diff -u llvm-test/SingleSource/Benchmarks/McGill/exptree.c:1.1
llvm-test/SingleSource/Benchmarks/McGill/exptree.c:1.2
--- llvm-test/SingleSource/Benchmarks/McGill/exptree.c:1.1 Tue Oct 5
15:58:37 2004
+++ llvm-test/SingleSource/Benchmarks/McGill/exptree.c Tue Nov 14 12:34:51 2006
@@ -381,8 +381,9 @@
doSearch();
}
-void main( int argc, char *argv[] )
+int main( int argc, char *argv[] )
{
if( getInput() )
search();
+return 0;
}
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[llvm-commits] CVS: llvm/lib/Target/X86/README.txt
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.144 -> 1.145
---
Log message:
it would be nice of ctlz were lowered to bsf etc.
---
Diffs of the changes: (+9 -0)
README.txt |9 +
1 files changed, 9 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.144
llvm/lib/Target/X86/README.txt:1.145
--- llvm/lib/Target/X86/README.txt:1.144Fri Nov 10 16:03:35 2006
+++ llvm/lib/Target/X86/README.txt Tue Nov 14 02:08:46 2006
@@ -114,6 +114,15 @@
however, check that these are defined for 0 and 32. Our intrinsics are, GCC's
aren't.
+Another example (use predsimplify to eliminate a select):
+
+int foo (unsigned long j) {
+ if (j)
+return __builtin_ffs (j) - 1;
+ else
+return 0;
+}
+
//===-===//
Use push/pop instructions in prolog/epilog sequences instead of stores off
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