[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp PPCMachOWriterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCMachOWriterInfo.cpp updated: 1.4 -> 1.5
PPCMachOWriterInfo.h updated: 1.3 -> 1.4
---
Log message:
More Mach-O writer improvements.
---
Diffs of the changes: (+16 -6)
PPCMachOWriterInfo.cpp | 20 +++-
PPCMachOWriterInfo.h |2 +-
2 files changed, 16 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp:1.4
llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp:1.5
--- llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp:1.4 Thu Feb 8 00:05:08 2007
+++ llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp Wed Feb 28 01:40:50 2007
@@ -35,13 +35,11 @@
unsigned ToIdx,
OutputBuffer &RelocOut,
OutputBuffer &SecOut,
- bool Scattered) const {
+ bool Scattered,
+ bool isExtern) const {
unsigned NumRelocs = 0;
uint64_t Addr = 0;
- // Keep track of whether or not this is an externally defined relocation.
- bool isExtern = false;
-
// Get the address of whatever it is we're relocating, if possible.
if (!isExtern)
Addr = (uintptr_t)MR.getResultPointer() + ToAddr;
@@ -83,12 +81,24 @@
break;
case PPC::reloc_pcrel_bx:
{
+ // FIXME: Presumably someday we will need to branch to other, non-extern
+ // functions too. Need to figure out some way to distinguish between
+ // target is BB and target is function.
+ if (isExtern) {
+MachORelocation BR24(MR.getMachineCodeOffset(), ToIdx, true, 2,
+ isExtern, PPC_RELOC_BR24, Scattered,
+ (intptr_t)MR.getMachineCodeOffset());
+RelocOut.outword(BR24.getAddress());
+RelocOut.outword(BR24.getPackedFields());
+++NumRelocs;
+ }
+
Addr -= MR.getMachineCodeOffset();
Addr >>= 2;
Addr &= 0xFF;
Addr <<= 2;
Addr |= (SecOut[MR.getMachineCodeOffset()] << 24);
-
+ Addr |= (SecOut[MR.getMachineCodeOffset()+3] & 0x3);
SecOut.fixword(Addr, MR.getMachineCodeOffset());
break;
}
Index: llvm/lib/Target/PowerPC/PPCMachOWriterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCMachOWriterInfo.h:1.3
llvm/lib/Target/PowerPC/PPCMachOWriterInfo.h:1.4
--- llvm/lib/Target/PowerPC/PPCMachOWriterInfo.h:1.3Fri Feb 2 20:41:58 2007
+++ llvm/lib/Target/PowerPC/PPCMachOWriterInfo.hWed Feb 28 01:40:50 2007
@@ -34,7 +34,7 @@
unsigned ToIdx,
OutputBuffer &RelocOut,
OutputBuffer &SecOut,
- bool Scattered) const;
+ bool Scattered, bool Extern) const;
// Constants for the relocation r_type field.
// See
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetMachOWriterInfo.h
Changes in directory llvm/include/llvm/Target:
TargetMachOWriterInfo.h updated: 1.3 -> 1.4
---
Log message:
More Mach-O writer improvements.
---
Diffs of the changes: (+2 -1)
TargetMachOWriterInfo.h |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Target/TargetMachOWriterInfo.h
diff -u llvm/include/llvm/Target/TargetMachOWriterInfo.h:1.3
llvm/include/llvm/Target/TargetMachOWriterInfo.h:1.4
--- llvm/include/llvm/Target/TargetMachOWriterInfo.h:1.3Fri Feb 2
20:38:57 2007
+++ llvm/include/llvm/Target/TargetMachOWriterInfo.hWed Feb 28 01:40:50 2007
@@ -100,7 +100,8 @@
unsigned ToIdx,
OutputBuffer &RelocOut,
OutputBuffer &SecOut,
- bool Scattered) const { return 0; }
+ bool Scattered,
+ bool Extern) const { return 0; }
uint32_t getCPUType() const { return CPUType; }
uint32_t getCPUSubType() const { return CPUSubType; }
___
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[llvm-commits] CVS: llvm/lib/CodeGen/MachOWriter.cpp MachOWriter.h
Changes in directory llvm/lib/CodeGen:
MachOWriter.cpp updated: 1.28 -> 1.29
MachOWriter.h updated: 1.1 -> 1.2
---
Log message:
More Mach-O writer improvements.
---
Diffs of the changes: (+61 -32)
MachOWriter.cpp | 85
MachOWriter.h |8 +++--
2 files changed, 61 insertions(+), 32 deletions(-)
Index: llvm/lib/CodeGen/MachOWriter.cpp
diff -u llvm/lib/CodeGen/MachOWriter.cpp:1.28
llvm/lib/CodeGen/MachOWriter.cpp:1.29
--- llvm/lib/CodeGen/MachOWriter.cpp:1.28 Wed Feb 14 20:26:09 2007
+++ llvm/lib/CodeGen/MachOWriter.cppWed Feb 28 01:40:50 2007
@@ -107,7 +107,7 @@
virtual intptr_t getConstantPoolEntryAddress(unsigned Index) const {
assert(CPLocations.size() > Index && "CP not emitted!");
- return CPLocations[Index];
+ return CPLocations[Index];\
}
virtual intptr_t getJumpTableEntryAddress(unsigned Index) const {
assert(JTLocations.size() > Index && "JT not emitted!");
@@ -225,7 +225,10 @@
Addr = getConstantPoolEntryAddress(MR.getConstantPoolIndex());
MR.setConstantVal(CPSections[MR.getConstantPoolIndex()]);
MR.setResultPointer((void*)Addr);
-} else if (!MR.isGlobalValue()) {
+} else if (MR.isGlobalValue()) {
+ // FIXME: This should be a set or something that uniques
+ MOW.PendingGlobals.push_back(MR.getGlobalValue());
+} else {
assert(0 && "Unhandled relocation type");
}
MOS->Relocations.push_back(MR);
@@ -334,8 +337,6 @@
if (Align == 0)
Align = TM.getTargetData()->getPrefTypeAlignment(Ty);
- MachOSym Sym(GV, Mang->getValueName(GV), Sec->Index, TM);
-
// Reserve space in the .bss section for this symbol while maintaining the
// desired section alignment, which must be at least as much as required by
// this symbol.
@@ -353,12 +354,17 @@
for (unsigned i = 0; i < AlignedSize; ++i)
SecDataOut.outbyte(0);
}
+ // Globals without external linkage apparently do not go in the symbol table.
+ if (GV->getLinkage() != GlobalValue::InternalLinkage) {
+MachOSym Sym(GV, Mang->getValueName(GV), Sec->Index, TM);
+Sym.n_value = Sec->size;
+SymbolTable.push_back(Sym);
+ }
+
// Record the offset of the symbol, and then allocate space for it.
// FIXME: remove when we have unified size + output buffer
- Sym.n_value = Sec->size;
Sec->size += Size;
- SymbolTable.push_back(Sym);
-
+
// Now that we know what section the GlovalVariable is going to be emitted
// into, update our mappings.
// FIXME: We may also need to update this when outputting non-GlobalVariable
@@ -387,12 +393,9 @@
// For undefined (N_UNDF) external (N_EXT) types, n_value is the size in
// bytes of the symbol.
ExtOrCommonSym.n_value = Size;
- // If the symbol is external, we'll put it on a list of symbols whose
- // addition to the symbol table is being pended until we find a reference
- if (NoInit)
-PendingSyms.push_back(ExtOrCommonSym);
- else
-SymbolTable.push_back(ExtOrCommonSym);
+ SymbolTable.push_back(ExtOrCommonSym);
+ // Remember that we've seen this symbol
+ GVOffset[GV] = Size;
return;
}
// Otherwise, this symbol is part of the .bss section.
@@ -526,7 +529,13 @@
currentAddr += MOS->size;
}
- // Step #6: Calculate the number of relocations for each section and write
out
+ // Step #6: Emit the symbol table to temporary buffers, so that we know the
+ // size of the string table when we write the next load command. This also
+ // sorts and assigns indices to each of the symbols, which is necessary for
+ // emitting relocations to externally-defined objects.
+ BufferSymbolAndStringTable();
+
+ // Step #7: Calculate the number of relocations for each section and write
out
// the section commands for each section
currentAddr += SEG.fileoff;
for (std::vector::iterator I = SectionList.begin(),
@@ -554,10 +563,6 @@
FHOut.outword(MOS->reserved3);
}
- // Step #7: Emit the symbol table to temporary buffers, so that we know the
- // size of the string table when we write the next load command.
- BufferSymbolAndStringTable();
-
// Step #8: Emit LC_SYMTAB/LC_DYSYMTAB load commands
SymTab.symoff = currentAddr;
SymTab.nsyms = SymbolTable.size();
@@ -632,6 +637,17 @@
// 2. defined external symbols (sorted by name)
// 3. undefined external symbols (sorted by name)
+ // Before sorting the symbols, check the PendingGlobals for any undefined
+ // globals that need to be put in the symbol table.
+ for (std::vector::iterator I = PendingGlobals.begin(),
+ E = PendingGlobals.end(); I != E; ++I) {
+if (GVOffset[*I] == 0 && GVSection[*I] == 0) {
+ MachOSym UndfSym(*I, Mang->getValueName(*I), MachOSym::NO_SECT, TM);
+ SymbolTable.push_back(UndfSym);
+ GVOffset[*I] = -1;
+}
+ }
+
// Sort the symbols by name, so that when we
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.354 -> 1.355
---
Log message:
use high-level functions in CCState
---
Diffs of the changes: (+6 -15)
X86ISelLowering.cpp | 21 ++---
1 files changed, 6 insertions(+), 15 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.354
llvm/lib/Target/X86/X86ISelLowering.cpp:1.355
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.354 Wed Feb 28 01:00:42 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Feb 28 01:09:55 2007
@@ -438,15 +438,8 @@
SmallVector RVLocs;
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
CCState CCInfo(CC, getTargetMachine(), RVLocs);
+ CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
- // Determine which register each value should be copied into.
- for (unsigned i = 0; i != Op.getNumOperands() / 2; ++i) {
-MVT::ValueType VT = Op.getOperand(i*2+1).getValueType();
-if (RetCC_X86(i, VT, VT, CCValAssign::Full,
- cast(Op.getOperand(i*2+2))->getValue(),
- CCInfo))
- assert(0 && "Unhandled result type!");
- }
// If this is the first return lowered for this function, add the regs to the
// liveout set for the function.
@@ -521,16 +514,14 @@
SDNode *X86TargetLowering::
LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
unsigned CallingConv, SelectionDAG &DAG) {
- SmallVector ResultVals;
-
+
+ // Assign locations to each value returned by this call.
SmallVector RVLocs;
CCState CCInfo(CallingConv, getTargetMachine(), RVLocs);
+ CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
+
- for (unsigned i = 0, e = TheCall->getNumValues() - 1; i != e; ++i) {
-MVT::ValueType VT = TheCall->getValueType(i);
-if (RetCC_X86(i, VT, VT, CCValAssign::Full, 0, CCInfo))
- assert(0 && "Unhandled result type!");
- }
+ SmallVector ResultVals;
// Copy all of the result registers out of their specified physreg.
if (RVLocs.size() != 1 || RVLocs[0].getLocReg() != X86::ST0) {
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/CallingConvLower.h
Changes in directory llvm/include/llvm/CodeGen: CallingConvLower.h updated: 1.3 -> 1.4 --- Log message: add methods for analysis of call results and return nodes. --- Diffs of the changes: (+11 -3) CallingConvLower.h | 14 +++--- 1 files changed, 11 insertions(+), 3 deletions(-) Index: llvm/include/llvm/CodeGen/CallingConvLower.h diff -u llvm/include/llvm/CodeGen/CallingConvLower.h:1.3 llvm/include/llvm/CodeGen/CallingConvLower.h:1.4 --- llvm/include/llvm/CodeGen/CallingConvLower.h:1.3Wed Feb 28 00:56:37 2007 +++ llvm/include/llvm/CodeGen/CallingConvLower.hWed Feb 28 01:09:40 2007 @@ -130,13 +130,21 @@ return UsedRegs[Reg/32] & (1 << (Reg&31)); } + /// AnalyzeFormalArguments - Analyze an ISD::FORMAL_ARGUMENTS node, + /// incorporating info about the formals into this state. + void AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn); + + /// AnalyzeReturn - Analyze the returned values of an ISD::RET node, + /// incorporating info about the result values into this state. + void AnalyzeReturn(SDNode *TheRet, CCAssignFn Fn); + /// AnalyzeCallOperands - Analyze an ISD::CALL node, incorporating info /// about the passed values into this state. void AnalyzeCallOperands(SDNode *TheCall, CCAssignFn Fn); - /// AnalyzeFormalArguments - Analyze an ISD::FORMAL_ARGUMENTS node, - /// incorporating info about the formals into this state. - void AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn); + /// AnalyzeCallResult - Analyze the return values of an ISD::CALL node, + /// incorporating info about the passed values into this state. + void AnalyzeCallResult(SDNode *TheCall, CCAssignFn Fn); /// getFirstUnallocated - Return the first unallocated register in the set, or ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
CallingConvLower.cpp updated: 1.3 -> 1.4
---
Log message:
add methods for analysis of call results and return nodes.
---
Diffs of the changes: (+42 -12)
CallingConvLower.cpp | 54 +++
1 files changed, 42 insertions(+), 12 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp:1.3
llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp:1.4
--- llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp:1.3 Wed Feb 28
00:56:20 2007
+++ llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp Wed Feb 28 01:09:40 2007
@@ -37,6 +37,39 @@
UsedRegs[Reg/32] |= 1 << (Reg&31);
}
+/// AnalyzeFormalArguments - Analyze an ISD::FORMAL_ARGUMENTS node,
+/// incorporating info about the formals into this state.
+void CCState::AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn) {
+ unsigned NumArgs = TheArgs->getNumValues()-1;
+
+ for (unsigned i = 0; i != NumArgs; ++i) {
+MVT::ValueType ArgVT = TheArgs->getValueType(i);
+SDOperand FlagOp = TheArgs->getOperand(3+i);
+unsigned ArgFlags = cast(FlagOp)->getValue();
+if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
+ cerr << "Formal argument #" << i << " has unhandled type "
+ << MVT::getValueTypeString(ArgVT) << "\n";
+ abort();
+}
+ }
+}
+
+/// AnalyzeReturn - Analyze the returned values of an ISD::RET node,
+/// incorporating info about the result values into this state.
+void CCState::AnalyzeReturn(SDNode *TheRet, CCAssignFn Fn) {
+ // Determine which register each value should be copied into.
+ for (unsigned i = 0, e = TheRet->getNumOperands() / 2; i != e; ++i) {
+MVT::ValueType VT = TheRet->getOperand(i*2+1).getValueType();
+if (Fn(i, VT, VT, CCValAssign::Full,
+ cast(TheRet->getOperand(i*2+2))->getValue(),
*this)){
+ cerr << "Return operand #" << i << " has unhandled type "
+ << MVT::getValueTypeString(VT) << "\n";
+ abort();
+}
+ }
+}
+
+
/// AnalyzeCallOperands - Analyze an ISD::CALL node, incorporating info
/// about the passed values into this state.
void CCState::AnalyzeCallOperands(SDNode *TheCall, CCAssignFn Fn) {
@@ -53,19 +86,16 @@
}
}
-/// AnalyzeFormalArguments - Analyze an ISD::FORMAL_ARGUMENTS node,
-/// incorporating info about the formals into this state.
-void CCState::AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn) {
- unsigned NumArgs = TheArgs->getNumValues()-1;
-
- for (unsigned i = 0; i != NumArgs; ++i) {
-MVT::ValueType ArgVT = TheArgs->getValueType(i);
-SDOperand FlagOp = TheArgs->getOperand(3+i);
-unsigned ArgFlags = cast(FlagOp)->getValue();
-if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
- cerr << "Formal argument #" << i << " has unhandled type "
- << MVT::getValueTypeString(ArgVT) << "\n";
+/// AnalyzeCallResult - Analyze the return values of an ISD::CALL node,
+/// incorporating info about the passed values into this state.
+void CCState::AnalyzeCallResult(SDNode *TheCall, CCAssignFn Fn) {
+ for (unsigned i = 0, e = TheCall->getNumValues() - 1; i != e; ++i) {
+MVT::ValueType VT = TheCall->getValueType(i);
+if (Fn(i, VT, VT, CCValAssign::Full, 0, *this)) {
+ cerr << "Call result #" << i << " has unhandled type "
+ << MVT::getValueTypeString(VT) << "\n";
abort();
}
}
}
+
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/CallingConvLower.h
Changes in directory llvm/include/llvm/CodeGen:
CallingConvLower.h updated: 1.2 -> 1.3
---
Log message:
add methods to analyze calls and formals.
---
Diffs of the changes: (+20 -1)
CallingConvLower.h | 21 -
1 files changed, 20 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/CodeGen/CallingConvLower.h
diff -u llvm/include/llvm/CodeGen/CallingConvLower.h:1.2
llvm/include/llvm/CodeGen/CallingConvLower.h:1.3
--- llvm/include/llvm/CodeGen/CallingConvLower.h:1.2Mon Feb 26 23:13:54 2007
+++ llvm/include/llvm/CodeGen/CallingConvLower.hWed Feb 28 00:56:37 2007
@@ -21,7 +21,9 @@
namespace llvm {
class MRegisterInfo;
class TargetMachine;
-
+ class CCState;
+ class SDNode;
+
/// CCValAssign - Represent assignment of one arg/retval to a location.
class CCValAssign {
public:
@@ -91,6 +93,12 @@
};
+/// CCAssignFn - This function assigns a location for Val, updating State to
+/// reflect the change.
+typedef bool CCAssignFn(unsigned ValNo, MVT::ValueType ValVT,
+MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo,
+unsigned ArgFlags, CCState &State);
+
/// CCState - This class holds information needed while lowering arguments and
/// return values. It captures which registers are already assigned and which
@@ -121,6 +129,15 @@
bool isAllocated(unsigned Reg) const {
return UsedRegs[Reg/32] & (1 << (Reg&31));
}
+
+ /// AnalyzeCallOperands - Analyze an ISD::CALL node, incorporating info
+ /// about the passed values into this state.
+ void AnalyzeCallOperands(SDNode *TheCall, CCAssignFn Fn);
+
+ /// AnalyzeFormalArguments - Analyze an ISD::FORMAL_ARGUMENTS node,
+ /// incorporating info about the formals into this state.
+ void AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn);
+
/// getFirstUnallocated - Return the first unallocated register in the set,
or
/// NumRegs if they are all allocated.
@@ -168,6 +185,8 @@
void MarkAllocated(unsigned Reg);
};
+
+
} // end namespace llvm
#endif
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
CallingConvLower.cpp updated: 1.2 -> 1.3
---
Log message:
add methods to analyze calls and formals.
---
Diffs of the changes: (+34 -0)
CallingConvLower.cpp | 34 ++
1 files changed, 34 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp:1.2
llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp:1.3
--- llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp:1.2 Mon Feb 26
23:13:54 2007
+++ llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp Wed Feb 28 00:56:20 2007
@@ -13,6 +13,7 @@
//===--===//
#include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
using namespace llvm;
@@ -35,3 +36,36 @@
for (; (Reg = *RegAliases); ++RegAliases)
UsedRegs[Reg/32] |= 1 << (Reg&31);
}
+
+/// AnalyzeCallOperands - Analyze an ISD::CALL node, incorporating info
+/// about the passed values into this state.
+void CCState::AnalyzeCallOperands(SDNode *TheCall, CCAssignFn Fn) {
+ unsigned NumOps = (TheCall->getNumOperands() - 5) / 2;
+ for (unsigned i = 0; i != NumOps; ++i) {
+MVT::ValueType ArgVT = TheCall->getOperand(5+2*i).getValueType();
+SDOperand FlagOp = TheCall->getOperand(5+2*i+1);
+unsigned ArgFlags =cast(FlagOp)->getValue();
+if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
+ cerr << "Call operand #" << i << " has unhandled type "
+ << MVT::getValueTypeString(ArgVT) << "\n";
+ abort();
+}
+ }
+}
+
+/// AnalyzeFormalArguments - Analyze an ISD::FORMAL_ARGUMENTS node,
+/// incorporating info about the formals into this state.
+void CCState::AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn) {
+ unsigned NumArgs = TheArgs->getNumValues()-1;
+
+ for (unsigned i = 0; i != NumArgs; ++i) {
+MVT::ValueType ArgVT = TheArgs->getValueType(i);
+SDOperand FlagOp = TheArgs->getOperand(3+i);
+unsigned ArgFlags = cast(FlagOp)->getValue();
+if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
+ cerr << "Formal argument #" << i << " has unhandled type "
+ << MVT::getValueTypeString(ArgVT) << "\n";
+ abort();
+}
+ }
+}
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[llvm-commits] CVS: llvm/lib/CodeGen/PrologEpilogInserter.cpp
Changes in directory llvm/lib/CodeGen: PrologEpilogInserter.cpp updated: 1.73 -> 1.74 --- Log message: add a newline at end of file --- Diffs of the changes: (+1 -0) PrologEpilogInserter.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.73 llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.74 --- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.73 Tue Feb 27 18:58:37 2007 +++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Wed Feb 28 00:42:11 2007 @@ -459,3 +459,4 @@ } } } + ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.352 -> 1.353
---
Log message:
switch LowerFastCCCallTo over to using the new fastcall description.
---
Diffs of the changes: (+40 -97)
X86ISelLowering.cpp | 137 +++-
1 files changed, 40 insertions(+), 97 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.352
llvm/lib/Target/X86/X86ISelLowering.cpp:1.353
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.352 Wed Feb 28 00:21:19 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Feb 28 00:26:33 2007
@@ -958,58 +958,19 @@
SDOperand Callee= Op.getOperand(4);
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
- // Count how many bytes are to be pushed on the stack.
- unsigned NumBytes = 0;
-
- // Keep track of the number of integer regs passed so far. This can be
either
- // 0 (neither EAX/ECX or EDX used), 1 (EAX/ECX is used) or 2 (EAX/ECX and EDX
- // are both used).
- unsigned NumIntRegs = 0;
- unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
-
- static const unsigned GPRArgRegs[][2] = {
-{ X86::CL, X86::DL },
-{ X86::CX, X86::DX },
-{ X86::ECX, X86::EDX }
- };
- static const unsigned XMMArgRegs[] = {
-X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
- };
-
+
+ SmallVector ArgLocs;
+ CCState CCInfo(CC, getTargetMachine(), ArgLocs);
+
for (unsigned i = 0; i != NumOps; ++i) {
-SDOperand Arg = Op.getOperand(5+2*i);
-
-switch (Arg.getValueType()) {
-default: assert(0 && "Unknown value type!");
-case MVT::i8:
-case MVT::i16:
-case MVT::i32:
- if (NumIntRegs < 2) {
- ++NumIntRegs;
- break;
- } // Fall through
-case MVT::f32:
- NumBytes += 4;
- break;
-case MVT::f64:
- NumBytes += 8;
- break;
-case MVT::v16i8:
-case MVT::v8i16:
-case MVT::v4i32:
-case MVT::v2i64:
-case MVT::v4f32:
-case MVT::v2f64:
- if (NumXMMRegs < 4)
-NumXMMRegs++;
- else {
-// XMM arguments have to be aligned on 16-byte boundary.
-NumBytes = ((NumBytes + 15) / 16) * 16;
-NumBytes += 16;
- }
- break;
-}
+MVT::ValueType ArgVT = Op.getOperand(5+2*i).getValueType();
+unsigned ArgFlags
=cast(Op.getOperand(5+2*i+1))->getValue();
+if (CC_X86_32_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
+ assert(0 && "Unhandled argument type!");
}
+
+ // Get a count of how many bytes are to be pushed on the stack.
+ unsigned NumBytes = CCInfo.getNextStackOffset();
// Make sure the instruction takes 8n+4 bytes to make sure the start of the
// arguments and the arguments after the retaddr has been pushed are aligned.
@@ -1018,59 +979,41 @@
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
getPointerTy()));
- // Arguments go on the stack in reverse order, as specified by the ABI.
- unsigned ArgOffset = 0;
- NumIntRegs = 0;
+
SmallVector, 8> RegsToPass;
SmallVector MemOpChains;
- SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
- for (unsigned i = 0; i != NumOps; ++i) {
-SDOperand Arg = Op.getOperand(5+2*i);
-
-switch (Arg.getValueType()) {
-default: assert(0 && "Unexpected ValueType for argument!");
-case MVT::i8:
-case MVT::i16:
-case MVT::i32:
- if (NumIntRegs < 2) {
-unsigned RegToUse =
- GPRArgRegs[Arg.getValueType()-MVT::i8][NumIntRegs];
-RegsToPass.push_back(std::make_pair(RegToUse, Arg));
-++NumIntRegs;
+
+ SDOperand StackPtr;
+
+ // Walk the register/memloc assignments, inserting copies/loads.
+ for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
+CCValAssign &VA = ArgLocs[i];
+SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
+
+// Promote the value if needed.
+switch (VA.getLocInfo()) {
+ default: assert(0 && "Unknown loc info!");
+ case CCValAssign::Full: break;
+ case CCValAssign::SExt:
+Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
+break;
+ case CCValAssign::ZExt:
+Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
+break;
+ case CCValAssign::AExt:
+Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
break;
- } // Fall through
-case MVT::f32: {
- SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
- PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
- MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
- ArgOffset += 4;
- break;
}
-case MVT::f64: {
- SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
+
+if (VA.isRegLoc()) {
+ RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
+} else {
+ assert(VA.isMemLoc());
+ if (StackPtr.Val == 0)
+StackPtr = DAG.getRegister(getStackPtrRe
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.351 -> 1.352
---
Log message:
switch LowerFastCCArguments over to using the autogenerated Fastcall
description.
---
Diffs of the changes: (+59 -174)
X86ISelLowering.cpp | 233 +---
1 files changed, 59 insertions(+), 174 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.351
llvm/lib/Target/X86/X86ISelLowering.cpp:1.352
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.351 Wed Feb 28 00:10:12 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Feb 28 00:21:19 2007
@@ -601,66 +601,6 @@
return VReg;
}
-/// HowToPassArgument - Returns how an formal argument of the specified type
-/// should be passed. If it is through stack, returns the size of the stack
-/// slot; if it is through integer or XMM register, returns the number of
-/// integer or XMM registers are needed.
-static void
-HowToPassCallArgument(MVT::ValueType ObjectVT,
- bool ArgInReg,
- unsigned NumIntRegs, unsigned NumXMMRegs,
- unsigned MaxNumIntRegs,
- unsigned &ObjSize, unsigned &ObjIntRegs,
- unsigned &ObjXMMRegs) {
- ObjSize = 0;
- ObjIntRegs = 0;
- ObjXMMRegs = 0;
-
- if (MaxNumIntRegs>3) {
-// We don't have too much registers on ia32! :)
-MaxNumIntRegs = 3;
- }
-
- switch (ObjectVT) {
- default: assert(0 && "Unhandled argument type!");
- case MVT::i8:
- if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
- ObjIntRegs = 1;
- else
- ObjSize = 1;
- break;
- case MVT::i16:
- if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
- ObjIntRegs = 1;
- else
- ObjSize = 2;
- break;
- case MVT::i32:
- if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
- ObjIntRegs = 1;
- else
- ObjSize = 4;
- break;
- case MVT::f32:
-ObjSize = 4;
-break;
- case MVT::f64:
-ObjSize = 8;
-break;
- case MVT::v16i8:
- case MVT::v8i16:
- case MVT::v4i32:
- case MVT::v2i64:
- case MVT::v4f32:
- case MVT::v2f64:
-if (NumXMMRegs < 4)
- ObjXMMRegs = 1;
-else
- ObjSize = 16;
-break;
- }
-}
-
SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
bool isStdCall) {
unsigned NumArgs = Op.Val->getNumValues() - 1;
@@ -929,138 +869,83 @@
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
SDOperand Root = Op.getOperand(0);
- SmallVector ArgValues;
-
- // Add DAG nodes to load the arguments... On entry to a function the stack
- // frame looks like this:
- //
- // [ESP] -- return address
- // [ESP + 4] -- first nonreg argument (leftmost lexically)
- // [ESP + 8] -- second nonreg argument, if 1st argument is <= 4 bytes in size
- //...
- unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
-
- // Keep track of the number of integer regs passed so far. This can be
either
- // 0 (neither EAX/ECX or EDX used), 1 (EAX/ECX is used) or 2 (EAX/ECX and EDX
- // are both used).
- unsigned NumIntRegs = 0;
- unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
-
- static const unsigned XMMArgRegs[] = {
-X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
- };
-
- static const unsigned GPRArgRegs[][2] = {
-{ X86::CL, X86::DL },
-{ X86::CX, X86::DX },
-{ X86::ECX, X86::EDX }
- };
- static const TargetRegisterClass* GPRClasses[3] = {
-X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass
- };
-
- for (unsigned i = 0; i < NumArgs; ++i) {
-MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
-unsigned ArgIncrement = 4;
-unsigned ObjSize = 0;
-unsigned ObjXMMRegs = 0;
-unsigned ObjIntRegs = 0;
-unsigned Reg = 0;
-SDOperand ArgValue;
-
-HowToPassCallArgument(ObjectVT,
- true, // Use as much registers as possible
- NumIntRegs, NumXMMRegs, 2,
- ObjSize, ObjIntRegs, ObjXMMRegs);
+ SmallVector ArgLocs;
+ CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
+ ArgLocs);
+
+ for (unsigned i = 0; i != NumArgs; ++i) {
+MVT::ValueType ArgVT = Op.getValue(i).getValueType();
+unsigned ArgFlags = cast(Op.getOperand(3+i))->getValue();
+if (CC_X86_32_FastCall(i, ArgVT, ArgVT, CCValAssign::Full,
ArgFlags,CCInfo))
+ assert(0 && "Unhandled argument type!");
+ }
+
+ SmallVector ArgValues;
+ unsigned LastVal = ~0U;
+ for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
+CCValAssign &VA = ArgLocs[i];
+// TODO: If an arg is passed in two places (e.g. reg and stack), skip later
+// places.
+assert(VA.getValNo() != LastVal &&
+ "Don't support value assigned to multiple locs yet");
+LastVal = VA.getValNo();
-if (Obj
[llvm-commits] CVS: llvm/lib/Target/X86/X86CallingConv.td
Changes in directory llvm/lib/Target/X86: X86CallingConv.td updated: 1.8 -> 1.9 --- Log message: add new CC_X86_32_FastCall calling conv, which describes fastcall on win32. Factor out a CC_X86_32_Common convention, which is the part shared between ccc, stdcall and fastcall --- Diffs of the changes: (+29 -10) X86CallingConv.td | 39 +-- 1 files changed, 29 insertions(+), 10 deletions(-) Index: llvm/lib/Target/X86/X86CallingConv.td diff -u llvm/lib/Target/X86/X86CallingConv.td:1.8 llvm/lib/Target/X86/X86CallingConv.td:1.9 --- llvm/lib/Target/X86/X86CallingConv.td:1.8 Tue Feb 27 23:31:48 2007 +++ llvm/lib/Target/X86/X86CallingConv.td Wed Feb 28 00:20:01 2007 @@ -111,22 +111,18 @@ // X86 C Calling Convention //===--===// -def CC_X86_32_C : CallingConv<[ - // Promote i8/i16 arguments to i32. - CCIfType<[i8, i16], CCPromoteToType>, - - // The first 3 integer arguments, if marked 'inreg', are passed in integer - // registers. - CCIfInReg>>, - - // Other Integer/Float values get stored in stack slots that are 4 bytes in +/// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP +/// values are spilled on the stack, and the first 4 vector values go in XMM +/// regs. +def CC_X86_32_Common : CallingConv<[ + // Integer/Float values get stored in stack slots that are 4 bytes in // size and 4-byte aligned. CCIfType<[i32, f32], CCAssignToStack<4, 4>>, // Doubles get 8-byte slots that are 4-byte aligned. CCIfType<[f64], CCAssignToStack<8, 4>>, - // The first 4 Vector arguments are passed in XMM registers. + // The first 4 vector arguments are passed in XMM registers. CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, @@ -134,5 +130,28 @@ CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>> ]>; +def CC_X86_32_C : CallingConv<[ + // Promote i8/i16 arguments to i32. + CCIfType<[i8, i16], CCPromoteToType>, + + // The first 3 integer arguments, if marked 'inreg', are passed in integer + // registers. + CCIfInReg>>, + + // Otherwise, same as everything else. + CCDelegateTo +]>; + + +def CC_X86_32_FastCall : CallingConv<[ + // Promote i8/i16 arguments to i32. + CCIfType<[i8, i16], CCPromoteToType>, + + // The first 2 integer arguments are passed in ECX/EDX + CCIfInReg>>, + + // Otherwise, same as everything else. + CCDelegateTo +]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.350 -> 1.351
---
Log message:
rearrange code
---
Diffs of the changes: (+441 -449)
X86ISelLowering.cpp | 890 +---
1 files changed, 441 insertions(+), 449 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.350
llvm/lib/Target/X86/X86ISelLowering.cpp:1.351
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.350 Wed Feb 28 00:05:16 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Feb 28 00:10:12 2007
@@ -912,211 +912,283 @@
//===--===//
-// X86-64 C Calling Convention implementation
+// FastCall Calling Convention implementation
//===--===//
-
-
-
+//
+// The X86 'fastcall' calling convention passes up to two integer arguments in
+// registers (an appropriate portion of ECX/EDX), passes arguments in C order,
+// and requires that the callee pop its arguments off the stack (allowing
proper
+// tail calls), and has the same return value conventions as C calling convs.
+//
+// This calling convention always arranges for the callee pop value to be 8n+4
+// bytes, which is needed for tail recursion elimination and stack alignment
+// reasons.
SDOperand
-X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
- unsigned NumArgs = Op.Val->getNumValues() - 1;
+X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
+ unsigned NumArgs = Op.Val->getNumValues()-1;
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
SDOperand Root = Op.getOperand(0);
- bool isVarArg = cast(Op.getOperand(2))->getValue() != 0;
+ SmallVector ArgValues;
+
+ // Add DAG nodes to load the arguments... On entry to a function the stack
+ // frame looks like this:
+ //
+ // [ESP] -- return address
+ // [ESP + 4] -- first nonreg argument (leftmost lexically)
+ // [ESP + 8] -- second nonreg argument, if 1st argument is <= 4 bytes in size
+ //...
+ unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
+
+ // Keep track of the number of integer regs passed so far. This can be
either
+ // 0 (neither EAX/ECX or EDX used), 1 (EAX/ECX is used) or 2 (EAX/ECX and EDX
+ // are both used).
+ unsigned NumIntRegs = 0;
+ unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
- static const unsigned GPR64ArgRegs[] = {
-X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
- };
static const unsigned XMMArgRegs[] = {
-X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
-X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
+X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
};
- SmallVector ArgLocs;
- CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
- ArgLocs);
-
- for (unsigned i = 0; i != NumArgs; ++i) {
-MVT::ValueType ArgVT = Op.getValue(i).getValueType();
-unsigned ArgFlags = cast(Op.getOperand(3+i))->getValue();
-if (CC_X86_64_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
- assert(0 && "Unhandled argument type!");
- }
-
- SmallVector ArgValues;
- unsigned LastVal = ~0U;
- for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
-CCValAssign &VA = ArgLocs[i];
-// TODO: If an arg is passed in two places (e.g. reg and stack), skip later
-// places.
-assert(VA.getValNo() != LastVal &&
- "Don't support value assigned to multiple locs yet");
-LastVal = VA.getValNo();
+ static const unsigned GPRArgRegs[][2] = {
+{ X86::CL, X86::DL },
+{ X86::CX, X86::DX },
+{ X86::ECX, X86::EDX }
+ };
+
+ static const TargetRegisterClass* GPRClasses[3] = {
+X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass
+ };
+
+ for (unsigned i = 0; i < NumArgs; ++i) {
+MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
+unsigned ArgIncrement = 4;
+unsigned ObjSize = 0;
+unsigned ObjXMMRegs = 0;
+unsigned ObjIntRegs = 0;
+unsigned Reg = 0;
+SDOperand ArgValue;
+
+HowToPassCallArgument(ObjectVT,
+ true, // Use as much registers as possible
+ NumIntRegs, NumXMMRegs, 2,
+ ObjSize, ObjIntRegs, ObjXMMRegs);
-if (VA.isRegLoc()) {
- MVT::ValueType RegVT = VA.getLocVT();
- TargetRegisterClass *RC;
- if (RegVT == MVT::i32)
-RC = X86::GR32RegisterClass;
- else if (RegVT == MVT::i64)
-RC = X86::GR64RegisterClass;
- else if (RegVT == MVT::f32)
-RC = X86::FR32RegisterClass;
- else if (RegVT == MVT::f64)
-RC = X86::FR64RegisterClass;
- else {
-assert(MVT::isVector(RegVT));
-RC = X86::VR128RegisterClass;
+if (ObjSize > 4)
+ ArgIncrement
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.349 -> 1.350
X86ISelLowering.h updated: 1.89 -> 1.90
---
Log message:
remove fastcc (not fastcall) support
---
Diffs of the changes: (+26 -58)
X86ISelLowering.cpp | 65
X86ISelLowering.h | 19 ---
2 files changed, 26 insertions(+), 58 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.349
llvm/lib/Target/X86/X86ISelLowering.cpp:1.350
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.349 Tue Feb 27 23:46:49 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Feb 28 00:05:16 2007
@@ -1223,8 +1223,7 @@
// bytes, which is needed for tail recursion elimination and stack alignment
// reasons.
SDOperand
-X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG,
-bool isFastCall) {
+X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
unsigned NumArgs = Op.Val->getNumValues()-1;
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
@@ -1250,17 +1249,16 @@
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
};
- static const unsigned GPRArgRegs[][2][2] = {
-{{ X86::AL, X86::DL }, { X86::CL, X86::DL }},
-{{ X86::AX, X86::DX }, { X86::CX, X86::DX }},
-{{ X86::EAX, X86::EDX }, { X86::ECX, X86::EDX }}
+ static const unsigned GPRArgRegs[][2] = {
+{ X86::CL, X86::DL },
+{ X86::CX, X86::DX },
+{ X86::ECX, X86::EDX }
};
static const TargetRegisterClass* GPRClasses[3] = {
X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass
};
- unsigned GPRInd = (isFastCall ? 1 : 0);
for (unsigned i = 0; i < NumArgs; ++i) {
MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
unsigned ArgIncrement = 4;
@@ -1272,8 +1270,7 @@
HowToPassCallArgument(ObjectVT,
true, // Use as much registers as possible
- NumIntRegs, NumXMMRegs,
- (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS),
+ NumIntRegs, NumXMMRegs, 2,
ObjSize, ObjIntRegs, ObjXMMRegs);
if (ObjSize > 4)
@@ -1285,7 +1282,7 @@
case MVT::i8:
case MVT::i16:
case MVT::i32: {
-unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][GPRInd][NumIntRegs];
+unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][NumIntRegs];
Reg = AddLiveIn(MF, RegToUse, GPRClasses[ObjectVT-MVT::i8]);
ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
break;
@@ -1296,7 +1293,6 @@
case MVT::v2i64:
case MVT::v4f32:
case MVT::v2f64: {
-assert(!isFastCall && "Unhandled argument type!");
Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass);
ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
break;
@@ -1360,7 +1356,6 @@
case MVT::v2i64:
case MVT::v4f32:
case MVT::v2f64:
-assert(!isFastCall && "Unknown result type");
MF.addLiveOut(X86::XMM0);
break;
}
@@ -1386,17 +1381,15 @@
unsigned NumIntRegs = 0;
unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
- static const unsigned GPRArgRegs[][2][2] = {
-{{ X86::AL, X86::DL }, { X86::CL, X86::DL }},
-{{ X86::AX, X86::DX }, { X86::CX, X86::DX }},
-{{ X86::EAX, X86::EDX }, { X86::ECX, X86::EDX }}
+ static const unsigned GPRArgRegs[][2] = {
+{ X86::CL, X86::DL },
+{ X86::CX, X86::DX },
+{ X86::ECX, X86::EDX }
};
static const unsigned XMMArgRegs[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
};
- bool isFastCall = CC == CallingConv::X86_FastCall;
- unsigned GPRInd = isFastCall ? 1 : 0;
for (unsigned i = 0; i != NumOps; ++i) {
SDOperand Arg = Op.getOperand(5+2*i);
@@ -1404,12 +1397,10 @@
default: assert(0 && "Unknown value type!");
case MVT::i8:
case MVT::i16:
-case MVT::i32: {
- unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS);
- if (NumIntRegs < MaxNumIntRegs) {
+case MVT::i32:
+ if (NumIntRegs < 2) {
++NumIntRegs;
break;
- }
} // Fall through
case MVT::f32:
NumBytes += 4;
@@ -1423,7 +1414,6 @@
case MVT::v2i64:
case MVT::v4f32:
case MVT::v2f64:
- assert(!isFastCall && "Unknown value type!");
if (NumXMMRegs < 4)
NumXMMRegs++;
else {
@@ -1455,16 +1445,14 @@
default: assert(0 && "Unexpected ValueType for argument!");
case MVT::i8:
case MVT::i16:
-case MVT::i32: {
- unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS);
- if (NumIntRegs < MaxNumIntRegs) {
- unsigned RegToUse =
- GPRArgRegs[Arg.getValueType()-MVT::i8][GPRInd][NumIntRegs];
- RegsToPass.push_back(std::make_pair(RegToUse,
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.348 -> 1.349
---
Log message:
switch LowerCCCArguments over to using autogenerated CC.
---
Diffs of the changes: (+62 -94)
X86ISelLowering.cpp | 156
1 files changed, 62 insertions(+), 94 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.348
llvm/lib/Target/X86/X86ISelLowering.cpp:1.349
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.348 Tue Feb 27 23:39:26 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Feb 27 23:46:49 2007
@@ -667,124 +667,92 @@
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
SDOperand Root = Op.getOperand(0);
- SmallVector ArgValues;
bool isVarArg = cast(Op.getOperand(2))->getValue() != 0;
- // Add DAG nodes to load the arguments... On entry to a function on the X86,
- // the stack frame looks like this:
- //
- // [ESP] -- return address
- // [ESP + 4] -- first argument (leftmost lexically)
- // [ESP + 8] -- second argument, if first argument is <= 4 bytes in size
- //...
- //
- unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
- unsigned NumSRetBytes= 0; // How much bytes on stack used for struct return
- unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
- unsigned NumIntRegs = 0; // Integer regs used for parameter passing
-
- static const unsigned XMMArgRegs[] = {
-X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
- };
- static const unsigned GPRArgRegs[][3] = {
-{ X86::AL, X86::DL, X86::CL },
-{ X86::AX, X86::DX, X86::CX },
-{ X86::EAX, X86::EDX, X86::ECX }
- };
- static const TargetRegisterClass* GPRClasses[3] = {
-X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass
- };
+ SmallVector ArgLocs;
+ CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
+ ArgLocs);
- // Handle regparm attribute
- SmallVector ArgInRegs(NumArgs, false);
- SmallVector SRetArgs(NumArgs, false);
- if (!isVarArg) {
-for (unsigned i = 0; i(Op.getOperand(3+i))->getValue();
- ArgInRegs[i] = (Flags >> 1) & 1;
- SRetArgs[i]= (Flags >> 2) & 1;
-}
+ for (unsigned i = 0; i != NumArgs; ++i) {
+MVT::ValueType ArgVT = Op.getValue(i).getValueType();
+unsigned ArgFlags = cast(Op.getOperand(3+i))->getValue();
+if (CC_X86_32_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
+ assert(0 && "Unhandled argument type!");
}
- for (unsigned i = 0; i < NumArgs; ++i) {
-MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
-unsigned ArgIncrement = 4;
-unsigned ObjSize = 0;
-unsigned ObjXMMRegs = 0;
-unsigned ObjIntRegs = 0;
-unsigned Reg = 0;
-SDOperand ArgValue;
-
-HowToPassCallArgument(ObjectVT,
- ArgInRegs[i],
- NumIntRegs, NumXMMRegs, 3,
- ObjSize, ObjIntRegs, ObjXMMRegs);
-
-if (ObjSize > 4)
- ArgIncrement = ObjSize;
-
-if (ObjIntRegs || ObjXMMRegs) {
- switch (ObjectVT) {
- default: assert(0 && "Unhandled argument type!");
- case MVT::i8:
- case MVT::i16:
- case MVT::i32: {
- unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][NumIntRegs];
- Reg = AddLiveIn(MF, RegToUse, GPRClasses[ObjectVT-MVT::i8]);
- ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
- break;
- }
- case MVT::v16i8:
- case MVT::v8i16:
- case MVT::v4i32:
- case MVT::v2i64:
- case MVT::v4f32:
- case MVT::v2f64:
- assert(!isStdCall && "Unhandled argument type!");
- Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass);
- ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
- break;
+ SmallVector ArgValues;
+ unsigned LastVal = ~0U;
+ for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
+CCValAssign &VA = ArgLocs[i];
+// TODO: If an arg is passed in two places (e.g. reg and stack), skip later
+// places.
+assert(VA.getValNo() != LastVal &&
+ "Don't support value assigned to multiple locs yet");
+LastVal = VA.getValNo();
+
+if (VA.isRegLoc()) {
+ MVT::ValueType RegVT = VA.getLocVT();
+ TargetRegisterClass *RC;
+ if (RegVT == MVT::i32)
+RC = X86::GR32RegisterClass;
+ else {
+assert(MVT::isVector(RegVT));
+RC = X86::VR128RegisterClass;
}
- NumIntRegs += ObjIntRegs;
- NumXMMRegs += ObjXMMRegs;
-}
-if (ObjSize) {
- // XMM arguments have to be aligned on 16-byte boundary.
- if (ObjSize == 16)
-ArgOffset = ((ArgOffset + 15) / 16) * 16;
- // Create the SelectionDAG nodes corresponding to a load from this
- // parameter.
- int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
- SDOperand FIN = DAG.getFrameInde
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.347 -> 1.348
---
Log message:
simplify sret handling
---
Diffs of the changes: (+5 -13)
X86ISelLowering.cpp | 18 +-
1 files changed, 5 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.347
llvm/lib/Target/X86/X86ISelLowering.cpp:1.348
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.347 Tue Feb 27 23:31:48 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Feb 27 23:39:26 2007
@@ -819,7 +819,6 @@
SmallVector MemOpChains;
SDOperand StackPtr;
- unsigned NumSRetBytes = 0;
// Walk the register/memloc assignments, inserting copies/loads.
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
@@ -850,19 +849,12 @@
SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
-
- // FIXME: What is this doing?
- unsigned Flags =
-cast(Op.getOperand(5+2*VA.getValNo()+1))->getValue();
- if ((Flags >> 2) & 1)
-NumSRetBytes += 4;
}
}
- // Sanity check: we haven't seen NumSRetBytes > 4
- assert((NumSRetBytes<=4) &&
- "Too much space for struct-return pointer requested");
-
+ // If the first argument is an sret pointer, remember it.
+ bool isSRet = NumOps
&&(cast(Op.getOperand(6))->getValue()&4);
+
if (!MemOpChains.empty())
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
&MemOpChains[0], MemOpChains.size());
@@ -926,14 +918,14 @@
if (CC == CallingConv::X86_StdCall) {
if (isVarArg)
- NumBytesForCalleeToPush = NumSRetBytes;
+ NumBytesForCalleeToPush = isSRet ? 4 : 0;
else
NumBytesForCalleeToPush = NumBytes;
} else {
// If this is is a call to a struct-return function, the callee
// pops the hidden struct pointer, so we have to push it back.
// This is common for Darwin/X86, Linux & Mingw32 targets.
-NumBytesForCalleeToPush = NumSRetBytes;
+NumBytesForCalleeToPush = isSRet ? 4 : 0;
}
NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
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[llvm-commits] CVS: llvm/lib/Target/X86/X86CallingConv.td X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86CallingConv.td updated: 1.7 -> 1.8
X86ISelLowering.cpp updated: 1.346 -> 1.347
---
Log message:
switch LowerallTo over to using an autogenerated callingconv
---
Diffs of the changes: (+71 -110)
X86CallingConv.td | 28 +
X86ISelLowering.cpp | 153 ++--
2 files changed, 71 insertions(+), 110 deletions(-)
Index: llvm/lib/Target/X86/X86CallingConv.td
diff -u llvm/lib/Target/X86/X86CallingConv.td:1.7
llvm/lib/Target/X86/X86CallingConv.td:1.8
--- llvm/lib/Target/X86/X86CallingConv.td:1.7 Tue Feb 27 23:30:29 2007
+++ llvm/lib/Target/X86/X86CallingConv.td Tue Feb 27 23:31:48 2007
@@ -107,4 +107,32 @@
]>;
+//===--===//
+// X86 C Calling Convention
+//===--===//
+
+def CC_X86_32_C : CallingConv<[
+ // Promote i8/i16 arguments to i32.
+ CCIfType<[i8, i16], CCPromoteToType>,
+
+ // The first 3 integer arguments, if marked 'inreg', are passed in integer
+ // registers.
+ CCIfInReg>>,
+
+ // Other Integer/Float values get stored in stack slots that are 4 bytes in
+ // size and 4-byte aligned.
+ CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
+
+ // Doubles get 8-byte slots that are 4-byte aligned.
+ CCIfType<[f64], CCAssignToStack<8, 4>>,
+
+ // The first 4 Vector arguments are passed in XMM registers.
+ CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
+ CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
+
+ // Other vectors get 16-byte stack slots that are 16-byte aligned.
+ CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>
+]>;
+
+
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.346
llvm/lib/Target/X86/X86ISelLowering.cpp:1.347
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.346 Tue Feb 27 22:55:35 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Feb 27 23:31:48 2007
@@ -641,14 +641,6 @@
else
ObjSize = 4;
break;
- case MVT::i64:
- if (ArgInReg && (NumIntRegs+2 <= MaxNumIntRegs)) {
- ObjIntRegs = 2;
- } else if (ArgInReg && (NumIntRegs+1 <= MaxNumIntRegs)) {
- ObjIntRegs = 1;
- ObjSize = 4;
- } else
- ObjSize = 8;
case MVT::f32:
ObjSize = 4;
break;
@@ -808,121 +800,62 @@
SDOperand Callee= Op.getOperand(4);
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
- static const unsigned XMMArgRegs[] = {
-X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
- };
- static const unsigned GPR32ArgRegs[] = {
-X86::EAX, X86::EDX, X86::ECX
- };
-
- // Count how many bytes are to be pushed on the stack.
- unsigned NumBytes = 0;
- // Keep track of the number of integer regs passed so far.
- unsigned NumIntRegs = 0;
- // Keep track of the number of XMM regs passed so far.
- unsigned NumXMMRegs = 0;
- // How much bytes on stack used for struct return
- unsigned NumSRetBytes= 0;
-
- // Handle regparm attribute
- SmallVector ArgInRegs(NumOps, false);
- SmallVector SRetArgs(NumOps, false);
- for (unsigned i = 0; i(Op.getOperand(5+2*i+1))->getValue();
-ArgInRegs[i] = (Flags >> 1) & 1;
-SRetArgs[i] = (Flags >> 2) & 1;
- }
+ SmallVector ArgLocs;
+ CCState CCInfo(CC, getTargetMachine(), ArgLocs);
- // Calculate stack frame size
for (unsigned i = 0; i != NumOps; ++i) {
-SDOperand Arg = Op.getOperand(5+2*i);
-unsigned ArgIncrement = 4;
-unsigned ObjSize = 0;
-unsigned ObjIntRegs = 0;
-unsigned ObjXMMRegs = 0;
-
-HowToPassCallArgument(Arg.getValueType(),
- ArgInRegs[i],
- NumIntRegs, NumXMMRegs, 3,
- ObjSize, ObjIntRegs, ObjXMMRegs);
-if (ObjSize > 4)
- ArgIncrement = ObjSize;
-
-NumIntRegs += ObjIntRegs;
-NumXMMRegs += ObjXMMRegs;
-if (ObjSize) {
- // XMM arguments have to be aligned on 16-byte boundary.
- if (ObjSize == 16)
-NumBytes = ((NumBytes + 15) / 16) * 16;
- NumBytes += ArgIncrement;
-}
+MVT::ValueType ArgVT = Op.getOperand(5+2*i).getValueType();
+unsigned ArgFlags
=cast(Op.getOperand(5+2*i+1))->getValue();
+if (CC_X86_32_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
+ assert(0 && "Unhandled argument type!");
}
+
+ // Get a count of how many bytes are to be pushed on the stack.
+ unsigned NumBytes = CCInfo.getNextStackOffset();
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
getPointerTy()));
- // Arguments go on the stack in reverse order, as specified by the ABI.
- unsigned ArgOffset = 0;
- NumXMMRegs = 0;
- NumIntRegs = 0;
SmallVector, 8> RegsToPass;
SmallVector MemOpChains;
- SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
- for (unsigned i = 0; i != NumOps; ++i) {
-SDOperand Arg = Op.getOperand(5+2*i);
-unsi
[llvm-commits] CVS: llvm/lib/Target/X86/X86CallingConv.td
Changes in directory llvm/lib/Target/X86: X86CallingConv.td updated: 1.6 -> 1.7 --- Log message: rename stuff --- Diffs of the changes: (+24 -24) X86CallingConv.td | 48 1 files changed, 24 insertions(+), 24 deletions(-) Index: llvm/lib/Target/X86/X86CallingConv.td diff -u llvm/lib/Target/X86/X86CallingConv.td:1.6 llvm/lib/Target/X86/X86CallingConv.td:1.7 --- llvm/lib/Target/X86/X86CallingConv.td:1.6 Tue Feb 27 22:51:41 2007 +++ llvm/lib/Target/X86/X86CallingConv.td Tue Feb 27 23:30:29 2007 @@ -12,9 +12,9 @@ // //===--===// -/// CCMatchIfSubtarget - Match if the current subtarget has a feature F. -class CCMatchIfSubtarget - : CCMatchIf().",F),A>; +/// CCIfSubtarget - Match if the current subtarget has a feature F. +class CCIfSubtarget + : CCIf().", F), A>; //===--===// // Return Value Calling Conventions @@ -23,22 +23,22 @@ // Return-value conventions common to all X86 CC's. def RetCC_X86Common : CallingConv<[ // Scalar values are returned in AX first, then DX. - CCMatchType<[i8] , CCAssignToReg<[AL]>>, - CCMatchType<[i16], CCAssignToReg<[AX]>>, - CCMatchType<[i32], CCAssignToReg<[EAX, EDX]>>, - CCMatchType<[i64], CCAssignToReg<[RAX, RDX]>>, + CCIfType<[i8] , CCAssignToReg<[AL]>>, + CCIfType<[i16], CCAssignToReg<[AX]>>, + CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>, + CCIfType<[i64], CCAssignToReg<[RAX, RDX]>>, // Vector types are always returned in XMM0. If the target doesn't have XMM0, // it won't have vector types. - CCMatchType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToReg<[XMM0]>> + CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToReg<[XMM0]>> ]>; // X86-32 C return-value convention. def RetCC_X86_32_C : CallingConv<[ // The X86-32 calling convention returns FP values in ST0, otherwise it is the // same as the common X86 calling conv. - CCMatchType<[f32], CCAssignToReg<[ST0]>>, - CCMatchType<[f64], CCAssignToReg<[ST0]>>, + CCIfType<[f32], CCAssignToReg<[ST0]>>, + CCIfType<[f64], CCAssignToReg<[ST0]>>, CCDelegateTo ]>; @@ -46,16 +46,16 @@ def RetCC_X86_32_Fast : CallingConv<[ // The X86-32 fastcc returns FP values in XMM0 if the target has SSE2, // otherwise it is the the C calling conventions. - CCMatchType<[f32], CCMatchIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>, - CCMatchType<[f64], CCMatchIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>, + CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>, + CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>, CCDelegateTo ]>; // X86-64 C return-value convention. def RetCC_X86_64_C : CallingConv<[ // The X86-64 calling convention always returns FP values in XMM0. - CCMatchType<[f32], CCAssignToReg<[XMM0]>>, - CCMatchType<[f64], CCAssignToReg<[XMM0]>>, + CCIfType<[f32], CCAssignToReg<[XMM0]>>, + CCIfType<[f64], CCAssignToReg<[XMM0]>>, CCDelegateTo ]>; @@ -64,7 +64,7 @@ // This is the root return-value convention for the X86-32 backend. def RetCC_X86_32 : CallingConv<[ // If FastCC, use RetCC_X86_32_Fast. - CCMatchIfCC<"CallingConv::Fast", CCDelegateTo>, + CCIfCC<"CallingConv::Fast", CCDelegateTo>, // Otherwise, use RetCC_X86_32_C. CCDelegateTo ]>; @@ -77,34 +77,34 @@ // This is the return-value convention used for the entire X86 backend. def RetCC_X86 : CallingConv<[ - CCMatchIfSubtarget<"is64Bit()", CCDelegateTo>, + CCIfSubtarget<"is64Bit()", CCDelegateTo>, CCDelegateTo ]>; //===--===// -// Argument Calling Conventions +// X86-64 Argument Calling Conventions //===--===// - def CC_X86_64_C : CallingConv<[ // Promote i8/i16 arguments to i32. - CCMatchType<[i8, i16], CCPromoteToType>, + CCIfType<[i8, i16], CCPromoteToType>, // The first 6 integer arguments are passed in integer registers. - CCMatchType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>, - CCMatchType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>, + CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>, + CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>, // The first 8 FP/Vector arguments are passed in XMM registers. - CCMatchType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], + CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>, // Integer/FP values get stored in stack slots that are 8 bytes in size and // 8-byte aligned if there are no more registers to hold them. - CCMatchType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>, + CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>, // Vectors get 16-byte stack
[llvm-commits] CVS: llvm/lib/Target/TargetCallingConv.td
Changes in directory llvm/lib/Target:
TargetCallingConv.td updated: 1.2 -> 1.3
---
Log message:
rename some CCActions, add CCIfInReg
---
Diffs of the changes: (+12 -7)
TargetCallingConv.td | 19 ---
1 files changed, 12 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/TargetCallingConv.td
diff -u llvm/lib/Target/TargetCallingConv.td:1.2
llvm/lib/Target/TargetCallingConv.td:1.3
--- llvm/lib/Target/TargetCallingConv.td:1.2Tue Feb 27 14:45:02 2007
+++ llvm/lib/Target/TargetCallingConv.tdTue Feb 27 23:29:33 2007
@@ -21,20 +21,25 @@
CCAction SubAction = A;
}
-/// CCMatchType - If the current argument is one of the specified types, apply
+/// CCIfType - If the current argument is one of the specified types, apply
/// Action A.
-class CCMatchType vts, CCAction A> : CCPredicateAction {
+class CCIfType vts, CCAction A> : CCPredicateAction {
list VTs = vts;
}
-/// CCMatchIf - If the predicate matches, apply A.
-class CCMatchIf : CCPredicateAction {
+/// CCIf - If the predicate matches, apply A.
+class CCIf : CCPredicateAction {
string Predicate = predicate;
}
-/// CCMatchIfCC - Match of the current calling convention is 'CC'.
-class CCMatchIfCC
- : CCMatchIf {}
+/// CCIfCC - Match of the current calling convention is 'CC'.
+class CCIfCC
+ : CCIf {}
+
+/// CCIfInReg - If this argument is marked with the 'inreg' attribute, apply
+/// the specified action.
+class CCIfInReg : CCIf<"ArgFlags & 2", A> {}
+
/// CCAssignToReg - This action matches if there is a register in the specified
/// list that is still available. If so, it assigns the value to the first
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[llvm-commits] CVS: llvm/utils/TableGen/CallingConvEmitter.cpp
Changes in directory llvm/utils/TableGen:
CallingConvEmitter.cpp updated: 1.3 -> 1.4
---
Log message:
rename some CCActions
---
Diffs of the changes: (+2 -2)
CallingConvEmitter.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/utils/TableGen/CallingConvEmitter.cpp
diff -u llvm/utils/TableGen/CallingConvEmitter.cpp:1.3
llvm/utils/TableGen/CallingConvEmitter.cpp:1.4
--- llvm/utils/TableGen/CallingConvEmitter.cpp:1.3 Tue Feb 27 22:43:48 2007
+++ llvm/utils/TableGen/CallingConvEmitter.cpp Tue Feb 27 23:29:06 2007
@@ -66,7 +66,7 @@
if (Action->isSubClassOf("CCPredicateAction")) {
O << IndentStr << "if (";
-if (Action->isSubClassOf("CCMatchType")) {
+if (Action->isSubClassOf("CCIfType")) {
ListInit *VTs = Action->getValueAsListInit("VTs");
for (unsigned i = 0, e = VTs->getSize(); i != e; ++i) {
Record *VT = VTs->getElementAsRecord(i);
@@ -74,7 +74,7 @@
O << "LocVT == " << getEnumName(getValueType(VT));
}
-} else if (Action->isSubClassOf("CCMatchIf")) {
+} else if (Action->isSubClassOf("CCIf")) {
O << Action->getValueAsString("Predicate");
} else {
Action->dump();
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[llvm-commits] CVS: llvm/Makefile.rules
Changes in directory llvm: Makefile.rules updated: 1.427 -> 1.428 --- Log message: correct dependency --- Diffs of the changes: (+1 -0) Makefile.rules |1 + 1 files changed, 1 insertion(+) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.427 llvm/Makefile.rules:1.428 --- llvm/Makefile.rules:1.427 Tue Feb 27 14:44:12 2007 +++ llvm/Makefile.rules Tue Feb 27 23:10:40 2007 @@ -1206,6 +1206,7 @@ TDFiles := $(strip $(wildcard $(PROJ_SRC_DIR)/*.td) \ $(LLVM_SRC_ROOT)/lib/Target/Target.td \ + $(LLVM_SRC_ROOT)/lib/Target/TargetCallingConv.td \ $(LLVM_SRC_ROOT)/lib/Target/TargetSelectionDAG.td \ $(LLVM_SRC_ROOT)/include/llvm/CodeGen/ValueTypes.td) \ $(wildcard $(LLVM_SRC_ROOT)/include/llvm/Intrinsics*.td) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.345 -> 1.346
---
Log message:
switch return value passing and the x86-64 calling convention information
over to being autogenerated from the X86CallingConv.td file.
---
Diffs of the changes: (+9 -137)
X86ISelLowering.cpp | 146 +++-
1 files changed, 9 insertions(+), 137 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.345
llvm/lib/Target/X86/X86ISelLowering.cpp:1.346
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.345 Mon Feb 26 23:28:59 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Feb 27 22:55:35 2007
@@ -429,67 +429,7 @@
// Return Value Calling Convention Implementation
//===--===//
-/// X86_RetCC_Assign - Implement the X86 return value conventions. This
returns
-/// true if the value wasn't handled by this CC.
-static bool X86_RetCC_Assign(unsigned ValNo, MVT::ValueType ValVT,
- unsigned ArgFlags, CCState &State) {
- MVT::ValueType LocVT = ValVT;
- CCValAssign::LocInfo LocInfo = CCValAssign::Full;
-
- // If this is a 32-bit value, assign to a 32-bit register if any are
- // available.
- if (LocVT == MVT::i8) {
-static const unsigned GPR8ArgRegs[] = { X86::AL, X86::DL };
-if (unsigned Reg = State.AllocateReg(GPR8ArgRegs, 2)) {
- State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
- return false;
-}
- }
- if (LocVT == MVT::i16) {
-static const unsigned GPR16ArgRegs[] = { X86::AX, X86::DX };
-if (unsigned Reg = State.AllocateReg(GPR16ArgRegs, 2)) {
- State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
- return false;
-}
- }
- if (LocVT == MVT::i32) {
-static const unsigned GPR32ArgRegs[] = { X86::EAX, X86::EDX };
-if (unsigned Reg = State.AllocateReg(GPR32ArgRegs, 2)) {
- State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
- return false;
-}
- }
- if (LocVT == MVT::i64) {
-static const unsigned GPR64ArgRegs[] = { X86::RAX, X86::RDX };
-if (unsigned Reg = State.AllocateReg(GPR64ArgRegs, 2)) {
- State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
- return false;
-}
- }
- if (MVT::isVector(LocVT)) {
-if (unsigned Reg = State.AllocateReg(X86::XMM0)) {
- State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
- return false;
-}
- }
- if (LocVT == MVT::f32 || LocVT == MVT::f64) {
-unsigned Reg;
-if (State.getTarget().getSubtarget().is64Bit())
- Reg = X86::XMM0; // FP values in X86-64 go in XMM0.
-else if (State.getCallingConv() == CallingConv::Fast &&
- State.getTarget().getSubtarget().hasSSE2())
- Reg = X86::XMM0; // FP values in X86-32 with fastcc go in XMM0.
-else
- Reg = X86::ST0; // FP values in X86-32 go in ST0.
-
-if ((Reg = State.AllocateReg(Reg))) {
- State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
- return false;
-}
- }
-
- return true;
-}
+#include "X86GenCallingConv.inc"
/// LowerRET - Lower an ISD::RET node.
SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
@@ -501,9 +441,10 @@
// Determine which register each value should be copied into.
for (unsigned i = 0; i != Op.getNumOperands() / 2; ++i) {
-if (X86_RetCC_Assign(i, Op.getOperand(i*2+1).getValueType(),
-
cast(Op.getOperand(i*2+2))->getValue(),
- CCInfo))
+MVT::ValueType VT = Op.getOperand(i*2+1).getValueType();
+if (RetCC_X86(i, VT, VT, CCValAssign::Full,
+ cast(Op.getOperand(i*2+2))->getValue(),
+ CCInfo))
assert(0 && "Unhandled result type!");
}
@@ -586,7 +527,8 @@
CCState CCInfo(CallingConv, getTargetMachine(), RVLocs);
for (unsigned i = 0, e = TheCall->getNumValues() - 1; i != e; ++i) {
-if (X86_RetCC_Assign(i, TheCall->getValueType(i), 0, CCInfo))
+MVT::ValueType VT = TheCall->getValueType(i);
+if (RetCC_X86(i, VT, VT, CCValAssign::Full, 0, CCInfo))
assert(0 && "Unhandled result type!");
}
@@ -1081,76 +1023,6 @@
//===--===//
-/// X86_64_CCC_AssignArgument - Implement the X86-64 C Calling Convention.
This
-/// returns true if the value was not handled by this calling convention.
-static bool X86_64_CCC_AssignArgument(unsigned ValNo,
- MVT::ValueType ArgVT, unsigned ArgFlags,
- CCState &State) {
- MVT::ValueType LocVT = ArgVT;
- CCValAssign::LocInfo LocInfo = CCValAssign::Full;
-
- // Promote the integer to 32 bits. If the input type is signed use a
- // sign exten
[llvm-commits] CVS: llvm/lib/Target/X86/X86CallingConv.td
Changes in directory llvm/lib/Target/X86: X86CallingConv.td updated: 1.5 -> 1.6 --- Log message: make subtarget references work. --- Diffs of the changes: (+7 -3) X86CallingConv.td | 10 +++--- 1 files changed, 7 insertions(+), 3 deletions(-) Index: llvm/lib/Target/X86/X86CallingConv.td diff -u llvm/lib/Target/X86/X86CallingConv.td:1.5 llvm/lib/Target/X86/X86CallingConv.td:1.6 --- llvm/lib/Target/X86/X86CallingConv.td:1.5 Tue Feb 27 00:59:52 2007 +++ llvm/lib/Target/X86/X86CallingConv.td Tue Feb 27 22:51:41 2007 @@ -12,6 +12,10 @@ // //===--===// +/// CCMatchIfSubtarget - Match if the current subtarget has a feature F. +class CCMatchIfSubtarget + : CCMatchIf().",F),A>; + //===--===// // Return Value Calling Conventions //===--===// @@ -42,8 +46,8 @@ def RetCC_X86_32_Fast : CallingConv<[ // The X86-32 fastcc returns FP values in XMM0 if the target has SSE2, // otherwise it is the the C calling conventions. - CCMatchType<[f32], CCMatchIf<"Subtarget->hasSSE2()", CCAssignToReg<[XMM0]>>>, - CCMatchType<[f64], CCMatchIf<"Subtarget->hasSSE2()", CCAssignToReg<[XMM0]>>>, + CCMatchType<[f32], CCMatchIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>, + CCMatchType<[f64], CCMatchIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>, CCDelegateTo ]>; @@ -73,7 +77,7 @@ // This is the return-value convention used for the entire X86 backend. def RetCC_X86 : CallingConv<[ - CCMatchIf<"Subtarget->is64Bit()", CCDelegateTo>, + CCMatchIfSubtarget<"is64Bit()", CCDelegateTo>, CCDelegateTo ]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/TableGen/CallingConvEmitter.cpp
Changes in directory llvm/utils/TableGen:
CallingConvEmitter.cpp updated: 1.2 -> 1.3
---
Log message:
implement CCPromoteToType
---
Diffs of the changes: (+13 -8)
CallingConvEmitter.cpp | 21 +
1 files changed, 13 insertions(+), 8 deletions(-)
Index: llvm/utils/TableGen/CallingConvEmitter.cpp
diff -u llvm/utils/TableGen/CallingConvEmitter.cpp:1.2
llvm/utils/TableGen/CallingConvEmitter.cpp:1.3
--- llvm/utils/TableGen/CallingConvEmitter.cpp:1.2 Tue Feb 27 16:08:27 2007
+++ llvm/utils/TableGen/CallingConvEmitter.cpp Tue Feb 27 22:43:48 2007
@@ -26,9 +26,11 @@
// other.
for (unsigned i = 0, e = CCs.size(); i != e; ++i) {
O << "static bool " << CCs[i]->getName()
- << "(unsigned ValNo, MVT::ValueType ValVT, MVT::ValueType LocVT,\n"
+ << "(unsigned ValNo, MVT::ValueType ValVT,\n"
<< std::string(CCs[i]->getName().size()+13, ' ')
- << "CCValAssign::LocInfo LocInfo, unsigned ArgFlags, CCState &State);\n";
+ << "MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo,\n"
+ << std::string(CCs[i]->getName().size()+13, ' ')
+ << "unsigned ArgFlags, CCState &State);\n";
}
// Emit each calling convention description in full.
@@ -42,11 +44,11 @@
Counter = 0;
O << "\n\nstatic bool " << CC->getName()
-<< "(unsigned ValNo, MVT::ValueType ValVT, MVT::ValueType LocVT,\n"
+<< "(unsigned ValNo, MVT::ValueType ValVT,\n"
+<< std::string(CC->getName().size()+13, ' ')
+<< "MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo,\n"
<< std::string(CC->getName().size()+13, ' ')
-<< "CCValAssign::LocInfo LocInfo, "
<< "unsigned ArgFlags, CCState &State) {\n";
-
// Emit all of the actions, in order.
for (unsigned i = 0, e = CCActions->getSize(); i != e; ++i) {
O << "\n";
@@ -68,7 +70,7 @@
ListInit *VTs = Action->getValueAsListInit("VTs");
for (unsigned i = 0, e = VTs->getSize(); i != e; ++i) {
Record *VT = VTs->getElementAsRecord(i);
-if (i != 0) O << " || \n" << IndentStr;
+if (i != 0) O << " ||\n" << IndentStr;
O << "LocVT == " << getEnumName(getValueType(VT));
}
@@ -115,11 +117,14 @@
O << IndentStr << "unsigned Offset" << ++Counter
<< " = State.AllocateStack(" << Size << ", " << Align << ");\n";
- O << IndentStr << "State.addLoc(CCValAssign::getMem(ValNo, ArgVT, Offset"
+ O << IndentStr << "State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset"
<< Counter << ", LocVT, LocInfo));\n";
O << IndentStr << "return false;\n";
} else if (Action->isSubClassOf("CCPromoteToType")) {
-
+ Record *DestTy = Action->getValueAsDef("DestTy");
+ O << IndentStr << "LocVT = " << getEnumName(getValueType(DestTy))
<<";\n";
+ O << IndentStr << "LocInfo = (ArgFlags & 1) ? CCValAssign::SExt"
+<< " : CCValAssign::ZExt;\n";
} else {
Action->dump();
throw "Unknown CCAction!";
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Re: [llvm-commits] GEP's too?
On Feb 27, 2007, at 6:52 PM, Reid Spencer wrote:
> Chris,
>
> How far do we want to go with conversion to APInt? Does this
> include GEP
> indices too? For example, consider this code from
> lib/Analysis/ConstantFolding.cpp
>
>>if (isFoldableGEP) {
>> uint64_t Offset = TD->getIndexedOffset(Ptr->getType(),
>> (Value**)Ops+1,
>> NumOps-1);
>> Constant *C = ConstantInt::get(TD->getIntPtrType(), Offset);
>> return ConstantExpr::getIntToPtr(C, ResultTy);
>> }
>
> The TargetData class could be altered to return an APInt value instead
> of a uint64_t. This would then be used to construct the ConstantInt.
> This would allow addressing beyond 64-bits but it seems like
> overkill to
> me.
I agree, totally overkill. GEP should continue to allow int32 or
int64 only,
Thanks,
-Chris
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[llvm-commits] GEP's too?
Chris,
How far do we want to go with conversion to APInt? Does this include GEP
indices too? For example, consider this code from
lib/Analysis/ConstantFolding.cpp
>if (isFoldableGEP) {
> uint64_t Offset = TD->getIndexedOffset(Ptr->getType(),
> (Value**)Ops+1, NumOps-1);
> Constant *C = ConstantInt::get(TD->getIntPtrType(), Offset);
> return ConstantExpr::getIntToPtr(C, ResultTy);
> }
The TargetData class could be altered to return an APInt value instead
of a uint64_t. This would then be used to construct the ConstantInt.
This would allow addressing beyond 64-bits but it seems like overkill to
me.
Your thoughts?
Reid.
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[llvm-commits] CVS: llvm/docs/BytecodeFormat.html
Changes in directory llvm/docs: BytecodeFormat.html updated: 1.66 -> 1.67 --- Log message: Describe how arbitrary precision integers are written to the bytecode. --- Diffs of the changes: (+13 -5) BytecodeFormat.html | 18 +- 1 files changed, 13 insertions(+), 5 deletions(-) Index: llvm/docs/BytecodeFormat.html diff -u llvm/docs/BytecodeFormat.html:1.66 llvm/docs/BytecodeFormat.html:1.67 --- llvm/docs/BytecodeFormat.html:1.66 Wed Feb 14 21:08:48 2007 +++ llvm/docs/BytecodeFormat.html Tue Feb 27 20:33:06 2007 @@ -1275,10 +1275,18 @@ Bool. This is written as an uint32_vbr of value 1U or 0U. - Signed Integers (sbyte,short,int,long). These are written as an - int64_vbr with the corresponding value. - Unsigned Integers (ubyte,ushort,uint,ulong). These are written as - an uint64_vbr with the corresponding value. + Signed Integers (sbyte,short,int,long) ≤ 64 bits. These are + written as an int64_vbr with the corresponding + value. + Unsigned Integers (ubyte,ushort,uint,ulong) ≤ 64 bits. These + are written as an uint64_vbr with the corresponding + value. + Integers > 64 bits. These are written as a length followed by a + series of 64-bit words. The length specifies the number of words that follow. + Any zero-valued high order words are elided. Words with the least significant + bits are written to the lowest file offsets (little endian). The length is + written as an uint32_vbr. Each word of the value + is written as an uint64_vbr. Floating Point. Both the float and double types are written literally in binary format. Arrays. Arrays are written simply as a list of @@ -2085,7 +2093,7 @@ mailto:[EMAIL PROTECTED]">Reid Spencer and mailto:[EMAIL PROTECTED]">Chris Lattner http://llvm.org";>The LLVM Compiler Infrastructure -Last modified: $Date: 2007/02/15 03:08:48 $ +Last modified: $Date: 2007/02/28 02:33:06 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.cpp
Changes in directory llvm/lib/Bytecode/Reader:
Reader.cpp updated: 1.241 -> 1.242
---
Log message:
Implement reading of arbitrary precision integers.
---
Diffs of the changes: (+9 -4)
Reader.cpp | 13 +
1 files changed, 9 insertions(+), 4 deletions(-)
Index: llvm/lib/Bytecode/Reader/Reader.cpp
diff -u llvm/lib/Bytecode/Reader/Reader.cpp:1.241
llvm/lib/Bytecode/Reader/Reader.cpp:1.242
--- llvm/lib/Bytecode/Reader/Reader.cpp:1.241 Wed Feb 14 21:39:18 2007
+++ llvm/lib/Bytecode/Reader/Reader.cpp Tue Feb 27 20:25:48 2007
@@ -1264,8 +1264,14 @@
error("Invalid constant integer read.");
Result = ConstantInt::get(IT, Val);
if (Handler) Handler->handleConstantValue(Result);
-} else
- assert(0 && "Integer types > 64 bits not supported");
+} else {
+ uint32_t numWords = read_vbr_uint();
+ uint64_t *data = new uint64_t[numWords];
+ for (uint32_t i = 0; i < numWords; ++i)
+data[i] = read_vbr_uint64();
+ Result = ConstantInt::get(IT, APInt(IT->getBitWidth(), numWords, data));
+ if (Handler) Handler->handleConstantValue(Result);
+}
break;
}
case Type::FloatTyID: {
@@ -1356,8 +1362,7 @@
// to a null value in a way that isn't predicted when a .bc file is initially
// produced.
assert((!isa(Result) || !cast(Result)->isNullValue()) ||
- !hasImplicitNull(TypeID) &&
- "Cannot read null values from bytecode!");
+ !hasImplicitNull(TypeID) && "Cannot read null values from bytecode!");
return Result;
}
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[llvm-commits] CVS: llvm/lib/Bytecode/Writer/Writer.cpp
Changes in directory llvm/lib/Bytecode/Writer:
Writer.cpp updated: 1.168 -> 1.169
---
Log message:
Implement writing of arbitrary precision integers.
---
Diffs of the changes: (+14 -4)
Writer.cpp | 18 ++
1 files changed, 14 insertions(+), 4 deletions(-)
Index: llvm/lib/Bytecode/Writer/Writer.cpp
diff -u llvm/lib/Bytecode/Writer/Writer.cpp:1.168
llvm/lib/Bytecode/Writer/Writer.cpp:1.169
--- llvm/lib/Bytecode/Writer/Writer.cpp:1.168 Wed Feb 14 20:26:09 2007
+++ llvm/lib/Bytecode/Writer/Writer.cpp Tue Feb 27 20:25:20 2007
@@ -307,13 +307,23 @@
switch (CPV->getType()->getTypeID()) {
case Type::IntegerTyID: { // Integer types...
+const ConstantInt *CI = cast(CPV);
unsigned NumBits = cast(CPV->getType())->getBitWidth();
if (NumBits <= 32)
- output_vbr(uint32_t(cast(CPV)->getZExtValue()));
+ output_vbr(uint32_t(CI->getZExtValue()));
else if (NumBits <= 64)
- output_vbr(uint64_t(cast(CPV)->getZExtValue()));
-else
- assert(0 && "Integer types > 64 bits not supported.");
+ output_vbr(uint64_t(CI->getZExtValue()));
+else {
+ // We have an arbitrary precision integer value to write whose
+ // bit width is > 64. However, in canonical unsigned integer
+ // format it is likely that the high bits are going to be zero.
+ // So, we only write the number of active words.
+ uint32_t activeWords = CI->getValue().getActiveWords();
+ const uint64_t *rawData = CI->getValue().getRawData();
+ output_vbr(activeWords);
+ for (uint32_t i = 0; i < activeWords; ++i)
+output_vbr(rawData[i]);
+}
break;
}
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[llvm-commits] CVS: llvm/lib/AsmParser/Lexer.l
Changes in directory llvm/lib/AsmParser:
Lexer.l updated: 1.98 -> 1.99
---
Log message:
Implement arbitrary integer constants through the use of APInt values.
Positive, negative, and hexadecimal integer constants will now return an
APInt for values having > 64 bits of precision.
---
Diffs of the changes: (+46 -14)
Lexer.l | 60 ++--
1 files changed, 46 insertions(+), 14 deletions(-)
Index: llvm/lib/AsmParser/Lexer.l
diff -u llvm/lib/AsmParser/Lexer.l:1.98 llvm/lib/AsmParser/Lexer.l:1.99
--- llvm/lib/AsmParser/Lexer.l:1.98 Thu Feb 1 20:16:22 2007
+++ llvm/lib/AsmParser/Lexer.l Tue Feb 27 20:24:27 2007
@@ -186,6 +186,7 @@
* it to deal with 64 bit numbers.
*/
HexIntConstant [us]0x[0-9A-Fa-f]+
+
%%
{Comment} { /* Ignore comments for now */ }
@@ -361,20 +362,51 @@
return ATSTRINGCONSTANT;
}
-
-
-{PInteger} { llvmAsmlval.UInt64Val = atoull(yytext); return EUINT64VAL; }
-{NInteger} {
- uint64_t Val = atoull(yytext+1);
- // +1: we have bigger negative range
- if (Val > (uint64_t)INT64_MAX+1)
-GenerateError("Constant too large for signed 64 bits!");
- llvmAsmlval.SInt64Val = -Val;
- return ESINT64VAL;
-}
-{HexIntConstant} {
- llvmAsmlval.UInt64Val = HexIntToVal(yytext+3);
- return yytext[0] == 's' ? ESINT64VAL : EUINT64VAL;
+{PInteger} { int len = strlen(yytext);
+ uint32_t numBits = ((len * 64) / 19) + 1;
+ APInt Tmp(numBits, yytext, len, 10);
+ uint32_t activeBits = Tmp.getActiveBits();
+ if (activeBits > 0 && activeBits < numBits)
+Tmp.trunc(activeBits);
+ if (Tmp.getBitWidth() > 64) {
+llvmAsmlval.APIntVal = new APInt(Tmp);
+return EUAPINTVAL;
+ } else {
+llvmAsmlval.UInt64Val = Tmp.getZExtValue();
+return EUINT64VAL;
+ }
+}
+{NInteger} { int len = strlen(yytext);
+ uint32_t numBits = (((len-1) * 64) / 19) + 1;
+ APInt Tmp(numBits, yytext, len, 10);
+ uint32_t minBits = Tmp.getMinSignedBits();
+ if (minBits > 0 && minBits < numBits)
+Tmp.trunc(minBits);
+ if (Tmp.getBitWidth() > 64) {
+llvmAsmlval.APIntVal = new APInt(Tmp);
+return ESAPINTVAL;
+ } else {
+llvmAsmlval.SInt64Val = Tmp.getSExtValue();
+return ESINT64VAL;
+ }
+}
+
+{HexIntConstant} { int len = strlen(yytext+3) - 3;
+ uint32_t bits = len * 4;
+ APInt Tmp(bits, yytext+3, len, 16);
+ uint32_t activeBits = Tmp.getActiveBits();
+ if (activeBits > 0 && activeBits < bits)
+ Tmp.trunc(activeBits);
+ if (Tmp.getBitWidth() > 64) {
+ llvmAsmlval.APIntVal = new APInt(Tmp);
+ return yytext[0] == 's' ? ESAPINTVAL : EUAPINTVAL;
+ } else if (yytext[0] == 's') {
+ llvmAsmlval.SInt64Val = Tmp.getSExtValue();
+ return ESINT64VAL;
+ } else {
+ llvmAsmlval.UInt64Val = Tmp.getZExtValue();
+ return EUINT64VAL;
+ }
}
{LocalVarID} {
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[llvm-commits] CVS: llvm/lib/AsmParser/llvmAsmParser.y
Changes in directory llvm/lib/AsmParser:
llvmAsmParser.y updated: 1.325 -> 1.326
---
Log message:
Implement support for aribrary precision integers by creating two new
tokens: ESAPINTVAL and EUAPINTVAL and adding an APInt* as a semantic value.
This allows us to extend the definition of an integer constant to allow
arbitrary precision integer constant values.
---
Diffs of the changes: (+41 -2)
llvmAsmParser.y | 43 +--
1 files changed, 41 insertions(+), 2 deletions(-)
Index: llvm/lib/AsmParser/llvmAsmParser.y
diff -u llvm/lib/AsmParser/llvmAsmParser.y:1.325
llvm/lib/AsmParser/llvmAsmParser.y:1.326
--- llvm/lib/AsmParser/llvmAsmParser.y:1.325Wed Feb 14 21:39:17 2007
+++ llvm/lib/AsmParser/llvmAsmParser.y Tue Feb 27 20:23:44 2007
@@ -925,6 +925,7 @@
llvm::GlobalValue::LinkageTypes Linkage;
llvm::GlobalValue::VisibilityTypes Visibility;
llvm::FunctionType::ParameterAttributes ParamAttrs;
+ llvm::APInt *APIntVal;
int64_t SInt64Val;
uint64_t UInt64Val;
int SIntVal;
@@ -978,6 +979,12 @@
// EUINT64VAL - A positive number within uns. long long range
%token EUINT64VAL
+// ESAPINTVAL - A negative number with arbitrary precision
+%token ESAPINTVAL
+
+// EUAPINTVAL - A positive number with arbitrary precision
+%token EUAPINTVAL
+
%token LOCALVAL_ID GLOBALVAL_ID // %123 @123
%token FPVAL // Float or Double constant
@@ -1704,13 +1711,45 @@
| IntType ESINT64VAL { // integral constants
if (!ConstantInt::isValueValidForType($1, $2))
GEN_ERROR("Constant value doesn't fit in type");
-$$ = ConstantInt::get($1, $2);
+APInt Val(64, $2);
+uint32_t BitWidth = cast($1)->getBitWidth();
+if (BitWidth > 64)
+ Val.sext(BitWidth);
+else if (BitWidth < 64)
+ Val.trunc(BitWidth);
+$$ = ConstantInt::get($1, Val);
+CHECK_FOR_ERROR
+ }
+ | IntType ESAPINTVAL { // arbitrary precision integer constants
+uint32_t BitWidth = cast($1)->getBitWidth();
+if ($2->getBitWidth() > BitWidth) {
+ GEN_ERROR("Constant value does not fit in type");
+} else if ($2->getBitWidth() < BitWidth)
+ $2->sext(BitWidth);
+else if ($2->getBitWidth() > BitWidth)
+ $2->trunc(BitWidth);
+$$ = ConstantInt::get($1, *$2);
+delete $2;
CHECK_FOR_ERROR
}
| IntType EUINT64VAL { // integral constants
if (!ConstantInt::isValueValidForType($1, $2))
GEN_ERROR("Constant value doesn't fit in type");
-$$ = ConstantInt::get($1, $2);
+uint32_t BitWidth = cast($1)->getBitWidth();
+APInt Val(BitWidth, $2);
+$$ = ConstantInt::get($1, Val);
+CHECK_FOR_ERROR
+ }
+ | IntType EUAPINTVAL { // arbitrary precision integer constants
+uint32_t BitWidth = cast($1)->getBitWidth();
+if ($2->getBitWidth() > BitWidth) {
+ GEN_ERROR("Constant value does not fit in type");
+} else if ($2->getBitWidth() < BitWidth)
+ $2->zext(BitWidth);
+else if ($2->getBitWidth() > BitWidth)
+ $2->trunc(BitWidth);
+$$ = ConstantInt::get($1, *$2);
+delete $2;
CHECK_FOR_ERROR
}
| INTTYPE TRUETOK { // Boolean constants
___
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[llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
Changes in directory llvm/include/llvm/ADT:
APInt.h updated: 1.28 -> 1.29
---
Log message:
getActiveWords should return the number of words, not the index of the
highest active words. Increment its result by one.
---
Diffs of the changes: (+1 -1)
APInt.h |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/include/llvm/ADT/APInt.h
diff -u llvm/include/llvm/ADT/APInt.h:1.28 llvm/include/llvm/ADT/APInt.h:1.29
--- llvm/include/llvm/ADT/APInt.h:1.28 Tue Feb 27 17:47:33 2007
+++ llvm/include/llvm/ADT/APInt.h Tue Feb 27 20:20:49 2007
@@ -450,7 +450,7 @@
/// APInt. This is used in conjunction with getActiveData to extract the raw
/// value of the APInt.
inline uint32_t getActiveWords() const {
-return whichWord(getActiveBits()-1);
+return whichWord(getActiveBits()-1) + 1;
}
/// This function returns a pointer to the internal storage of the APInt.
___
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[llvm-commits] CVS: llvm/lib/Support/APInt.cpp
Changes in directory llvm/lib/Support: APInt.cpp updated: 1.57 -> 1.58 --- Log message: Fix a bug in RoundDoubleToAPInt where it would force the size to 64 bits instead of honoring the client's requested bit width. --- Diffs of the changes: (+1 -1) APInt.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Support/APInt.cpp diff -u llvm/lib/Support/APInt.cpp:1.57 llvm/lib/Support/APInt.cpp:1.58 --- llvm/lib/Support/APInt.cpp:1.57 Tue Feb 27 17:49:07 2007 +++ llvm/lib/Support/APInt.cpp Tue Feb 27 19:30:08 2007 @@ -808,7 +808,7 @@ // If the exponent is negative, the value is < 0 so just return 0. if (exp < 0) -return APInt(64u, 0u); +return APInt(width, 0u); // Extract the mantissa by clearing the top 12 bits (sign + exponent). uint64_t mantissa = (T.I & (~0ULL >> 12)) | 1ULL << 52; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp ARMRegisterInfo.h ARMRegisterInfo.td
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.74 -> 1.75
ARMRegisterInfo.h updated: 1.14 -> 1.15
ARMRegisterInfo.td updated: 1.12 -> 1.13
---
Log message:
Make requiresRegisterScavenging determination on a per MachineFunction basis.
---
Diffs of the changes: (+13 -11)
ARMRegisterInfo.cpp |6 --
ARMRegisterInfo.h |2 +-
ARMRegisterInfo.td | 16
3 files changed, 13 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.74
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.75
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.74Tue Feb 27 18:21:58 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Tue Feb 27 18:59:19 2007
@@ -326,8 +326,10 @@
return Reserved;
}
-bool ARMRegisterInfo::requiresRegisterScavenging() const {
- return EnableScavenging;
+bool
+ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
+ const ARMFunctionInfo *AFI = MF.getInfo();
+ return EnableScavenging && !AFI->isThumbFunction();
}
/// hasFP - Return true if the specified function should have a dedicated frame
Index: llvm/lib/Target/ARM/ARMRegisterInfo.h
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.14
llvm/lib/Target/ARM/ARMRegisterInfo.h:1.15
--- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.14 Tue Feb 27 18:21:17 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.h Tue Feb 27 18:59:19 2007
@@ -74,7 +74,7 @@
BitVector getReservedRegs(const MachineFunction &MF) const;
- bool requiresRegisterScavenging() const;
+ bool requiresRegisterScavenging(const MachineFunction &MF) const;
bool hasFP(const MachineFunction &MF) const;
Index: llvm/lib/Target/ARM/ARMRegisterInfo.td
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.td:1.12
llvm/lib/Target/ARM/ARMRegisterInfo.td:1.13
--- llvm/lib/Target/ARM/ARMRegisterInfo.td:1.12 Tue Feb 27 18:22:44 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.td Tue Feb 27 18:59:19 2007
@@ -163,14 +163,14 @@
return THUMB_GPR_AO;
if (Subtarget.useThumbBacktraces()) {
if (Subtarget.isR9Reserved())
- return RI->requiresRegisterScavenging() ? ARM_GPR_AO_8 :
ARM_GPR_AO_4;
+ return RI->requiresRegisterScavenging(MF) ?
ARM_GPR_AO_8:ARM_GPR_AO_4;
else
- return RI->requiresRegisterScavenging() ? ARM_GPR_AO_7 :
ARM_GPR_AO_3;
+ return RI->requiresRegisterScavenging(MF) ?
ARM_GPR_AO_7:ARM_GPR_AO_3;
} else {
if (Subtarget.isR9Reserved())
- return RI->requiresRegisterScavenging() ? ARM_GPR_AO_6 :
ARM_GPR_AO_2;
+ return RI->requiresRegisterScavenging(MF) ?
ARM_GPR_AO_6:ARM_GPR_AO_2;
else
- return RI->requiresRegisterScavenging() ? ARM_GPR_AO_5 :
ARM_GPR_AO_1;
+ return RI->requiresRegisterScavenging(MF) ?
ARM_GPR_AO_5:ARM_GPR_AO_1;
}
}
@@ -184,24 +184,24 @@
I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
else if (Subtarget.useThumbBacktraces()) {
if (Subtarget.isR9Reserved()) {
- if (RI->requiresRegisterScavenging())
+ if (RI->requiresRegisterScavenging(MF))
I = ARM_GPR_AO_8 + (sizeof(ARM_GPR_AO_8)/sizeof(unsigned));
else
I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
} else {
- if (RI->requiresRegisterScavenging())
+ if (RI->requiresRegisterScavenging(MF))
I = ARM_GPR_AO_7 + (sizeof(ARM_GPR_AO_7)/sizeof(unsigned));
else
I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned));
}
} else {
if (Subtarget.isR9Reserved()) {
- if (RI->requiresRegisterScavenging())
+ if (RI->requiresRegisterScavenging(MF))
I = ARM_GPR_AO_6 + (sizeof(ARM_GPR_AO_6)/sizeof(unsigned));
else
I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
} else {
- if (RI->requiresRegisterScavenging())
+ if (RI->requiresRegisterScavenging(MF))
I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned));
else
I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));
___
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[llvm-commits] CVS: llvm/lib/CodeGen/PrologEpilogInserter.cpp
Changes in directory llvm/lib/CodeGen:
PrologEpilogInserter.cpp updated: 1.72 -> 1.73
---
Log message:
Make requiresRegisterScavenging determination on a per MachineFunction basis.
---
Diffs of the changes: (+1 -1)
PrologEpilogInserter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp
diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.72
llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.73
--- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.72 Tue Feb 27 18:17:36 2007
+++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Tue Feb 27 18:58:37 2007
@@ -442,7 +442,7 @@
const TargetMachine &TM = Fn.getTarget();
assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!");
const MRegisterInfo &MRI = *TM.getRegisterInfo();
- RegScavenger *RS = MRI.requiresRegisterScavenging() ? new
RegScavenger():NULL;
+ RegScavenger *RS=MRI.requiresRegisterScavenging(Fn) ? new
RegScavenger():NULL;
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB)
{
if (RS) RS->reset(BB);
___
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.99 -> 1.100
---
Log message:
Make requiresRegisterScavenging determination on a per MachineFunction basis.
---
Diffs of the changes: (+1 -1)
MRegisterInfo.h |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.99
llvm/include/llvm/Target/MRegisterInfo.h:1.100
--- llvm/include/llvm/Target/MRegisterInfo.h:1.99 Tue Feb 27 18:16:54 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hTue Feb 27 18:57:39 2007
@@ -394,7 +394,7 @@
/// requiresRegisterScavenging - returns true if the target requires (and
/// can make use of) the register scavenger.
- virtual bool requiresRegisterScavenging() const {
+ virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
return false;
}
___
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[llvm-commits] CVS: llvm/test/CodeGen/ARM/shifter_operand.ll
Changes in directory llvm/test/CodeGen/ARM:
shifter_operand.ll updated: 1.1 -> 1.2
---
Log message:
Fix test case.
---
Diffs of the changes: (+2 -2)
shifter_operand.ll |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/test/CodeGen/ARM/shifter_operand.ll
diff -u llvm/test/CodeGen/ARM/shifter_operand.ll:1.1
llvm/test/CodeGen/ARM/shifter_operand.ll:1.2
--- llvm/test/CodeGen/ARM/shifter_operand.ll:1.1Fri Jan 19 03:20:23 2007
+++ llvm/test/CodeGen/ARM/shifter_operand.llTue Feb 27 18:36:33 2007
@@ -1,5 +1,5 @@
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep 'add r0, r0, r1,
lsl r2' &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep 'bic r0, r0, r1,
asr r2'
+; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep add | grep lsl &&
+; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep bic | grep asr
int %test1(int %X, int %Y, ubyte %sh) {
%A = shl int %Y, ubyte %sh
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.td
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.td updated: 1.11 -> 1.12
---
Log message:
Temporary: make R12 available in ARM mode if RegScavenger is being used.
---
Diffs of the changes: (+53 -12)
ARMRegisterInfo.td | 65 +++--
1 files changed, 53 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.td
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.td:1.11
llvm/lib/Target/ARM/ARMRegisterInfo.td:1.12
--- llvm/lib/Target/ARM/ARMRegisterInfo.td:1.11 Tue Feb 27 17:03:55 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.td Tue Feb 27 18:22:44 2007
@@ -123,6 +123,32 @@
ARM::R4, ARM::R5, ARM::R6, ARM::R8,
ARM::R10,ARM::R11,
ARM::LR, ARM::R7 };
+
+// FP is R11, R9 is available, R12 is available.
+static const unsigned ARM_GPR_AO_5[] = {
+ ARM::R3, ARM::R2, ARM::R1, ARM::R0,
+ ARM::R4, ARM::R5, ARM::R6, ARM::R7,
+ ARM::R8, ARM::R9, ARM::R10,ARM::R12,
+ ARM::LR, ARM::R11 };
+// FP is R11, R9 is not available, R12 is available.
+static const unsigned ARM_GPR_AO_6[] = {
+ ARM::R3, ARM::R2, ARM::R1, ARM::R0,
+ ARM::R4, ARM::R5, ARM::R6, ARM::R7,
+ ARM::R8, ARM::R10,ARM::R12,
+ ARM::LR, ARM::R11 };
+// FP is R7, R9 is available, R12 is available.
+static const unsigned ARM_GPR_AO_7[] = {
+ ARM::R3, ARM::R2, ARM::R1, ARM::R0,
+ ARM::R4, ARM::R5, ARM::R6, ARM::R8,
+ ARM::R9, ARM::R10,ARM::R11,ARM::R12,
+ ARM::LR, ARM::R7 };
+// FP is R7, R9 is not available, R12 is available.
+static const unsigned ARM_GPR_AO_8[] = {
+ ARM::R3, ARM::R2, ARM::R1, ARM::R0,
+ ARM::R4, ARM::R5, ARM::R6, ARM::R8,
+ ARM::R10,ARM::R11,ARM::R12,
+ ARM::LR, ARM::R7 };
+
// FP is R7, only low registers available.
static const unsigned THUMB_GPR_AO[] = {
ARM::R2, ARM::R1, ARM::R0,
@@ -131,19 +157,20 @@
GPRClass::iterator
GPRClass::allocation_order_begin(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
+ const MRegisterInfo *RI = TM.getRegisterInfo();
const ARMSubtarget &Subtarget = TM.getSubtarget();
if (Subtarget.isThumb())
return THUMB_GPR_AO;
if (Subtarget.useThumbBacktraces()) {
if (Subtarget.isR9Reserved())
- return ARM_GPR_AO_4;
+ return RI->requiresRegisterScavenging() ? ARM_GPR_AO_8 :
ARM_GPR_AO_4;
else
- return ARM_GPR_AO_3;
+ return RI->requiresRegisterScavenging() ? ARM_GPR_AO_7 :
ARM_GPR_AO_3;
} else {
if (Subtarget.isR9Reserved())
- return ARM_GPR_AO_2;
+ return RI->requiresRegisterScavenging() ? ARM_GPR_AO_6 :
ARM_GPR_AO_2;
else
- return ARM_GPR_AO_1;
+ return RI->requiresRegisterScavenging() ? ARM_GPR_AO_5 :
ARM_GPR_AO_1;
}
}
@@ -156,15 +183,29 @@
if (Subtarget.isThumb())
I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
else if (Subtarget.useThumbBacktraces()) {
-if (Subtarget.isR9Reserved())
- I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
-else
- I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned));
+if (Subtarget.isR9Reserved()) {
+ if (RI->requiresRegisterScavenging())
+I = ARM_GPR_AO_8 + (sizeof(ARM_GPR_AO_8)/sizeof(unsigned));
+ else
+I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
+} else {
+ if (RI->requiresRegisterScavenging())
+I = ARM_GPR_AO_7 + (sizeof(ARM_GPR_AO_7)/sizeof(unsigned));
+ else
+I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned));
+}
} else {
-if (Subtarget.isR9Reserved())
- I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
-else
- I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));
+if (Subtarget.isR9Reserved()) {
+ if (RI->requiresRegisterScavenging())
+I = ARM_GPR_AO_6 + (sizeof(ARM_GPR_AO_6)/sizeof(unsigned));
+ else
+I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
+} else {
+ if (RI->requiresRegisterScavenging())
+I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned));
+ else
+I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));
+}
}
// Mac OS X requires FP not to be clobbered for backtracing purpose.
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.73 -> 1.74
---
Log message:
Start making use of RegScavenger.
---
Diffs of the changes: (+12 -8)
ARMRegisterInfo.cpp | 20
1 files changed, 12 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.73
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.74
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.73Tue Feb 27 15:12:35 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Tue Feb 27 18:21:58 2007
@@ -85,17 +85,13 @@
: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
TII(tii), STI(sti),
FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) {
- RS = new RegScavenger();
+ RS = (EnableScavenging) ? new RegScavenger() : NULL;
}
ARMRegisterInfo::~ARMRegisterInfo() {
delete RS;
}
-RegScavenger *ARMRegisterInfo::getRegScavenger() const {
- return EnableScavenging ? RS : NULL;
-}
-
bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector &CSI) const
{
@@ -330,6 +326,10 @@
return Reserved;
}
+bool ARMRegisterInfo::requiresRegisterScavenging() const {
+ return EnableScavenging;
+}
+
/// hasFP - Return true if the specified function should have a dedicated frame
/// pointer register. This is true if the function has variable sized allocas
/// or if frame pointer elimination is disabled.
@@ -616,7 +616,8 @@
.addReg(DestReg, false, false, true);
}
-void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II)
const{
+void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+ RegScavenger *RS) const{
unsigned i = 0;
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
@@ -898,9 +899,12 @@
// If the offset we have is too large to fit into the instruction, we need
// to form it with a series of ADDri's. Do this by taking 8-bit chunks
// out of 'Offset'.
-emitARMRegPlusImmediate(MBB, II, ARM::R12, FrameReg,
+unsigned ScratchReg = RS
+ ? RS->FindUnusedReg(&ARM::GPRRegClass, true) : (unsigned)ARM::R12;
+assert(ScratchReg != 0 && "Unable to find a free call-clobbered
register!");
+emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
isSub ? -Offset : Offset, TII);
-MI.getOperand(i).ChangeToRegister(ARM::R12, false, false, true);
+MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
}
}
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.h
Changes in directory llvm/lib/Target/ARM: ARMRegisterInfo.h updated: 1.13 -> 1.14 --- Log message: PEI now passes a RegScavenger ptr to eliminateFrameIndex. --- Diffs of the changes: (+4 -3) ARMRegisterInfo.h |7 --- 1 files changed, 4 insertions(+), 3 deletions(-) Index: llvm/lib/Target/ARM/ARMRegisterInfo.h diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.13 llvm/lib/Target/ARM/ARMRegisterInfo.h:1.14 --- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.13 Tue Feb 27 15:12:35 2007 +++ llvm/lib/Target/ARM/ARMRegisterInfo.h Tue Feb 27 18:21:17 2007 @@ -38,8 +38,6 @@ ~ARMRegisterInfo(); - RegScavenger *getRegScavenger() const; - /// getRegisterNumbering - Given the enum value for some register, e.g. /// ARM::LR, return the number that it corresponds to (e.g. 14). static unsigned getRegisterNumbering(unsigned RegEnum); @@ -76,13 +74,16 @@ BitVector getReservedRegs(const MachineFunction &MF) const; + bool requiresRegisterScavenging() const; + bool hasFP(const MachineFunction &MF) const; void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; - void eliminateFrameIndex(MachineBasicBlock::iterator II) const; + void eliminateFrameIndex(MachineBasicBlock::iterator II, + RegScavenger *RS = NULL) const; void processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86RegisterInfo.h
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.205 -> 1.206
X86RegisterInfo.h updated: 1.49 -> 1.50
---
Log message:
PEI now passes a RegScavenger ptr to eliminateFrameIndex.
---
Diffs of the changes: (+4 -2)
X86RegisterInfo.cpp |3 ++-
X86RegisterInfo.h |3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.205
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.206
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.205 Thu Feb 22 19:10:04 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Feb 27 18:20:26 2007
@@ -968,7 +968,8 @@
MBB.erase(I);
}
-void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II)
const{
+void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+ RegScavenger *RS) const{
unsigned i = 0;
MachineInstr &MI = *II;
MachineFunction &MF = *MI.getParent()->getParent();
Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.49
llvm/lib/Target/X86/X86RegisterInfo.h:1.50
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.49 Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.h Tue Feb 27 18:20:26 2007
@@ -90,7 +90,8 @@
MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const;
- void eliminateFrameIndex(MachineBasicBlock::iterator MI) const;
+ void eliminateFrameIndex(MachineBasicBlock::iterator MI,
+ RegScavenger *RS = NULL) const;
void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
___
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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp SparcRegisterInfo.h
Changes in directory llvm/lib/Target/Sparc:
SparcRegisterInfo.cpp updated: 1.56 -> 1.57
SparcRegisterInfo.h updated: 1.21 -> 1.22
---
Log message:
PEI now passes a RegScavenger ptr to eliminateFrameIndex.
---
Diffs of the changes: (+4 -3)
SparcRegisterInfo.cpp |4 ++--
SparcRegisterInfo.h |3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.56
llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.57
--- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.56Thu Feb 22 19:10:04 2007
+++ llvm/lib/Target/Sparc/SparcRegisterInfo.cpp Tue Feb 27 18:20:02 2007
@@ -155,8 +155,8 @@
MBB.erase(I);
}
-void
-SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
+void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+RegScavenger *RS) const {
unsigned i = 0;
MachineInstr &MI = *II;
while (!MI.getOperand(i).isFrameIndex()) {
Index: llvm/lib/Target/Sparc/SparcRegisterInfo.h
diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.21
llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.22
--- llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.21 Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/Sparc/SparcRegisterInfo.h Tue Feb 27 18:20:02 2007
@@ -60,7 +60,8 @@
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;
- void eliminateFrameIndex(MachineBasicBlock::iterator II) const;
+ void eliminateFrameIndex(MachineBasicBlock::iterator II,
+ RegScavenger *RS = NULL) const;
void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.114 -> 1.115
PPCRegisterInfo.h updated: 1.31 -> 1.32
---
Log message:
PEI now passes a RegScavenger ptr to eliminateFrameIndex.
---
Diffs of the changes: (+4 -3)
PPCRegisterInfo.cpp |4 ++--
PPCRegisterInfo.h |3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.114
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.115
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.114 Tue Feb 27 05:55:45 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Feb 27 18:19:26 2007
@@ -623,8 +623,8 @@
MBB.erase(II);
}
-void
-PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
+void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+ RegScavenger *RS) const {
// Get the instruction.
MachineInstr &MI = *II;
// Get the instruction's basic block.
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.31
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.32
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.31 Tue Feb 27 05:55:45 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Tue Feb 27 18:19:26 2007
@@ -76,7 +76,8 @@
bool usesLR(MachineFunction &MF) const;
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
- void eliminateFrameIndex(MachineBasicBlock::iterator II) const;
+ void eliminateFrameIndex(MachineBasicBlock::iterator II,
+ RegScavenger *RS = NULL) const;
/// determineFrameLayout - Determine the size of the frame and maximum call
/// frame size.
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.cpp IA64RegisterInfo.h
Changes in directory llvm/lib/Target/IA64:
IA64RegisterInfo.cpp updated: 1.33 -> 1.34
IA64RegisterInfo.h updated: 1.15 -> 1.16
---
Log message:
PEI now passes a RegScavenger ptr to eliminateFrameIndex.
---
Diffs of the changes: (+4 -2)
IA64RegisterInfo.cpp |3 ++-
IA64RegisterInfo.h |3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.33
llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.34
--- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.33 Thu Feb 22 19:10:03 2007
+++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp Tue Feb 27 18:18:52 2007
@@ -167,7 +167,8 @@
MBB.erase(I);
}
-void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator
II)const{
+void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+ RegScavenger *RS)const{
unsigned i = 0;
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
Index: llvm/lib/Target/IA64/IA64RegisterInfo.h
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.h:1.15
llvm/lib/Target/IA64/IA64RegisterInfo.h:1.16
--- llvm/lib/Target/IA64/IA64RegisterInfo.h:1.15Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/IA64/IA64RegisterInfo.h Tue Feb 27 18:18:52 2007
@@ -56,7 +56,8 @@
MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const;
- void eliminateFrameIndex(MachineBasicBlock::iterator MI) const;
+ void eliminateFrameIndex(MachineBasicBlock::iterator MI,
+ RegScavenger *RS = NULL) const;
void emitPrologue(MachineFunction &MF) const;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp AlphaRegisterInfo.h
Changes in directory llvm/lib/Target/Alpha:
AlphaRegisterInfo.cpp updated: 1.62 -> 1.63
AlphaRegisterInfo.h updated: 1.21 -> 1.22
---
Log message:
PEI now passes a RegScavenger ptr to eliminateFrameIndex.
---
Diffs of the changes: (+4 -3)
AlphaRegisterInfo.cpp |4 ++--
AlphaRegisterInfo.h |3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.62
llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.63
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.62Thu Feb 22 19:10:03 2007
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Tue Feb 27 18:18:31 2007
@@ -245,8 +245,8 @@
//variable locals
//<- SP
-void
-AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
+void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+RegScavenger *RS) const {
unsigned i = 0;
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.h
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.21
llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.22
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.21 Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.h Tue Feb 27 18:18:31 2007
@@ -57,7 +57,8 @@
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;
- void eliminateFrameIndex(MachineBasicBlock::iterator II) const;
+ void eliminateFrameIndex(MachineBasicBlock::iterator II,
+ RegScavenger *RS = NULL) const;
//void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
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[llvm-commits] CVS: llvm/lib/CodeGen/PrologEpilogInserter.cpp
Changes in directory llvm/lib/CodeGen:
PrologEpilogInserter.cpp updated: 1.71 -> 1.72
---
Log message:
MRegisterInfo disowns RegScavenger. It's immutable.
---
Diffs of the changes: (+2 -2)
PrologEpilogInserter.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp
diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.71
llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.72
--- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.71 Tue Feb 27 15:10:33 2007
+++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Tue Feb 27 18:17:36 2007
@@ -442,7 +442,7 @@
const TargetMachine &TM = Fn.getTarget();
assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!");
const MRegisterInfo &MRI = *TM.getRegisterInfo();
- RegScavenger *RS = MRI.getRegScavenger();
+ RegScavenger *RS = MRI.requiresRegisterScavenging() ? new
RegScavenger():NULL;
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB)
{
if (RS) RS->reset(BB);
@@ -451,7 +451,7 @@
if (I->getOperand(i).isFrameIndex()) {
// If this instruction has a FrameIndex operand, we need to use that
// target machine register info object to eliminate it.
- MRI.eliminateFrameIndex(I);
+ MRI.eliminateFrameIndex(I, RS);
break;
}
// Update register states.
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.98 -> 1.99
---
Log message:
MRegisterInfo disowns RegScavenger. It's immutable.
---
Diffs of the changes: (+8 -7)
MRegisterInfo.h | 15 ---
1 files changed, 8 insertions(+), 7 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.98
llvm/include/llvm/Target/MRegisterInfo.h:1.99
--- llvm/include/llvm/Target/MRegisterInfo.h:1.98 Tue Feb 27 15:08:07 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hTue Feb 27 18:16:54 2007
@@ -214,12 +214,6 @@
virtual ~MRegisterInfo();
public:
- /// getRegScavenger - Returns pointer to an instance of register scavenger it
- /// the specific target is making use of one.
- virtual RegScavenger *getRegScavenger() const {
-return NULL;
- }
-
enum {// Define some target independent constants
/// NoRegister - This physical register is not a real target register. It
/// is useful as a sentinal.
@@ -398,6 +392,12 @@
return false;
}
+ /// requiresRegisterScavenging - returns true if the target requires (and
+ /// can make use of) the register scavenger.
+ virtual bool requiresRegisterScavenging() const {
+return false;
+ }
+
/// hasFP - Return true if the specified function should have a dedicated
frame
/// pointer register. For most targets this is true only if the function has
/// variable sized allocas or if frame pointer elimination is disabled.
@@ -452,7 +452,8 @@
/// finished product. The return value is the number of instructions
/// added to (negative if removed from) the basic block.
///
- virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
+ virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
+ RegScavenger *RS = NULL) const = 0;
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function. The return value is the number of instructions
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[llvm-commits] CVS: llvm/lib/Support/APInt.cpp
Changes in directory llvm/lib/Support:
APInt.cpp updated: 1.56 -> 1.57
---
Log message:
Join two lines that can be joined.
---
Diffs of the changes: (+1 -2)
APInt.cpp |3 +--
1 files changed, 1 insertion(+), 2 deletions(-)
Index: llvm/lib/Support/APInt.cpp
diff -u llvm/lib/Support/APInt.cpp:1.56 llvm/lib/Support/APInt.cpp:1.57
--- llvm/lib/Support/APInt.cpp:1.56 Tue Feb 27 15:59:26 2007
+++ llvm/lib/Support/APInt.cpp Tue Feb 27 17:49:07 2007
@@ -42,8 +42,7 @@
return result;
}
-APInt::APInt(uint32_t numBits, uint64_t val)
- : BitWidth(numBits), VAL(0) {
+APInt::APInt(uint32_t numBits, uint64_t val) : BitWidth(numBits), VAL(0) {
assert(BitWidth >= IntegerType::MIN_INT_BITS && "bitwidth too small");
assert(BitWidth <= IntegerType::MAX_INT_BITS && "bitwidth too large");
if (isSingleWord())
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[llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
Changes in directory llvm/include/llvm/ADT:
APInt.h updated: 1.27 -> 1.28
---
Log message:
Add some syntactic sugar.
---
Diffs of the changes: (+31 -0)
APInt.h | 31 +++
1 files changed, 31 insertions(+)
Index: llvm/include/llvm/ADT/APInt.h
diff -u llvm/include/llvm/ADT/APInt.h:1.27 llvm/include/llvm/ADT/APInt.h:1.28
--- llvm/include/llvm/ADT/APInt.h:1.27 Tue Feb 27 15:59:26 2007
+++ llvm/include/llvm/ADT/APInt.h Tue Feb 27 17:47:33 2007
@@ -446,6 +446,29 @@
return BitWidth - countLeadingZeros();
}
+ /// This function returns the number of active words in the value of this
+ /// APInt. This is used in conjunction with getActiveData to extract the raw
+ /// value of the APInt.
+ inline uint32_t getActiveWords() const {
+return whichWord(getActiveBits()-1);
+ }
+
+ /// This function returns a pointer to the internal storage of the APInt.
+ /// This is useful for writing out the APInt in binary form without any
+ /// conversions.
+ inline const uint64_t* getRawData() const {
+if (isSingleWord())
+ return &VAL;
+return &pVal[0];
+ }
+
+ /// Computes the minimum bit width for this APInt while considering it to be
+ /// a signed (and probably negative) value. If the value is not negative,
+ /// this function returns the same value as getActiveBits(). Otherwise, it
+ /// returns the smallest bit width that will retain the negative value. For
+ /// example, -1 can be written as 0b1 or 0xFF. 0b1 is shorter and so
+ /// for -1, this function will always return 1.
+ /// @brief Get the minimum bit size for this signed APInt
inline uint32_t getMinSignedBits() const {
if (isNegative())
return BitWidth - countLeadingOnes() + 1;
@@ -658,6 +681,14 @@
}
};
+inline bool operator==(uint64_t V1, const APInt& V2) {
+ return V2 == V1;
+}
+
+inline bool operator!=(uint64_t V1, const APInt& V2) {
+ return V2 != V1;
+}
+
namespace APIntOps {
/// @brief Check if the specified APInt has a N-bits integer value.
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[llvm-commits] LowerSwitch improvement patch for review
Hello, Everyone.
Please review attached patch for LowerSwitch. Actually, it just "merges"
adjacent cases with same destination in one big "case cluster". During
emiting comparison tree such clusters result to range comparisons. This
is pretty cheap but useful transformation.
The same technique is planned for SDISel variant of switch lowering.
--
With best regards, Anton Korobeynikov.
Faculty of Mathematics & Mechanics, Saint Petersburg State University.
diff -r 87cd8438fce8 lib/Transforms/Utils/LowerSwitch.cpp
--- a/lib/Transforms/Utils/LowerSwitch.cpp Mon Feb 26 18:56:07 2007 +
+++ b/lib/Transforms/Utils/LowerSwitch.cpp Wed Feb 28 02:34:32 2007 +0300
@@ -22,6 +22,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
#include
+#include
using namespace llvm;
namespace {
@@ -40,9 +41,19 @@ namespace {
AU.addPreservedID(LowerInvokePassID);
AU.addPreservedID(LowerAllocationsID);
}
-
-typedef std::pair Case;
-typedef std::vector::iterator CaseItr;
+
+struct Case {
+ Constant* Low;
+ Constant* High;
+ BasicBlock* BB;
+
+ Case(Constant* _Low = NULL, Constant* _High = NULL,
+ BasicBlock* _BB = NULL):
+Low(_Low), High(_High), BB(_BB) { }
+};
+
+typedef std::vector CaseVector;
+typedef std::vector::iterator CaseItr;
private:
void processSwitchInst(SwitchInst *SI);
@@ -50,16 +61,18 @@ namespace {
BasicBlock* OrigBlock, BasicBlock* Default);
BasicBlock* newLeafBlock(Case& Leaf, Value* Val,
BasicBlock* OrigBlock, BasicBlock* Default);
+unsigned Clusterify(CaseVector& Cases, SwitchInst *SI);
};
/// The comparison function for sorting the switch case values in the vector.
+ /// WARNING: Case ranges should be disjoint!
struct CaseCmp {
bool operator () (const LowerSwitch::Case& C1,
const LowerSwitch::Case& C2) {
- const ConstantInt* CI1 = cast(C1.first);
- const ConstantInt* CI2 = cast(C2.first);
- return CI1->getZExtValue() < CI2->getZExtValue();
+ const ConstantInt* CI1 = cast(C1.Low);
+ const ConstantInt* CI2 = cast(C2.High);
+ return CI1->getSExtValue() < CI2->getSExtValue();
}
};
@@ -91,19 +104,20 @@ bool LowerSwitch::runOnFunction(Function
// operator<< - Used for debugging purposes.
//
-std::ostream& operator<<(std::ostream &O,
- const std::vector &C) {
+static std::ostream& operator<<(std::ostream &O,
+const LowerSwitch::CaseVector &C) {
O << "[";
- for (std::vector::const_iterator B = C.begin(),
+ for (LowerSwitch::CaseVector::const_iterator B = C.begin(),
E = C.end(); B != E; ) {
-O << *B->first;
+O << *B->Low << " -" << *B->High;
if (++B != E) O << ", ";
}
return O << "]";
}
-OStream& operator<<(OStream &O, const std::vector &C) {
+
+static OStream& operator<<(OStream &O, const LowerSwitch::CaseVector &C) {
if (O.stream()) *O.stream() << C;
return O;
}
@@ -128,7 +142,8 @@ BasicBlock* LowerSwitch::switchConvert(C
Case& Pivot = *(Begin + Mid);
DOUT << "Pivot ==> "
- << cast(Pivot.first)->getSExtValue() << "\n";
+ << cast(Pivot.Low)->getSExtValue() << " -"
+ << cast(Pivot.High)->getSExtValue() << "\n";
BasicBlock* LBranch = switchConvert(LHS.begin(), LHS.end(), Val,
OrigBlock, Default);
@@ -141,7 +156,7 @@ BasicBlock* LowerSwitch::switchConvert(C
BasicBlock* NewNode = new BasicBlock("NodeBlock");
F->getBasicBlockList().insert(OrigBlock->getNext(), NewNode);
- ICmpInst* Comp = new ICmpInst(ICmpInst::ICMP_ULT, Val, Pivot.first, "Pivot");
+ ICmpInst* Comp = new ICmpInst(ICmpInst::ICMP_ULT, Val, Pivot.Low, "Pivot");
NewNode->getInstList().push_back(Comp);
new BranchInst(LBranch, RBranch, Comp, NewNode);
return NewNode;
@@ -161,25 +176,93 @@ BasicBlock* LowerSwitch::newLeafBlock(Ca
BasicBlock* NewLeaf = new BasicBlock("LeafBlock");
F->getBasicBlockList().insert(OrigBlock->getNext(), NewLeaf);
- // Make the seteq instruction...
- ICmpInst* Comp = new ICmpInst(ICmpInst::ICMP_EQ, Val,
-Leaf.first, "SwitchLeaf");
- NewLeaf->getInstList().push_back(Comp);
+ // Emit comparison
+ ICmpInst* Comp = NULL;
+ if (Leaf.Low == Leaf.High) {
+// Make the seteq instruction...
+Comp = new ICmpInst(ICmpInst::ICMP_EQ, Val, Leaf.Low,
+"SwitchLeaf", NewLeaf);
+ } else {
+// Make range comparison
+if (cast(Leaf.Low)->isMinValue(true /*isSigned*/)) {
+ // Val >= Min && Val <= Hi --> Val <= Hi
+ Comp = new ICmpInst(ICmpInst::ICMP_SLE, Val, Leaf.High,
+ "SwitchLeaf", NewLeaf);
+} else {
+ // Emit V-Lo <=u Hi-Lo
+ Constant* NegLo = ConstantExpr::getNeg(Leaf.Low);
+ Instruction* Add = BinaryOperator::createAdd(Val, NegL
Re: [llvm-commits] CVS: llvm/lib/VMCore/ConstantFold.cpp
On Feb 27, 2007, at 3:35 PM, Reid Spencer wrote:
> On Tue, 2007-02-27 at 14:17 -0800, Chris Lattner wrote:
This seems like a poor choice of API. RoundDoubleToAPInt should
take
a result bitwidth. Without this, this appears like it could make a
"large" APInt, then truncate it down to a small one when converting
from double, which is very inefficient.
>>>
>>> Done.
>>
>> Thanks, but why the default argument?
>
> For compatibility with existing code that didn't have that parameter.
> Call me lazy but I didn't feel like messing with all the test cases
> that
> use this.
The test cases are temporary, right? When they go, the default will
go? If you want, I can file a bug so that we don't forget this.
>>
>> The the interface takes a pointer to uint32_t or uint64_t, it doesn't
>> matter what the internal size is, it has to work with that array.
>
> I have since made a bunch of things in the APInt interface private,
> including these enum values.
Thanks!
>>
>> Additionally, why are you checking this here? What does
>> APINT_BITS_PER_WORD have to do with whether or not this operation can
>> be constant folded?
>
> It doesn't. Don't know what I was thinking when I wrote that.
ok
>> I'm just saying that instead of: APInt::doFoo(x, bool), we should
>> have APInt::doFooSigned(x) and APInt::doFooUnsigned(x). This is an
>> interface change, not a functionality change.
>
> Did it several hours ago.
thanks
>>
>
> @@ -382,7 +412,7 @@
> Ops.reserve(numOps);
> for (unsigned i = 0; i < numOps; ++i) {
>const Constant *Op =
> -(i == idxVal) ? Elt : Constant::getNullValue(Elt->getType
> ());
> +(idxVal == i) ? Elt : Constant::getNullValue(Elt->getType
> ());
This sort of change makes the diff more noisy, and there is no
apparent reason for doing it. Generally, the mutating value (i) is
on the LHS, why do this (in many places)?
>>>
>>> Becasue there is no operator==(int, APInt) but there is an
>>> APInt::operator==(int).
>>
>> Okay, can you add the other one?
>
> You have two options:
>
> 1. Overload global operator== (bad practice in my books)
> 2. Deal with calls like: APIntOps::operator==(i, idxVal) which is
> uglier
> than
>just reversing the operands.
>
> What's the big deal about reversing the order of the operands?
What's the problem with #1? It's already overloaded for many other
things, as is global operator<< (for printing).
-Chris
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Re: [llvm-commits] CVS: llvm/lib/VMCore/ConstantFold.cpp
On Tue, 2007-02-27 at 14:17 -0800, Chris Lattner wrote:
> >> This seems like a poor choice of API. RoundDoubleToAPInt should take
> >> a result bitwidth. Without this, this appears like it could make a
> >> "large" APInt, then truncate it down to a small one when converting
> >> from double, which is very inefficient.
> >
> > Done.
>
> Thanks, but why the default argument?
For compatibility with existing code that didn't have that parameter.
Call me lazy but I didn't feel like messing with all the test cases that
use this.
>
> >>>case Instruction::UIToFP:
> >>> if (const ConstantInt *CI = dyn_cast(V))
> >>> - return ConstantFP::get(DestTy, double(CI->getZExtValue()));
> >>> + if (CI->getType()->getBitWidth() <=
> >>> APInt::APINT_BITS_PER_WORD)
> >>> +return ConstantFP::get(DestTy, CI->getValue().roundToDouble
> >>> (false));
> >>
> >> Why the check for APINT_BITS_PER_WORD here? APINT_BITS_PER_WORD is
> >> an implementation detail of APInt, not a part of its public
> >> interface.
> >
> > Actually it is part of the public interface and it needs to be. For
> > example, the constructor that takes an array of words (as might be
> > used
> > by bcreader) needs to know how many bits are in those words. This
> > constant tells you.
>
> The the interface takes a pointer to uint32_t or uint64_t, it doesn't
> matter what the internal size is, it has to work with that array.
I have since made a bunch of things in the APInt interface private,
including these enum values.
>
> Additionally, why are you checking this here? What does
> APINT_BITS_PER_WORD have to do with whether or not this operation can
> be constant folded?
It doesn't. Don't know what I was thinking when I wrote that.
>
> >> Also, please split the roundToDouble method into two
> >> methods which don't take a bool.
> >
> > I don't understand this comment at all. What should these methods do
> > differently?
>
> I'm just saying that instead of: APInt::doFoo(x, bool), we should
> have APInt::doFooSigned(x) and APInt::doFooUnsigned(x). This is an
> interface change, not a functionality change.
Did it several hours ago.
>
> >>>
> >>> @@ -382,7 +412,7 @@
> >>> Ops.reserve(numOps);
> >>> for (unsigned i = 0; i < numOps; ++i) {
> >>>const Constant *Op =
> >>> -(i == idxVal) ? Elt : Constant::getNullValue(Elt->getType
> >>> ());
> >>> +(idxVal == i) ? Elt : Constant::getNullValue(Elt->getType
> >>> ());
> >>
> >> This sort of change makes the diff more noisy, and there is no
> >> apparent reason for doing it. Generally, the mutating value (i) is
> >> on the LHS, why do this (in many places)?
> >
> > Becasue there is no operator==(int, APInt) but there is an
> > APInt::operator==(int).
>
> Okay, can you add the other one?
You have two options:
1. Overload global operator== (bad practice in my books)
2. Deal with calls like: APIntOps::operator==(i, idxVal) which is uglier
than
just reversing the operands.
What's the big deal about reversing the order of the operands?
>
> -Chris
>
>
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[llvm-commits] CVS: llvm/lib/VMCore/ConstantFold.cpp
Changes in directory llvm/lib/VMCore:
ConstantFold.cpp updated: 1.142 -> 1.143
---
Log message:
Pull out the stops.
---
Diffs of the changes: (+2 -4)
ConstantFold.cpp |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
Index: llvm/lib/VMCore/ConstantFold.cpp
diff -u llvm/lib/VMCore/ConstantFold.cpp:1.142
llvm/lib/VMCore/ConstantFold.cpp:1.143
--- llvm/lib/VMCore/ConstantFold.cpp:1.142 Tue Feb 27 14:25:25 2007
+++ llvm/lib/VMCore/ConstantFold.cppTue Feb 27 17:33:03 2007
@@ -198,13 +198,11 @@
return 0; // Other pointer types cannot be casted
case Instruction::UIToFP:
if (const ConstantInt *CI = dyn_cast(V))
- if (CI->getType()->getBitWidth() <= 64)
-return ConstantFP::get(DestTy, CI->getValue().roundToDouble());
+ return ConstantFP::get(DestTy, CI->getValue().roundToDouble());
return 0;
case Instruction::SIToFP:
if (const ConstantInt *CI = dyn_cast(V))
- if (CI->getType()->getBitWidth() <= 64)
-return ConstantFP::get(DestTy, CI->getValue().signedRoundToDouble());
+ return ConstantFP::get(DestTy, CI->getValue().signedRoundToDouble());
return 0;
case Instruction::ZExt:
if (const ConstantInt *CI = dyn_cast(V)) {
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[llvm-commits] CVS: llvm/lib/VMCore/Constants.cpp
Changes in directory llvm/lib/VMCore:
Constants.cpp updated: 1.223 -> 1.224
---
Log message:
Remove some redundancy.
---
Diffs of the changes: (+1 -4)
Constants.cpp |5 +
1 files changed, 1 insertion(+), 4 deletions(-)
Index: llvm/lib/VMCore/Constants.cpp
diff -u llvm/lib/VMCore/Constants.cpp:1.223 llvm/lib/VMCore/Constants.cpp:1.224
--- llvm/lib/VMCore/Constants.cpp:1.223 Tue Feb 27 01:57:53 2007
+++ llvm/lib/VMCore/Constants.cpp Tue Feb 27 17:27:26 2007
@@ -115,10 +115,7 @@
// Static constructor to create an integral constant with all bits set
ConstantInt *ConstantInt::getAllOnesValue(const Type *Ty) {
if (const IntegerType* ITy = dyn_cast(Ty))
-if (ITy->getBitWidth() == 1)
- return ConstantInt::getTrue();
-else
- return ConstantInt::get(Ty, APInt::getAllOnesValue(ITy->getBitWidth()));
+return ConstantInt::get(Ty, APInt::getAllOnesValue(ITy->getBitWidth()));
return 0;
}
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Re: [llvm-commits] CVS: llvm/lib/VMCore/Constants.cpp
On Tue, 2007-02-27 at 14:20 -0800, Chris Lattner wrote: > On Feb 27, 2007, at 12:51 PM, Reid Spencer wrote: > > Can't we just change this part of ConstantInt: .. snip .. > > > > into: .. snip .. > Yes we could. I would like to do that, but we should do (compile > time) timings to see if it is a significant perf hit. It's basically a DenseMap lookup versus returning a global value. Its going to be slower, but I doubt it makes much difference in the overall scheme of things. In any event, I'm going to leave it as is since we know it will make it slower. The only question is whether cleaning up the extra globals is worth the performance hit. Reid. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.td
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.td updated: 1.10 -> 1.11
---
Log message:
Minor tweak. Allocate r0 to r3 in reverse order, r3 is least likely to be
livein to a function.
---
Diffs of the changes: (+5 -5)
ARMRegisterInfo.td | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.td
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.td:1.10
llvm/lib/Target/ARM/ARMRegisterInfo.td:1.11
--- llvm/lib/Target/ARM/ARMRegisterInfo.td:1.10 Mon Jan 29 16:23:02 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.td Tue Feb 27 17:03:55 2007
@@ -101,31 +101,31 @@
let MethodBodies = [{
// FP is R11, R9 is available.
static const unsigned ARM_GPR_AO_1[] = {
- ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R3, ARM::R2, ARM::R1, ARM::R0,
ARM::R4, ARM::R5, ARM::R6, ARM::R7,
ARM::R8, ARM::R9, ARM::R10,
ARM::LR, ARM::R11 };
// FP is R11, R9 is not available.
static const unsigned ARM_GPR_AO_2[] = {
- ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R3, ARM::R2, ARM::R1, ARM::R0,
ARM::R4, ARM::R5, ARM::R6, ARM::R7,
ARM::R8, ARM::R10,
ARM::LR, ARM::R11 };
// FP is R7, R9 is available.
static const unsigned ARM_GPR_AO_3[] = {
- ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R3, ARM::R2, ARM::R1, ARM::R0,
ARM::R4, ARM::R5, ARM::R6, ARM::R8,
ARM::R9, ARM::R10,ARM::R11,
ARM::LR, ARM::R7 };
// FP is R7, R9 is not available.
static const unsigned ARM_GPR_AO_4[] = {
- ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R3, ARM::R2, ARM::R1, ARM::R0,
ARM::R4, ARM::R5, ARM::R6, ARM::R8,
ARM::R10,ARM::R11,
ARM::LR, ARM::R7 };
// FP is R7, only low registers available.
static const unsigned THUMB_GPR_AO[] = {
- ARM::R0, ARM::R1, ARM::R2,
+ ARM::R2, ARM::R1, ARM::R0,
ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
GPRClass::iterator
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[llvm-commits] CVS: llvm/lib/CodeGen/RegisterScavenging.cpp
Changes in directory llvm/lib/CodeGen:
RegisterScavenging.cpp updated: 1.6 -> 1.7
---
Log message:
Some more code clean up.
---
Diffs of the changes: (+29 -23)
RegisterScavenging.cpp | 52 +++--
1 files changed, 29 insertions(+), 23 deletions(-)
Index: llvm/lib/CodeGen/RegisterScavenging.cpp
diff -u llvm/lib/CodeGen/RegisterScavenging.cpp:1.6
llvm/lib/CodeGen/RegisterScavenging.cpp:1.7
--- llvm/lib/CodeGen/RegisterScavenging.cpp:1.6 Tue Feb 27 16:10:52 2007
+++ llvm/lib/CodeGen/RegisterScavenging.cpp Tue Feb 27 16:58:43 2007
@@ -26,44 +26,50 @@
using namespace llvm;
void RegScavenger::init(MachineBasicBlock *mbb) {
- if (mbb)
-MBB = mbb;
-
- const MachineFunction &MF = *MBB->getParent();
+ const MachineFunction &MF = *mbb->getParent();
const TargetMachine &TM = MF.getTarget();
const MRegisterInfo *RegInfo = TM.getRegisterInfo();
- MBBI = MBB->begin();
- NumPhysRegs = RegInfo->getNumRegs();
- RegStates.resize(NumPhysRegs, true);
+ assert((NumPhysRegs == 0 || NumPhysRegs == RegInfo->getNumRegs()) &&
+ "Target changed?");
+
+ if (!MBB) {
+NumPhysRegs = RegInfo->getNumRegs();
+ReservedRegs = RegInfo->getReservedRegs(MF);
+RegStates.resize(NumPhysRegs);
+
+// Create callee-saved registers bitvector.
+CalleeSavedRegs.resize(NumPhysRegs);
+const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
+if (CSRegs != NULL)
+ for (unsigned i = 0; CSRegs[i]; ++i)
+CalleeSavedRegs.set(CSRegs[i]);
+ }
+
+ MBB = mbb;
+
+ // All registers started out unused.
+ RegStates.set();
// Create reserved registers bitvector.
- ReservedRegs = RegInfo->getReservedRegs(MF);
RegStates ^= ReservedRegs;
- // Create callee-saved registers bitvector.
- CalleeSavedRegs.resize(NumPhysRegs);
- const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
- if (CSRegs != NULL)
-for (unsigned i = 0; CSRegs[i]; ++i)
- CalleeSavedRegs.set(CSRegs[i]);
-
// Live-in registers are in use.
if (!MBB->livein_empty())
for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
E = MBB->livein_end(); I != E; ++I)
setUsed(*I);
-
- Initialized = true;
}
void RegScavenger::forward() {
- assert(MBBI != MBB->end() && "Already at the end of the basic block!");
// Move ptr forward.
- if (!Initialized)
-init();
- else
+ if (!Tracking) {
+MBBI = MBB->begin();
+Tracking = true;
+ } else {
+assert(MBBI != MBB->end() && "Already at the end of the basic block!");
MBBI = next(MBBI);
+ }
MachineInstr *MI = MBBI;
// Process uses first.
@@ -102,6 +108,7 @@
}
void RegScavenger::backward() {
+ assert(Tracking && "Not tracking states!");
assert(MBBI != MBB->begin() && "Already at start of basic block!");
// Move ptr backward.
MBBI = prior(MBBI);
@@ -168,7 +175,6 @@
MBB = NULL;
}
- NumPhysRegs = 0;
- Initialized = false;
+ Tracking = false;
RegStates.clear();
}
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/RegisterScavenging.h
Changes in directory llvm/include/llvm/CodeGen:
RegisterScavenging.h updated: 1.4 -> 1.5
---
Log message:
Some more code clean up.
---
Diffs of the changes: (+6 -5)
RegisterScavenging.h | 11 ++-
1 files changed, 6 insertions(+), 5 deletions(-)
Index: llvm/include/llvm/CodeGen/RegisterScavenging.h
diff -u llvm/include/llvm/CodeGen/RegisterScavenging.h:1.4
llvm/include/llvm/CodeGen/RegisterScavenging.h:1.5
--- llvm/include/llvm/CodeGen/RegisterScavenging.h:1.4 Tue Feb 27 16:10:52 2007
+++ llvm/include/llvm/CodeGen/RegisterScavenging.h Tue Feb 27 16:58:43 2007
@@ -29,8 +29,9 @@
MachineBasicBlock::iterator MBBI;
unsigned NumPhysRegs;
- /// Initialized - All states are initialized and ready to go!
- bool Initialized;
+ /// Tracking - True if RegScavenger is currently tracking the liveness of
+ /// registers.
+ bool Tracking;
/// RegStates - The current state of all the physical registers immediately
/// before MBBI. One bit per physical register. If bit is set that means it's
@@ -39,14 +40,14 @@
public:
RegScavenger()
-: MBB(NULL), Initialized(false) {};
+: MBB(NULL), NumPhysRegs(0), Tracking(false) {};
RegScavenger(MachineBasicBlock *mbb)
-: MBB(mbb), Initialized(false) {};
+: MBB(mbb), NumPhysRegs(0), Tracking(false) {};
/// Init - Initialize the states.
///
- void init(MachineBasicBlock *mbb = NULL);
+ void init(MachineBasicBlock *mbb);
/// Reset - Discard previous states and re-initialize the states given for
/// the specific basic block.
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Re: [llvm-commits] CVS: llvm/lib/VMCore/Constants.cpp
On Feb 27, 2007, at 12:51 PM, Reid Spencer wrote:
> Can't we just change this part of ConstantInt:
>
> /// getTrue/getFalse - Return the singleton true/false values.
> static inline ConstantInt *getTrue() {
> if (TheTrueVal) return TheTrueVal;
> return CreateTrueFalseVals(true);
> }
> static inline ConstantInt *getFalse() {
> if (TheFalseVal) return TheFalseVal;
> return CreateTrueFalseVals(false);
> }
>
> into:
> /// getTrue/getFalse - Return the singleton true/false values.
> static inline ConstantInt *getTrue() {
> return get(Type::Int1Ty, 1);
> }
> static inline ConstantInt *getFalse() {
> return get(Type::Int1Ty, 0);
> }
>
> and get rid of all the special handling of true/false values? Or
> have we
> provided this simply as an optimization on frequently obtained integer
> values?
Yes we could. I would like to do that, but we should do (compile
time) timings to see if it is a significant perf hit.
-Chris
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Re: [llvm-commits] CVS: llvm/lib/VMCore/AsmWriter.cpp ConstantFold.cpp
> @@ -464,7 +464,7 @@ > if (CI->getType() == Type::Int1Ty) >Out << (CI->getZExtValue() ? "true" : "false"); > else > - Out << CI->getValue().toString(10,/*wantSigned=*/true); > + Out << CI->getValue().toStringSigned(10); Thanks! >case Instruction::UIToFP: > if (const ConstantInt *CI = dyn_cast(V)) > - if (CI->getType()->getBitWidth() <= APInt::APINT_BITS_PER_WORD) > -return ConstantFP::get(DestTy, CI->getValue().roundToDouble > (false)); > + if (CI->getType()->getBitWidth() <= 64) > +return ConstantFP::get(DestTy, CI->getValue().roundToDouble > ()); > return 0; >case Instruction::SIToFP: > if (const ConstantInt *CI = dyn_cast(V)) > - if (CI->getType()->getBitWidth() <= APInt::APINT_BITS_PER_WORD) > -return ConstantFP::get(DestTy, CI->getValue().roundToDouble > (true)); > + if (CI->getType()->getBitWidth() <= 64) > +return ConstantFP::get(DestTy, CI->getValue > ().signedRoundToDouble()); > return 0; Okay, I'm still not seeing why "64 and less" can be constant folded, but larger things can't... -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/VMCore/ConstantFold.cpp
>> This seems like a poor choice of API. RoundDoubleToAPInt should take
>> a result bitwidth. Without this, this appears like it could make a
>> "large" APInt, then truncate it down to a small one when converting
>> from double, which is very inefficient.
>
> Done.
Thanks, but why the default argument?
>>>case Instruction::UIToFP:
>>> if (const ConstantInt *CI = dyn_cast(V))
>>> - return ConstantFP::get(DestTy, double(CI->getZExtValue()));
>>> + if (CI->getType()->getBitWidth() <=
>>> APInt::APINT_BITS_PER_WORD)
>>> +return ConstantFP::get(DestTy, CI->getValue().roundToDouble
>>> (false));
>>
>> Why the check for APINT_BITS_PER_WORD here? APINT_BITS_PER_WORD is
>> an implementation detail of APInt, not a part of its public
>> interface.
>
> Actually it is part of the public interface and it needs to be. For
> example, the constructor that takes an array of words (as might be
> used
> by bcreader) needs to know how many bits are in those words. This
> constant tells you.
The the interface takes a pointer to uint32_t or uint64_t, it doesn't
matter what the internal size is, it has to work with that array.
Additionally, why are you checking this here? What does
APINT_BITS_PER_WORD have to do with whether or not this operation can
be constant folded?
>> Also, please split the roundToDouble method into two
>> methods which don't take a bool.
>
> I don't understand this comment at all. What should these methods do
> differently?
I'm just saying that instead of: APInt::doFoo(x, bool), we should
have APInt::doFooSigned(x) and APInt::doFooUnsigned(x). This is an
interface change, not a functionality change.
>>>
>>> @@ -382,7 +412,7 @@
>>> Ops.reserve(numOps);
>>> for (unsigned i = 0; i < numOps; ++i) {
>>>const Constant *Op =
>>> -(i == idxVal) ? Elt : Constant::getNullValue(Elt->getType
>>> ());
>>> +(idxVal == i) ? Elt : Constant::getNullValue(Elt->getType
>>> ());
>>
>> This sort of change makes the diff more noisy, and there is no
>> apparent reason for doing it. Generally, the mutating value (i) is
>> on the LHS, why do this (in many places)?
>
> Becasue there is no operator==(int, APInt) but there is an
> APInt::operator==(int).
Okay, can you add the other one?
-Chris
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Re: [llvm-commits] CVS: llvm/lib/VMCore/Constants.cpp
On Feb 27, 2007, at 11:34 AM, Reid Spencer wrote:
> On Tue, 2007-02-27 at 09:10 -0800, Chris Lattner wrote:
>>> Index: llvm/lib/VMCore/Constants.cpp
>>> diff -u llvm/lib/VMCore/Constants.cpp:1.222 llvm/lib/VMCore/
>>> Constants.cpp:1.223
>>> --- llvm/lib/VMCore/Constants.cpp:1.222 Mon Feb 26 21:05:06 2007
>>> +++ llvm/lib/VMCore/Constants.cpp Tue Feb 27 01:57:53 2007
>>> @@ -118,7 +118,7 @@
>>> if (ITy->getBitWidth() == 1)
>>>return ConstantInt::getTrue();
>>> else
>>> - return ConstantInt::get(Ty, int64_t(-1));
>>> + return ConstantInt::get(Ty, APInt::getAllOnesValue(ITy-
getBitWidth()));
>>>return 0;
>>> }
>>
>> The special case for 'i1' can be removed, right?
>
> I assumed the special case was because of this mess:
>
Nope, it's not needed, ConstantInt::get(Type::Int1Ty, x) works.
>> ConstantInt *ConstantInt::TheTrueVal = 0;
>> ConstantInt *ConstantInt::TheFalseVal = 0;
>>
>> namespace llvm {
>> void CleanupTrueFalse(void *) {
>> ConstantInt::ResetTrueFalse();
>> }
>> }
>>
>> static ManagedCleanup TrueFalseCleanup;
>>
>> ConstantInt *ConstantInt::CreateTrueFalseVals(bool WhichOne) {
>> assert(TheTrueVal == 0 && TheFalseVal == 0);
>> TheTrueVal = get(Type::Int1Ty, 1);
>> TheFalseVal = get(Type::Int1Ty, 0);
>>
>> // Ensure that llvm_shutdown nulls out TheTrueVal/TheFalseVal.
>> TrueFalseCleanup.Register();
>>
>> return WhichOne ? TheTrueVal : TheFalseVal;
>> }
>
> why do we need this?
This is needed to make ConstantInt::getTrue() / getFalse() efficient.
-Chris
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[llvm-commits] CVS: llvm/lib/Target/X86/Makefile
Changes in directory llvm/lib/Target/X86: Makefile updated: 1.33 -> 1.34 --- Log message: reenable generation of CC info --- Diffs of the changes: (+1 -1) Makefile |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/Makefile diff -u llvm/lib/Target/X86/Makefile:1.33 llvm/lib/Target/X86/Makefile:1.34 --- llvm/lib/Target/X86/Makefile:1.33 Tue Feb 27 15:47:22 2007 +++ llvm/lib/Target/X86/MakefileTue Feb 27 16:12:19 2007 @@ -15,6 +15,6 @@ X86GenRegisterInfo.inc X86GenInstrNames.inc \ X86GenInstrInfo.inc X86GenAsmWriter.inc \ X86GenAsmWriter1.inc X86GenDAGISel.inc \ -X86GenSubtarget.inc +X86GenCallingConv.inc X86GenSubtarget.inc include $(LEVEL)/Makefile.common ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/RegisterScavenging.h
Changes in directory llvm/include/llvm/CodeGen:
RegisterScavenging.h updated: 1.3 -> 1.4
---
Log message:
Oops.
---
Diffs of the changes: (+2 -3)
RegisterScavenging.h |5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
Index: llvm/include/llvm/CodeGen/RegisterScavenging.h
diff -u llvm/include/llvm/CodeGen/RegisterScavenging.h:1.3
llvm/include/llvm/CodeGen/RegisterScavenging.h:1.4
--- llvm/include/llvm/CodeGen/RegisterScavenging.h:1.3 Tue Feb 27 15:09:11 2007
+++ llvm/include/llvm/CodeGen/RegisterScavenging.h Tue Feb 27 16:10:52 2007
@@ -46,14 +46,13 @@
/// Init - Initialize the states.
///
- void init();
+ void init(MachineBasicBlock *mbb = NULL);
/// Reset - Discard previous states and re-initialize the states given for
/// the specific basic block.
void reset(MachineBasicBlock *mbb) {
-MBB = mbb;
clear();
-init();
+init(mbb);
}
/// forward / backward - Move the internal MBB iterator and update register
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[llvm-commits] CVS: llvm/lib/CodeGen/RegisterScavenging.cpp
Changes in directory llvm/lib/CodeGen:
RegisterScavenging.cpp updated: 1.5 -> 1.6
---
Log message:
Oops.
---
Diffs of the changes: (+4 -1)
RegisterScavenging.cpp |5 -
1 files changed, 4 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/RegisterScavenging.cpp
diff -u llvm/lib/CodeGen/RegisterScavenging.cpp:1.5
llvm/lib/CodeGen/RegisterScavenging.cpp:1.6
--- llvm/lib/CodeGen/RegisterScavenging.cpp:1.5 Tue Feb 27 15:09:48 2007
+++ llvm/lib/CodeGen/RegisterScavenging.cpp Tue Feb 27 16:10:52 2007
@@ -25,7 +25,10 @@
#include "llvm/ADT/STLExtras.h"
using namespace llvm;
-void RegScavenger::init() {
+void RegScavenger::init(MachineBasicBlock *mbb) {
+ if (mbb)
+MBB = mbb;
+
const MachineFunction &MF = *MBB->getParent();
const TargetMachine &TM = MF.getTarget();
const MRegisterInfo *RegInfo = TM.getRegisterInfo();
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[llvm-commits] CVS: llvm/utils/TableGen/CallingConvEmitter.cpp CodeGenTarget.cpp Record.cpp Record.h TableGen.cpp
Changes in directory llvm/utils/TableGen:
CallingConvEmitter.cpp updated: 1.1 -> 1.2
CodeGenTarget.cpp updated: 1.84 -> 1.85
Record.cpp updated: 1.57 -> 1.58
Record.h updated: 1.61 -> 1.62
TableGen.cpp updated: 1.49 -> 1.50
---
Log message:
reapply
---
Diffs of the changes: (+20 -8)
CallingConvEmitter.cpp |3 ++-
CodeGenTarget.cpp |8 ++--
Record.cpp |7 +++
Record.h |2 ++
TableGen.cpp |8 +++-
5 files changed, 20 insertions(+), 8 deletions(-)
Index: llvm/utils/TableGen/CallingConvEmitter.cpp
diff -u llvm/utils/TableGen/CallingConvEmitter.cpp:1.1
llvm/utils/TableGen/CallingConvEmitter.cpp:1.2
--- llvm/utils/TableGen/CallingConvEmitter.cpp:1.1 Tue Feb 27 16:05:51 2007
+++ llvm/utils/TableGen/CallingConvEmitter.cpp Tue Feb 27 16:08:27 2007
@@ -125,4 +125,5 @@
throw "Unknown CCAction!";
}
}
-}
\ No newline at end of file
+}
+
Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.84
llvm/utils/TableGen/CodeGenTarget.cpp:1.85
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.84 Tue Feb 27 15:44:08 2007
+++ llvm/utils/TableGen/CodeGenTarget.cpp Tue Feb 27 16:08:27 2007
@@ -604,9 +604,7 @@
// Parse the list of argument types.
ListInit *TypeList = R->getValueAsListInit("Types");
for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
-DefInit *DI = dynamic_cast(TypeList->getElement(i));
-assert(DI && "Invalid list type!");
-Record *TyEl = DI->getDef();
+Record *TyEl = TypeList->getElementAsRecord(i);
assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
ArgTypes.push_back(TyEl->getValueAsString("TypeVal"));
@@ -620,9 +618,7 @@
// Parse the intrinsic properties.
ListInit *PropList = R->getValueAsListInit("Properties");
for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) {
-DefInit *DI = dynamic_cast(PropList->getElement(i));
-assert(DI && "Invalid list type!");
-Record *Property = DI->getDef();
+Record *Property = PropList->getElementAsRecord(i);
assert(Property->isSubClassOf("IntrinsicProperty") &&
"Expected a property!");
Index: llvm/utils/TableGen/Record.cpp
diff -u llvm/utils/TableGen/Record.cpp:1.57 llvm/utils/TableGen/Record.cpp:1.58
--- llvm/utils/TableGen/Record.cpp:1.57 Tue Feb 27 15:44:08 2007
+++ llvm/utils/TableGen/Record.cpp Tue Feb 27 16:08:27 2007
@@ -337,6 +337,13 @@
return new ListInit(Vals);
}
+Record *ListInit::getElementAsRecord(unsigned i) const {
+ assert(i < Values.size() && "List element index out of range!");
+ DefInit *DI = dynamic_cast(Values[i]);
+ if (DI == 0) throw "Expected record in list!";
+ return DI->getDef();
+}
+
Init *ListInit::resolveReferences(Record &R, const RecordVal *RV) {
std::vector Resolved;
Resolved.reserve(getSize());
Index: llvm/utils/TableGen/Record.h
diff -u llvm/utils/TableGen/Record.h:1.61 llvm/utils/TableGen/Record.h:1.62
--- llvm/utils/TableGen/Record.h:1.61 Tue Feb 27 15:44:08 2007
+++ llvm/utils/TableGen/Record.hTue Feb 27 16:08:27 2007
@@ -626,6 +626,8 @@
return Values[i];
}
+ Record *getElementAsRecord(unsigned i) const;
+
Init *convertInitListSlice(const std::vector &Elements);
virtual Init *convertInitializerTo(RecTy *Ty) {
Index: llvm/utils/TableGen/TableGen.cpp
diff -u llvm/utils/TableGen/TableGen.cpp:1.49
llvm/utils/TableGen/TableGen.cpp:1.50
--- llvm/utils/TableGen/TableGen.cpp:1.49 Tue Feb 27 15:44:08 2007
+++ llvm/utils/TableGen/TableGen.cppTue Feb 27 16:08:27 2007
@@ -20,6 +20,7 @@
#include "llvm/Support/Streams.h"
#include "llvm/System/Signals.h"
#include "llvm/Support/FileUtilities.h"
+#include "CallingConvEmitter.h"
#include "CodeEmitterGen.h"
#include "RegisterInfoEmitter.h"
#include "InstrInfoEmitter.h"
@@ -38,6 +39,7 @@
GenEmitter,
GenRegisterEnums, GenRegister, GenRegisterHeader,
GenInstrEnums, GenInstrs, GenAsmWriter,
+ GenCallingConv,
GenDAGISel,
GenSubtarget,
GenIntrinsic,
@@ -61,6 +63,8 @@
"Generate enum values for instructions"),
clEnumValN(GenInstrs, "gen-instr-desc",
"Generate instruction descriptions"),
+clEnumValN(GenCallingConv, "gen-callingconv",
+ "Generate calling convention descriptions"),
clEnumValN(GenAsmWriter, "gen-asm-writer",
"Generate assembly writer"),
clEnumValN(GenDAGISel, "gen-dag-isel",
@@ -138,7 +142,9 @@
case GenInstrs:
InstrInfoEmitter(Records).run(*Out);
break;
-
+case GenCallingConv:
+ CallingConvEmitter(Records).run(*Out);
+ break;
case GenAsmWriter:
AsmWriterEmitter(Records).run(*Out);
break;
___
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[llvm-commits] CVS: llvm/utils/TableGen/CallingConvEmitter.h CallingConvEmitter.cpp
Changes in directory llvm/utils/TableGen:
CallingConvEmitter.h added (r1.1)
CallingConvEmitter.cpp added (r1.1)
---
Log message:
---
Diffs of the changes: (+166 -0)
CallingConvEmitter.cpp | 128 +
CallingConvEmitter.h | 38 ++
2 files changed, 166 insertions(+)
Index: llvm/utils/TableGen/CallingConvEmitter.h
diff -c /dev/null llvm/utils/TableGen/CallingConvEmitter.h:1.1
*** /dev/null Tue Feb 27 16:06:01 2007
--- llvm/utils/TableGen/CallingConvEmitter.hTue Feb 27 16:05:51 2007
***
*** 0
--- 1,38
+ //===- CallingConvEmitter.h - Generate calling conventions --*- C++
-*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Chris Lattner and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for
details.
+ //
+
//===--===//
+ //
+ // This tablegen backend is responsible for emitting descriptions of the
calling
+ // conventions supported by this target.
+ //
+
//===--===//
+
+ #ifndef CALLINGCONV_EMITTER_H
+ #define CALLINGCONV_EMITTER_H
+
+ #include "TableGenBackend.h"
+ #include
+ #include
+ #include
+
+ namespace llvm {
+ class CallingConvEmitter : public TableGenBackend {
+ RecordKeeper &Records;
+ public:
+ CallingConvEmitter(RecordKeeper &R) : Records(R) {}
+
+ // run - Output the asmwriter, returning true on failure.
+ void run(std::ostream &o);
+
+ private:
+ void EmitCallingConv(Record *CC, std::ostream &O);
+ void EmitAction(Record *Action, unsigned Indent, std::ostream &O);
+ unsigned Counter;
+ };
+ }
+ #endif
Index: llvm/utils/TableGen/CallingConvEmitter.cpp
diff -c /dev/null llvm/utils/TableGen/CallingConvEmitter.cpp:1.1
*** /dev/null Tue Feb 27 16:06:08 2007
--- llvm/utils/TableGen/CallingConvEmitter.cpp Tue Feb 27 16:05:51 2007
***
*** 0
--- 1,128
+ //===- CallingConvEmitter.cpp - Generate calling conventions
--===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Chris Lattner and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for
details.
+ //
+
//===--===//
+ //
+ // This tablegen backend is responsible for emitting descriptions of the
calling
+ // conventions supported by this target.
+ //
+
//===--===//
+
+ #include "CallingConvEmitter.h"
+ #include "Record.h"
+ #include "CodeGenTarget.h"
+ using namespace llvm;
+
+ void CallingConvEmitter::run(std::ostream &O) {
+ EmitSourceFileHeader("Calling Convention Implementation Fragment", O);
+
+ std::vector CCs = Records.getAllDerivedDefinitions("CallingConv");
+
+ // Emit prototypes for all of the CC's so that they can forward ref each
+ // other.
+ for (unsigned i = 0, e = CCs.size(); i != e; ++i) {
+ O << "static bool " << CCs[i]->getName()
+ << "(unsigned ValNo, MVT::ValueType ValVT, MVT::ValueType LocVT,\n"
+ << std::string(CCs[i]->getName().size()+13, ' ')
+ << "CCValAssign::LocInfo LocInfo, unsigned ArgFlags, CCState
&State);\n";
+ }
+
+ // Emit each calling convention description in full.
+ for (unsigned i = 0, e = CCs.size(); i != e; ++i)
+ EmitCallingConv(CCs[i], O);
+ }
+
+
+ void CallingConvEmitter::EmitCallingConv(Record *CC, std::ostream &O) {
+ ListInit *CCActions = CC->getValueAsListInit("Actions");
+ Counter = 0;
+
+ O << "\n\nstatic bool " << CC->getName()
+ << "(unsigned ValNo, MVT::ValueType ValVT, MVT::ValueType LocVT,\n"
+ << std::string(CC->getName().size()+13, ' ')
+ << "CCValAssign::LocInfo LocInfo, "
+ << "unsigned ArgFlags, CCState &State) {\n";
+
+ // Emit all of the actions, in order.
+ for (unsigned i = 0, e = CCActions->getSize(); i != e; ++i) {
+ O << "\n";
+ EmitAction(CCActions->getElementAsRecord(i), 2, O);
+ }
+
+ O << "\n return true; // CC didn't match.\n";
+ O << "}\n";
+ }
+
+ void CallingConvEmitter::EmitAction(Record *Action,
+ unsigned Indent, std::ostream &O) {
+ std::string IndentStr = std::string(Indent, ' ');
+
+ if (Action->isSubClassOf("CCPredicateAction")) {
+ O << IndentStr << "if (";
+
+ if (Action->isSubClassOf("CCMatchType")) {
+ ListInit *VTs = Action->getValueAsListInit("VTs");
+ for (unsigned i = 0, e = VTs->getSize(); i != e; ++i) {
+ Record *VT = VTs->getElementAsRecord(i);
+ if (i != 0) O << " || \n" << IndentStr;
+ O << "LocVT == " << getEnumName(getValueType(VT));
+ }
+
+ } else if (Action->isSubClassOf("CCMatchIf")) {
+
[llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
Changes in directory llvm/include/llvm/ADT:
APInt.h updated: 1.26 -> 1.27
---
Log message:
Implement countLeadingOnes() and getMinSignedBits(). This helps to minimize
the bit width of negative numbers by computing the minimum bit width for a
negative value. E.g. 0x1800 could be just 0x8000
---
Diffs of the changes: (+14 -1)
APInt.h | 15 ++-
1 files changed, 14 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/ADT/APInt.h
diff -u llvm/include/llvm/ADT/APInt.h:1.26 llvm/include/llvm/ADT/APInt.h:1.27
--- llvm/include/llvm/ADT/APInt.h:1.26 Tue Feb 27 14:24:31 2007
+++ llvm/include/llvm/ADT/APInt.h Tue Feb 27 15:59:26 2007
@@ -446,6 +446,12 @@
return BitWidth - countLeadingZeros();
}
+ inline uint32_t getMinSignedBits() const {
+if (isNegative())
+ return BitWidth - countLeadingOnes() + 1;
+return getActiveBits();
+ }
+
/// This method attempts to return the value of this APInt as a zero extended
/// uint64_t. The bitwidth must be <= 64 or the value must fit within a
/// uint64_t. Otherwise an assertion will result.
@@ -587,9 +593,16 @@
/// @returns getNumWords() * APINT_BITS_PER_WORD if the value is zero.
/// @returns the number of zeros from the most significant bit to the first
/// one bits.
- /// @brief Count the number of trailing one bits.
+ /// @brief Count the number of leading one bits.
uint32_t countLeadingZeros() const;
+ /// countLeadingOnes - This function counts the number of contiguous 1 bits
+ /// in the high order bits. The count stops when the first 0 bit is reached.
+ /// @returns 0 if the high order bit is not set
+ /// @returns the number of 1 bits from the most significant to the least
+ /// @brief Count the number of leading one bits.
+ uint32_t countLeadingOnes() const;
+
/// countTrailingZeros - This function is an APInt version of the
/// countTrailingZoers_{32,64} functions in MathExtras.h. It counts
/// the number of zeros from the least significant bit to the first one bit.
___
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[llvm-commits] CVS: llvm/lib/Support/APInt.cpp
Changes in directory llvm/lib/Support:
APInt.cpp updated: 1.55 -> 1.56
---
Log message:
Implement countLeadingOnes() and getMinSignedBits(). This helps to minimize
the bit width of negative numbers by computing the minimum bit width for a
negative value. E.g. 0x1800 could be just 0x8000
---
Diffs of the changes: (+34 -1)
APInt.cpp | 35 ++-
1 files changed, 34 insertions(+), 1 deletion(-)
Index: llvm/lib/Support/APInt.cpp
diff -u llvm/lib/Support/APInt.cpp:1.55 llvm/lib/Support/APInt.cpp:1.56
--- llvm/lib/Support/APInt.cpp:1.55 Tue Feb 27 14:24:31 2007
+++ llvm/lib/Support/APInt.cpp Tue Feb 27 15:59:26 2007
@@ -702,6 +702,38 @@
return Count;
}
+static uint32_t countLeadingOnes_64(uint64_t V, uint32_t skip) {
+ uint32_t Count = 0;
+ if (skip)
+V <<= skip;
+ while (V && (V & (1ULL << 63))) {
+Count++;
+V <<= 1;
+ }
+ return Count;
+}
+
+uint32_t APInt::countLeadingOnes() const {
+ if (isSingleWord())
+return countLeadingOnes_64(VAL, APINT_BITS_PER_WORD - BitWidth);
+
+ uint32_t highWordBits = BitWidth % APINT_BITS_PER_WORD;
+ uint32_t shift = (highWordBits == 0 ? 0 : APINT_BITS_PER_WORD -
highWordBits);
+ int i = getNumWords() - 1;
+ uint32_t Count = countLeadingOnes_64(pVal[i], shift);
+ if (Count == highWordBits) {
+for (i--; i >= 0; --i) {
+ if (pVal[i] == -1ULL)
+Count += APINT_BITS_PER_WORD;
+ else {
+Count += countLeadingOnes_64(pVal[i], 0);
+break;
+ }
+}
+ }
+ return Count;
+}
+
uint32_t APInt::countTrailingZeros() const {
if (isSingleWord())
return CountTrailingZeros_64(VAL);
@@ -1701,6 +1733,7 @@
else for (unsigned i = getNumWords(); i > 0; i--) {
cerr << pVal[i-1] << " ";
}
- cerr << " (" << this->toString(10) << ")\n" << std::setbase(10);
+ cerr << " U(" << this->toString(10) << ") S(" << this->toStringSigned(10)
+ << ")\n" << std::setbase(10);
}
#endif
___
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[llvm-commits] CVS: llvm/lib/Target/X86/Makefile
Changes in directory llvm/lib/Target/X86: Makefile updated: 1.32 -> 1.33 --- Log message: Back out previous commit temporarily. --- Diffs of the changes: (+1 -1) Makefile |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/Makefile diff -u llvm/lib/Target/X86/Makefile:1.32 llvm/lib/Target/X86/Makefile:1.33 --- llvm/lib/Target/X86/Makefile:1.32 Tue Feb 27 14:44:31 2007 +++ llvm/lib/Target/X86/MakefileTue Feb 27 15:47:22 2007 @@ -15,6 +15,6 @@ X86GenRegisterInfo.inc X86GenInstrNames.inc \ X86GenInstrInfo.inc X86GenAsmWriter.inc \ X86GenAsmWriter1.inc X86GenDAGISel.inc \ -X86GenCallingConv.inc X86GenSubtarget.inc +X86GenSubtarget.inc include $(LEVEL)/Makefile.common ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp Record.cpp Record.h TableGen.cpp
Changes in directory llvm/utils/TableGen:
CodeGenTarget.cpp updated: 1.83 -> 1.84
Record.cpp updated: 1.56 -> 1.57
Record.h updated: 1.60 -> 1.61
TableGen.cpp updated: 1.48 -> 1.49
---
Log message:
Backing out
CodeGenTarget.cpp updated: 1.82 -> 1.83
Record.cpp updated: 1.55 -> 1.56
Record.h updated: 1.59 -> 1.60
TableGen.cpp updated: 1.47 -> 1.48
It's missing CallingConvEmitter.h
---
Diffs of the changes: (+7 -18)
CodeGenTarget.cpp |8 ++--
Record.cpp|7 ---
Record.h |2 --
TableGen.cpp |8 +---
4 files changed, 7 insertions(+), 18 deletions(-)
Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.83
llvm/utils/TableGen/CodeGenTarget.cpp:1.84
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.83 Tue Feb 27 14:43:37 2007
+++ llvm/utils/TableGen/CodeGenTarget.cpp Tue Feb 27 15:44:08 2007
@@ -604,7 +604,9 @@
// Parse the list of argument types.
ListInit *TypeList = R->getValueAsListInit("Types");
for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
-Record *TyEl = TypeList->getElementAsRecord(i);
+DefInit *DI = dynamic_cast(TypeList->getElement(i));
+assert(DI && "Invalid list type!");
+Record *TyEl = DI->getDef();
assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
ArgTypes.push_back(TyEl->getValueAsString("TypeVal"));
@@ -618,7 +620,9 @@
// Parse the intrinsic properties.
ListInit *PropList = R->getValueAsListInit("Properties");
for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) {
-Record *Property = PropList->getElementAsRecord(i);
+DefInit *DI = dynamic_cast(PropList->getElement(i));
+assert(DI && "Invalid list type!");
+Record *Property = DI->getDef();
assert(Property->isSubClassOf("IntrinsicProperty") &&
"Expected a property!");
Index: llvm/utils/TableGen/Record.cpp
diff -u llvm/utils/TableGen/Record.cpp:1.56 llvm/utils/TableGen/Record.cpp:1.57
--- llvm/utils/TableGen/Record.cpp:1.56 Tue Feb 27 14:43:37 2007
+++ llvm/utils/TableGen/Record.cpp Tue Feb 27 15:44:08 2007
@@ -337,13 +337,6 @@
return new ListInit(Vals);
}
-Record *ListInit::getElementAsRecord(unsigned i) const {
- assert(i < Values.size() && "List element index out of range!");
- DefInit *DI = dynamic_cast(Values[i]);
- if (DI == 0) throw "Expected record in list!";
- return DI->getDef();
-}
-
Init *ListInit::resolveReferences(Record &R, const RecordVal *RV) {
std::vector Resolved;
Resolved.reserve(getSize());
Index: llvm/utils/TableGen/Record.h
diff -u llvm/utils/TableGen/Record.h:1.60 llvm/utils/TableGen/Record.h:1.61
--- llvm/utils/TableGen/Record.h:1.60 Tue Feb 27 14:43:37 2007
+++ llvm/utils/TableGen/Record.hTue Feb 27 15:44:08 2007
@@ -626,8 +626,6 @@
return Values[i];
}
- Record *getElementAsRecord(unsigned i) const;
-
Init *convertInitListSlice(const std::vector &Elements);
virtual Init *convertInitializerTo(RecTy *Ty) {
Index: llvm/utils/TableGen/TableGen.cpp
diff -u llvm/utils/TableGen/TableGen.cpp:1.48
llvm/utils/TableGen/TableGen.cpp:1.49
--- llvm/utils/TableGen/TableGen.cpp:1.48 Tue Feb 27 14:43:37 2007
+++ llvm/utils/TableGen/TableGen.cppTue Feb 27 15:44:08 2007
@@ -20,7 +20,6 @@
#include "llvm/Support/Streams.h"
#include "llvm/System/Signals.h"
#include "llvm/Support/FileUtilities.h"
-#include "CallingConvEmitter.h"
#include "CodeEmitterGen.h"
#include "RegisterInfoEmitter.h"
#include "InstrInfoEmitter.h"
@@ -39,7 +38,6 @@
GenEmitter,
GenRegisterEnums, GenRegister, GenRegisterHeader,
GenInstrEnums, GenInstrs, GenAsmWriter,
- GenCallingConv,
GenDAGISel,
GenSubtarget,
GenIntrinsic,
@@ -63,8 +61,6 @@
"Generate enum values for instructions"),
clEnumValN(GenInstrs, "gen-instr-desc",
"Generate instruction descriptions"),
-clEnumValN(GenCallingConv, "gen-callingconv",
- "Generate calling convention descriptions"),
clEnumValN(GenAsmWriter, "gen-asm-writer",
"Generate assembly writer"),
clEnumValN(GenDAGISel, "gen-dag-isel",
@@ -142,9 +138,7 @@
case GenInstrs:
InstrInfoEmitter(Records).run(*Out);
break;
-case GenCallingConv:
- CallingConvEmitter(Records).run(*Out);
- break;
+
case GenAsmWriter:
AsmWriterEmitter(Records).run(*Out);
break;
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp ARMRegisterInfo.h
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.72 -> 1.73
ARMRegisterInfo.h updated: 1.12 -> 1.13
---
Log message:
Let MRegisterInfo now owns RegScavenger; eliminateFrameIndex must preserve
register kill info.
---
Diffs of the changes: (+51 -30)
ARMRegisterInfo.cpp | 70 +++-
ARMRegisterInfo.h | 11 +---
2 files changed, 51 insertions(+), 30 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.72
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.73
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.72Fri Feb 23 15:53:48 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Tue Feb 27 15:12:35 2007
@@ -25,6 +25,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLocation.h"
+#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
@@ -84,6 +85,15 @@
: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
TII(tii), STI(sti),
FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) {
+ RS = new RegScavenger();
+}
+
+ARMRegisterInfo::~ARMRegisterInfo() {
+ delete RS;
+}
+
+RegScavenger *ARMRegisterInfo::getRegScavenger() const {
+ return EnableScavenging ? RS : NULL;
}
bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
@@ -328,10 +338,6 @@
return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
}
-bool ARMRegisterInfo::requiresRegisterScavenging() const {
- return EnableScavenging;
-}
-
/// emitARMRegPlusImmediate - Emits a series of instructions to materialize
/// a destreg = basereg + immediate in ARM code.
static
@@ -356,7 +362,7 @@
// Build the new ADD / SUB.
BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
- .addReg(BaseReg).addImm(SOImmVal);
+ .addReg(BaseReg, false, false, true).addImm(SOImmVal);
BaseReg = DestReg;
}
}
@@ -423,28 +429,29 @@
if (DestReg == ARM::SP) {
assert(BaseReg == ARM::SP && "Unexpected!");
LdReg = ARM::R3;
- BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3);
+ BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12)
+.addReg(ARM::R3, false, false, true);
}
if (NumBytes <= 255 && NumBytes >= 0)
BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes);
else if (NumBytes < 0 && NumBytes >= -255) {
BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes);
- BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg).addReg(LdReg);
+ BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
+.addReg(LdReg, false, false, true);
} else
emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII);
// Emit add / sub.
int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
-if (DestReg == ARM::SP)
- MIB.addReg(BaseReg).addReg(LdReg);
-else if (isSub)
- MIB.addReg(BaseReg).addReg(LdReg);
+if (DestReg == ARM::SP || isSub)
+ MIB.addReg(BaseReg).addReg(LdReg, false, false, true);
else
- MIB.addReg(LdReg).addReg(BaseReg);
+ MIB.addReg(LdReg).addReg(BaseReg, false, false, true);
if (DestReg == ARM::SP)
- BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3).addReg(ARM::R12);
+ BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3)
+.addReg(ARM::R12, false, false, true);
}
/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
@@ -510,9 +517,10 @@
unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
Bytes -= ThisVal;
BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
-.addReg(BaseReg).addImm(ThisVal);
+.addReg(BaseReg, false, false, true).addImm(ThisVal);
} else {
- BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg).addReg(BaseReg);
+ BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg)
+.addReg(BaseReg, false, false, true);
}
BaseReg = DestReg;
}
@@ -526,7 +534,9 @@
if (isTwoAddr)
BuildMI(MBB, MBBI, TII.get(Opc),
DestReg).addReg(DestReg).addImm(ThisVal);
else {
- BuildMI(MBB, MBBI, TII.get(Opc),
DestReg).addReg(BaseReg).addImm(ThisVal);
+ bool isKill = BaseReg != ARM::SP;
+ BuildMI(MBB, MBBI, TII.get(Opc), DestReg)
+.addReg(BaseReg, false, false, isKill).addImm(ThisVal);
BaseReg = DestReg;
if (Opc == ARM::tADDrSPi) {
@@ -543,7 +553,8 @@
}
if (ExtraOpc)
-BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg).addReg(DestReg)
+BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg)
+ .addReg(DestReg, false, false, true)
.addImm(((unsigned)NumBytes) & 3);
}
@@ -601,7 +612,8 @@
if (Imm > 0)
emitThumbRegPlu
[llvm-commits] CVS: llvm/lib/CodeGen/PrologEpilogInserter.cpp
Changes in directory llvm/lib/CodeGen:
PrologEpilogInserter.cpp updated: 1.70 -> 1.71
---
Log message:
Let MRegisterInfo now owns RegScavenger.
---
Diffs of the changes: (+3 -3)
PrologEpilogInserter.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp
diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.70
llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.71
--- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.70 Mon Feb 26 19:58:04 2007
+++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Tue Feb 27 15:10:33 2007
@@ -442,9 +442,10 @@
const TargetMachine &TM = Fn.getTarget();
assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!");
const MRegisterInfo &MRI = *TM.getRegisterInfo();
+ RegScavenger *RS = MRI.getRegScavenger();
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB)
{
-RegScavenger RS(BB);
+if (RS) RS->reset(BB);
for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ++I) {
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
if (I->getOperand(i).isFrameIndex()) {
@@ -454,8 +455,7 @@
break;
}
// Update register states.
- if (MRI.requiresRegisterScavenging())
-RS.forward(I);
+ if (RS) RS->forward(I);
}
}
}
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[llvm-commits] CVS: llvm/lib/CodeGen/RegisterScavenging.cpp
Changes in directory llvm/lib/CodeGen:
RegisterScavenging.cpp updated: 1.4 -> 1.5
---
Log message:
RegScavenger interface change to make it more flexible.
---
Diffs of the changes: (+18 -16)
RegisterScavenging.cpp | 34 ++
1 files changed, 18 insertions(+), 16 deletions(-)
Index: llvm/lib/CodeGen/RegisterScavenging.cpp
diff -u llvm/lib/CodeGen/RegisterScavenging.cpp:1.4
llvm/lib/CodeGen/RegisterScavenging.cpp:1.5
--- llvm/lib/CodeGen/RegisterScavenging.cpp:1.4 Mon Feb 26 19:58:04 2007
+++ llvm/lib/CodeGen/RegisterScavenging.cpp Tue Feb 27 15:09:48 2007
@@ -25,12 +25,12 @@
#include "llvm/ADT/STLExtras.h"
using namespace llvm;
-RegScavenger::RegScavenger(MachineBasicBlock *mbb)
- : MBB(mbb), MBBIInited(false) {
+void RegScavenger::init() {
const MachineFunction &MF = *MBB->getParent();
const TargetMachine &TM = MF.getTarget();
const MRegisterInfo *RegInfo = TM.getRegisterInfo();
+ MBBI = MBB->begin();
NumPhysRegs = RegInfo->getNumRegs();
RegStates.resize(NumPhysRegs, true);
@@ -50,15 +50,16 @@
for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
E = MBB->livein_end(); I != E; ++I)
setUsed(*I);
+
+ Initialized = true;
}
void RegScavenger::forward() {
assert(MBBI != MBB->end() && "Already at the end of the basic block!");
// Move ptr forward.
- if (!MBBIInited) {
-MBBI = MBB->begin();
-MBBIInited = true;
- } else
+ if (!Initialized)
+init();
+ else
MBBI = next(MBBI);
MachineInstr *MI = MBBI;
@@ -133,16 +134,6 @@
setUsed(ChangedRegs);
}
-void RegScavenger::forward(MachineBasicBlock::iterator I) {
- while (MBBI != I)
-forward();
-}
-
-void RegScavenger::backward(MachineBasicBlock::iterator I) {
- while (MBBI != I)
-backward();
-}
-
/// CreateRegClassMask - Set the bits that represent the registers in the
/// TargetRegisterClass.
static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask)
{
@@ -167,3 +158,14 @@
int Reg = RegStatesCopy.find_first();
return (Reg == -1) ? 0 : Reg;
}
+
+void RegScavenger::clear() {
+ if (MBB) {
+MBBI = MBB->end();
+MBB = NULL;
+ }
+
+ NumPhysRegs = 0;
+ Initialized = false;
+ RegStates.clear();
+}
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/RegisterScavenging.h
Changes in directory llvm/include/llvm/CodeGen:
RegisterScavenging.h updated: 1.2 -> 1.3
---
Log message:
RegScavenger interface change to make it more flexible.
---
Diffs of the changes: (+32 -4)
RegisterScavenging.h | 36
1 files changed, 32 insertions(+), 4 deletions(-)
Index: llvm/include/llvm/CodeGen/RegisterScavenging.h
diff -u llvm/include/llvm/CodeGen/RegisterScavenging.h:1.2
llvm/include/llvm/CodeGen/RegisterScavenging.h:1.3
--- llvm/include/llvm/CodeGen/RegisterScavenging.h:1.2 Mon Feb 26 19:58:48 2007
+++ llvm/include/llvm/CodeGen/RegisterScavenging.h Tue Feb 27 15:09:11 2007
@@ -27,16 +27,34 @@
class RegScavenger {
MachineBasicBlock *MBB;
MachineBasicBlock::iterator MBBI;
- bool MBBIInited;
unsigned NumPhysRegs;
+ /// Initialized - All states are initialized and ready to go!
+ bool Initialized;
+
/// RegStates - The current state of all the physical registers immediately
/// before MBBI. One bit per physical register. If bit is set that means it's
/// available, unset means the register is currently being used.
BitVector RegStates;
public:
- RegScavenger(MachineBasicBlock *mbb);
+ RegScavenger()
+: MBB(NULL), Initialized(false) {};
+
+ RegScavenger(MachineBasicBlock *mbb)
+: MBB(mbb), Initialized(false) {};
+
+ /// Init - Initialize the states.
+ ///
+ void init();
+
+ /// Reset - Discard previous states and re-initialize the states given for
+ /// the specific basic block.
+ void reset(MachineBasicBlock *mbb) {
+MBB = mbb;
+clear();
+init();
+ }
/// forward / backward - Move the internal MBB iterator and update register
/// states.
@@ -45,8 +63,12 @@
/// forward / backward - Move the internal MBB iterator and update register
/// states until it has reached but not processed the specific iterator.
- void forward(MachineBasicBlock::iterator I);
- void backward(MachineBasicBlock::iterator I);
+ void forward(MachineBasicBlock::iterator I) {
+while (MBBI != I) forward();
+ }
+ void backward(MachineBasicBlock::iterator I) {
+while (MBBI != I) backward();
+ }
/// isReserved - Returns true if a register is reserved. It is never
"unused".
bool isReserved(unsigned Reg) const { return ReservedRegs[Reg]; }
@@ -69,10 +91,16 @@
bool ExCalleeSaved = false) const;
private:
+ /// clear - Clear states.
+ ///
+ void clear();
+
/// CalleeSavedrRegs - A bitvector of callee saved registers for the target.
+ ///
BitVector CalleeSavedRegs;
/// ReservedRegs - A bitvector of reserved registers.
+ ///
BitVector ReservedRegs;
};
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.97 -> 1.98
---
Log message:
Let MRegisterInfo owns RegScavenger.
---
Diffs of the changes: (+10 -9)
MRegisterInfo.h | 19 ++-
1 files changed, 10 insertions(+), 9 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.97
llvm/include/llvm/Target/MRegisterInfo.h:1.98
--- llvm/include/llvm/Target/MRegisterInfo.h:1.97 Thu Feb 22 19:07:04 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hTue Feb 27 15:08:07 2007
@@ -23,14 +23,15 @@
namespace llvm {
-class Type;
+class BitVector;
+class CalleeSavedInfo;
class MachineFunction;
class MachineInstr;
class MachineLocation;
class MachineMove;
+class RegScavenger;
class TargetRegisterClass;
-class CalleeSavedInfo;
-class BitVector;
+class Type;
/// TargetRegisterDesc - This record contains all of the information known
about
/// a particular register. The AliasSet field (if not null) contains a pointer
@@ -213,6 +214,12 @@
virtual ~MRegisterInfo();
public:
+ /// getRegScavenger - Returns pointer to an instance of register scavenger it
+ /// the specific target is making use of one.
+ virtual RegScavenger *getRegScavenger() const {
+return NULL;
+ }
+
enum {// Define some target independent constants
/// NoRegister - This physical register is not a real target register. It
/// is useful as a sentinal.
@@ -391,12 +398,6 @@
return false;
}
- /// requiresRegisterScavenging - returns true if the target requires (and
- /// can make use of) the register scavenger.
- virtual bool requiresRegisterScavenging() const {
-return false;
- }
-
/// hasFP - Return true if the specified function should have a dedicated
frame
/// pointer register. For most targets this is true only if the function has
/// variable sized allocas or if frame pointer elimination is disabled.
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h
Changes in directory llvm/include/llvm/CodeGen:
MachineInstr.h updated: 1.213 -> 1.214
---
Log message:
Pass IsImp, IsKill, and IsDead to ChangeToRegister.
---
Diffs of the changes: (+5 -4)
MachineInstr.h |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
Index: llvm/include/llvm/CodeGen/MachineInstr.h
diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.213
llvm/include/llvm/CodeGen/MachineInstr.h:1.214
--- llvm/include/llvm/CodeGen/MachineInstr.h:1.213 Thu Feb 22 19:03:39 2007
+++ llvm/include/llvm/CodeGen/MachineInstr.hTue Feb 27 15:06:57 2007
@@ -280,13 +280,14 @@
/// ChangeToRegister - Replace this operand with a new register operand of
/// the specified value. If an operand is known to be an register already,
/// the setReg method should be used.
- void ChangeToRegister(unsigned Reg, bool isDef) {
+ void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
+bool isKill = false, bool isDead = false) {
opType = MO_Register;
contents.RegNo = Reg;
IsDef = isDef;
-IsImp = false;
-IsKill = false;
-IsDead = false;
+IsImp = isImp;
+IsKill = isKill;
+IsDead = isDead;
}
friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop)
{
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Re: [llvm-commits] CVS: llvm/lib/VMCore/Constants.cpp
Chris,
Can't we just change this part of ConstantInt:
/// getTrue/getFalse - Return the singleton true/false values.
static inline ConstantInt *getTrue() {
if (TheTrueVal) return TheTrueVal;
return CreateTrueFalseVals(true);
}
static inline ConstantInt *getFalse() {
if (TheFalseVal) return TheFalseVal;
return CreateTrueFalseVals(false);
}
into:
/// getTrue/getFalse - Return the singleton true/false values.
static inline ConstantInt *getTrue() {
return get(Type::Int1Ty, 1);
}
static inline ConstantInt *getFalse() {
return get(Type::Int1Ty, 0);
}
and get rid of all the special handling of true/false values? Or have we
provided this simply as an optimization on frequently obtained integer
values?
Reid.
On Tue, 2007-02-27 at 11:34 -0800, Reid Spencer wrote:
> On Tue, 2007-02-27 at 09:10 -0800, Chris Lattner wrote:
> > > Index: llvm/lib/VMCore/Constants.cpp
> > > diff -u llvm/lib/VMCore/Constants.cpp:1.222 llvm/lib/VMCore/
> > > Constants.cpp:1.223
> > > --- llvm/lib/VMCore/Constants.cpp:1.222 Mon Feb 26 21:05:06 2007
> > > +++ llvm/lib/VMCore/Constants.cpp Tue Feb 27 01:57:53 2007
> > > @@ -118,7 +118,7 @@
> > > if (ITy->getBitWidth() == 1)
> > >return ConstantInt::getTrue();
> > > else
> > > - return ConstantInt::get(Ty, int64_t(-1));
> > > + return ConstantInt::get(Ty, APInt::getAllOnesValue(ITy-
> > > >getBitWidth()));
> > >return 0;
> > > }
> >
> > The special case for 'i1' can be removed, right?
>
> I assumed the special case was because of this mess:
>
> > ConstantInt *ConstantInt::TheTrueVal = 0;
> > ConstantInt *ConstantInt::TheFalseVal = 0;
> >
> > namespace llvm {
> > void CleanupTrueFalse(void *) {
> > ConstantInt::ResetTrueFalse();
> > }
> > }
> >
> > static ManagedCleanup TrueFalseCleanup;
> >
> > ConstantInt *ConstantInt::CreateTrueFalseVals(bool WhichOne) {
> > assert(TheTrueVal == 0 && TheFalseVal == 0);
> > TheTrueVal = get(Type::Int1Ty, 1);
> > TheFalseVal = get(Type::Int1Ty, 0);
> >
> > // Ensure that llvm_shutdown nulls out TheTrueVal/TheFalseVal.
> > TrueFalseCleanup.Register();
> >
> > return WhichOne ? TheTrueVal : TheFalseVal;
> > }
>
> why do we need this?
>
> >
> > -Chris
>
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[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Integer/APInt/gptest.cpp
Changes in directory llvm-test/SingleSource/UnitTests/Integer/APInt:
gptest.cpp updated: 1.6 -> 1.7
---
Log message:
Adjust to changes in the APInt interface.
---
Diffs of the changes: (+7 -3)
gptest.cpp | 10 +++---
1 files changed, 7 insertions(+), 3 deletions(-)
Index: llvm-test/SingleSource/UnitTests/Integer/APInt/gptest.cpp
diff -u llvm-test/SingleSource/UnitTests/Integer/APInt/gptest.cpp:1.6
llvm-test/SingleSource/UnitTests/Integer/APInt/gptest.cpp:1.7
--- llvm-test/SingleSource/UnitTests/Integer/APInt/gptest.cpp:1.6 Tue Feb
27 11:58:33 2007
+++ llvm-test/SingleSource/UnitTests/Integer/APInt/gptest.cpp Tue Feb 27
14:48:20 2007
@@ -23,7 +23,11 @@
static int input = 0, output = 0;
void print(const APInt& X, bool wantSigned = false, bool withNL = true) {
- std::string decstr = X.toString(10,wantSigned);
+ std::string decstr;
+ if (wantSigned)
+decstr = X.toStringSigned(10);
+ else
+decstr = X.toString(10);
printf("%s", decstr.c_str());
if (withNL)
printf("\n");
@@ -367,8 +371,8 @@
APInt one(bits,1);
APInt two(bits,2);
APInt three(bits,3);
-APInt min = APInt::getMinValue(bits, true);
-APInt max = APInt::getMaxValue(bits, true);
+APInt min = APInt::getSignedMinValue(bits);
+APInt max = APInt::getSignedMaxValue(bits);
APInt mid = APIntOps::lshr(max, bits/2);
APInt r1 = randomAPInt(bits);
APInt r2 = randomAPInt(bits);
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[llvm-commits] CVS: llvm/test/CodeGen/PowerPC/calls.ll
Changes in directory llvm/test/CodeGen/PowerPC: calls.ll updated: 1.4 -> 1.5 --- Log message: This test passes on x86/Linux now. --- Diffs of the changes: (+0 -1) calls.ll |1 - 1 files changed, 1 deletion(-) Index: llvm/test/CodeGen/PowerPC/calls.ll diff -u llvm/test/CodeGen/PowerPC/calls.ll:1.4 llvm/test/CodeGen/PowerPC/calls.ll:1.5 --- llvm/test/CodeGen/PowerPC/calls.ll:1.4 Mon Feb 26 20:45:12 2007 +++ llvm/test/CodeGen/PowerPC/calls.ll Tue Feb 27 14:46:44 2007 @@ -3,7 +3,6 @@ ; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep 'bl ' | wc -l | grep 2 && ; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep 'bctrl' | wc -l | grep 1 && ; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep 'bla ' | wc -l | grep 1 -; XFAIL: [0-9x]86-pc-linux.* declare void %foo() ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetCallingConv.td
Changes in directory llvm/lib/Target:
TargetCallingConv.td updated: 1.1 -> 1.2
---
Log message:
implement CCMatchIfCC in terms of CCMatchIf
---
Diffs of the changes: (+4 -4)
TargetCallingConv.td |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/TargetCallingConv.td
diff -u llvm/lib/Target/TargetCallingConv.td:1.1
llvm/lib/Target/TargetCallingConv.td:1.2
--- llvm/lib/Target/TargetCallingConv.td:1.1Mon Feb 26 23:57:32 2007
+++ llvm/lib/Target/TargetCallingConv.tdTue Feb 27 14:45:02 2007
@@ -23,7 +23,8 @@
/// CCMatchType - If the current argument is one of the specified types, apply
/// Action A.
-class CCMatchType VTs, CCAction A> : CCPredicateAction {
+class CCMatchType vts, CCAction A> : CCPredicateAction {
+ list VTs = vts;
}
/// CCMatchIf - If the predicate matches, apply A.
@@ -32,9 +33,8 @@
}
/// CCMatchIfCC - Match of the current calling convention is 'CC'.
-class CCMatchIfCC : CCPredicateAction {
- string CallingConv = CC;
-}
+class CCMatchIfCC
+ : CCMatchIf {}
/// CCAssignToReg - This action matches if there is a register in the specified
/// list that is still available. If so, it assigns the value to the first
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[llvm-commits] CVS: llvm/lib/Target/X86/Makefile
Changes in directory llvm/lib/Target/X86: Makefile updated: 1.31 -> 1.32 --- Log message: build cc info --- Diffs of the changes: (+1 -1) Makefile |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/Makefile diff -u llvm/lib/Target/X86/Makefile:1.31 llvm/lib/Target/X86/Makefile:1.32 --- llvm/lib/Target/X86/Makefile:1.31 Fri Oct 27 19:48:27 2006 +++ llvm/lib/Target/X86/MakefileTue Feb 27 14:44:31 2007 @@ -15,6 +15,6 @@ X86GenRegisterInfo.inc X86GenInstrNames.inc \ X86GenInstrInfo.inc X86GenAsmWriter.inc \ X86GenAsmWriter1.inc X86GenDAGISel.inc \ -X86GenSubtarget.inc +X86GenCallingConv.inc X86GenSubtarget.inc include $(LEVEL)/Makefile.common ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/Makefile.rules
Changes in directory llvm: Makefile.rules updated: 1.426 -> 1.427 --- Log message: target for generating CC info --- Diffs of the changes: (+5 -0) Makefile.rules |5 + 1 files changed, 5 insertions(+) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.426 llvm/Makefile.rules:1.427 --- llvm/Makefile.rules:1.426 Fri Feb 9 11:09:14 2007 +++ llvm/Makefile.rules Tue Feb 27 14:44:12 2007 @@ -1275,6 +1275,11 @@ $(Echo) "Building $(http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp Record.cpp Record.h TableGen.cpp
Changes in directory llvm/utils/TableGen:
CodeGenTarget.cpp updated: 1.82 -> 1.83
Record.cpp updated: 1.55 -> 1.56
Record.h updated: 1.59 -> 1.60
TableGen.cpp updated: 1.47 -> 1.48
---
Log message:
initial support for calling convention generation, still unfinished.
---
Diffs of the changes: (+18 -7)
CodeGenTarget.cpp |8 ++--
Record.cpp|7 +++
Record.h |2 ++
TableGen.cpp |8 +++-
4 files changed, 18 insertions(+), 7 deletions(-)
Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.82
llvm/utils/TableGen/CodeGenTarget.cpp:1.83
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.82 Fri Jan 26 11:29:20 2007
+++ llvm/utils/TableGen/CodeGenTarget.cpp Tue Feb 27 14:43:37 2007
@@ -604,9 +604,7 @@
// Parse the list of argument types.
ListInit *TypeList = R->getValueAsListInit("Types");
for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
-DefInit *DI = dynamic_cast(TypeList->getElement(i));
-assert(DI && "Invalid list type!");
-Record *TyEl = DI->getDef();
+Record *TyEl = TypeList->getElementAsRecord(i);
assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
ArgTypes.push_back(TyEl->getValueAsString("TypeVal"));
@@ -620,9 +618,7 @@
// Parse the intrinsic properties.
ListInit *PropList = R->getValueAsListInit("Properties");
for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) {
-DefInit *DI = dynamic_cast(PropList->getElement(i));
-assert(DI && "Invalid list type!");
-Record *Property = DI->getDef();
+Record *Property = PropList->getElementAsRecord(i);
assert(Property->isSubClassOf("IntrinsicProperty") &&
"Expected a property!");
Index: llvm/utils/TableGen/Record.cpp
diff -u llvm/utils/TableGen/Record.cpp:1.55 llvm/utils/TableGen/Record.cpp:1.56
--- llvm/utils/TableGen/Record.cpp:1.55 Thu Dec 7 16:21:48 2006
+++ llvm/utils/TableGen/Record.cpp Tue Feb 27 14:43:37 2007
@@ -337,6 +337,13 @@
return new ListInit(Vals);
}
+Record *ListInit::getElementAsRecord(unsigned i) const {
+ assert(i < Values.size() && "List element index out of range!");
+ DefInit *DI = dynamic_cast(Values[i]);
+ if (DI == 0) throw "Expected record in list!";
+ return DI->getDef();
+}
+
Init *ListInit::resolveReferences(Record &R, const RecordVal *RV) {
std::vector Resolved;
Resolved.reserve(getSize());
Index: llvm/utils/TableGen/Record.h
diff -u llvm/utils/TableGen/Record.h:1.59 llvm/utils/TableGen/Record.h:1.60
--- llvm/utils/TableGen/Record.h:1.59 Thu Dec 7 16:21:48 2006
+++ llvm/utils/TableGen/Record.hTue Feb 27 14:43:37 2007
@@ -626,6 +626,8 @@
return Values[i];
}
+ Record *getElementAsRecord(unsigned i) const;
+
Init *convertInitListSlice(const std::vector &Elements);
virtual Init *convertInitializerTo(RecTy *Ty) {
Index: llvm/utils/TableGen/TableGen.cpp
diff -u llvm/utils/TableGen/TableGen.cpp:1.47
llvm/utils/TableGen/TableGen.cpp:1.48
--- llvm/utils/TableGen/TableGen.cpp:1.47 Thu Dec 7 16:21:48 2006
+++ llvm/utils/TableGen/TableGen.cppTue Feb 27 14:43:37 2007
@@ -20,6 +20,7 @@
#include "llvm/Support/Streams.h"
#include "llvm/System/Signals.h"
#include "llvm/Support/FileUtilities.h"
+#include "CallingConvEmitter.h"
#include "CodeEmitterGen.h"
#include "RegisterInfoEmitter.h"
#include "InstrInfoEmitter.h"
@@ -38,6 +39,7 @@
GenEmitter,
GenRegisterEnums, GenRegister, GenRegisterHeader,
GenInstrEnums, GenInstrs, GenAsmWriter,
+ GenCallingConv,
GenDAGISel,
GenSubtarget,
GenIntrinsic,
@@ -61,6 +63,8 @@
"Generate enum values for instructions"),
clEnumValN(GenInstrs, "gen-instr-desc",
"Generate instruction descriptions"),
+clEnumValN(GenCallingConv, "gen-callingconv",
+ "Generate calling convention descriptions"),
clEnumValN(GenAsmWriter, "gen-asm-writer",
"Generate assembly writer"),
clEnumValN(GenDAGISel, "gen-dag-isel",
@@ -138,7 +142,9 @@
case GenInstrs:
InstrInfoEmitter(Records).run(*Out);
break;
-
+case GenCallingConv:
+ CallingConvEmitter(Records).run(*Out);
+ break;
case GenAsmWriter:
AsmWriterEmitter(Records).run(*Out);
break;
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[llvm-commits] CVS: llvm/lib/VMCore/AsmWriter.cpp ConstantFold.cpp
Changes in directory llvm/lib/VMCore:
AsmWriter.cpp updated: 1.262 -> 1.263
ConstantFold.cpp updated: 1.141 -> 1.142
---
Log message:
Adjust to changes in the APInt interface.
---
Diffs of the changes: (+5 -5)
AsmWriter.cpp|2 +-
ConstantFold.cpp |8
2 files changed, 5 insertions(+), 5 deletions(-)
Index: llvm/lib/VMCore/AsmWriter.cpp
diff -u llvm/lib/VMCore/AsmWriter.cpp:1.262 llvm/lib/VMCore/AsmWriter.cpp:1.263
--- llvm/lib/VMCore/AsmWriter.cpp:1.262 Tue Feb 27 02:34:09 2007
+++ llvm/lib/VMCore/AsmWriter.cpp Tue Feb 27 14:25:25 2007
@@ -464,7 +464,7 @@
if (CI->getType() == Type::Int1Ty)
Out << (CI->getZExtValue() ? "true" : "false");
else
- Out << CI->getValue().toString(10,/*wantSigned=*/true);
+ Out << CI->getValue().toStringSigned(10);
} else if (const ConstantFP *CFP = dyn_cast(CV)) {
// We would like to output the FP constant value in exponential notation,
// but we cannot do this if doing so will lose precision. Check here to
Index: llvm/lib/VMCore/ConstantFold.cpp
diff -u llvm/lib/VMCore/ConstantFold.cpp:1.141
llvm/lib/VMCore/ConstantFold.cpp:1.142
--- llvm/lib/VMCore/ConstantFold.cpp:1.141 Tue Feb 27 13:29:54 2007
+++ llvm/lib/VMCore/ConstantFold.cppTue Feb 27 14:25:25 2007
@@ -198,13 +198,13 @@
return 0; // Other pointer types cannot be casted
case Instruction::UIToFP:
if (const ConstantInt *CI = dyn_cast(V))
- if (CI->getType()->getBitWidth() <= APInt::APINT_BITS_PER_WORD)
-return ConstantFP::get(DestTy, CI->getValue().roundToDouble(false));
+ if (CI->getType()->getBitWidth() <= 64)
+return ConstantFP::get(DestTy, CI->getValue().roundToDouble());
return 0;
case Instruction::SIToFP:
if (const ConstantInt *CI = dyn_cast(V))
- if (CI->getType()->getBitWidth() <= APInt::APINT_BITS_PER_WORD)
-return ConstantFP::get(DestTy, CI->getValue().roundToDouble(true));
+ if (CI->getType()->getBitWidth() <= 64)
+return ConstantFP::get(DestTy, CI->getValue().signedRoundToDouble());
return 0;
case Instruction::ZExt:
if (const ConstantInt *CI = dyn_cast(V)) {
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[llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
Changes in directory llvm/include/llvm/ADT:
APInt.h updated: 1.25 -> 1.26
---
Log message:
Improve APInt interface:
1. Add unsigned and signed versions of methods so a "bool" argument doesn't
need to be passed in.
2. Make the various getMin/getMax functions all be inline since they are
so simple.
3. Simplify sdiv and srem code.
---
Diffs of the changes: (+67 -22)
APInt.h | 89
1 files changed, 67 insertions(+), 22 deletions(-)
Index: llvm/include/llvm/ADT/APInt.h
diff -u llvm/include/llvm/ADT/APInt.h:1.25 llvm/include/llvm/ADT/APInt.h:1.26
--- llvm/include/llvm/ADT/APInt.h:1.25 Tue Feb 27 12:22:31 2007
+++ llvm/include/llvm/ADT/APInt.h Tue Feb 27 14:24:31 2007
@@ -59,7 +59,6 @@
///
/// @brief Class for arbitrary precision integers.
class APInt {
-public:
uint32_t BitWidth; ///< The number of bits in this APInt.
@@ -374,8 +373,8 @@
/// Signed divide this APInt by APInt RHS.
/// @brief Signed division function for APInt.
inline APInt sdiv(const APInt& RHS) const {
-bool isNegativeLHS = (*this)[BitWidth - 1];
-bool isNegativeRHS = RHS[RHS.BitWidth - 1];
+bool isNegativeLHS = isNegative();
+bool isNegativeRHS = RHS.isNegative();
APInt Result = APIntOps::udiv(
isNegativeLHS ? -(*this) : (*this), isNegativeRHS ? -RHS : RHS);
return isNegativeLHS != isNegativeRHS ? -Result : Result;
@@ -388,8 +387,8 @@
/// Signed remainder operation on APInt.
/// @brief Function for signed remainder operation.
inline APInt srem(const APInt& RHS) const {
-bool isNegativeLHS = (*this)[BitWidth - 1];
-bool isNegativeRHS = RHS[RHS.BitWidth - 1];
+bool isNegativeLHS = isNegative();
+bool isNegativeRHS = RHS.isNegative();
APInt Result = APIntOps::urem(
isNegativeLHS ? -(*this) : (*this), isNegativeRHS ? -RHS : RHS);
return isNegativeLHS ? -Result : Result;
@@ -470,24 +469,37 @@
return int64_t(pVal[0]);
}
- /// @returns the largest value for an APInt of the specified bit-width and
- /// if isSign == true, it should be largest signed value, otherwise largest
- /// unsigned value.
- /// @brief Gets max value of the APInt with bitwidth <= 64.
- static APInt getMaxValue(uint32_t numBits, bool isSigned);
-
- /// @returns the smallest value for an APInt of the given bit-width and
- /// if isSign == true, it should be smallest signed value, otherwise zero.
- /// @brief Gets min value of the APInt with bitwidth <= 64.
- static APInt getMinValue(uint32_t numBits, bool isSigned);
+ /// @brief Gets maximum unsigned value of APInt for specific bit width.
+ static APInt getMaxValue(uint32_t numBits) {
+return APInt(numBits, 0).set();
+ }
+
+ /// @brief Gets maximum signed value of APInt for a specific bit width.
+ static APInt getSignedMaxValue(uint32_t numBits) {
+return APInt(numBits, 0).set().clear(numBits - 1);
+ }
+
+ /// @brief Gets minimum unsigned value of APInt for a specific bit width.
+ static APInt getMinValue(uint32_t numBits) {
+return APInt(numBits, 0);
+ }
+
+ /// @brief Gets minimum signed value of APInt for a specific bit width.
+ static APInt getSignedMinValue(uint32_t numBits) {
+return APInt(numBits, 0).set(numBits - 1);
+ }
/// @returns the all-ones value for an APInt of the specified bit-width.
/// @brief Get the all-ones value.
- static APInt getAllOnesValue(uint32_t numBits);
+ static APInt getAllOnesValue(uint32_t numBits) {
+return APInt(numBits, 0).set();
+ }
/// @returns the '0' value for an APInt of the specified bit-width.
/// @brief Get the '0' value.
- static APInt getNullValue(uint32_t numBits);
+ static APInt getNullValue(uint32_t numBits) {
+return APInt(numBits, 0);
+ }
/// The hash value is computed as the sum of the words and the bit width.
/// @returns A hash value computed from the sum of the APInt words.
@@ -536,8 +548,25 @@
isNegative() && countPopulation() == 1;
}
- /// @returns a character interpretation of the APInt.
- std::string toString(uint8_t radix = 10, bool wantSigned = true) const;
+ /// This is used internally to convert an APInt to a string.
+ /// @brief Converts an APInt to a std::string
+ std::string toString(uint8_t radix, bool wantSigned) const;
+
+ /// Considers the APInt to be unsigned and converts it into a string in the
+ /// radix given. The radix can be 2, 8, 10 or 16.
+ /// @returns a character interpretation of the APInt
+ /// @brief Convert unsigned APInt to string representation.
+ inline std::string toString(uint8_t radix = 10) const {
+return toString(radix, false);
+ }
+
+ /// Considers the APInt to be unsigned and converts it into a string in the
+ /// radix given. The radix can be 2, 8, 10 or 16.
+ /// @returns a character interpretation of the APInt
+ /// @brief Convert unsigned APInt to string representation.
+ inline std::string toStringSigned(ui
[llvm-commits] CVS: llvm/lib/Support/APInt.cpp
Changes in directory llvm/lib/Support:
APInt.cpp updated: 1.54 -> 1.55
---
Log message:
Improve APInt interface:
1. Add unsigned and signed versions of methods so a "bool" argument doesn't
need to be passed in.
2. Make the various getMin/getMax functions all be inline since they are
so simple.
3. Simplify sdiv and srem code.
---
Diffs of the changes: (+1 -34)
APInt.cpp | 35 +--
1 files changed, 1 insertion(+), 34 deletions(-)
Index: llvm/lib/Support/APInt.cpp
diff -u llvm/lib/Support/APInt.cpp:1.54 llvm/lib/Support/APInt.cpp:1.55
--- llvm/lib/Support/APInt.cpp:1.54 Tue Feb 27 13:31:09 2007
+++ llvm/lib/Support/APInt.cpp Tue Feb 27 14:24:31 2007
@@ -654,39 +654,6 @@
return *this;
}
-/// getMaxValue - This function returns the largest value
-/// for an APInt of the specified bit-width and if isSign == true,
-/// it should be largest signed value, otherwise unsigned value.
-APInt APInt::getMaxValue(uint32_t numBits, bool isSign) {
- APInt Result(numBits, 0);
- Result.set();
- if (isSign)
-Result.clear(numBits - 1);
- return Result;
-}
-
-/// getMinValue - This function returns the smallest value for
-/// an APInt of the given bit-width and if isSign == true,
-/// it should be smallest signed value, otherwise zero.
-APInt APInt::getMinValue(uint32_t numBits, bool isSign) {
- APInt Result(numBits, 0);
- if (isSign)
-Result.set(numBits - 1);
- return Result;
-}
-
-/// getAllOnesValue - This function returns an all-ones value for
-/// an APInt of the specified bit-width.
-APInt APInt::getAllOnesValue(uint32_t numBits) {
- return getMaxValue(numBits, false);
-}
-
-/// getNullValue - This function creates an '0' value for an
-/// APInt of the specified bit-width.
-APInt APInt::getNullValue(uint32_t numBits) {
- return getMinValue(numBits, false);
-}
-
uint64_t APInt::getHashValue() const {
// Put the bit width into the low order bits.
uint64_t hash = BitWidth;
@@ -1734,6 +1701,6 @@
else for (unsigned i = getNumWords(); i > 0; i--) {
cerr << pVal[i-1] << " ";
}
- cerr << " (" << this->toString(10, false) << ")\n" << std::setbase(10);
+ cerr << " (" << this->toString(10) << ")\n" << std::setbase(10);
}
#endif
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[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Integer/APInt/arith.cpp
Changes in directory llvm-test/SingleSource/UnitTests/Integer/APInt:
arith.cpp updated: 1.11 -> 1.12
---
Log message:
Update for changes in APInt interface.
---
Diffs of the changes: (+30 -24)
arith.cpp | 54 ++
1 files changed, 30 insertions(+), 24 deletions(-)
Index: llvm-test/SingleSource/UnitTests/Integer/APInt/arith.cpp
diff -u llvm-test/SingleSource/UnitTests/Integer/APInt/arith.cpp:1.11
llvm-test/SingleSource/UnitTests/Integer/APInt/arith.cpp:1.12
--- llvm-test/SingleSource/UnitTests/Integer/APInt/arith.cpp:1.11 Tue Feb
20 14:39:34 2007
+++ llvm-test/SingleSource/UnitTests/Integer/APInt/arith.cppTue Feb 27
14:13:37 2007
@@ -10,6 +10,8 @@
//===--===//
#include "llvm/ADT/APInt.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/ManagedStatic.h"
#include
#include
@@ -19,8 +21,12 @@
APInt y(21, 0x0f);
void print(const APInt& X, bool wantSigned = false, bool withNL = true) {
- std::string decstr = X.toString(10,wantSigned);
- std::string hexstr = X.toString(16,false);
+ std::string decstr;
+ if (wantSigned)
+decstr = X.toStringSigned(10);
+ else
+decstr = X.toString(10);
+ std::string hexstr = X.toString(16);
printf("%s (%s)", decstr.c_str(), hexstr.c_str());
if (withNL)
printf("\n");
@@ -41,10 +47,10 @@
unsigned bitwidth = val.getBitWidth();
unsigned pos = rand() % bitwidth;
printf("val[%u] = %d\n", pos, val[pos]);
- APInt smax(APInt::getMaxValue(bitwidth, true));
- APInt umax(APInt::getMaxValue(bitwidth, false));
- APInt smin(APInt::getMinValue(bitwidth, true));
- APInt umin(APInt::getMinValue(bitwidth, false));
+ APInt smax(APInt::getSignedMaxValue(bitwidth));
+ APInt umax(APInt::getMaxValue(bitwidth));
+ APInt smin(APInt::getSignedMinValue(bitwidth));
+ APInt umin(APInt::getMinValue(bitwidth));
printf("APInt::getMinValue(%d, true) = ", bitwidth); print(smin,true);
printf("APInt::getMaxValue(%d, true) = ", bitwidth); print(smax,true);
printf("APInt::getMinValue(%d, false) = ", bitwidth); print(umin);
@@ -104,13 +110,15 @@
x = val.byteSwap();
printf("val.byteSwap() = "); print(x);
}
- printf("val.roundToDouble(false) = %f\n", val.roundToDouble(false));
- printf("val.roundToDouble(true) = %f\n", val.roundToDouble(true));
+ printf("val.roundToDouble() = %f\n", val.roundToDouble());
+ printf("val.signedRoundToDouble() = %f\n", val.signedRoundToDouble());
printf("val.getValue() = ");
if (val.getBitWidth() > 64)
printf("too wide\n");
- else
-printf("%lu\n", val.getValue());
+ else {
+printf("%lu\n", val.getZExtValue());
+printf("%ld\n", val.getSExtValue());
+ }
}
void test_binops(const APInt &v1, const APInt &v2) {
@@ -184,7 +192,7 @@
void test_multiple() {
srand(0);
- for (unsigned bits = 1; bits <= 256; ++bits) {
+ for (unsigned bits = 257; bits <= 257; ++bits) {
printf("\nTEST CASE: %d BITS\n\n", bits);
APInt zero(bits,0);
APInt one(bits,1);
@@ -199,12 +207,13 @@
}
APInt two(bits,1);
APInt three(bits,1);
-APInt min = APInt::getMinValue(bits, true);
-APInt max = APInt::getMaxValue(bits, true);
+APInt min = APInt::getSignedMinValue(bits);
+APInt max = APInt::getSignedMaxValue(bits);
APInt mid = APIntOps::lshr(max, bits/2);
APInt r1 = randomAPInt(bits);
APInt r2 = randomAPInt(bits);
-APInt *list[9];
+APInt r3 = randomAPInt(bits);
+APInt *list[10];
list[0] = &zero;
list[1] = &one;
list[2] = &two;
@@ -214,26 +223,23 @@
list[6] = ∣
list[7] = &r2;
list[8] = &max;
-for (unsigned i = 0; i < 9; ++i) {
+list[9] = &r3;
+for (unsigned i = 0; i < 10; ++i) {
test_interface(*(list[i]));
test_unops(*(list[i]));
}
-for (unsigned i = 0; i < 9; ++i) {
- for (unsigned j = 0; j < 9; ++j) {
+for (unsigned i = 0; i < 10; ++i) {
+ for (unsigned j = 0; j < 10; ++j) {
test_binops(*(list[i]), *(list[j]));
}
}
}
}
-int main()
+int main(int argc, char** argv)
{
- APInt X(48, 100);
- APInt Y(48, 10);
- APInt Q(1,0);
- APInt R(1,0);
- APInt::divide(X, 1, Y, 1, &Q, &R);
+ cl::ParseCommandLineOptions(argc, argv, "APInt arithmetic test\n");
test_multiple();
+ llvm_shutdown();
return 0;
}
-
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Re: [llvm-commits] CVS: llvm/lib/VMCore/Constants.cpp
On Tue, 2007-02-27 at 09:10 -0800, Chris Lattner wrote:
> > Index: llvm/lib/VMCore/Constants.cpp
> > diff -u llvm/lib/VMCore/Constants.cpp:1.222 llvm/lib/VMCore/
> > Constants.cpp:1.223
> > --- llvm/lib/VMCore/Constants.cpp:1.222 Mon Feb 26 21:05:06 2007
> > +++ llvm/lib/VMCore/Constants.cpp Tue Feb 27 01:57:53 2007
> > @@ -118,7 +118,7 @@
> > if (ITy->getBitWidth() == 1)
> >return ConstantInt::getTrue();
> > else
> > - return ConstantInt::get(Ty, int64_t(-1));
> > + return ConstantInt::get(Ty, APInt::getAllOnesValue(ITy-
> > >getBitWidth()));
> >return 0;
> > }
>
> The special case for 'i1' can be removed, right?
I assumed the special case was because of this mess:
> ConstantInt *ConstantInt::TheTrueVal = 0;
> ConstantInt *ConstantInt::TheFalseVal = 0;
>
> namespace llvm {
> void CleanupTrueFalse(void *) {
> ConstantInt::ResetTrueFalse();
> }
> }
>
> static ManagedCleanup TrueFalseCleanup;
>
> ConstantInt *ConstantInt::CreateTrueFalseVals(bool WhichOne) {
> assert(TheTrueVal == 0 && TheFalseVal == 0);
> TheTrueVal = get(Type::Int1Ty, 1);
> TheFalseVal = get(Type::Int1Ty, 0);
>
> // Ensure that llvm_shutdown nulls out TheTrueVal/TheFalseVal.
> TrueFalseCleanup.Register();
>
> return WhichOne ? TheTrueVal : TheFalseVal;
> }
why do we need this?
>
> -Chris
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[llvm-commits] CVS: llvm/lib/Support/APInt.cpp
Changes in directory llvm/lib/Support: APInt.cpp updated: 1.53 -> 1.54 --- Log message: Conform to single person attribution in file comment. --- Diffs of the changes: (+2 -3) APInt.cpp |5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) Index: llvm/lib/Support/APInt.cpp diff -u llvm/lib/Support/APInt.cpp:1.53 llvm/lib/Support/APInt.cpp:1.54 --- llvm/lib/Support/APInt.cpp:1.53 Tue Feb 27 12:23:40 2007 +++ llvm/lib/Support/APInt.cpp Tue Feb 27 13:31:09 2007 @@ -2,9 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by Sheng Zhou and Reid Spencer and is distributed -// under the University of Illinois Open Source License. See LICENSE.TXT -// for details. +// This file was developed by Sheng Zhou and is distributed under the +// University of Illinois Open Source License. See LICENSE.TXT for details. // //===--===// // ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/VMCore/ConstantFold.cpp
Changes in directory llvm/lib/VMCore:
ConstantFold.cpp updated: 1.140 -> 1.141
---
Log message:
For PR1205: http://llvm.org/PR1205 :
Implement review feedback:
1. Use new APInt::RoundDoubleToAPInt interface to specify the bit width so
that we don't have to truncate or extend in constant folding.
2. Fix a pasteo in SDiv that prevented a check for overflow.
3. Fix the shift operators: undef happens when the shift amount is equal
to the bitwidth.
---
Diffs of the changes: (+5 -14)
ConstantFold.cpp | 19 +--
1 files changed, 5 insertions(+), 14 deletions(-)
Index: llvm/lib/VMCore/ConstantFold.cpp
diff -u llvm/lib/VMCore/ConstantFold.cpp:1.140
llvm/lib/VMCore/ConstantFold.cpp:1.141
--- llvm/lib/VMCore/ConstantFold.cpp:1.140 Tue Feb 27 00:23:51 2007
+++ llvm/lib/VMCore/ConstantFold.cppTue Feb 27 13:29:54 2007
@@ -176,23 +176,15 @@
return 0; // Can't fold.
case Instruction::FPToUI:
if (const ConstantFP *FPC = dyn_cast(V)) {
- APInt Val(APIntOps::RoundDoubleToAPInt(FPC->getValue()));
uint32_t DestBitWidth = cast(DestTy)->getBitWidth();
- if (Val.getBitWidth() > DestBitWidth)
-Val.trunc(DestBitWidth);
- else if (Val.getBitWidth() < DestBitWidth)
-Val.zext(DestBitWidth);
+ APInt Val(APIntOps::RoundDoubleToAPInt(FPC->getValue(), DestBitWidth));
return ConstantInt::get(DestTy, Val);
}
return 0; // Can't fold.
case Instruction::FPToSI:
if (const ConstantFP *FPC = dyn_cast(V)) {
- APInt Val(APIntOps::RoundDoubleToAPInt(FPC->getValue()));
uint32_t DestBitWidth = cast(DestTy)->getBitWidth();
- if (Val.getBitWidth() > DestBitWidth)
-Val.trunc(DestBitWidth);
- else if (Val.getBitWidth() < DestBitWidth)
-Val.sext(DestBitWidth);
+ APInt Val(APIntOps::RoundDoubleToAPInt(FPC->getValue(), DestBitWidth));
return ConstantInt::get(DestTy, Val);
}
return 0; // Can't fold.
@@ -604,7 +596,6 @@
case Instruction::SDiv:
if (CI2->isNullValue())
return 0;// X / 0 -> can't fold
-return ConstantInt::get(C1->getType(), C1V.sdiv(C2V));
if (C2V.isAllOnesValue() && C1V.isMinSignedValue())
return 0;// MIN_INT / -1 -> overflow
return ConstantInt::get(C1->getType(), C1V.sdiv(C2V));
@@ -626,21 +617,21 @@
return ConstantInt::get(C1->getType(), C1V ^ C2V);
case Instruction::Shl:
if (uint32_t shiftAmt = C2V.getZExtValue())
- if (shiftAmt <= C1V.getBitWidth())
+ if (shiftAmt < C1V.getBitWidth())
return ConstantInt::get(C1->getType(), C1V.shl(shiftAmt));
else
return UndefValue::get(C1->getType()); // too big shift is undef
return const_cast(CI1); // Zero shift is identity
case Instruction::LShr:
if (uint32_t shiftAmt = C2V.getZExtValue())
- if (shiftAmt <= C1V.getBitWidth())
+ if (shiftAmt < C1V.getBitWidth())
return ConstantInt::get(C1->getType(), C1V.lshr(shiftAmt));
else
return UndefValue::get(C1->getType()); // too big shift is undef
return const_cast(CI1); // Zero shift is identity
case Instruction::AShr:
if (uint32_t shiftAmt = C2V.getZExtValue())
- if (shiftAmt <= C1V.getBitWidth())
+ if (shiftAmt < C1V.getBitWidth())
return ConstantInt::get(C1->getType(), C1V.ashr(shiftAmt));
else
return UndefValue::get(C1->getType()); // too big shift is undef
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[llvm-commits] CVS: llvm/test/Integer/a1.ll a1.ll.out
Changes in directory llvm/test/Integer: a1.ll updated: 1.5 -> 1.6 a1.ll.out updated: 1.4 -> 1.5 --- Log message: Update for constant folding now generating undef and overflow correctly. --- Diffs of the changes: (+8 -8) a1.ll |6 +++--- a1.ll.out | 10 +- 2 files changed, 8 insertions(+), 8 deletions(-) Index: llvm/test/Integer/a1.ll diff -u llvm/test/Integer/a1.ll:1.5 llvm/test/Integer/a1.ll:1.6 --- llvm/test/Integer/a1.ll:1.5 Mon Feb 26 20:34:02 2007 +++ llvm/test/Integer/a1.ll Tue Feb 27 13:26:40 2007 @@ -10,14 +10,14 @@ @f = constant i1 sub(i1 1 , i1 -1) @g = constant i1 sub(i1 1 , i1 1) [EMAIL PROTECTED] = constant i1 shl(i1 1 , i1 1) [EMAIL PROTECTED] = constant i1 shl(i1 1 , i1 1) ; undefined @i = constant i1 shl(i1 1 , i1 0) @j = constant i1 lshr(i1 1, i1 1) ; undefined @m = constant i1 ashr(i1 1, i1 1) ; undefined @n = constant i1 mul(i1 -1, i1 1) [EMAIL PROTECTED] = constant i1 sdiv(i1 -1, i1 1) [EMAIL PROTECTED] = constant i1 sdiv(i1 1 , i1 -1) [EMAIL PROTECTED] = constant i1 sdiv(i1 -1, i1 1) ; overflow [EMAIL PROTECTED] = constant i1 sdiv(i1 1 , i1 -1); overflow @q = constant i1 udiv(i1 -1, i1 1) @r = constant i1 udiv(i1 1, i1 -1) @s = constant i1 srem(i1 -1, i1 1) ; overflow Index: llvm/test/Integer/a1.ll.out diff -u llvm/test/Integer/a1.ll.out:1.4 llvm/test/Integer/a1.ll.out:1.5 --- llvm/test/Integer/a1.ll.out:1.4 Mon Feb 26 20:34:02 2007 +++ llvm/test/Integer/a1.ll.out Tue Feb 27 13:26:40 2007 @@ -5,13 +5,13 @@ @e = constant i1 false ; [#uses=0] @f = constant i1 false ; [#uses=0] @g = constant i1 false ; [#uses=0] [EMAIL PROTECTED] = constant i1 false ; [#uses=0] [EMAIL PROTECTED] = constant i1 undef ; [#uses=0] @i = constant i1 true ; [#uses=0] [EMAIL PROTECTED] = constant i1 false ; [#uses=0] [EMAIL PROTECTED] = constant i1 false ; [#uses=0] [EMAIL PROTECTED] = constant i1 undef ; [#uses=0] [EMAIL PROTECTED] = constant i1 undef ; [#uses=0] @n = constant i1 true ; [#uses=0] [EMAIL PROTECTED] = constant i1 true; [#uses=0] [EMAIL PROTECTED] = constant i1 true; [#uses=0] [EMAIL PROTECTED] = constant i1 sdiv (i1 true, i1 true) ; [#uses=0] [EMAIL PROTECTED] = constant i1 sdiv (i1 true, i1 true) ; [#uses=0] @q = constant i1 true ; [#uses=0] @r = constant i1 true ; [#uses=0] @s = constant i1 srem (i1 true, i1 true) ; [#uses=0] ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Integer/a15.ll.out a17.ll.out a31.ll.out a33.ll.out a63.ll.out a7.ll.out a9.ll.out
Changes in directory llvm/test/Integer: a15.ll.out updated: 1.4 -> 1.5 a17.ll.out updated: 1.4 -> 1.5 a31.ll.out updated: 1.4 -> 1.5 a33.ll.out updated: 1.4 -> 1.5 a63.ll.out updated: 1.4 -> 1.5 a7.ll.out updated: 1.5 -> 1.6 a9.ll.out updated: 1.4 -> 1.5 --- Log message: Shifting by the bit width now produces undef, not 0. --- Diffs of the changes: (+7 -7) a15.ll.out |2 +- a17.ll.out |2 +- a31.ll.out |2 +- a33.ll.out |2 +- a63.ll.out |2 +- a7.ll.out |2 +- a9.ll.out |2 +- 7 files changed, 7 insertions(+), 7 deletions(-) Index: llvm/test/Integer/a15.ll.out diff -u llvm/test/Integer/a15.ll.out:1.4 llvm/test/Integer/a15.ll.out:1.5 --- llvm/test/Integer/a15.ll.out:1.4Mon Feb 26 20:34:02 2007 +++ llvm/test/Integer/a15.ll.outTue Feb 27 13:22:36 2007 @@ -5,7 +5,7 @@ @e = constant i15 -1 ; [#uses=0] @f = constant i15 1; [#uses=0] @g = constant i15 3; [#uses=0] [EMAIL PROTECTED] = constant i15 0 ; [#uses=0] [EMAIL PROTECTED] = constant i15 undef ; [#uses=0] @i = constant i15 -16384 ; [#uses=0] @j = constant i15 1; [#uses=0] @l = constant i15 -1 ; [#uses=0] Index: llvm/test/Integer/a17.ll.out diff -u llvm/test/Integer/a17.ll.out:1.4 llvm/test/Integer/a17.ll.out:1.5 --- llvm/test/Integer/a17.ll.out:1.4Mon Feb 26 20:34:02 2007 +++ llvm/test/Integer/a17.ll.outTue Feb 27 13:22:36 2007 @@ -5,7 +5,7 @@ @e = constant i17 -1 ; [#uses=0] @f = constant i17 1; [#uses=0] @g = constant i17 3; [#uses=0] [EMAIL PROTECTED] = constant i17 0 ; [#uses=0] [EMAIL PROTECTED] = constant i17 undef ; [#uses=0] @i = constant i17 -65536 ; [#uses=0] @j = constant i17 1; [#uses=0] @l = constant i17 -1 ; [#uses=0] Index: llvm/test/Integer/a31.ll.out diff -u llvm/test/Integer/a31.ll.out:1.4 llvm/test/Integer/a31.ll.out:1.5 --- llvm/test/Integer/a31.ll.out:1.4Mon Feb 26 20:34:02 2007 +++ llvm/test/Integer/a31.ll.outTue Feb 27 13:22:36 2007 @@ -5,7 +5,7 @@ @e = constant i31 -1 ; [#uses=0] @f = constant i31 1; [#uses=0] @g = constant i31 3; [#uses=0] [EMAIL PROTECTED] = constant i31 0 ; [#uses=0] [EMAIL PROTECTED] = constant i31 undef ; [#uses=0] @i = constant i31 -1073741824 ; [#uses=0] @j = constant i31 1; [#uses=0] @l = constant i31 -1 ; [#uses=0] Index: llvm/test/Integer/a33.ll.out diff -u llvm/test/Integer/a33.ll.out:1.4 llvm/test/Integer/a33.ll.out:1.5 --- llvm/test/Integer/a33.ll.out:1.4Mon Feb 26 20:34:02 2007 +++ llvm/test/Integer/a33.ll.outTue Feb 27 13:22:36 2007 @@ -5,7 +5,7 @@ @e = constant i33 -1 ; [#uses=0] @f = constant i33 1; [#uses=0] @g = constant i33 3; [#uses=0] [EMAIL PROTECTED] = constant i33 0 ; [#uses=0] [EMAIL PROTECTED] = constant i33 undef ; [#uses=0] @i = constant i33 -4294967296 ; [#uses=0] @j = constant i33 1; [#uses=0] @l = constant i33 -1 ; [#uses=0] Index: llvm/test/Integer/a63.ll.out diff -u llvm/test/Integer/a63.ll.out:1.4 llvm/test/Integer/a63.ll.out:1.5 --- llvm/test/Integer/a63.ll.out:1.4Mon Feb 26 20:34:02 2007 +++ llvm/test/Integer/a63.ll.outTue Feb 27 13:22:36 2007 @@ -5,7 +5,7 @@ @e = constant i63 -1 ; [#uses=0] @f = constant i63 1; [#uses=0] @g = constant i63 3; [#uses=0] [EMAIL PROTECTED] = constant i63 0 ; [#uses=0] [EMAIL PROTECTED] = constant i63 undef ; [#uses=0] @i = constant i63 -4611686018427387904 ; [#uses=0] @j = constant i63 1; [#uses=0] @l = constant i63 -1 ; [#uses=0] Index: llvm/test/Integer/a7.ll.out diff -u llvm/test/Integer/a7.ll.out:1.5 llvm/test/Integer/a7.ll.out:1.6 --- llvm/test/Integer/a7.ll.out:1.5 Mon Feb 26 20:34:02 2007 +++ llvm/test/Integer/a7.ll.out Tue Feb 27 13:22:36 2007 @@ -8,7 +8,7 @@ @g = constant i7 3 ; [#uses=0] @r = constant i7 5 ; [#uses=0] @s = constant i7 5 ; [#uses=0] [EMAIL PROTECTED] = constant i7 0 ; [#uses=0] [EMAIL PROTECTED] = constant i7 undef ; [#uses=0] @i = constant i7 -64 ; [#uses=0] @j = constant i7 1 ; [#uses=0] @l = constant i7 -1; [#uses=0] Index: llvm/test/Integer/a9.ll.out diff -u llvm/test/Integer/a9.ll.out:1.4 llvm/test/Integer/a9.ll.out:1.5 --- llvm/test/Integer/a9.ll.out:1.4 Mon Feb 26 20:34:02 2007 +++ llvm/test/Integer/a9.ll.out Tue Feb 27 13:22:36 2007 @@ -5,7 +5,7 @@ @e = constant i9 -1; [#uses=0] @f = constant i9 1 ; [#uses=0] @g = constant i9 3 ; [#uses=0] [EMAIL PROTECTED] = constant i9 0 ; [#uses=0] [EMAIL PROTECTED] = constant i9 undef
[llvm-commits] [see] CVS: llvm-poolalloc/lib/DSA/Local.cpp
Changes in directory llvm-poolalloc/lib/DSA:
Local.cpp updated: 1.158.2.4 -> 1.158.2.4.2.1
---
Log message:
The llva_save_stackp() function returns the stack pointer.
It should be marked with the incomplete, unknown, and stack flags.
---
Diffs of the changes: (+3 -1)
Local.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm-poolalloc/lib/DSA/Local.cpp
diff -u llvm-poolalloc/lib/DSA/Local.cpp:1.158.2.4
llvm-poolalloc/lib/DSA/Local.cpp:1.158.2.4.2.1
--- llvm-poolalloc/lib/DSA/Local.cpp:1.158.2.4 Mon Jan 22 15:18:48 2007
+++ llvm-poolalloc/lib/DSA/Local.cppTue Feb 27 12:52:19 2007
@@ -1232,11 +1232,13 @@
if (DSNode *N = RetNH.getNode())
N->setModifiedMarker()->setReadMarker();
return true;
-#if 0
+#if 1
} else if (F->getName() == "llva_save_stackp") {
// Create a new DSNode for the memory returned by llva_save_stackp()
DSNode *N = createNode();
N->setAllocaNodeMarker();
+ N->setUnknownNodeMarker();
+ N->setIncompleteMarker();
//
// TODO:
___
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Re: [llvm-commits] CVS: llvm/lib/VMCore/ConstantFold.cpp
On Tue, 2007-02-27 at 09:08 -0800, Chris Lattner wrote:
> On Feb 26, 2007, at 10:24 PM, Reid Spencer wrote:
>
> >case Instruction::FPToUI:
> > -if (const ConstantFP *FPC = dyn_cast(V))
> > - return ConstantInt::get(DestTy,(uint64_t) FPC->getValue());
> > +if (const ConstantFP *FPC = dyn_cast(V)) {
> > + APInt Val(APIntOps::RoundDoubleToAPInt(FPC->getValue()));
> > + uint32_t DestBitWidth = cast(DestTy)-
> > >getBitWidth();
> > + if (Val.getBitWidth() > DestBitWidth)
> > +Val.trunc(DestBitWidth);
>
> This seems like a poor choice of API. RoundDoubleToAPInt should take
> a result bitwidth. Without this, this appears like it could make a
> "large" APInt, then truncate it down to a small one when converting
> from double, which is very inefficient.
Done.
>
> > @@ -191,23 +206,37 @@
> > return 0; // Other pointer types cannot be
> > casted
> >case Instruction::UIToFP:
> > if (const ConstantInt *CI = dyn_cast(V))
> > - return ConstantFP::get(DestTy, double(CI->getZExtValue()));
> > + if (CI->getType()->getBitWidth() <= APInt::APINT_BITS_PER_WORD)
> > +return ConstantFP::get(DestTy, CI->getValue().roundToDouble
> > (false));
>
> Why the check for APINT_BITS_PER_WORD here? APINT_BITS_PER_WORD is
> an implementation detail of APInt, not a part of its public
> interface.
Actually it is part of the public interface and it needs to be. For
example, the constructor that takes an array of words (as might be used
by bcreader) needs to know how many bits are in those words. This
constant tells you.
> Also, please split the roundToDouble method into two
> methods which don't take a bool.
I don't understand this comment at all. What should these methods do
differently?
>
> > return 0;
> >case Instruction::SIToFP:
> > if (const ConstantInt *CI = dyn_cast(V))
> > - return ConstantFP::get(DestTy, double(CI->getSExtValue()));
> > + if (CI->getType()->getBitWidth() <= APInt::APINT_BITS_PER_WORD)
> > +return ConstantFP::get(DestTy, CI->getValue().roundToDouble
> > (true));
> > return 0;
>
> Likewise.
>
> >
> > @@ -382,7 +412,7 @@
> > Ops.reserve(numOps);
> > for (unsigned i = 0; i < numOps; ++i) {
> >const Constant *Op =
> > -(i == idxVal) ? Elt : Constant::getNullValue(Elt->getType());
> > +(idxVal == i) ? Elt : Constant::getNullValue(Elt->getType());
>
> This sort of change makes the diff more noisy, and there is no
> apparent reason for doing it. Generally, the mutating value (i) is
> on the LHS, why do this (in many places)?
Becasue there is no operator==(int, APInt) but there is an
APInt::operator==(int).
>
>
> > @@ -554,56 +585,66 @@
> >case Instruction::SDiv:
> > +if (CI2->isNullValue())
> > + return 0;// X / 0 -> can't fold
> > +return ConstantInt::get(C1->getType(), C1V.sdiv(C2V));
> > +if (C2V.isAllOnesValue() && C1V.isMinSignedValue())
> > + return 0;// MIN_INT / -1 -> overflow
> > +return ConstantInt::get(C1->getType(), C1V.sdiv(C2V));
>
> This isn't right, remove the first return.
Typo .. nice catch .. thanks.
>
> >case Instruction::Shl:
> > -return ConstantInt::get(C1->getType(), C1Val << C2Val);
> > +if (uint32_t shiftAmt = C2V.getZExtValue())
> > + if (shiftAmt <= C1V.getBitWidth())
>
> This should be <, not <=, likewise for other shifts.
Right.
> -Chris
>
>
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[llvm-commits] CVS: llvm/lib/Support/APInt.cpp
Changes in directory llvm/lib/Support:
APInt.cpp updated: 1.52 -> 1.53
---
Log message:
1. Fix three serious bugs in the comparison code.
2. Change RoundDoubleToAPInt to take a bit width parameter. Use that
parameter to limit the bit width of the result.
---
Diffs of the changes: (+22 -18)
APInt.cpp | 40 ++--
1 files changed, 22 insertions(+), 18 deletions(-)
Index: llvm/lib/Support/APInt.cpp
diff -u llvm/lib/Support/APInt.cpp:1.52 llvm/lib/Support/APInt.cpp:1.53
--- llvm/lib/Support/APInt.cpp:1.52 Tue Feb 27 01:35:18 2007
+++ llvm/lib/Support/APInt.cpp Tue Feb 27 12:23:40 2007
@@ -540,7 +540,8 @@
return pVal[0] < RHS.pVal[0];
// Otherwise, compare all words
- for (int i = whichWord(n1 - 1); i >= 0; --i) {
+ uint32_t topWord = whichWord(std::max(n1,n2)-1);
+ for (int i = topWord; i >= 0; --i) {
if (pVal[i] > RHS.pVal[i])
return false;
if (pVal[i] < RHS.pVal[i])
@@ -558,30 +559,28 @@
}
APInt lhs(*this);
- APInt rhs(*this);
- bool lhsNegative = false;
- bool rhsNegative = false;
- if (lhs[BitWidth-1]) {
-// Sign bit is set so make a note of it and perform two's complement
-lhsNegative = true;
+ APInt rhs(RHS);
+ bool lhsNeg = isNegative();
+ bool rhsNeg = rhs.isNegative();
+ if (lhsNeg) {
+// Sign bit is set so perform two's complement to make it positive
lhs.flip();
lhs++;
}
- if (rhs[BitWidth-1]) {
-// Sign bit is set so make a note of it and perform two's complement
-rhsNegative = true;
+ if (rhsNeg) {
+// Sign bit is set so perform two's complement to make it positive
rhs.flip();
rhs++;
}
// Now we have unsigned values to compare so do the comparison if necessary
// based on the negativeness of the values.
- if (lhsNegative)
-if (rhsNegative)
- return !lhs.ult(rhs);
+ if (lhsNeg)
+if (rhsNeg)
+ return lhs.ugt(rhs);
else
return true;
- else if (rhsNegative)
+ else if (rhsNeg)
return false;
else
return lhs.ult(rhs);
@@ -797,7 +796,7 @@
return A;
}
-APInt llvm::APIntOps::RoundDoubleToAPInt(double Double) {
+APInt llvm::APIntOps::RoundDoubleToAPInt(double Double, uint32_t width) {
union {
double D;
uint64_t I;
@@ -819,11 +818,16 @@
// If the exponent doesn't shift all bits out of the mantissa
if (exp < 52)
-return isNeg ? -APInt(64u, mantissa >> (52 - exp)) :
-APInt(64u, mantissa >> (52 - exp));
+return isNeg ? -APInt(width, mantissa >> (52 - exp)) :
+APInt(width, mantissa >> (52 - exp));
+
+ // If the client didn't provide enough bits for us to shift the mantissa into
+ // then the result is undefined, just return 0
+ if (width <= exp - 52)
+return APInt(width, 0);
// Otherwise, we have to shift the mantissa bits up to the right location
- APInt Tmp(exp+1, mantissa);
+ APInt Tmp(width, mantissa);
Tmp = Tmp.shl(exp - 52);
return isNeg ? -Tmp : Tmp;
}
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[llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h
Changes in directory llvm/include/llvm/ADT: APInt.h updated: 1.24 -> 1.25 --- Log message: Allow the RoundDoubleToAPInt function to specify a width to use. --- Diffs of the changes: (+1 -1) APInt.h |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/ADT/APInt.h diff -u llvm/include/llvm/ADT/APInt.h:1.24 llvm/include/llvm/ADT/APInt.h:1.25 --- llvm/include/llvm/ADT/APInt.h:1.24 Mon Feb 26 15:06:05 2007 +++ llvm/include/llvm/ADT/APInt.h Tue Feb 27 12:22:31 2007 @@ -654,7 +654,7 @@ /// RoundDoubleToAPInt - This function convert a double value to an APInt value. /// @brief Converts the given double value into a APInt. -APInt RoundDoubleToAPInt(double Double); +APInt RoundDoubleToAPInt(double Double, uint32_t width = 64); /// RoundFloatToAPInt - Converts a float value into an APInt value. /// @brief Converts a float value into a APInt. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Integer/APInt/gptest.cpp
Changes in directory llvm-test/SingleSource/UnitTests/Integer/APInt:
gptest.cpp updated: 1.5 -> 1.6
---
Log message:
Add tests for signed comparisons.
Add tests for truncation and extension.
Attempt to test ashr. This doesn't work right because gp doesn't have
the concept of a signed shift right.
---
Diffs of the changes: (+78 -12)
gptest.cpp | 90 -
1 files changed, 78 insertions(+), 12 deletions(-)
Index: llvm-test/SingleSource/UnitTests/Integer/APInt/gptest.cpp
diff -u llvm-test/SingleSource/UnitTests/Integer/APInt/gptest.cpp:1.5
llvm-test/SingleSource/UnitTests/Integer/APInt/gptest.cpp:1.6
--- llvm-test/SingleSource/UnitTests/Integer/APInt/gptest.cpp:1.5 Sat Feb
24 14:20:46 2007
+++ llvm-test/SingleSource/UnitTests/Integer/APInt/gptest.cpp Tue Feb 27
11:58:33 2007
@@ -207,7 +207,6 @@
}
void doShift(const APInt &v1) {
- APInt mask = APInt::getAllOnesValue(v1.getBitWidth());
for (int i = 1; i <= v1.getBitWidth(); i++) {
std::string cmd;
cmd += "bitand(truncate(shift(";
@@ -234,16 +233,78 @@
printf(" u>> %d = %s (not %s)\n", i, gpresult.c_str(), apresult.c_str());
fflush(stdout);
}
+if (v1.isNegative())
+ cmd = "shift(" + v1.toString(10,true) + ",-" + utostr(i) + ")-1\n";
+else
+ cmd = "shift(" + v1.toString(10,false) + ",-" + utostr(i) + ")\n";
+gpresult = getResult(cmd);
+R1 = v1.ashr(i);
+if (v1.isNegative())
+ apresult = R1.toString(10,true);
+else
+ apresult = R1.toString(10,false);
+if (gpresult != apresult) {
+ if (v1.isNegative())
+print(v1, true, false);
+ else
+print(v1, false, false);
+ printf(" s>> %d = %s (not %s)\n", i, gpresult.c_str(), apresult.c_str());
+ fflush(stdout);
+}
+ }
+}
+
+void doTruncExt(const APInt &v1) {
+ if (v1.getBitWidth() < 33)
+return;
+ std::string cmd;
+ for (int i = 1; i < v1.getBitWidth(); i++) {
+cmd = "bitand(" + v1.toString(10,false) + ",bitneg(0,";
+cmd += utostr(unsigned(i)) + "))\n";
+std::string gpresult = getResult(cmd);
+APInt V1(v1);
+V1.trunc(i);
+std::string apresult = V1.toString(10,false);
+if (gpresult != apresult) {
+ print(v1, false, false);
+ printf(".trunc(%d) = %s (not %s)\n", i, gpresult.c_str(),
apresult.c_str());
+ fflush(stdout);
+}
+ }
+ for (int i = v1.getBitWidth()+1; i < v1.getBitWidth()*2+2; ++i) {
+cmd = "bitand(" + v1.toString(10,false) + ",bitneg(0,";
+cmd += utostr(unsigned(i)) + "))\n";
+std::string gpresult = getResult(cmd);
+APInt V1(v1);
+V1.zext(i);
+std::string apresult = V1.toString(10,false);
+if (gpresult != apresult) {
+ print(v1, false, false);
+ printf(".zext(%d) = %s (not %s)\n", i, gpresult.c_str(),
apresult.c_str());
+ fflush(stdout);
+}
+cmd = "bitand(" + v1.toString(10,true) + ",bitneg(0,";
+cmd += utostr(unsigned(i)) + "))\n";
+gpresult = getResult(cmd);
+APInt V2(v1);
+V2.sext(i);
+apresult = V2.toString(10,false);
+if (gpresult != apresult) {
+ print(v1, true, false);
+ printf(".sext(%d) = %s (not %s)\n", i, gpresult.c_str(),
apresult.c_str());
+ fflush(stdout);
+}
}
}
void doCompare(const APInt &v1, const std::string &op,
-const APInt &v2, bool apresult) {
- std::string cmd = v1.toString(10, false) + op +
-v2.toString(10, false) + '\n';
+const APInt &v2, bool isSigned, bool apresult) {
+ std::string cmd = v1.toString(10, isSigned) + op +
+v2.toString(10, isSigned) + '\n';
bool gpresult = atoi(getResult(cmd).c_str());
if (gpresult != apresult)
-report(v1,v2, op, (apresult?"true":"false"), (apresult?"true":"false"));
+report(v1,v2, (isSigned? " s"+op : " u"+op),
+(gpresult?"true":"false"), (apresult?"true":"false"));
}
void test_binops(const APInt &v1, const APInt &v2) {
@@ -255,13 +316,17 @@
doAnd(v1,v2);
doOr(v1,v2);
doXor(v1,v2);
- doCompare(v1, "==", v2, v1 == v2);
- doCompare(v1, "!=", v2, v1 != v2);
- doCompare(v1, "< ", v2, v1.ult(v2));
- doCompare(v1, "<=", v2, v1.ule(v2));
- doCompare(v1, "> ", v2, v1.ugt(v2));
- doCompare(v1, ">=", v2, v1.uge(v2));
-}
+ doCompare(v1, " == ", v2, false, v1 == v2);
+ doCompare(v1, " != ", v2, false, v1 != v2);
+ doCompare(v1, " < ", v2, false, v1.ult(v2));
+ doCompare(v1, " <= ", v2, false, v1.ule(v2));
+ doCompare(v1, " > ", v2, false, v1.ugt(v2));
+ doCompare(v1, " >= ", v2, false, v1.uge(v2));
+ doCompare(v1, " < ", v2, true, v1.slt(v2));
+ doCompare(v1, " <= ", v2, true, v1.sle(v2));
+ doCompare(v1, " > ", v2, true, v1.sgt(v2));
+ doCompare(v1, " >= ", v2, true, v1.sge(v2));
+ }
void Shutdown() {
// Be nice and tell gp to stop
@@ -327,6 +392,7 @@
doComplement(*(list[i]));
doBitTest(*(list[i]));
doShift(*(list[i]));
+ doTruncExt(*(list[i]));
[llvm-commits] frameaddress intrinsincs for PPC
This patch implements the frameaddress intrinsincs for PPC.
OK to commit?
Index: PPCISelLowering.h
===
RCS file: /var/cvs/llvm/llvm/lib/Target/PowerPC/PPCISelLowering.h,v
retrieving revision 1.60
diff -t -d -u -p -5 -r1.60 PPCISelLowering.h
--- PPCISelLowering.h 27 Feb 2007 13:01:19 - 1.60
+++ PPCISelLowering.h 27 Feb 2007 17:32:38 -
@@ -238,9 +238,11 @@ namespace llvm {
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode.
virtual bool isLegalAddressImmediate(int64_t V) const;
virtual bool isLegalAddressImmediate(llvm::GlobalValue*) const;
+
+SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
};
}
#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
Index: PPCISelLowering.cpp
===
RCS file: /var/cvs/llvm/llvm/lib/Target/PowerPC/PPCISelLowering.cpp,v
retrieving revision 1.258
diff -t -d -u -p -5 -r1.258 PPCISelLowering.cpp
--- PPCISelLowering.cpp 27 Feb 2007 13:01:19 - 1.258
+++ PPCISelLowering.cpp 27 Feb 2007 17:32:44 -
@@ -2698,11 +2698,11 @@ SDOperand PPCTargetLowering::LowerOperat
case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
case ISD::MUL:return LowerMUL(Op, DAG);
// Frame & Return address. Currently unimplemented
case ISD::RETURNADDR: break;
- case ISD::FRAMEADDR: break;
+ case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
}
return SDOperand();
}
//===--===//
@@ -3169,5 +3169,27 @@ bool PPCTargetLowering::isLegalAddressIm
}
bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
return TargetLowering::isLegalAddressImmediate(GV);
}
+
+SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG)
+{
+ // Depths > 0 not supported yet!
+ if (cast(Op.getOperand(0))->getValue() > 0)
+return SDOperand();
+
+ MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
+ bool isPPC64 = PtrVT == MVT::i64;
+
+ MachineFunction &MF = DAG.getMachineFunction();
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+ bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
+ && MFI->getStackSize();
+
+ if (isPPC64)
+return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
+ MVT::i32);
+ else
+return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,
+ MVT::i32);
+}
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[llvm-commits] llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Here's a patch that fixes linux/PPC FramePointer. It reserves the offset
of the frame pointer before
calculating the offsets of callee saved registers.
OK to commit?
Index: PPCRegisterInfo.cpp
===
RCS file: /var/cvs/llvm/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp,v
retrieving revision 1.114
diff -t -d -u -p -5 -r1.114 PPCRegisterInfo.cpp
--- PPCRegisterInfo.cpp 27 Feb 2007 11:55:45 - 1.114
+++ PPCRegisterInfo.cpp 27 Feb 2007 17:29:51 -
@@ -879,10 +879,30 @@ void PPCRegisterInfo::processFunctionBef
// Save and clear the LR state.
PPCFunctionInfo *FI = MF.getInfo();
unsigned LR = getRARegister();
FI->setUsesLR(MF.isPhysRegUsed(LR));
MF.changePhyRegUsed(LR, false);
+
+
+ // Save R31 if necessary
+ int FPSI = FI->getFramePointerSaveIndex();
+ bool IsPPC64 = Subtarget.isPPC64();
+ bool IsMachoABI = Subtarget.isMachoABI();
+ const MachineFrameInfo *MFI = MF.getFrameInfo();
+
+ // If the frame pointer save index hasn't been defined yet.
+ if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects())
+ && !IsMachoABI) {
+// Find out what the fix offset of the frame pointer save area.
+int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
+ IsMachoABI);
+// Allocate the frame index for frame pointer save area.
+FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
+// Save the result.
+FI->setFramePointerSaveIndex(FPSI);
+ }
+
}
void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
MachineBasicBlock::iterator MBBI = MBB.begin();
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