[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.281 - 1.282
---
Log message:
SIGN_EXTEND_INREG requires one extra operand, a ValueType node.
---
Diffs of the changes: (+6 -2)
DAGCombiner.cpp |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.281
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.282
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.281 Fri Mar 23 19:02:43 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Mar 26 02:12:51 2007
@@ -2327,8 +2327,12 @@
CombineTo(N-getOperand(0).Val, Load);
} else
CombineTo(N0.Val, Load, Load.getValue(1));
-if (ShAmt)
- return DAG.getNode(N-getOpcode(), VT, Load);
+if (ShAmt) {
+ if (Opc == ISD::SIGN_EXTEND_INREG)
+return DAG.getNode(Opc, VT, Load, N-getOperand(1));
+ else
+return DAG.getNode(Opc, VT, Load);
+}
return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}
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[llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp
Changes in directory llvm/utils/TableGen:
CodeGenTarget.cpp updated: 1.86 - 1.87
---
Log message:
Add support for the v1i64 type. This makes better code for this:
#include mmintrin.h
extern __m64 C;
void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}
We get this:
_baz:
call L1$pb
L1$pb:
popl %eax
movl L_C$non_lazy_ptr-L1$pb(%eax), %eax
movq (%eax), %mm0
movl 4(%esp), %eax
movq %mm0, (%eax)
emms
ret
GCC gives us this:
_baz:
pushl %ebx
callL3
L001$pb:
L3:
popl%ebx
subl$8, %esp
movlL_C$non_lazy_ptr-L001$pb(%ebx), %eax
movl(%eax), %edx
movl4(%eax), %ecx
movl16(%esp), %eax
movl%edx, (%eax)
movl%ecx, 4(%eax)
emms
addl$8, %esp
popl%ebx
ret
---
Diffs of the changes: (+2 -0)
CodeGenTarget.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.86
llvm/utils/TableGen/CodeGenTarget.cpp:1.87
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.86 Mon Mar 19 01:20:37 2007
+++ llvm/utils/TableGen/CodeGenTarget.cpp Mon Mar 26 02:53:08 2007
@@ -52,6 +52,7 @@
case MVT::v8i8: return MVT::v8i8;
case MVT::v4i16: return MVT::v4i16;
case MVT::v2i32: return MVT::v2i32;
+ case MVT::v1i64: return MVT::v1i64;
case MVT::v16i8: return MVT::v16i8;
case MVT::v8i16: return MVT::v8i16;
case MVT::v4i32: return MVT::v4i32;
@@ -82,6 +83,7 @@
case MVT::v8i8: return MVT::v8i8;
case MVT::v4i16: return MVT::v4i16;
case MVT::v2i32: return MVT::v2i32;
+ case MVT::v1i64: return MVT::v1i64;
case MVT::v16i8: return MVT::v16i8;
case MVT::v8i16: return MVT::v8i16;
case MVT::v4i32: return MVT::v4i32;
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[llvm-commits] CVS: llvm/include/llvm/Intrinsics.td
Changes in directory llvm/include/llvm:
Intrinsics.td updated: 1.50 - 1.51
---
Log message:
Add support for the v1i64 type. This makes better code for this:
#include mmintrin.h
extern __m64 C;
void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}
We get this:
_baz:
call L1$pb
L1$pb:
popl %eax
movl L_C$non_lazy_ptr-L1$pb(%eax), %eax
movq (%eax), %mm0
movl 4(%esp), %eax
movq %mm0, (%eax)
emms
ret
GCC gives us this:
_baz:
pushl %ebx
callL3
L001$pb:
L3:
popl%ebx
subl$8, %esp
movlL_C$non_lazy_ptr-L001$pb(%ebx), %eax
movl(%eax), %edx
movl4(%eax), %ecx
movl16(%esp), %eax
movl%edx, (%eax)
movl%ecx, 4(%eax)
emms
addl$8, %esp
popl%ebx
ret
---
Diffs of the changes: (+1 -0)
Intrinsics.td |1 +
1 files changed, 1 insertion(+)
Index: llvm/include/llvm/Intrinsics.td
diff -u llvm/include/llvm/Intrinsics.td:1.50
llvm/include/llvm/Intrinsics.td:1.51
--- llvm/include/llvm/Intrinsics.td:1.50Thu Mar 8 16:09:11 2007
+++ llvm/include/llvm/Intrinsics.td Mon Mar 26 02:53:08 2007
@@ -94,6 +94,7 @@
def llvm_v8i16_ty : LLVMVectorTypev8i16, 8, llvm_i16_ty; // 8 x i16
def llvm_v2i64_ty : LLVMVectorTypev2i64, 2, llvm_i64_ty; // 2 x i64
def llvm_v2i32_ty : LLVMVectorTypev2i32, 2, llvm_i32_ty; // 2 x i32
+def llvm_v1i64_ty : LLVMVectorTypev1i64, 1, llvm_i64_ty; // 1 x i64
def llvm_v4i32_ty : LLVMVectorTypev4i32, 4, llvm_i32_ty; // 4 x i32
def llvm_v4f32_ty : LLVMVectorTypev4f32, 4, llvm_float_ty; // 4 x float
def llvm_v2f64_ty : LLVMVectorTypev2f64, 2, llvm_double_ty;// 2 x
double
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td X86RegisterInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.377 - 1.378
X86InstrMMX.td updated: 1.24 - 1.25
X86RegisterInfo.td updated: 1.40 - 1.41
---
Log message:
Add support for the v1i64 type. This makes better code for this:
#include mmintrin.h
extern __m64 C;
void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}
We get this:
_baz:
call L1$pb
L1$pb:
popl %eax
movl L_C$non_lazy_ptr-L1$pb(%eax), %eax
movq (%eax), %mm0
movl 4(%esp), %eax
movq %mm0, (%eax)
emms
ret
GCC gives us this:
_baz:
pushl %ebx
callL3
L001$pb:
L3:
popl%ebx
subl$8, %esp
movlL_C$non_lazy_ptr-L001$pb(%ebx), %eax
movl(%eax), %edx
movl4(%eax), %ecx
movl16(%esp), %eax
movl%edx, (%eax)
movl%ecx, 4(%eax)
emms
addl$8, %esp
popl%ebx
ret
---
Diffs of the changes: (+58 -28)
X86ISelLowering.cpp |9 --
X86InstrMMX.td | 75 +++-
X86RegisterInfo.td |2 -
3 files changed, 58 insertions(+), 28 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.377
llvm/lib/Target/X86/X86ISelLowering.cpp:1.378
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.377 Sat Mar 24 21:14:49 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Mar 26 02:53:08 2007
@@ -314,6 +314,7 @@
addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
+addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
// FIXME: add MMX packed arithmetics
@@ -347,10 +348,12 @@
setOperationAction(ISD::XOR,MVT::v2i32, Legal);
setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
-AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
+AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
-AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v2i32);
-setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
+AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
+setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
+AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
+setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.24
llvm/lib/Target/X86/X86InstrMMX.td:1.25
--- llvm/lib/Target/X86/X86InstrMMX.td:1.24 Fri Mar 23 17:35:46 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Mon Mar 26 02:53:08 2007
@@ -37,12 +37,13 @@
def : Pat(v8i8 (undef)), (IMPLICIT_DEF_VR64);
def : Pat(v4i16 (undef)), (IMPLICIT_DEF_VR64);
def : Pat(v2i32 (undef)), (IMPLICIT_DEF_VR64);
+def : Pat(v1i64 (undef)), (IMPLICIT_DEF_VR64);
//===--===//
// MMX Pattern Fragments
//===--===//
-def loadv2i32 : PatFrag(ops node:$ptr), (v2i32 (load node:$ptr));
+def loadv1i64 : PatFrag(ops node:$ptr), (v1i64 (load node:$ptr));
def bc_v8i8 : PatFrag(ops node:$in), (v8i8 (bitconvert node:$in));
def bc_v4i16 : PatFrag(ops node:$in), (v4i16 (bitconvert node:$in));
@@ -65,7 +66,7 @@
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR64:$dst, (OpVT (OpNode VR64:$src1,
(bitconvert
- (loadv2i32 addr:$src2)];
+ (loadv1i64 addr:$src2)];
}
multiclass MMXI_binop_rm_intbits8 opc, string OpcodeStr, Intrinsic IntId,
@@ -78,25 +79,25 @@
def rm : MMXIopc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR64:$dst, (IntId VR64:$src1,
- (bitconvert (loadv2i32 addr:$src2];
+ (bitconvert (loadv1i64 addr:$src2];
}
- // MMXI_binop_rm_v2i32 - Simple MMX binary operator whose type is v2i32.
+ // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
//
// FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen
knew
// to collapse (bitconvert VT to VT) into its operand.
//
- multiclass MMXI_binop_rm_v2i32bits8 opc, string OpcodeStr, SDNode OpNode,
+ multiclass MMXI_binop_rm_v1i64bits8 opc, string OpcodeStr, SDNode
[llvm-commits] CVS: llvm/lib/Target/X86/README-MMX.txt
Changes in directory llvm/lib/Target/X86:
README-MMX.txt updated: 1.1 - 1.2
---
Log message:
Updated.
---
Diffs of the changes: (+0 -54)
README-MMX.txt | 54 --
1 files changed, 54 deletions(-)
Index: llvm/lib/Target/X86/README-MMX.txt
diff -u llvm/lib/Target/X86/README-MMX.txt:1.1
llvm/lib/Target/X86/README-MMX.txt:1.2
--- llvm/lib/Target/X86/README-MMX.txt:1.1 Thu Mar 22 13:42:45 2007
+++ llvm/lib/Target/X86/README-MMX.txt Mon Mar 26 02:55:58 2007
@@ -3,57 +3,3 @@
//===-===//
//===-===//
-
-We should compile
-
-#include mmintrin.h
-
-extern __m64 C;
-
-void baz(__v2si *A, __v2si *B)
-{
- *A = __builtin_ia32_psllq(*B, C);
- _mm_empty();
-}
-
-to:
-
-.globl _baz
-_baz:
- callL3
-L001$pb:
-L3:
- popl%ecx
- subl$12, %esp
- movl20(%esp), %eax
- movq(%eax), %mm0
- movlL_C$non_lazy_ptr-L001$pb(%ecx), %eax
- movq(%eax), %mm1
- movl16(%esp), %eax
- psllq %mm1, %mm0
- movq%mm0, (%eax)
- emms
- addl$12, %esp
- ret
-
-not:
-
-_baz:
- subl $12, %esp
- call L1$pb
-L1$pb:
- popl %eax
- movl L_C$non_lazy_ptr-L1$pb(%eax), %eax
- movl (%eax), %ecx
- movl %ecx, (%esp)
- movl 4(%eax), %eax
- movl %eax, 4(%esp)
- movl 20(%esp), %eax
- movq (%eax), %mm0
- movq (%esp), %mm1
- psllq %mm1, %mm0
- movl 16(%esp), %eax
- movq %mm0, (%eax)
- emms
- addl $12, %esp
- ret
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.378 - 1.379 --- Log message: Promote to v1i64 type... --- Diffs of the changes: (+15 -9) X86ISelLowering.cpp | 24 +++- 1 files changed, 15 insertions(+), 9 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.378 llvm/lib/Target/X86/X86ISelLowering.cpp:1.379 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.378 Mon Mar 26 02:53:08 2007 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Mar 26 03:03:33 2007 @@ -330,22 +330,28 @@ setOperationAction(ISD::MUL,MVT::v4i16, Legal); setOperationAction(ISD::AND,MVT::v8i8, Promote); -AddPromotedToType (ISD::AND,MVT::v8i8, MVT::v2i32); +AddPromotedToType (ISD::AND,MVT::v8i8, MVT::v1i64); setOperationAction(ISD::AND,MVT::v4i16, Promote); -AddPromotedToType (ISD::AND,MVT::v4i16, MVT::v2i32); -setOperationAction(ISD::AND,MVT::v2i32, Legal); +AddPromotedToType (ISD::AND,MVT::v4i16, MVT::v1i64); +setOperationAction(ISD::AND,MVT::v2i32, Promote); +AddPromotedToType (ISD::AND,MVT::v2i32, MVT::v1i64); +setOperationAction(ISD::AND,MVT::v1i64, Legal); setOperationAction(ISD::OR, MVT::v8i8, Promote); -AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v2i32); +AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); setOperationAction(ISD::OR, MVT::v4i16, Promote); -AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v2i32); -setOperationAction(ISD::OR, MVT::v2i32, Legal); +AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); +setOperationAction(ISD::OR, MVT::v2i32, Promote); +AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); +setOperationAction(ISD::OR, MVT::v1i64, Legal); setOperationAction(ISD::XOR,MVT::v8i8, Promote); -AddPromotedToType (ISD::XOR,MVT::v8i8, MVT::v2i32); +AddPromotedToType (ISD::XOR,MVT::v8i8, MVT::v1i64); setOperationAction(ISD::XOR,MVT::v4i16, Promote); -AddPromotedToType (ISD::XOR,MVT::v4i16, MVT::v2i32); -setOperationAction(ISD::XOR,MVT::v2i32, Legal); +AddPromotedToType (ISD::XOR,MVT::v4i16, MVT::v1i64); +setOperationAction(ISD::XOR,MVT::v2i32, Promote); +AddPromotedToType (ISD::XOR,MVT::v2i32, MVT::v1i64); +setOperationAction(ISD::XOR,MVT::v1i64, Legal); setOperationAction(ISD::LOAD, MVT::v8i8, Promote); AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Transforms/InstCombine/apint-not.ll apint-sub.ll
Changes in directory llvm/test/Transforms/InstCombine:
apint-not.ll updated: 1.1 - 1.2
apint-sub.ll updated: 1.1 - 1.2
---
Log message:
Fix testsuite hang.
---
Diffs of the changes: (+2 -2)
apint-not.ll |2 +-
apint-sub.ll |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/test/Transforms/InstCombine/apint-not.ll
diff -u llvm/test/Transforms/InstCombine/apint-not.ll:1.1
llvm/test/Transforms/InstCombine/apint-not.ll:1.2
--- llvm/test/Transforms/InstCombine/apint-not.ll:1.1 Fri Mar 23 15:48:34 2007
+++ llvm/test/Transforms/InstCombine/apint-not.ll Mon Mar 26 05:59:13 2007
@@ -1,7 +1,7 @@
; This test makes sure that the xor instructions are properly eliminated
; when arbitrary precision integers are used.
-; RUN: llvm-as | opt -instcombine | llvm-dis | not grep xor
+; RUN: llvm-as %s | opt -instcombine | llvm-dis | not grep xor
define i33 @test1(i33 %A) {
%B = xor i33 %A, -1
Index: llvm/test/Transforms/InstCombine/apint-sub.ll
diff -u llvm/test/Transforms/InstCombine/apint-sub.ll:1.1
llvm/test/Transforms/InstCombine/apint-sub.ll:1.2
--- llvm/test/Transforms/InstCombine/apint-sub.ll:1.1 Fri Mar 23 15:48:34 2007
+++ llvm/test/Transforms/InstCombine/apint-sub.ll Mon Mar 26 05:59:13 2007
@@ -2,7 +2,7 @@
; even with arbitrary precision integers.
;
-; RUN: llvm-as | opt -instcombine | llvm-dis | \
+; RUN: llvm-as %s | opt -instcombine | llvm-dis | \
; RUN: grep -v 'sub i19 %Cok, %Bok' | not grep sub
define i23 @test1(i23 %A) {
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[llvm-commits] CVS: llvm-test/MultiSource/Applications/minisat/Main.cpp
Changes in directory llvm-test/MultiSource/Applications/minisat: Main.cpp updated: 1.2 - 1.3 --- Log message: Fix compilation on arm-linux. --- Diffs of the changes: (+1 -1) Main.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/MultiSource/Applications/minisat/Main.cpp diff -u llvm-test/MultiSource/Applications/minisat/Main.cpp:1.2 llvm-test/MultiSource/Applications/minisat/Main.cpp:1.3 --- llvm-test/MultiSource/Applications/minisat/Main.cpp:1.2 Thu Feb 8 02:40:59 2007 +++ llvm-test/MultiSource/Applications/minisat/Main.cpp Mon Mar 26 11:15:37 2007 @@ -286,7 +286,7 @@ reportf(This is MiniSat 2.0 beta\n); -#if defined(__linux__) +#if defined(__linux__) defined(_FPU_EXTENDED) defined(_FPU_DOUBLE) fpu_control_t oldcw, newcw; _FPU_GETCW(oldcw); newcw = (oldcw ~_FPU_EXTENDED) | _FPU_DOUBLE; _FPU_SETCW(newcw); reportf(WARNING: for repeatability, setting FPU to use double precision\n); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.692 - 1.693 --- Log message: Get the number of bits to set in a mask correct for a shl/lshr transform. --- Diffs of the changes: (+1 -1) InstructionCombining.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.692 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.693 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.692 Mon Mar 26 00:25:00 2007 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Mon Mar 26 12:18:58 2007 @@ -5858,7 +5858,7 @@ BinaryOperator::createLShr(X, ConstantInt::get(Ty, ShiftDiff)); InsertNewInstBefore(Shift, I); -APInt Mask(APInt::getLowBitsSet(TypeBits, ShiftAmt2)); +APInt Mask(APInt::getLowBitsSet(TypeBits, TypeBits - ShiftAmt2)); return BinaryOperator::createAnd(Shift, ConstantInt::get(Mask)); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.693 - 1.694
---
Log message:
Get better debug output by having modified instructions print both the
original and new instruction. A slight performance hit with ostringstream
but it is only for debug.
Also, clean up an uninitialized variable warning noticed in a release build.
---
Diffs of the changes: (+10 -2)
InstructionCombining.cpp | 12 ++--
1 files changed, 10 insertions(+), 2 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.693
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.694
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.693 Mon Mar 26
12:18:58 2007
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Mon Mar 26 12:44:01 2007
@@ -57,6 +57,9 @@
#include llvm/ADT/STLExtras.h
#include algorithm
#include set
+#ifndef NDEBUG
+#include sstream
+#endif
using namespace llvm;
using namespace llvm::PatternMatch;
@@ -3134,7 +3137,7 @@
// Otherwise, if Mask is 0+1+0+, and if B is known to have the low 0+
// part, we don't need any explicit masks to take them out of A. If that
// is all N is, ignore it.
- unsigned MB, ME;
+ unsigned MB = 0, ME = 0;
if (isRunOfOnes(Mask, MB, ME)) { // begin/end bit of run, inclusive
uint32_t BitWidth = castIntegerType(RHS-getType())-getBitWidth();
APInt Mask(APInt::getAllOnesValue(BitWidth));
@@ -9445,6 +9448,10 @@
}
// Now that we have an instruction, try combining it to simplify it...
+#ifndef NDEBUG
+std::string OrigI;
+#endif
+DEBUG(std::ostringstream SS; I-print(SS); OrigI = SS.str(););
if (Instruction *Result = visit(*I)) {
++NumCombined;
// Should we replace the old instruction with a new one?
@@ -9483,7 +9490,8 @@
// Erase the old instruction.
InstParent-getInstList().erase(I);
} else {
-DOUT IC: MOD = *I;
+DOUT IC: Mod = OrigI
+ New = *I;
// If the instruction was modified, it's possible that it is now dead.
// if so, remove it.
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[llvm-commits] CVS: llvm/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll
Changes in directory llvm/test/Transforms/InstCombine:
2007-03-25-BadShiftMask.ll updated: 1.1 - 1.2
---
Log message:
Fix this test case to match output after a bug was fixed.
---
Diffs of the changes: (+2 -1)
2007-03-25-BadShiftMask.ll |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll
diff -u llvm/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll:1.1
llvm/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll:1.2
--- llvm/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll:1.1 Mon Mar
26 00:32:16 2007
+++ llvm/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll Mon Mar 26
13:04:38 2007
@@ -1,5 +1,6 @@
; PR1271
-; RUN: llvm-as %s | opt -instcombine | llvm-dis | grep 'br i1 %1'
+; RUN: llvm-as %s | opt -instcombine | llvm-dis | \
+; RUN:grep 'icmp eq i32 .tmp.*, 2146435072'
%struct..0anon = type { i32, i32 }
%struct..1anon = type { double }
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Re: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
@@ -57,6 +57,9 @@
#include llvm/ADT/STLExtras.h
#include algorithm
#include set
+#ifndef NDEBUG
+#include sstream
+#endif
Please don't conditionally #include files.
Thanks for the patch, making instcombine's debug output nicer would
be very helpful,
-chris
using namespace llvm;
using namespace llvm::PatternMatch;
@@ -3134,7 +3137,7 @@
// Otherwise, if Mask is 0+1+0+, and if B is known to have
the low 0+
// part, we don't need any explicit masks to take them out
of A. If that
// is all N is, ignore it.
- unsigned MB, ME;
+ unsigned MB = 0, ME = 0;
if (isRunOfOnes(Mask, MB, ME)) { // begin/end bit of run,
inclusive
uint32_t BitWidth = castIntegerType(RHS-getType())-
getBitWidth();
APInt Mask(APInt::getAllOnesValue(BitWidth));
@@ -9445,6 +9448,10 @@
}
// Now that we have an instruction, try combining it to
simplify it...
+#ifndef NDEBUG
+std::string OrigI;
+#endif
+DEBUG(std::ostringstream SS; I-print(SS); OrigI = SS.str(););
if (Instruction *Result = visit(*I)) {
++NumCombined;
// Should we replace the old instruction with a new one?
@@ -9483,7 +9490,8 @@
// Erase the old instruction.
InstParent-getInstList().erase(I);
} else {
-DOUT IC: MOD = *I;
+DOUT IC: Mod = OrigI
+ New = *I;
// If the instruction was modified, it's possible that it
is now dead.
// if so, remove it.
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Re: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
On Mon, 2007-03-26 at 11:29 -0700, Chris Lattner wrote:
@@ -57,6 +57,9 @@
#include llvm/ADT/STLExtras.h
#include algorithm
#include set
+#ifndef NDEBUG
+#include sstream
+#endif
Please don't conditionally #include files.
Why? You would get sstream #included in a release build when it isn't
used in a release build. Seems pointless to me.
Thanks for the patch, making instcombine's debug output nicer would
be very helpful,
Yup .. helped verify that the test case I had yesterday was wrong (after
the fix).
Reid.
-chris
using namespace llvm;
using namespace llvm::PatternMatch;
@@ -3134,7 +3137,7 @@
// Otherwise, if Mask is 0+1+0+, and if B is known to have
the low 0+
// part, we don't need any explicit masks to take them out
of A. If that
// is all N is, ignore it.
- unsigned MB, ME;
+ unsigned MB = 0, ME = 0;
if (isRunOfOnes(Mask, MB, ME)) { // begin/end bit of run,
inclusive
uint32_t BitWidth = castIntegerType(RHS-getType())-
getBitWidth();
APInt Mask(APInt::getAllOnesValue(BitWidth));
@@ -9445,6 +9448,10 @@
}
// Now that we have an instruction, try combining it to
simplify it...
+#ifndef NDEBUG
+std::string OrigI;
+#endif
+DEBUG(std::ostringstream SS; I-print(SS); OrigI = SS.str(););
if (Instruction *Result = visit(*I)) {
++NumCombined;
// Should we replace the old instruction with a new one?
@@ -9483,7 +9490,8 @@
// Erase the old instruction.
InstParent-getInstList().erase(I);
} else {
-DOUT IC: MOD = *I;
+DOUT IC: Mod = OrigI
+ New = *I;
// If the instruction was modified, it's possible that it
is now dead.
// if so, remove it.
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Re: [llvm-commits] CVS: llvm-www/ProjectsWithLLVM/index.html
On 3/26/07, Chris Lattner [EMAIL PROTECTED] wrote: +a href=http://compilers/fernando/projects/soc/;Project page./a Relative URL alert! -bw ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
On Mar 26, 2007, at 11:33 AM, Reid Spencer wrote: On Mon, 2007-03-26 at 11:29 -0700, Chris Lattner wrote: @@ -57,6 +57,9 @@ #include llvm/ADT/STLExtras.h #include algorithm #include set +#ifndef NDEBUG +#include sstream +#endif Please don't conditionally #include files. Why? You would get sstream #included in a release build when it isn't used in a release build. Seems pointless to me. Because someone will later add code to instcombine that uses sstream that isn't itself guarded by the NDEBUG ifdef. Suddenly the release builds start failing. -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-www/ProjectsWithLLVM/index.html
Changes in directory llvm-www/ProjectsWithLLVM: index.html updated: 1.33 - 1.34 --- Log message: Fix URL, thanks to Bill for noticing this! --- Diffs of the changes: (+1 -1) index.html |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-www/ProjectsWithLLVM/index.html diff -u llvm-www/ProjectsWithLLVM/index.html:1.33 llvm-www/ProjectsWithLLVM/index.html:1.34 --- llvm-www/ProjectsWithLLVM/index.html:1.33 Mon Mar 26 13:46:43 2007 +++ llvm-www/ProjectsWithLLVM/index.htmlMon Mar 26 14:05:37 2007 @@ -99,7 +99,7 @@ /P p -a href=http://compilers/fernando/projects/soc/;Project page./a +a href=http://compilers.cs.ucla.edu/fernando/projects/soc/;Project page./a /p /div ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/VMCore/ConstantFold.cpp
Changes in directory llvm/lib/VMCore: ConstantFold.cpp updated: 1.149 - 1.150 --- Log message: Add a comment to explain a folding transform. --- Diffs of the changes: (+1 -0) ConstantFold.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/VMCore/ConstantFold.cpp diff -u llvm/lib/VMCore/ConstantFold.cpp:1.149 llvm/lib/VMCore/ConstantFold.cpp:1.150 --- llvm/lib/VMCore/ConstantFold.cpp:1.149 Sun Mar 25 00:47:04 2007 +++ llvm/lib/VMCore/ConstantFold.cppMon Mar 26 15:09:02 2007 @@ -554,6 +554,7 @@ if (C2-isNullValue()) return const_castConstant*(C1); // X ^ 0 == X break; case Instruction::AShr: +// ashr (zext C to Ty), C2 - lshr (zext C, CSA), C2 if (CE1-getOpcode() == Instruction::ZExt) // Top bits known zero. return ConstantExpr::getLShr(const_castConstant*(C1), const_castConstant*(C2)); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.694 - 1.695
---
Log message:
eliminate use of std::set
---
Diffs of the changes: (+4 -6)
InstructionCombining.cpp | 10 --
1 files changed, 4 insertions(+), 6 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.694
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.695
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.694 Mon Mar 26
12:44:01 2007
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Mon Mar 26 15:40:50 2007
@@ -56,10 +56,7 @@
#include llvm/ADT/Statistic.h
#include llvm/ADT/STLExtras.h
#include algorithm
-#include set
-#ifndef NDEBUG
#include sstream
-#endif
using namespace llvm;
using namespace llvm::PatternMatch;
@@ -7808,12 +7805,13 @@
/// DeadPHICycle - Return true if this PHI node is only used by a PHI node
cycle
/// that is dead.
-static bool DeadPHICycle(PHINode *PN, std::setPHINode* PotentiallyDeadPHIs)
{
+static bool DeadPHICycle(PHINode *PN,
+ SmallPtrSetPHINode*, 16 PotentiallyDeadPHIs) {
if (PN-use_empty()) return true;
if (!PN-hasOneUse()) return false;
// Remember this node, and if we find the cycle, return.
- if (!PotentiallyDeadPHIs.insert(PN).second)
+ if (!PotentiallyDeadPHIs.insert(PN))
return true;
if (PHINode *PU = dyn_castPHINode(PN-use_back()))
@@ -7844,7 +7842,7 @@
if (PN.hasOneUse()) {
Instruction *PHIUser = castInstruction(PN.use_back());
if (PHINode *PU = dyn_castPHINode(PHIUser)) {
- std::setPHINode* PotentiallyDeadPHIs;
+ SmallPtrSetPHINode*, 16 PotentiallyDeadPHIs;
PotentiallyDeadPHIs.insert(PN);
if (DeadPHICycle(PU, PotentiallyDeadPHIs))
return ReplaceInstUsesWith(PN, UndefValue::get(PN.getType()));
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/RegisterScavenging.h
Changes in directory llvm/include/llvm/CodeGen:
RegisterScavenging.h updated: 1.11 - 1.12
---
Log message:
Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable to
hopefully forestall similar errors.
---
Diffs of the changes: (+8 -8)
RegisterScavenging.h | 16
1 files changed, 8 insertions(+), 8 deletions(-)
Index: llvm/include/llvm/CodeGen/RegisterScavenging.h
diff -u llvm/include/llvm/CodeGen/RegisterScavenging.h:1.11
llvm/include/llvm/CodeGen/RegisterScavenging.h:1.12
--- llvm/include/llvm/CodeGen/RegisterScavenging.h:1.11 Tue Mar 20 16:35:06 2007
+++ llvm/include/llvm/CodeGen/RegisterScavenging.h Mon Mar 26 17:23:54 2007
@@ -47,10 +47,10 @@
///
const TargetRegisterClass *ScavengedRC;
- /// RegStates - The current state of all the physical registers immediately
+ /// RegsAvailable - The current state of all the physical registers
immediately
/// before MBBI. One bit per physical register. If bit is set that means it's
/// available, unset means the register is currently being used.
- BitVector RegStates;
+ BitVector RegsAvailable;
public:
RegScavenger()
@@ -88,18 +88,18 @@
/// isUsed / isUsed - Test if a register is currently being used.
///
- bool isUsed(unsigned Reg) const { return !RegStates[Reg]; }
- bool isUnused(unsigned Reg) const { return RegStates[Reg]; }
+ bool isUsed(unsigned Reg) const { return !RegsAvailable[Reg]; }
+ bool isUnused(unsigned Reg) const { return RegsAvailable[Reg]; }
/// getRegsUsed - return all registers currently in use in used.
void getRegsUsed(BitVector used, bool includeReserved);
/// setUsed / setUnused - Mark the state of one or a number of registers.
///
- void setUsed(unsigned Reg) { RegStates.reset(Reg); }
- void setUsed(BitVector Regs) { RegStates = ~Regs; }
- void setUnused(unsigned Reg) { RegStates.set(Reg); }
- void setUnused(BitVector Regs) { RegStates |= Regs; }
+ void setUsed(unsigned Reg) { RegsAvailable.reset(Reg); }
+ void setUsed(BitVector Regs) { RegsAvailable = ~Regs; }
+ void setUnused(unsigned Reg) { RegsAvailable.set(Reg); }
+ void setUnused(BitVector Regs) { RegsAvailable |= Regs; }
/// FindUnusedReg - Find a unused register of the specified register class
/// from the specified set of registers. It return 0 is none is found.
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[llvm-commits] CVS: llvm/lib/CodeGen/RegisterScavenging.cpp
Changes in directory llvm/lib/CodeGen:
RegisterScavenging.cpp updated: 1.13 - 1.14
---
Log message:
Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable to
hopefully forestall similar errors.
---
Diffs of the changes: (+15 -15)
RegisterScavenging.cpp | 30 +++---
1 files changed, 15 insertions(+), 15 deletions(-)
Index: llvm/lib/CodeGen/RegisterScavenging.cpp
diff -u llvm/lib/CodeGen/RegisterScavenging.cpp:1.13
llvm/lib/CodeGen/RegisterScavenging.cpp:1.14
--- llvm/lib/CodeGen/RegisterScavenging.cpp:1.13Tue Mar 20 16:35:06 2007
+++ llvm/lib/CodeGen/RegisterScavenging.cpp Mon Mar 26 17:23:54 2007
@@ -36,7 +36,7 @@
if (!MBB) {
NumPhysRegs = RegInfo-getNumRegs();
-RegStates.resize(NumPhysRegs);
+RegsAvailable.resize(NumPhysRegs);
// Create reserved registers bitvector.
ReservedRegs = RegInfo-getReservedRegs(MF);
@@ -54,10 +54,10 @@
ScavengedRC = NULL;
// All registers started out unused.
- RegStates.set();
+ RegsAvailable.set();
// Reserved registers are always used.
- RegStates ^= ReservedRegs;
+ RegsAvailable ^= ReservedRegs;
// Live-in registers are in use.
if (!MBB-livein_empty())
@@ -182,9 +182,9 @@
void RegScavenger::getRegsUsed(BitVector used, bool includeReserved) {
if (includeReserved)
-used = RegStates;
+used = ~RegsAvailable;
else
-used = RegStates ~ReservedRegs;
+used = ~RegsAvailable ~ReservedRegs;
}
/// CreateRegClassMask - Set the bits that represent the registers in the
@@ -198,32 +198,32 @@
unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
const BitVector Candidates) const {
// Mask off the registers which are not in the TargetRegisterClass.
- BitVector RegStatesCopy(NumPhysRegs, false);
- CreateRegClassMask(RegClass, RegStatesCopy);
- RegStatesCopy = RegStates;
+ BitVector RegsAvailableCopy(NumPhysRegs, false);
+ CreateRegClassMask(RegClass, RegsAvailableCopy);
+ RegsAvailableCopy = RegsAvailable;
// Restrict the search to candidates.
- RegStatesCopy = Candidates;
+ RegsAvailableCopy = Candidates;
// Returns the first unused (bit is set) register, or 0 is none is found.
- int Reg = RegStatesCopy.find_first();
+ int Reg = RegsAvailableCopy.find_first();
return (Reg == -1) ? 0 : Reg;
}
unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
bool ExCalleeSaved) const {
// Mask off the registers which are not in the TargetRegisterClass.
- BitVector RegStatesCopy(NumPhysRegs, false);
- CreateRegClassMask(RegClass, RegStatesCopy);
- RegStatesCopy = RegStates;
+ BitVector RegsAvailableCopy(NumPhysRegs, false);
+ CreateRegClassMask(RegClass, RegsAvailableCopy);
+ RegsAvailableCopy = RegsAvailable;
// If looking for a non-callee-saved register, mask off all the callee-saved
// registers.
if (ExCalleeSaved)
-RegStatesCopy = ~CalleeSavedRegs;
+RegsAvailableCopy = ~CalleeSavedRegs;
// Returns the first unused (bit is set) register, or 0 is none is found.
- int Reg = RegStatesCopy.find_first();
+ int Reg = RegsAvailableCopy.find_first();
return (Reg == -1) ? 0 : Reg;
}
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h
Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.214 - 1.215 --- Log message: Change findRegisterUseOperand() to return operand index instead. --- Diffs of the changes: (+3 -3) MachineInstr.h |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.214 llvm/include/llvm/CodeGen/MachineInstr.h:1.215 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.214 Tue Feb 27 15:06:57 2007 +++ llvm/include/llvm/CodeGen/MachineInstr.hMon Mar 26 17:37:45 2007 @@ -390,10 +390,10 @@ delete removeFromParent(); } - /// findRegisterUseOperand() - Returns the MachineOperand that is a use of - /// the specific register or NULL if it is not found. It further tightening + /// findRegisterUseOperand() - Returns the operand index that is a use of + /// the specific register or -1 if it is not found. It further tightening /// the search criteria to a use that kills the register if isKill is true. - MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false); + int findRegisterUseOperand(unsigned Reg, bool isKill = false); /// findRegisterDefOperand() - Returns the MachineOperand that is a def of /// the specific register or NULL if it is not found. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/tools/llc/llc.cpp
Changes in directory llvm/tools/llc:
llc.cpp updated: 1.144 - 1.145
---
Log message:
For PR1277: http://llvm.org/PR1277 :
Implement error handling for bytecode parsing.
Patch by Scott Michel.
---
Diffs of the changes: (+4 -1)
llc.cpp |5 -
1 files changed, 4 insertions(+), 1 deletion(-)
Index: llvm/tools/llc/llc.cpp
diff -u llvm/tools/llc/llc.cpp:1.144 llvm/tools/llc/llc.cpp:1.145
--- llvm/tools/llc/llc.cpp:1.144Wed Feb 7 19:41:07 2007
+++ llvm/tools/llc/llc.cpp Mon Mar 26 17:38:01 2007
@@ -177,10 +177,13 @@
sys::PrintStackTraceOnErrorSignal();
// Load the module to be compiled...
+std::string errmsg;
std::auto_ptrModule M(ParseBytecodeFile(InputFilename,
-
Compressor::decompressToNewBuffer));
+
Compressor::decompressToNewBuffer,
+ errmsg));
if (M.get() == 0) {
std::cerr argv[0] : bytecode didn't read correctly.\n;
+ std::cerr Reason: errmsg \n;
return 1;
}
Module mod = *M.get();
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[llvm-commits] CVS: llvm/lib/CodeGen/VirtRegMap.cpp LiveIntervalAnalysis.cpp
Changes in directory llvm/lib/CodeGen:
VirtRegMap.cpp updated: 1.105 - 1.106
LiveIntervalAnalysis.cpp updated: 1.227 - 1.228
---
Log message:
Fix for PR1266: http://llvm.org/PR1266 . Don't mark a two address operand
IsKill.
---
Diffs of the changes: (+33 -22)
LiveIntervalAnalysis.cpp |6 ++---
VirtRegMap.cpp | 49 ---
2 files changed, 33 insertions(+), 22 deletions(-)
Index: llvm/lib/CodeGen/VirtRegMap.cpp
diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.105
llvm/lib/CodeGen/VirtRegMap.cpp:1.106
--- llvm/lib/CodeGen/VirtRegMap.cpp:1.105 Tue Mar 20 03:13:50 2007
+++ llvm/lib/CodeGen/VirtRegMap.cpp Mon Mar 26 17:40:42 2007
@@ -754,10 +754,11 @@
// necessary.
bool WasKill = false;
if (SSMI) {
-MachineOperand *MOK = SSMI-findRegisterUseOperand(PhysReg, true);
-if (MOK) {
- WasKill = MOK-isKill();
- MOK-unsetIsKill();
+int UIdx = SSMI-findRegisterUseOperand(PhysReg, true);
+if (UIdx != -1) {
+ MachineOperand MOK = SSMI-getOperand(UIdx);
+ WasKill = MOK.isKill();
+ MOK.unsetIsKill();
}
}
if (ti == -1) {
@@ -840,17 +841,20 @@
// necessary.
bool WasKill = false;
if (SSMI) {
- MachineOperand *MOK = SSMI-findRegisterUseOperand(PhysReg, true);
- if (MOK) {
-WasKill = MOK-isKill();
-MOK-unsetIsKill();
+ int UIdx = SSMI-findRegisterUseOperand(PhysReg, true);
+ if (UIdx != -1) {
+MachineOperand MOK = SSMI-getOperand(UIdx);
+WasKill = MOK.isKill();
+MOK.unsetIsKill();
}
}
MachineInstr *CopyMI = prior(MII);
if (WasKill) {
// Transfer kill to the next use.
- MachineOperand *MOU = CopyMI-findRegisterUseOperand(PhysReg);
- MOU-setIsKill();
+ int UIdx = CopyMI-findRegisterUseOperand(PhysReg);
+ assert(UIdx != -1);
+ MachineOperand MOU = CopyMI-getOperand(UIdx);
+ MOU.setIsKill();
}
Spills.addLastUse(PhysReg, CopyMI);
@@ -945,18 +949,25 @@
// extended. Remove its kill.
bool WasKill = false;
if (SSMI) {
-MachineOperand *MOK = SSMI-findRegisterUseOperand(InReg,
true);
-if (MOK) {
- WasKill = MOK-isKill();
- MOK-unsetIsKill();
+int UIdx = SSMI-findRegisterUseOperand(InReg, true);
+if (UIdx != -1) {
+ MachineOperand MOK = SSMI-getOperand(UIdx);
+ WasKill = MOK.isKill();
+ MOK.unsetIsKill();
}
}
if (NextMII != MBB.end()) {
-// If NextMII uses InReg (must be the copy?), mark it killed.
-MachineOperand *MOU = NextMII-findRegisterUseOperand(InReg);
-if (MOU) {
- if (WasKill)
-MOU-setIsKill();
+// If NextMII uses InReg and the use is not a two address
+// operand, mark it killed.
+int UIdx = NextMII-findRegisterUseOperand(InReg);
+if (UIdx != -1) {
+ MachineOperand MOU = NextMII-getOperand(UIdx);
+ if (WasKill) {
+const TargetInstrDescriptor *NTID =
+ NextMII-getInstrDescriptor();
+if (NTID-getOperandConstraint(UIdx, TOI::TIED_TO) == -1)
+ MOU.setIsKill();
+ }
Spills.addLastUse(InReg, (*NextMII));
}
}
Index: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
diff -u llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.227
llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.228
--- llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.227 Wed Mar 21 20:26:05 2007
+++ llvm/lib/CodeGen/LiveIntervalAnalysis.cpp Mon Mar 26 17:40:42 2007
@@ -854,9 +854,9 @@
// If the source instruction was killing the source register before the
// merge, unset the isKill marker given the live range has been extended.
- MachineOperand *MOK = ValLREndInst-findRegisterUseOperand(IntB.reg, true);
- if (MOK)
-MOK-unsetIsKill();
+ int UIdx = ValLREndInst-findRegisterUseOperand(IntB.reg, true);
+ if (UIdx != -1)
+ValLREndInst-getOperand(UIdx).unsetIsKill();
// Finally, delete the copy instruction.
RemoveMachineInstrFromMaps(CopyMI);
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp ARMLoadStoreOptimizer.cpp
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.17 - 1.18
ARMLoadStoreOptimizer.cpp updated: 1.6 - 1.7
---
Log message:
findRegisterUseOperand() changed.
---
Diffs of the changes: (+3 -3)
ARMInstrInfo.cpp |4 ++--
ARMLoadStoreOptimizer.cpp |2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp
diff -u llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.17
llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.18
--- llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.17 Mon Mar 19 02:48:02 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.cppMon Mar 26 17:41:48 2007
@@ -278,8 +278,8 @@
for (unsigned j = 0; j 2; ++j) {
// Look at the two new MI's in reverse order.
MachineInstr *NewMI = NewMIs[j];
- MachineOperand *NMO = NewMI-findRegisterUseOperand(Reg);
- if (!NMO)
+ int NIdx = NewMI-findRegisterUseOperand(Reg);
+ if (NIdx != -1)
continue;
LV.addVirtualRegisterKilled(Reg, NewMI);
if (VI.removeKill(MI))
Index: llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
diff -u llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp:1.6
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp:1.7
--- llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp:1.6 Wed Mar 7 20:55:08 2007
+++ llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Mon Mar 26 17:41:48 2007
@@ -221,7 +221,7 @@
}
}
- bool BaseKill = Loc-findRegisterUseOperand(Base, true) != NULL;
+ bool BaseKill = Loc-findRegisterUseOperand(Base, true) != -1;
if (mergeOps(MBB, ++Loc, SOffset, Base, BaseKill, Opcode,Scratch,Regs, TII))
{
Merges.push_back(prior(Loc));
for (unsigned i = SIndex, e = MemOps.size(); i != e; ++i) {
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[llvm-commits] CVS: llvm/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll
Changes in directory llvm/test/CodeGen/ARM:
2007-03-26-RegScavengerAssert.ll added (r1.1)
---
Log message:
Test case for PR1266: http://llvm.org/PR1266 .
---
Diffs of the changes: (+948 -0)
2007-03-26-RegScavengerAssert.ll | 948 +++
1 files changed, 948 insertions(+)
Index: llvm/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll
diff -c /dev/null llvm/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll:1.1
*** /dev/null Mon Mar 26 17:58:45 2007
--- llvm/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll Mon Mar 26
17:58:35 2007
***
*** 0
--- 1,948
+ ; RUN: llvm-as %s | llc -march=arm
+ ; PR1266
+
+ target datalayout =
e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64
+ target triple = arm-linux-gnueabi
+ %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32 }
+ %struct.FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*,
i8*, i8*, %struct._IO_marker*, %struct.FILE*, i32, i32, i32, i16, i8, [1 x i8],
i8*, i64, i8*, i8*, i32, [52 x i8] }
+ %struct.VEC_edge = type { i32, i32, [1 x %struct.edge_def*] }
+ %struct.VEC_tree = type { i32, i32, [1 x %struct.tree_node*] }
+ %struct._IO_marker = type { %struct._IO_marker*, %struct.FILE*, i32 }
+ %struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] }
+ %struct.addr_diff_vec_flags = type { i8, i8, i8, i8 }
+ %struct.arm_stack_offsets = type { i32, i32, i32, i32, i32 }
+ %struct.attribute_spec = type { i8*, i32, i32, i8, i8, i8,
%struct.tree_node* (%struct.tree_node**, %struct.tree_node*,
%struct.tree_node*, i32, i8*)* }
+ %struct.basic_block_def = type { %struct.rtx_def*, %struct.rtx_def*,
%struct.tree_node*, %struct.VEC_edge*, %struct.VEC_edge*,
%struct.bitmap_head_def*, %struct.bitmap_head_def*, i8*, %struct.loop*, [2 x
%struct.et_node*], %struct.basic_block_def*, %struct.basic_block_def*,
%struct.reorder_block_def*, %struct.bb_ann_d*, i64, i32, i32, i32, i32 }
+ %struct.bb_ann_d = type { %struct.tree_node*, i8,
%struct.edge_prediction* }
+ %struct.bitmap_element_def = type { %struct.bitmap_element_def*,
%struct.bitmap_element_def*, i32, [4 x i32] }
+ %struct.bitmap_head_def = type { %struct.bitmap_element_def*,
%struct.bitmap_element_def*, i32, %struct.bitmap_obstack* }
+ %struct.bitmap_obstack = type { %struct.bitmap_element_def*,
%struct.bitmap_head_def*, %struct.obstack }
+ %struct.cgraph_edge = type { %struct.cgraph_node*,
%struct.cgraph_node*, %struct.cgraph_edge*, %struct.cgraph_edge*,
%struct.cgraph_edge*, %struct.cgraph_edge*, %struct.tree_node*, i8*, i8* }
+ %struct.cgraph_global_info = type { %struct.cgraph_node*, i32, i8 }
+ %struct.cgraph_local_info = type { i32, i8, i8, i8, i8, i8, i8, i8 }
+ %struct.cgraph_node = type { %struct.tree_node*, %struct.cgraph_edge*,
%struct.cgraph_edge*, %struct.cgraph_node*, %struct.cgraph_node*,
%struct.cgraph_node*, %struct.cgraph_node*, %struct.cgraph_node*,
%struct.cgraph_node*, %struct.cgraph_node*, i8*, %struct.cgraph_local_info,
%struct.cgraph_global_info, %struct.cgraph_rtl_info, i32, i8, i8, i8, i8, i8 }
+ %struct.cgraph_rtl_info = type { i32, i8, i8 }
+ %struct.cl_perfunc_opts = type { i8, i8, i8, i8, i8, i8, i8, i8, i8,
i8, i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.cselib_val_struct = type opaque
+ %struct.dataflow_d = type { %struct.varray_head_tag*, [2 x
%struct.tree_node*] }
+ %struct.def_operand_ptr = type { %struct.tree_node** }
+ %struct.def_optype_d = type { i32, [1 x %struct.def_operand_ptr] }
+ %struct.diagnostic_context = type { %struct.pretty_printer*, [8 x i32],
i8, i8, i8, void (%struct.diagnostic_context*, %struct.diagnostic_info*)*, void
(%struct.diagnostic_context*, %struct.diagnostic_info*)*, void (i8*, i8**)*,
%struct.tree_node*, i32, i32 }
+ %struct.diagnostic_info = type { %struct.text_info, %struct.location_t,
i32 }
+ %struct.die_struct = type opaque
+ %struct.edge_def = type { %struct.basic_block_def*,
%struct.basic_block_def*, %struct.edge_def_insns, i8*, %struct.location_t*,
i32, i32, i64, i32 }
+ %struct.edge_def_insns = type { %struct.rtx_def* }
+ %struct.edge_prediction = type { %struct.edge_prediction*,
%struct.edge_def*, i32, i32 }
+ %struct.eh_status = type opaque
+ %struct.elt_list = type opaque
+ %struct.elt_t = type { %struct.tree_node*, %struct.tree_node* }
+ %struct.emit_status = type { i32, i32, %struct.rtx_def*,
%struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*,
%struct.rtx_def** }
+ %struct.et_node = type opaque
+ %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*,
%struct.rtx_def*, %struct.rtx_def* }
+ %struct.function = type { %struct.eh_status*, %struct.expr_status*,
%struct.emit_status*,
[llvm-commits] CVS: llvm/lib/VMCore/Dominators.cpp
Changes in directory llvm/lib/VMCore:
Dominators.cpp updated: 1.80 - 1.81
---
Log message:
Use std::vectorDFCalculateWorkObject instead of
std::vectorDFCalculateWorkObject * to reduce malloc/free traffic.
---
Diffs of the changes: (+4 -7)
Dominators.cpp | 11 ---
1 files changed, 4 insertions(+), 7 deletions(-)
Index: llvm/lib/VMCore/Dominators.cpp
diff -u llvm/lib/VMCore/Dominators.cpp:1.80 llvm/lib/VMCore/Dominators.cpp:1.81
--- llvm/lib/VMCore/Dominators.cpp:1.80 Tue Mar 20 16:25:31 2007
+++ llvm/lib/VMCore/Dominators.cpp Mon Mar 26 18:17:19 2007
@@ -455,13 +455,12 @@
BasicBlock *BB = Node-getBlock();
DomSetType *Result = NULL;
- std::vectorDFCalculateWorkObject * workList;
+ std::vectorDFCalculateWorkObject workList;
std::setBasicBlock * visited;
- DFCalculateWorkObject *W = new DFCalculateWorkObject(BB, NULL, Node, NULL);
- workList.push_back(W);
+ workList.push_back(DFCalculateWorkObject(BB, NULL, Node, NULL));
do {
-DFCalculateWorkObject *currentW = workList.back();
+DFCalculateWorkObject *currentW = workList.back();
assert (currentW Missing work object.);
BasicBlock *currentBB = currentW-currentBB;
@@ -494,9 +493,7 @@
DominatorTree::Node *IDominee = *NI;
BasicBlock *childBB = IDominee-getBlock();
if (visited.count(childBB) == 0) {
-DFCalculateWorkObject *newW =
- new DFCalculateWorkObject(childBB, currentBB, IDominee, currentNode);
-workList.push_back(newW);
+workList.push_back(DFCalculateWorkObject(childBB, currentBB, IDominee,
currentNode));
visitChild = true;
}
}
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[llvm-commits] CVS: llvm/lib/VMCore/Dominators.cpp
Changes in directory llvm/lib/VMCore: Dominators.cpp updated: 1.81 - 1.82 --- Log message: It is not possible to determie dominance between two PHI nodes based on their ordering. --- Diffs of the changes: (+6 -0) Dominators.cpp |6 ++ 1 files changed, 6 insertions(+) Index: llvm/lib/VMCore/Dominators.cpp diff -u llvm/lib/VMCore/Dominators.cpp:1.81 llvm/lib/VMCore/Dominators.cpp:1.82 --- llvm/lib/VMCore/Dominators.cpp:1.81 Mon Mar 26 18:17:19 2007 +++ llvm/lib/VMCore/Dominators.cpp Mon Mar 26 18:18:28 2007 @@ -19,6 +19,7 @@ #include llvm/Assembly/Writer.h #include llvm/ADT/DepthFirstIterator.h #include llvm/ADT/SetOperations.h +#include llvm/Instructions.h #include algorithm using namespace llvm; @@ -265,6 +266,11 @@ BasicBlock *BBA = A-getParent(), *BBB = B-getParent(); if (BBA != BBB) return dominates(BBA, BBB); + // It is not possible to determie dominance between two PHI nodes + // based on their ordering. + if (isaPHINode(A) isaPHINode(B)) +return false; + // Loop through the basic block until we find A or B. BasicBlock::iterator I = BBA-begin(); for (; *I != A *I != B; ++I) /*empty*/; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
Changes in directory llvm/lib/Transforms/Utils:
PromoteMemoryToRegister.cpp updated: 1.95 - 1.96
---
Log message:
Reduce malloc/free traffic.
---
Diffs of the changes: (+8 -12)
PromoteMemoryToRegister.cpp | 20
1 files changed, 8 insertions(+), 12 deletions(-)
Index: llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
diff -u llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.95
llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.96
--- llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.95 Fri Mar 9
17:41:03 2007
+++ llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp Mon Mar 26
18:19:29 2007
@@ -77,7 +77,7 @@
class VISIBILITY_HIDDEN RenamePassData {
public:
RenamePassData(BasicBlock *B, BasicBlock *P,
- std::vectorValue * V) : BB(B), Pred(P), Values(V) {}
+ const std::vectorValue * V) : BB(B), Pred(P), Values(V)
{}
BasicBlock *BB;
BasicBlock *Pred;
std::vectorValue * Values;
@@ -123,7 +123,7 @@
DenseMapBasicBlock*, unsigned BBNumbers;
/// RenamePassWorkList - Worklist used by RenamePass()
-std::vectorRenamePassData * RenamePassWorkList;
+std::vectorRenamePassData RenamePassWorkList;
public:
PromoteMem2Reg(const std::vectorAllocaInst* A,
@@ -407,13 +407,12 @@
// and inserting the phi nodes we marked as necessary
//
RenamePassWorkList.clear();
- RenamePassData *RPD = new RenamePassData(F.begin(), 0, Values);
- RenamePassWorkList.push_back(RPD);
+ RenamePassWorkList.push_back(RenamePassData(F.begin(), 0, Values));
while(!RenamePassWorkList.empty()) {
-RenamePassData *RPD = RenamePassWorkList.back();
RenamePassWorkList.pop_back();
+RenamePassData RPD = RenamePassWorkList.back();
+RenamePassWorkList.pop_back();
// RenamePass may add new worklist entries.
-RenamePass(RPD-BB, RPD-Pred, RPD-Values);
-delete RPD;
+RenamePass(RPD.BB, RPD.Pred, RPD.Values);
}
// The renamer uses the Visited set to avoid infinite loops. Clear it now.
@@ -794,11 +793,8 @@
// Recurse to our successors.
TerminatorInst *TI = BB-getTerminator();
- for (unsigned i = 0; i != TI-getNumSuccessors(); i++) {
-RenamePassData *RPD = new RenamePassData(TI-getSuccessor(i), BB,
- IncomingVals);
-RenamePassWorkList.push_back(RPD);
- }
+ for (unsigned i = 0; i != TI-getNumSuccessors(); i++)
+RenamePassWorkList.push_back(RenamePassData(TI-getSuccessor(i), BB,
IncomingVals));
}
/// PromoteMemToReg - Promote the specified list of alloca instructions into
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.695 - 1.696 --- Log message: For PR1271: http://llvm.org/PR1271 : Fix another incorrectly converted shift mask. --- Diffs of the changes: (+1 -1) InstructionCombining.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.695 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.696 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.695 Mon Mar 26 15:40:50 2007 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Mon Mar 26 18:45:51 2007 @@ -5887,7 +5887,7 @@ BinaryOperator::createShl(X, ConstantInt::get(Ty, ShiftDiff)); InsertNewInstBefore(Shift, I); -APInt Mask(APInt::getHighBitsSet(TypeBits, TypeBits - ShiftAmt2)); +APInt Mask(APInt::getLowBitsSet(TypeBits, TypeBits - ShiftAmt2)); return BinaryOperator::createAnd(Shift, ConstantInt::get(Mask)); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Transforms/InstCombine/2007-03-26-BadShiftMask.ll
Changes in directory llvm/test/Transforms/InstCombine:
2007-03-26-BadShiftMask.ll added (r1.1)
---
Log message:
Another test case for PR1271: http://llvm.org/PR1271 where bad shift masks
were generated.
---
Diffs of the changes: (+35 -0)
2007-03-26-BadShiftMask.ll | 35 +++
1 files changed, 35 insertions(+)
Index: llvm/test/Transforms/InstCombine/2007-03-26-BadShiftMask.ll
diff -c /dev/null
llvm/test/Transforms/InstCombine/2007-03-26-BadShiftMask.ll:1.1
*** /dev/null Mon Mar 26 18:49:03 2007
--- llvm/test/Transforms/InstCombine/2007-03-26-BadShiftMask.ll Mon Mar 26
18:48:52 2007
***
*** 0
--- 1,35
+ ; PR1271
+ ; RUN: llvm-as %s | opt -instcombine | llvm-dis | \
+ ; RUN:grep 'ashr i32 %.mp137, 2'
+ target datalayout =
e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64
+ target triple = i686-pc-linux-gnu
+
+ implementation ; Functions:
+
+ define i1 @test(i32* %tmp141, i32* %tmp145,
+ i32 %b8, i32 %iftmp.430.0, i32* %tmp134.out, i32* %tmp137.out)
+ {
+ newFuncRoot:
+ %tmp133 = and i32 %b8, 1; i32 [#uses=1]
+ %tmp134 = shl i32 %tmp133, 3; i32 [#uses=3]
+ %tmp136 = ashr i32 %b8, 1 ; i32 [#uses=1]
+ %tmp137 = shl i32 %tmp136, 3; i32 [#uses=3]
+ %tmp139 = ashr i32 %tmp134, 2 ; i32 [#uses=1]
+ store i32 %tmp139, i32* %tmp141
+ %tmp143 = ashr i32 %tmp137, 2 ; i32 [#uses=1]
+ store i32 %tmp143, i32* %tmp145
+ icmp eq i32 %iftmp.430.0, 0 ; i1:0 [#uses=1]
+ zext i1 %0 to i8; i8:1 [#uses=1]
+ icmp ne i8 %1, 0; i1:2 [#uses=1]
+ br i1 %2, label %cond_true147.exitStub, label %cond_false252.exitStub
+
+ cond_true147.exitStub:; preds = %newFuncRoot
+ store i32 %tmp134, i32* %tmp134.out
+ store i32 %tmp137, i32* %tmp137.out
+ ret i1 true
+
+ cond_false252.exitStub: ; preds = %newFuncRoot
+ store i32 %tmp134, i32* %tmp134.out
+ store i32 %tmp137, i32* %tmp137.out
+ ret i1 false
+ }
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.696 - 1.697
---
Log message:
Implement some minor review feedback.
---
Diffs of the changes: (+3 -3)
InstructionCombining.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.696
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.697
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.696 Mon Mar 26
18:45:51 2007
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Mon Mar 26 18:58:26 2007
@@ -2455,7 +2455,7 @@
// Check to see if this is an unsigned division with an exact power of 2,
// if so, convert to a right shift.
if (ConstantInt *C = dyn_castConstantInt(Op1)) {
-if (!C-isZero() C-getValue().isPowerOf2()) // Don't break X / 0
+if (C-getValue().isPowerOf2()) // 0 not included in isPowerOf2
return BinaryOperator::createLShr(Op0,
ConstantInt::get(Op0-getType(), C-getValue().logBase2()));
}
@@ -3149,7 +3149,7 @@
// If the AndRHS is a power of two minus one (0+1+), and NMask == 0
if ((Mask-getValue().countLeadingZeros() +
Mask-getValue().countPopulation()) == Mask-getValue().getBitWidth()
- And(N, Mask)-isNullValue())
+ And(N, Mask)-isZero())
break;
return 0;
}
@@ -3180,7 +3180,7 @@
APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
if (SimplifyDemandedBits(I, APInt::getAllOnesValue(BitWidth),
KnownZero, KnownOne))
-return I;
+ return I;
} else {
if (ConstantVector *CP = dyn_castConstantVector(Op1)) {
if (CP-isAllOnesValue())
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[llvm-commits] CVS: llvm/lib/VMCore/Dominators.cpp
Changes in directory llvm/lib/VMCore: Dominators.cpp updated: 1.82 - 1.83 --- Log message: Spell check. --- Diffs of the changes: (+1 -1) Dominators.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/VMCore/Dominators.cpp diff -u llvm/lib/VMCore/Dominators.cpp:1.82 llvm/lib/VMCore/Dominators.cpp:1.83 --- llvm/lib/VMCore/Dominators.cpp:1.82 Mon Mar 26 18:18:28 2007 +++ llvm/lib/VMCore/Dominators.cpp Mon Mar 26 19:16:08 2007 @@ -266,7 +266,7 @@ BasicBlock *BBA = A-getParent(), *BBB = B-getParent(); if (BBA != BBB) return dominates(BBA, BBB); - // It is not possible to determie dominance between two PHI nodes + // It is not possible to determine dominance between two PHI nodes // based on their ordering. if (isaPHINode(A) isaPHINode(B)) return false; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/VirtRegMap.cpp
Changes in directory llvm/lib/CodeGen:
VirtRegMap.cpp updated: 1.106 - 1.107
---
Log message:
Don't call getOperandConstraint() if operand index is greater than
TID-numOperands.
---
Diffs of the changes: (+2 -1)
VirtRegMap.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/VirtRegMap.cpp
diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.106
llvm/lib/CodeGen/VirtRegMap.cpp:1.107
--- llvm/lib/CodeGen/VirtRegMap.cpp:1.106 Mon Mar 26 17:40:42 2007
+++ llvm/lib/CodeGen/VirtRegMap.cpp Mon Mar 26 19:48:28 2007
@@ -965,7 +965,8 @@
if (WasKill) {
const TargetInstrDescriptor *NTID =
NextMII-getInstrDescriptor();
-if (NTID-getOperandConstraint(UIdx, TOI::TIED_TO) == -1)
+if (UIdx = NTID-numOperands ||
+NTID-getOperandConstraint(UIdx, TOI::TIED_TO) == -1)
MOU.setIsKill();
}
Spills.addLastUse(InReg, (*NextMII));
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.394 - 1.395 --- Log message: SDISel does not preserve all, it changes CFG and other info. --- Diffs of the changes: (+0 -1) SelectionDAGISel.cpp |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.394 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.395 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.394Sun Mar 25 10:07:15 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Mar 26 19:53:36 2007 @@ -3776,7 +3776,6 @@ // updates dom and loop info. AU.addRequiredAliasAnalysis(); AU.addRequiredLoopInfo(); - AU.setPreservesAll(); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/docs/Passes.html
Changes in directory llvm/docs: Passes.html updated: 1.1 - 1.2 --- Log message: For PR601: http://llvm.org/PR601 : Add a little flesh to the document skeleton. --- Diffs of the changes: (+49 -7) Passes.html | 56 +--- 1 files changed, 49 insertions(+), 7 deletions(-) Index: llvm/docs/Passes.html diff -u llvm/docs/Passes.html:1.1 llvm/docs/Passes.html:1.2 --- llvm/docs/Passes.html:1.1 Mon Mar 26 04:32:31 2007 +++ llvm/docs/Passes.html Mon Mar 26 21:49:31 2007 @@ -477,7 +477,10 @@ a name=adceAggressive Dead Code Elimination/a /div div class=doc_text - pYet to be written./p + pADCE aggressively tries to eliminate code. This pass is similar to + a href=#dceDCE/a but it assumes that values are dead until proven + otherwise. This is similar to a href=#sccpSCCP/a, except applied to + the liveness of values./p /div !-- -- @@ -493,7 +496,21 @@ a name=block-placementProfile Guided Basic Block Placement/a /div div class=doc_text - pYet to be written./p + pThis pass implements a very simple profile guided basic block placement + algorithm. The idea is to put frequently executed blocks together at the + start of the function, and hopefully increase the number of fall-through + conditional branches. If there is no profile information for a particular + function, this pass basically orders blocks in depth-first order./p + pThe algorithm implemented here is basically Algo1 from Profile Guided + Code Positioning by Pettis and Hansen, except that it uses basic block + counts instead of edge counts. This could be improved in many ways, but is + very simple for now./p + pBasically we place the entry block, then loop over all successors in a + DFO, placing the most frequently executed successor until we run out of + blocks. Did we mention that this was bextremely/b simplistic? This is + also much slower than it could be. When it becomes important, this pass + will be rewritten to use a better algorithm, and then we can worry about + efficiency./p /div !-- -- @@ -509,7 +526,23 @@ a name=ceeCorrelated Expression Elimination/a /div div class=doc_text - pYet to be written./p + pCorrelated Expression Elimination propagates information from conditional + branches to blocks dominated by destinations of the branch. It propagates + information from the condition check itself into the body of the branch, + allowing transformations like these for example: + pre +if (i == 7) + ... 4*i; // constant propagation + +M = i+1; N = j+1; +if (i == j) + X = M-N; // = M-M == 0; + /pre/p + + pThis is called Correlated Expression Elimination because we eliminate or + simplify expressions that are correlated with the direction of a branch. In + this way we use static information to give us some information about the + dynamic value of a variable./p /div !-- -- @@ -517,7 +550,8 @@ a name=condpropConditional Propagation/a /div div class=doc_text - pYet to be written./p + pThis pass propagates information about conditional expressions through the + program, allowing it to eliminate conditional branches in some cases./p /div !-- -- @@ -530,10 +564,18 @@ !-- -- div class=doc_subsection - a name=constpropSimple constant propagation/a + a name=constpropConstant Propagation/a /div div class=doc_text - pYet to be written./p + pThis file implements constant propagation and merging. It looks for + instructions involving only constant operands and replaces them with a + constant value instead of an instruction. For example: + preadd i32 1, 2/prebr/ + becomes + prei32 3/pre/p + pNOTE: this pass has a habit of making definitions be dead. It is a good + idea to to run a a href=#dieDIE/a (Dead Instruction Elimination) pass + sometime after running this pass./p /div !-- -- @@ -977,7 +1019,7 @@ a href=mailto:[EMAIL PROTECTED]Reid Spencer/abr a href=http://llvm.org;LLVM Compiler Infrastructure/abr - Last modified: $Date: 2007/03/26 09:32:31 $ + Last modified: $Date: 2007/03/27 02:49:31 $ /address /body ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/docs/Makefile
Changes in directory llvm/docs:
Makefile updated: 1.13 - 1.14
---
Log message:
For PR1276: http://llvm.org/PR1276 :
Allow doxygen documentation to be rebuilt manually with make regendoc
separately from make install.
Patch by Scott Michel.
---
Diffs of the changes: (+4 -2)
Makefile |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/docs/Makefile
diff -u llvm/docs/Makefile:1.13 llvm/docs/Makefile:1.14
--- llvm/docs/Makefile:1.13 Sat Mar 3 18:45:50 2007
+++ llvm/docs/Makefile Tue Mar 27 01:06:15 2007
@@ -67,14 +67,16 @@
$(FIND) . -type f -exec \
$(DataInstall) {} $(PROJ_docsdir)/html/doxygen \;
-doxygen: $(PROJ_OBJ_DIR)/doxygen.tar.gz
+doxygen: regendoc $(PROJ_OBJ_DIR)/doxygen.tar.gz
-$(PROJ_OBJ_DIR)/doxygen.tar.gz: $(DOXYFILES) $(PROJ_OBJ_DIR)/doxygen.cfg
+regendoc:
$(Echo) Building doxygen documentation
$(Verb) if test -e $(PROJ_OBJ_DIR)/doxygen ; then \
$(RM) -rf $(PROJ_OBJ_DIR)/doxygen ; \
fi
$(Verb) $(DOXYGEN) $(PROJ_OBJ_DIR)/doxygen.cfg
+
+$(PROJ_OBJ_DIR)/doxygen.tar.gz: $(DOXYFILES) $(PROJ_OBJ_DIR)/doxygen.cfg
$(Echo) Packaging doxygen documentation
$(Verb) $(RM) -rf $@ $(PROJ_OBJ_DIR)/doxygen.tar
$(Verb) $(TAR) cf $(PROJ_OBJ_DIR)/doxygen.tar doxygen
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