[llvm-commits] CVS: llvm/lib/VMCore/Globals.cpp
Changes in directory llvm/lib/VMCore:
Globals.cpp updated: 1.22 - 1.23
---
Log message:
Fix typo. Interesting, but old variant worked too :)
---
Diffs of the changes: (+1 -1)
Globals.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/VMCore/Globals.cpp
diff -u llvm/lib/VMCore/Globals.cpp:1.22 llvm/lib/VMCore/Globals.cpp:1.23
--- llvm/lib/VMCore/Globals.cpp:1.22Sun Apr 29 13:02:48 2007
+++ llvm/lib/VMCore/Globals.cpp Mon Apr 30 05:28:40 2007
@@ -217,7 +217,7 @@
return GV;
else {
const ConstantExpr *CE = 0;
- if ((CE = dyn_castConstantExpr(Aliasee))
+ if ((CE = dyn_castConstantExpr(C))
(CE-getOpcode() == Instruction::BitCast))
return castGlobalValue(CE-getOperand(0));
else
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Re: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
Evan,
The problem is the semantics. A possible solution is rename
UseThumbBacktraces to UseThumbFramePtrReg.
Lauro
2007/4/27, Evan Cheng [EMAIL PROTECTED]:
Hi Lauro,
It would be better to fix ARMSubtarget.cpp instead. Just initialize
UseThumbBacktraces to the value of input parameter thumb to the
ARMSubtarget ctor.
Evan
On Apr 27, 2007, at 10:58 AM, Lauro Ramos Venancio wrote:
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.88 - 1.89
---
Log message:
In Thumb mode, the frame register must be R7.
---
Diffs of the changes: (+2 -2)
ARMRegisterInfo.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.88 llvm/lib/
Target/ARM/ARMRegisterInfo.cpp:1.89
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.88 Wed Apr 25
17:13:27 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Fri Apr 27 12:58:03 2007
@@ -85,7 +85,7 @@
const ARMSubtarget sti)
: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
TII(tii), STI(sti),
-FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) {
+FramePtr(STI.useThumbBacktraces() || STI.isThumb() ? ARM::R7 :
ARM::R11) {
}
bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock
MBB,
@@ -1472,7 +1472,7 @@
unsigned ARMRegisterInfo::getFrameRegister(MachineFunction MF)
const {
if (STI.isTargetDarwin() || hasFP(MF))
-return STI.useThumbBacktraces() ? ARM::R7 : ARM::R11;
+return STI.useThumbBacktraces() || STI.isThumb() ? ARM::R7 :
ARM::R11;
else
return ARM::SP;
}
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[llvm-commits] Patch for bug in llvm-ld
Hello!
I've been told to send this here. In tools/llvm-ld/llvm-ld.cpp,
line 360, a const char* to a temporary std::string is being
stored, with the string going out of scope right after, making
that pointer invalid.
std::string lib_name = -l + LinkItems[index].first;
args.push_back(lib_name.c_str());
end of scope
The attached patch fixes this in a simple way.
jlh
Index: llvm-ld.cpp
===
RCS file: /var/cvs/llvm/llvm/tools/llvm-ld/llvm-ld.cpp,v
retrieving revision 1.51
diff -u -r1.51 llvm-ld.cpp
--- llvm-ld.cpp 29 Apr 2007 23:59:47 - 1.51
+++ llvm-ld.cpp 30 Apr 2007 13:34:21 -
@@ -330,6 +330,9 @@
// We can't just assemble and link the file with the system assembler
// and linker because we don't know where to put the _start symbol.
// GCC mysteriously knows how to do it.
+
+ // args_temp is for storing temporary strings while we have a const char * to them
+ std::vectorstd::string args_temp;
std::vectorconst char* args;
args.push_back(gcc.c_str());
args.push_back(-fno-strict-aliasing);
@@ -354,8 +357,8 @@
for (unsigned index = 0; index LinkItems.size(); index++)
if (LinkItems[index].first != crtend) {
if (LinkItems[index].second) {
-std::string lib_name = -l + LinkItems[index].first;
-args.push_back(lib_name.c_str());
+args_temp.push_back(-l + LinkItems[index].first);
+args.push_back(args_temp.back().c_str());
} else
args.push_back(LinkItems[index].first.c_str());
}
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[llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp
Changes in directory llvm/lib/CodeGen:
AsmPrinter.cpp updated: 1.159 - 1.160
---
Log message:
Clean up multi-line asam string printing. Instead of printing:
# InlineAsm Start
subfc r3,r5,r4
subfze r4,r3
# InlineAsm End
print:
# InlineAsm Start
subfc r3,r5,r4
subfze r4,r3
# InlineAsm End
---
Diffs of the changes: (+1 -1)
AsmPrinter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.159
llvm/lib/CodeGen/AsmPrinter.cpp:1.160
--- llvm/lib/CodeGen/AsmPrinter.cpp:1.159 Sun Apr 29 13:02:48 2007
+++ llvm/lib/CodeGen/AsmPrinter.cpp Mon Apr 30 12:00:18 2007
@@ -954,7 +954,7 @@
}
case '\n':
++LastEmitted; // Consume newline character.
- O \n\t; // Indent code with newline.
+ O \n; // Indent code with newline.
break;
case '$': {
++LastEmitted; // Consume '$' character.
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.439 - 1.440
---
Log message:
refactor some code, no functionality change
---
Diffs of the changes: (+52 -44)
SelectionDAGISel.cpp | 96 +++
1 files changed, 52 insertions(+), 44 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.439
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.440
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.439Sun Apr 29
13:58:03 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr 30 12:16:27 2007
@@ -3134,44 +3134,6 @@
return RegsForValue();
}
-/// getConstraintGenerality - Return an integer indicating how general CT is.
-static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
- switch (CT) {
- default: assert(0 Unknown constraint type!);
- case TargetLowering::C_Other:
- case TargetLowering::C_Unknown:
-return 0;
- case TargetLowering::C_Register:
-return 1;
- case TargetLowering::C_RegisterClass:
-return 2;
- case TargetLowering::C_Memory:
-return 3;
- }
-}
-
-static std::string GetMostGeneralConstraint(std::vectorstd::string C,
-const TargetLowering TLI) {
- assert(!C.empty() Must have at least one constraint);
- if (C.size() == 1) return C[0];
-
- std::string *Current = C[0];
- // If we have multiple constraints, try to pick the most general one ahead
- // of time. This isn't a wonderful solution, but handles common cases.
- TargetLowering::ConstraintType Flavor = TLI.getConstraintType(Current[0]);
- for (unsigned j = 1, e = C.size(); j != e; ++j) {
-TargetLowering::ConstraintType ThisFlavor = TLI.getConstraintType(C[j]);
-if (getConstraintGenerality(ThisFlavor)
-getConstraintGenerality(Flavor)) {
- // This constraint letter is more general than the previous one,
- // use it.
- Flavor = ThisFlavor;
- Current = C[j];
-}
- }
- return *Current;
-}
-
namespace {
/// AsmOperandInfo - This contains information for each constraint that we are
/// lowering.
@@ -3197,9 +3159,59 @@
ConstraintType(TargetLowering::C_Unknown),
CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
}
+
+ void ComputeConstraintToUse(const TargetLowering TLI);
};
} // end anon namespace.
+/// getConstraintGenerality - Return an integer indicating how general CT is.
+static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
+ switch (CT) {
+default: assert(0 Unknown constraint type!);
+case TargetLowering::C_Other:
+case TargetLowering::C_Unknown:
+ return 0;
+case TargetLowering::C_Register:
+ return 1;
+case TargetLowering::C_RegisterClass:
+ return 2;
+case TargetLowering::C_Memory:
+ return 3;
+ }
+}
+
+void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering TLI) {
+ assert(!Codes.empty() Must have at least one constraint);
+
+ std::string *Current = Codes[0];
+ TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
+ if (Codes.size() == 1) { // Single-letter constraints ('r') are very
common.
+ConstraintCode = *Current;
+ConstraintType = CurType;
+return;
+ }
+
+ unsigned CurGenerality = getConstraintGenerality(CurType);
+
+ // If we have multiple constraints, try to pick the most general one ahead
+ // of time. This isn't a wonderful solution, but handles common cases.
+ for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
+TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
+unsigned ThisGenerality = getConstraintGenerality(ThisType);
+if (ThisGenerality CurGenerality) {
+ // This constraint letter is more general than the previous one,
+ // use it.
+ CurType = ThisType;
+ Current = Codes[j];
+ CurGenerality = ThisGenerality;
+}
+ }
+
+ ConstraintCode = *Current;
+ ConstraintType = CurType;
+}
+
+
/// visitInlineAsm - Handle a call to an InlineAsm object.
///
void SelectionDAGLowering::visitInlineAsm(CallInst I) {
@@ -3274,12 +3286,8 @@
OpInfo.ConstraintVT = OpVT;
-// Compute the constraint code to use.
-OpInfo.ConstraintCode = GetMostGeneralConstraint(OpInfo.Codes, TLI);
-
-// Compute the constraint type.
-// FIXME: merge this into GetMostGeneralConstraint.
-OpInfo.ConstraintType = TLI.getConstraintType(OpInfo.ConstraintCode);
+// Compute the constraint code and ConstraintType to use.
+OpInfo.ComputeConstraintToUse(TLI);
// If this is a memory input, and if the operand is not indirect, do what
we
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[llvm-commits] CVS: nightlytest-serverside/AcceptTestResults.php
Changes in directory nightlytest-serverside: AcceptTestResults.php updated: 1.1 - 1.2 --- Log message: Removed extra call to function. --- Diffs of the changes: (+1 -2) AcceptTestResults.php |3 +-- 1 files changed, 1 insertion(+), 2 deletions(-) Index: nightlytest-serverside/AcceptTestResults.php diff -u nightlytest-serverside/AcceptTestResults.php:1.1 nightlytest-serverside/AcceptTestResults.php:1.2 --- nightlytest-serverside/AcceptTestResults.php:1.1Sun Apr 29 13:56:27 2007 +++ nightlytest-serverside/AcceptTestResults.phpMon Apr 30 12:28:47 2007 @@ -548,5 +548,4 @@ shutdown($mysql_link); } -acceptTestResults(); -? \ No newline at end of file +? ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.440 - 1.441
---
Log message:
refactor GetRegistersForValue to take OpInfo as an argument instead of various
pieces of it. No functionality change.
---
Diffs of the changes: (+101 -98)
SelectionDAGISel.cpp | 199 +--
1 files changed, 101 insertions(+), 98 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.440
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.441
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.440Mon Apr 30
12:16:27 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr 30 12:29:31 2007
@@ -82,6 +82,8 @@
createDefaultScheduler);
} // namespace
+namespace { struct AsmOperandInfo; }
+
namespace {
/// RegsForValue - This struct represents the physical registers that a
/// particular value is assigned and the type information about the value.
@@ -516,8 +518,7 @@
N = NewN;
}
- RegsForValue GetRegistersForValue(const std::string ConstrCode,
-MVT::ValueType VT,
+ RegsForValue GetRegistersForValue(AsmOperandInfo OpInfo,
bool OutReg, bool InReg,
std::setunsigned OutputRegs,
std::setunsigned InputRegs);
@@ -3013,23 +3014,105 @@
return FoundRC;
}
+
+namespace {
+/// AsmOperandInfo - This contains information for each constraint that we are
+/// lowering.
+struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
+ /// ConstraintCode - This contains the actual string for the code, like m.
+ std::string ConstraintCode;
+
+ /// ConstraintType - Information about the constraint code, e.g. Register,
+ /// RegisterClass, Memory, Other, Unknown.
+ TargetLowering::ConstraintType ConstraintType;
+
+ /// CallOperand/CallOperandval - If this is the result output operand or a
+ /// clobber, this is null, otherwise it is the incoming operand to the
+ /// CallInst. This gets modified as the asm is processed.
+ SDOperand CallOperand;
+ Value *CallOperandVal;
+
+ /// ConstraintVT - The ValueType for the operand value.
+ MVT::ValueType ConstraintVT;
+
+ AsmOperandInfo(const InlineAsm::ConstraintInfo info)
+: InlineAsm::ConstraintInfo(info),
+ ConstraintType(TargetLowering::C_Unknown),
+ CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
+ }
+
+ void ComputeConstraintToUse(const TargetLowering TLI);
+};
+} // end anon namespace.
+
+/// getConstraintGenerality - Return an integer indicating how general CT is.
+static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
+ switch (CT) {
+default: assert(0 Unknown constraint type!);
+case TargetLowering::C_Other:
+case TargetLowering::C_Unknown:
+ return 0;
+case TargetLowering::C_Register:
+ return 1;
+case TargetLowering::C_RegisterClass:
+ return 2;
+case TargetLowering::C_Memory:
+ return 3;
+ }
+}
+
+void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering TLI) {
+ assert(!Codes.empty() Must have at least one constraint);
+
+ std::string *Current = Codes[0];
+ TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
+ if (Codes.size() == 1) { // Single-letter constraints ('r') are very
common.
+ConstraintCode = *Current;
+ConstraintType = CurType;
+return;
+ }
+
+ unsigned CurGenerality = getConstraintGenerality(CurType);
+
+ // If we have multiple constraints, try to pick the most general one ahead
+ // of time. This isn't a wonderful solution, but handles common cases.
+ for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
+TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
+unsigned ThisGenerality = getConstraintGenerality(ThisType);
+if (ThisGenerality CurGenerality) {
+ // This constraint letter is more general than the previous one,
+ // use it.
+ CurType = ThisType;
+ Current = Codes[j];
+ CurGenerality = ThisGenerality;
+}
+ }
+
+ ConstraintCode = *Current;
+ ConstraintType = CurType;
+}
+
+
RegsForValue SelectionDAGLowering::
-GetRegistersForValue(const std::string ConstrCode,
- MVT::ValueType VT, bool isOutReg, bool isInReg,
+GetRegistersForValue(AsmOperandInfo OpInfo, bool isOutReg, bool isInReg,
std::setunsigned OutputRegs,
std::setunsigned InputRegs) {
std::pairunsigned, const TargetRegisterClass* PhysReg =
-TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
+
TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,OpInfo.ConstraintVT);
std::vectorunsigned Regs;
- unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
+ unsigned NumRegs = 1;
+ if
[llvm-commits] CVS: nightlytest-serverside/AcceptTestResults.php
Changes in directory nightlytest-serverside:
AcceptTestResults.php updated: 1.2 - 1.3
---
Log message:
Adding target triple.
---
Diffs of the changes: (+7 -1)
AcceptTestResults.php |8 +++-
1 files changed, 7 insertions(+), 1 deletion(-)
Index: nightlytest-serverside/AcceptTestResults.php
diff -u nightlytest-serverside/AcceptTestResults.php:1.2
nightlytest-serverside/AcceptTestResults.php:1.3
--- nightlytest-serverside/AcceptTestResults.php:1.2Mon Apr 30 12:28:47 2007
+++ nightlytest-serverside/AcceptTestResults.phpMon Apr 30 13:05:20 2007
@@ -367,7 +367,7 @@
$machine_data = $_POST['machine_data'];
if (!isset($_POST['machine_data'])) {
- shutdown();
+ shutdown($mysql_link);
}
$MACHINE_DATA = split(\n, $machine_data);
@@ -379,6 +379,12 @@
$time = matchOne(/time\:\s*(.+)/, $MACHINE_DATA[5], );
$nickname = $_POST['nickname'];
+if(!isset($_POST['target_triple'])) {
+ shutdown($mysql_link);
+}
+
+$targetTriple = $_POST['target_triple'];
+
//Get machine id or add new machine
$machineId = getMachineID($targetTriple, $hostname, $nickname);
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[llvm-commits] CVS: llvm/lib/CodeGen/README.txt
Changes in directory llvm/lib/CodeGen: README.txt updated: 1.4 - 1.5 --- Log message: Updates. --- Diffs of the changes: (+57 -1) README.txt | 58 +- 1 files changed, 57 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/README.txt diff -u llvm/lib/CodeGen/README.txt:1.4 llvm/lib/CodeGen/README.txt:1.5 --- llvm/lib/CodeGen/README.txt:1.4 Mon Apr 16 13:10:22 2007 +++ llvm/lib/CodeGen/README.txt Mon Apr 30 13:42:09 2007 @@ -85,4 +85,60 @@ //===-===// -Re-Materialize load from frame index. +Use local info (i.e. register scavenger) to assign it a free register to allow +reuse: + ldr r3, [sp, #+4] + add r3, r3, #3 + ldr r2, [sp, #+8] + add r2, r2, #2 + ldr r1, [sp, #+4] == + add r1, r1, #1 + ldr r0, [sp, #+4] + add r0, r0, #2 + +//===-===// + +LLVM aggressively lift CSE out of loop. Sometimes this can be negative side- +effects: + +R1 = X + 4 +R2 = X + 7 +R3 = X + 15 + +loop: +load [i + R1] +... +load [i + R2] +... +load [i + R3] + +Suppose there is high register pressure, R1, R2, R3, can be spilled. We need +to implement proper re-materialization to handle this: + +R1 = X + 4 +R2 = X + 7 +R3 = X + 15 + +loop: +R1 = X + 4 @ re-materialized +load [i + R1] +... +R2 = X + 7 @ re-materialized +load [i + R2] +... +R3 = X + 15 @ re-materialized +load [i + R3] + +Furthermore, with re-association, we can enable sharing: + +R1 = X + 4 +R2 = X + 7 +R3 = X + 15 + +loop: +T = i + X +load [T + 4] +... +load [T + 7] +... +load [T + 15] ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: nightlytest-serverside/AcceptTestResults.php
Changes in directory nightlytest-serverside:
AcceptTestResults.php updated: 1.3 - 1.4
---
Log message:
target triple not require for now.
---
Diffs of the changes: (+0 -4)
AcceptTestResults.php |4
1 files changed, 4 deletions(-)
Index: nightlytest-serverside/AcceptTestResults.php
diff -u nightlytest-serverside/AcceptTestResults.php:1.3
nightlytest-serverside/AcceptTestResults.php:1.4
--- nightlytest-serverside/AcceptTestResults.php:1.3Mon Apr 30 13:05:20 2007
+++ nightlytest-serverside/AcceptTestResults.phpMon Apr 30 14:12:42 2007
@@ -379,10 +379,6 @@
$time = matchOne(/time\:\s*(.+)/, $MACHINE_DATA[5], );
$nickname = $_POST['nickname'];
-if(!isset($_POST['target_triple'])) {
- shutdown($mysql_link);
-}
-
$targetTriple = $_POST['target_triple'];
//Get machine id or add new machine
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[llvm-commits] [126737] Fix the race condition where a dylib is used before it' s actually created.
Revision: 126737
Author: bwendlin
Date: 2007-04-30 12:14:35 -0700 (Mon, 30 Apr 2007)
Log Message:
---
Fix the race condition where a dylib is used before it's actually created.
Naming it a unique name for each stage will fix this.
Modified Paths:
--
apple-local/branches/llvm/gcc/Makefile.in
Modified: apple-local/branches/llvm/gcc/Makefile.in
===
--- apple-local/branches/llvm/gcc/Makefile.in 2007-04-30 19:04:35 UTC (rev
126736)
+++ apple-local/branches/llvm/gcc/Makefile.in 2007-04-30 19:14:35 UTC (rev
126737)
@@ -1124,16 +1124,16 @@
# llvm-linker-hack.cpp
DYLIB_COMPILE_FLAGS := $(filter-out -mdynamic-no-pic, \
$(ALL_CXXFLAGS) $(ALL_CPPFLAGS))
-libllvmgcc.dylib: llvm-linker-hack.cpp $(LLVMLIBFILES)
+libllvmgcc$(LLVM_STAGE).dylib: llvm-linker-hack.cpp $(LLVMLIBFILES)
echo $(LLVMLIBFILES)
$(CXX) $(DYLIB_COMPILE_FLAGS) $(INCLUDES) -o $@ \
$ $(LLVMLIBFILES) -dynamiclib -single_module \
-install_name @executable_path/$@
-LLVMBACKENDFILES := libllvmgcc.dylib
+LLVMBACKENDFILES := libllvmgcc$(LLVM_STAGE).dylib
# Make sure that 'make install' knows about the dylib.
-EXTRA_PROGRAMS += libllvmgcc.dylib
+EXTRA_PROGRAMS += libllvmgcc$(LLVM_STAGE).dylib
# APPLE LOCAL begin LLVM - set DYLD path
SET_DYLIB_PATH=1
@@ -4073,7 +4073,8 @@
$(MAKE) CC=$(CC) libdir=$(libdir) LANGUAGES=$(BOOT_LANGUAGES) \
CFLAGS=$(STAGE1_CFLAGS) $(STAGE1_CHECKING) \
MAKEINFO=$(MAKEINFO) MAKEINFOFLAGS=$(MAKEINFOFLAGS) \
- COVERAGE_FLAGS= OBJS-onestep=$(OBJS)
+ COVERAGE_FLAGS= OBJS-onestep=$(OBJS) \
+ LLVM_STAGE=-stage1
$(STAMP) stage1_build
echo stage1_build stage_last
@@ -4083,13 +4084,11 @@
echo stage2_build stage_last
stage2_build: stage1_copy
- if test ${SET_DYLIB_PATH} = 1; then \
- DYLD_LIBRARY_PATH=`${PWD_COMMAND}`/stage1; \
- fi; \
$(MAKE) CC=$(STAGE_CC_WRAPPER) stage1/xgcc$(exeext) -Bstage1/
-B$(build_tooldir)/bin/ CC_FOR_BUILD=$(STAGE_CC_WRAPPER) stage1/xgcc$(exeext)
-Bstage1/ -B$(build_tooldir)/bin/ \
STAGE_PREFIX=stage1/ \
$(POSTSTAGE1_FLAGS_TO_PASS) \
-$(STAGE2_FLAGS_TO_PASS)
+$(STAGE2_FLAGS_TO_PASS) \
+LLVM_STAGE=-stage2
$(STAMP) stage2_build
echo stage2_build stage_last
@@ -4099,13 +4098,11 @@
echo stage3_build stage_last
stageprofile_build: stage1_copy
- if test ${SET_DYLIB_PATH} = 1; then \
- DYLD_LIBRARY_PATH=`${PWD_COMMAND}`/stage1; \
- fi; \
$(MAKE) CC=$(STAGE_CC_WRAPPER) stage1/xgcc$(exeext) -Bstage1/
-B$(build_tooldir)/bin/ CC_FOR_BUILD=$(STAGE_CC_WRAPPER) stage1/xgcc$(exeext)
-Bstage1/ -B$(build_tooldir)/bin/ \
STAGE_PREFIX=stage1/ \
$(POSTSTAGE1_FLAGS_TO_PASS) \
-$(STAGEPROFILE_FLAGS_TO_PASS)
+$(STAGEPROFILE_FLAGS_TO_PASS) \
+LLVM_STAGE=-stage_profile
$(STAMP) stageprofile_build
echo stageprofile_build stage_last
@@ -4115,24 +4112,20 @@
echo stagefeedback_build stage_last
stage3_build: stage2_copy
- if test ${SET_DYLIB_PATH} = 1; then \
- DYLD_LIBRARY_PATH=`${PWD_COMMAND}`/stage2; \
- fi; \
$(MAKE) CC=$(STAGE_CC_WRAPPER) stage2/xgcc$(exeext) -Bstage2/
-B$(build_tooldir)/bin/ CC_FOR_BUILD=$(STAGE_CC_WRAPPER) stage2/xgcc$(exeext)
-Bstage2/ -B$(build_tooldir)/bin/ \
STAGE_PREFIX=stage2/ \
$(POSTSTAGE1_FLAGS_TO_PASS) \
-$(STAGE2_FLAGS_TO_PASS)
+$(STAGE2_FLAGS_TO_PASS) \
+LLVM_STAGE=
$(STAMP) stage3_build
echo stage3_build stage_last
stagefeedback_build: stageprofile_copy stage1_copy
- if test ${SET_DYLIB_PATH} = 1; then \
- DYLD_LIBRARY_PATH=`${PWD_COMMAND}`/stage1; \
- fi; \
$(MAKE) CC=$(STAGE_CC_WRAPPER) stage1/xgcc$(exeext) -Bstage1/
-B$(build_tooldir)/bin/ CC_FOR_BUILD=$(STAGE_CC_WRAPPER) stage1/xgcc$(exeext)
-Bstage1/ -B$(build_tooldir)/bin/ \
STAGE_PREFIX=stage1/ \
$(POSTSTAGE1_FLAGS_TO_PASS) \
-$(STAGEFEEDBACK_FLAGS_TO_PASS)
+$(STAGEFEEDBACK_FLAGS_TO_PASS) \
+LLVM_STAGE=-stage_feedback
$(STAMP) stagefeedback_build
echo stagefeedback_build stage_last
@@ -4148,9 +4141,6 @@
echo stage4_build stage_last
stage4_build: stage3_copy
- if test ${SET_DYLIB_PATH} = 1; then \
- DYLD_LIBRARY_PATH=`${PWD_COMMAND}`/stage3; \
- fi; \
$(MAKE) CC=$(STAGE_CC_WRAPPER) stage3/xgcc$(exeext) -Bstage3/
-B$(build_tooldir)/bin/ CC_FOR_BUILD=$(STAGE_CC_WRAPPER) stage3/xgcc$(exeext)
-Bstage3/ -B$(build_tooldir)/bin/ \
STAGE_PREFIX=stage3/ \
[llvm-commits] CVS: llvm/include/llvm/GlobalValue.h
Changes in directory llvm/include/llvm: GlobalValue.h updated: 1.41 - 1.42 --- Log message: Fix comment --- Diffs of the changes: (+4 -3) GlobalValue.h |7 --- 1 files changed, 4 insertions(+), 3 deletions(-) Index: llvm/include/llvm/GlobalValue.h diff -u llvm/include/llvm/GlobalValue.h:1.41 llvm/include/llvm/GlobalValue.h:1.42 --- llvm/include/llvm/GlobalValue.h:1.41Sun Apr 29 13:35:00 2007 +++ llvm/include/llvm/GlobalValue.h Mon Apr 30 14:14:56 2007 @@ -8,9 +8,10 @@ //===--===// // // This file is a common base class of all globally definable objects. As such, -// it is subclassed by GlobalVariable and by Function. This is used because you -// can do certain things with these global objects that you can't do to anything -// else. For example, use the address of one as a constant. +// it is subclassed by GlobalVariable, GlobalAlias and by Function. This is +// used because you can do certain things with these global objects that you +// can't do to anything else. For example, use the address of one as a +// constant. // //===--===// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
That's fine. Thanks.
Evan
On Apr 30, 2007, at 6:55 AM, Lauro Ramos Venancio wrote:
Evan,
The problem is the semantics. A possible solution is rename
UseThumbBacktraces to UseThumbFramePtrReg.
Lauro
2007/4/27, Evan Cheng [EMAIL PROTECTED]:
Hi Lauro,
It would be better to fix ARMSubtarget.cpp instead. Just initialize
UseThumbBacktraces to the value of input parameter thumb to the
ARMSubtarget ctor.
Evan
On Apr 27, 2007, at 10:58 AM, Lauro Ramos Venancio wrote:
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.88 - 1.89
---
Log message:
In Thumb mode, the frame register must be R7.
---
Diffs of the changes: (+2 -2)
ARMRegisterInfo.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp: 1.88 llvm/lib/
Target/ARM/ARMRegisterInfo.cpp:1.89
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.88 Wed Apr 25
17:13:27 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Fri Apr 27 12:58:03
2007
@@ -85,7 +85,7 @@
const ARMSubtarget sti)
: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
TII(tii), STI(sti),
-FramePtr( STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) {
+FramePtr(STI.useThumbBacktraces() || STI.isThumb() ? ARM::R7 :
ARM::R11) {
}
bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock
MBB,
@@ -1472,7 +1472,7 @@
unsigned ARMRegisterInfo::getFrameRegister(MachineFunction MF)
const {
if (STI.isTargetDarwin() || hasFP(MF))
-return STI.useThumbBacktraces () ? ARM::R7 : ARM::R11;
+return STI.useThumbBacktraces() || STI.isThumb() ? ARM::R7 :
ARM::R11;
else
return ARM::SP;
}
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/ELFRelocation.h
Changes in directory llvm/include/llvm/CodeGen:
ELFRelocation.h added (r1.1)
---
Log message:
Header file for ELF relocations.
---
Diffs of the changes: (+49 -0)
ELFRelocation.h | 49 +
1 files changed, 49 insertions(+)
Index: llvm/include/llvm/CodeGen/ELFRelocation.h
diff -c /dev/null llvm/include/llvm/CodeGen/ELFRelocation.h:1.1
*** /dev/null Mon Apr 30 15:41:18 2007
--- llvm/include/llvm/CodeGen/ELFRelocation.h Mon Apr 30 15:41:08 2007
***
*** 0
--- 1,49
+ //=== ELFRelocation.h - ELF Relocation Info -*- C++
-*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Christopher Lamb and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+
//===--===//
+ //
+ // This file defines the ELFRelocation class.
+ //
+
//===--===//
+
+ #ifndef LLVM_CODEGEN_ELF_RELOCATION_H
+ #define LLVM_CODEGEN_ELF_RELOCATION_H
+
+ namespace llvm {
+
+ /// ELFRelocation - This class contains all the information necessary to
+ /// to generate any 32-bit or 64-bit ELF relocation entry.
+ class ELFRelocation {
+ uint64_t r_offset;// offset in the section of the object this applies
to
+ uint32_t r_symidx;// symbol table index of the symbol to use
+ uint32_t r_type; // machine specific relocation type
+ int64_t r_add; // explicit relocation addend
+ bool r_rela; // if true then the addend is part of the entry
+ // otherwise the addend is at the location specified
+ // by r_offset
+ public:
+
+ uint64_t getInfo(bool is64Bit = false) const {
+ if (is64Bit)
+ return ((uint64_t)r_symidx 32) + ((uint64_t)r_type 0xL);
+ else
+ return (r_symidx 8) + (r_type 0xFFL);
+ }
+
+ uint64_t getOffset() const { return r_offset; }
+ uint64_t getAddress() const { return r_add; }
+
+ ELFRelocation(uint64_t off, uint32_t sym, uint32_t type,
+ bool rela = true, int64_t addend = 0) :
+ r_offset(off), r_symidx(sym), r_type(type),
+ r_add(addend), r_rela(rela) {}
+ };
+
+ } // end llvm namespace
+
+ #endif // LLVM_CODEGEN_ELF_RELOCATION_H
\ No newline at end of file
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[llvm-commits] CVS: llvm/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
Changes in directory llvm/test/CodeGen/PowerPC:
2007-04-30-InlineAsmEarlyClobber.ll added (r1.1)
---
Log message:
testcase for PR1357: http://llvm.org/PR1357
---
Diffs of the changes: (+27 -0)
2007-04-30-InlineAsmEarlyClobber.ll | 27 +++
1 files changed, 27 insertions(+)
Index: llvm/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
diff -c /dev/null
llvm/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll:1.1
*** /dev/null Mon Apr 30 16:10:23 2007
--- llvm/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll Mon Apr
30 16:10:13 2007
***
*** 0
--- 1,27
+ ; RUN: llvm-as %s | llc | grep {subfc r2,r5,r4}
+ ; RUN: llvm-as %s | llc | grep {subfze r4,r3}
+
+ ; PR1357
+
+ target datalayout =
E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64
+ target triple = powerpc-apple-darwin8.8.0
+
+ ;long long test(int A, int B, int C) {
+ ; unsigned X, Y;
+ ; __asm__ (subf%I3c %1,%4,%3\n\tsubfze %0,%2
+ ; : =r (X), =r (Y)
+ ; : r (A), rI (B), r (C));
+ ; return ((long long)Y 32) | X;
+ ;}
+
+ define i64 @test(i32 %A, i32 %B, i32 %C) {
+ entry:
+ %Y = alloca i32, align 4; i32* [#uses=2]
+ %tmp4 = call i32 asm subf${3:I}c $1,$4,$3\0A\09subfze $0,$2,
=r,=*r,r,rI,r( i32* %Y, i32 %A, i32 %B, i32 %C ) ; i32
[#uses=1]
+ %tmp5 = load i32* %Y; i32 [#uses=1]
+ %tmp56 = zext i32 %tmp5 to i64 ; i64 [#uses=1]
+ %tmp7 = shl i64 %tmp56, 32 ; i64 [#uses=1]
+ %tmp89 = zext i32 %tmp4 to i64 ; i64 [#uses=1]
+ %tmp10 = or i64 %tmp7, %tmp89 ; i64 [#uses=1]
+ ret i64 %tmp10
+ }
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.441 - 1.442
---
Log message:
Continue refactoring inline asm code. If there is an earlyclobber output
register, preallocate all input registers and the early clobbered output.
This fixes PR1357: http://llvm.org/PR1357 and
CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
---
Diffs of the changes: (+108 -79)
SelectionDAGISel.cpp | 187 +--
1 files changed, 108 insertions(+), 79 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.441
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.442
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.441Mon Apr 30
12:29:31 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr 30 16:11:17 2007
@@ -518,10 +518,9 @@
N = NewN;
}
- RegsForValue GetRegistersForValue(AsmOperandInfo OpInfo,
-bool OutReg, bool InReg,
-std::setunsigned OutputRegs,
-std::setunsigned InputRegs);
+ void GetRegistersForValue(AsmOperandInfo OpInfo, bool HasEarlyClobber,
+std::setunsigned OutputRegs,
+std::setunsigned InputRegs);
void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
@@ -3035,6 +3034,10 @@
/// ConstraintVT - The ValueType for the operand value.
MVT::ValueType ConstraintVT;
+ /// AssignedRegs - If this is a register or register class operand, this
+ /// contains the set of register corresponding to the operand.
+ RegsForValue AssignedRegs;
+
AsmOperandInfo(const InlineAsm::ConstraintInfo info)
: InlineAsm::ConstraintInfo(info),
ConstraintType(TargetLowering::C_Unknown),
@@ -3042,6 +3045,17 @@
}
void ComputeConstraintToUse(const TargetLowering TLI);
+
+ /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
+ /// busy in OutputRegs/InputRegs.
+ void MarkAllocatedRegs(bool isOutReg, bool isInReg,
+ std::setunsigned OutputRegs,
+ std::setunsigned InputRegs) const {
+ if (isOutReg)
+ OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
+ if (isInReg)
+ InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
+ }
};
} // end anon namespace.
@@ -3093,13 +3107,42 @@
}
-RegsForValue SelectionDAGLowering::
-GetRegistersForValue(AsmOperandInfo OpInfo, bool isOutReg, bool isInReg,
+void SelectionDAGLowering::
+GetRegistersForValue(AsmOperandInfo OpInfo, bool HasEarlyClobber,
std::setunsigned OutputRegs,
std::setunsigned InputRegs) {
- std::pairunsigned, const TargetRegisterClass* PhysReg =
-
TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,OpInfo.ConstraintVT);
+ // Compute whether this value requires an input register, an output register,
+ // or both.
+ bool isOutReg = false;
+ bool isInReg = false;
+ switch (OpInfo.Type) {
+ case InlineAsm::isOutput:
+isOutReg = true;
+
+// If this is an early-clobber output, or if there is an input
+// constraint that matches this, we need to reserve the input register
+// so no other inputs allocate to it.
+isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
+break;
+ case InlineAsm::isInput:
+isInReg = true;
+isOutReg = false;
+break;
+ case InlineAsm::isClobber:
+isOutReg = true;
+isInReg = true;
+break;
+ }
+
+
+ MachineFunction MF = DAG.getMachineFunction();
std::vectorunsigned Regs;
+
+ // If this is a constraint for a single physreg, or a constraint for a
+ // register class, find it.
+ std::pairunsigned, const TargetRegisterClass* PhysReg =
+TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
+ OpInfo.ConstraintVT);
unsigned NumRegs = 1;
if (OpInfo.ConstraintVT != MVT::Other)
@@ -3107,7 +3150,6 @@
MVT::ValueType RegVT;
MVT::ValueType ValueVT = OpInfo.ConstraintVT;
- MachineFunction MF = DAG.getMachineFunction();
// If this is a constraint for a specific physical register, like {r17},
// assign it now.
@@ -3137,7 +3179,9 @@
Regs.push_back(*I);
}
}
-return RegsForValue(Regs, RegVT, ValueVT);
+OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
+OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
+return;
}
// Otherwise, if this was a reference to an LLVM register class, create vregs
@@ -3147,7 +3191,11 @@
// If this is an early clobber or tied register, our regalloc doesn't know
// how to maintain the constraint. If it isn't, go ahead and create vreg
// and let the
[llvm-commits] [126738] This function isn't used when ENABLE_LLVM is defined.
Revision: 126738
Author: bwendlin
Date: 2007-04-30 14:36:53 -0700 (Mon, 30 Apr 2007)
Log Message:
---
This function isn't used when ENABLE_LLVM is defined.
Modified Paths:
--
apple-local/branches/llvm/gcc/varasm.c
Modified: apple-local/branches/llvm/gcc/varasm.c
===
--- apple-local/branches/llvm/gcc/varasm.c 2007-04-30 19:14:35 UTC (rev
126737)
+++ apple-local/branches/llvm/gcc/varasm.c 2007-04-30 21:36:53 UTC (rev
126738)
@@ -4634,6 +4634,8 @@
/* Given an assembly name, find the decl it is associated with. At the
same time, mark it needed for cgraph. */
+/* APPLE LOCAL LLVM */
+#ifndef ENABLE_LLVM
static tree
find_decl_and_mark_needed (tree decl, tree target)
{
@@ -4671,6 +4673,8 @@
else
return NULL_TREE;
}
+/* APPLE LOCAL LLVM */
+#endif
static void
do_assemble_alias (tree decl, tree target)
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Re: [llvm-commits] CVS: llvm/include/llvm/CodeGen/ELFRelocation.h
Header file for ELF relocations.
Oooh cool
+ #ifndef LLVM_CODEGEN_ELF_RELOCATION_H
+ #define LLVM_CODEGEN_ELF_RELOCATION_H
Please #include llvm/Support/DataTypes.h, since this file uses
int64_t etc.
+
+ namespace llvm {
...
+ ELFRelocation(uint64_t off, uint32_t sym, uint32_t type,
+ bool rela = true, int64_t addend = 0) :
+ r_offset(off), r_symidx(sym), r_type(type),
+ r_add(addend), r_rela(rela) {}
+ };
+
+ } // end llvm namespace
+
+ #endif // LLVM_CODEGEN_ELF_RELOCATION_H
\ No newline at end of file
Please add a newline at eof :)
-Chris
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[llvm-commits] [126740] Don't strip the libstdc++.dylib thingy.
Revision: 126740 Author: bwendlin Date: 2007-04-30 15:37:52 -0700 (Mon, 30 Apr 2007) Log Message: --- Don't strip the libstdc++.dylib thingy. Modified Paths: -- apple-local/branches/llvm/build_gcc Modified: apple-local/branches/llvm/build_gcc === --- apple-local/branches/llvm/build_gcc 2007-04-30 22:03:04 UTC (rev 126739) +++ apple-local/branches/llvm/build_gcc 2007-04-30 22:37:52 UTC (rev 126740) @@ -457,7 +457,8 @@ cp -p /usr/lib/libstdc++.6.dylib \ .$DEST_ROOT/lib/gcc/$t-apple-darwin$DARWIN_VERS/$VERS/libstdc++.dylib \ || exit 1 - strip -x -c .$DEST_ROOT/lib/gcc/$t-apple-darwin$DARWIN_VERS/$VERS/libstdc++.dylib || exit 1 +# APPLE LOCAL LLVM +# strip -x -c .$DEST_ROOT/lib/gcc/$t-apple-darwin$DARWIN_VERS/$VERS/libstdc++.dylib || exit 1 done # include ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/MachineBasicBlock.cpp
Changes in directory llvm/lib/CodeGen:
MachineBasicBlock.cpp updated: 1.43 - 1.44
---
Log message:
print isLandingPad() for MBBs
---
Diffs of the changes: (+5 -3)
MachineBasicBlock.cpp |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/MachineBasicBlock.cpp
diff -u llvm/lib/CodeGen/MachineBasicBlock.cpp:1.43
llvm/lib/CodeGen/MachineBasicBlock.cpp:1.44
--- llvm/lib/CodeGen/MachineBasicBlock.cpp:1.43 Fri Mar 9 02:29:08 2007
+++ llvm/lib/CodeGen/MachineBasicBlock.cpp Mon Apr 30 18:12:53 2007
@@ -111,9 +111,11 @@
const BasicBlock *LBB = getBasicBlock();
OS \n;
- if (LBB) OS LBB-getName();
- OS ( (const void*)this
- , LLVM BB @ (const void*) LBB , ID# getNumber() ):\n;
+ if (LBB) OS LBB-getName() : ;
+ OS (const void*)this
+ , LLVM BB @ (const void*) LBB , ID# getNumber();
+ if (isLandingPad()) OS , EH LANDING PAD;
+ OS :\n;
const MRegisterInfo *MRI = MF-getTarget().getRegisterInfo();
if (livein_begin() != livein_end()) {
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[llvm-commits] CVS: llvm/test/CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll
Changes in directory llvm/test/CodeGen/Generic:
2007-04-30-LandingPadBranchFolding.ll added (r1.1)
---
Log message:
testcase for PR1228: http://llvm.org/PR1228
---
Diffs of the changes: (+59 -0)
2007-04-30-LandingPadBranchFolding.ll | 59 ++
1 files changed, 59 insertions(+)
Index: llvm/test/CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll
diff -c /dev/null
llvm/test/CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll:1.1
*** /dev/null Mon Apr 30 18:34:56 2007
--- llvm/test/CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll Mon Apr
30 18:34:46 2007
***
*** 0
--- 1,59
+ ; RUN: llvm-as %s | llc
+ ; PR1228
+
+
struct.std::basic_stringchar,std::char_traitschar,std::allocatorchar
::_Alloc_hider = type { i8* }
+ struct.std::locale = type { struct.std::locale::_Impl* }
+ struct.std::locale::_Impl = type { i32,
struct.std::locale::facet**, i32, struct.std::locale::facet**, i8** }
+ struct.std::locale::facet = type { i32 (...)**, i32 }
+ struct.std::string = type {
struct.std::basic_stringchar,std::char_traitschar,std::allocatorchar
::_Alloc_hider }
+
+ define void @_ZNKSt6locale4nameEv(struct.std::string* %agg.result) {
+ entry:
+ %tmp105 = icmp eq i8* null, null; i1 [#uses=1]
+ br i1 %tmp105, label %cond_true, label %cond_true222
+
+ cond_true:; preds = %entry
+ invoke void @_ZNSs14_M_replace_auxEjjjc( )
+ to label %cond_next1328 unwind label %cond_true1402
+
+ cond_true222: ; preds = %cond_true222, %entry
+ %tmp207 = call i32 @strcmp( ) ; i32 [#uses=1]
+ %tmp208 = icmp eq i32 %tmp207, 0; i1 [#uses=2]
+ %bothcond1480 = and i1 %tmp208, false ; i1 [#uses=1]
+ br i1 %bothcond1480, label %cond_true222, label %cond_next226.loopexit
+
+ cond_next226.loopexit:; preds = %cond_true222
+ %phitmp = xor i1 %tmp208, true ; i1 [#uses=1]
+ br i1 %phitmp, label %cond_false280, label %cond_true235
+
+ cond_true235: ; preds = %cond_next226.loopexit
+ invoke void @_ZNSs6assignEPKcj( )
+ to label %cond_next1328 unwind label %cond_true1402
+
+ cond_false280:; preds = %cond_next226.loopexit
+ invoke void @_ZNSs7reserveEj( )
+ to label %invcont282 unwind label %cond_true1402
+
+ invcont282: ; preds = %cond_false280
+ invoke void @_ZNSs6appendEPKcj( )
+ to label %invcont317 unwind label %cond_true1402
+
+ invcont317: ; preds = %invcont282
+ ret void
+
+ cond_next1328:; preds = %cond_true235, %cond_true
+ ret void
+
+ cond_true1402:; preds = %invcont282, %cond_false280,
%cond_true235, %cond_true
+ ret void
+ }
+
+ declare void @_ZNSs14_M_replace_auxEjjjc()
+
+ declare i32 @strcmp()
+
+ declare void @_ZNSs6assignEPKcj()
+
+ declare void @_ZNSs7reserveEj()
+
+ declare void @_ZNSs6appendEPKcj()
___
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[llvm-commits] CVS: llvm/lib/CodeGen/BranchFolding.cpp
Changes in directory llvm/lib/CodeGen:
BranchFolding.cpp updated: 1.45 - 1.46
---
Log message:
Fix PR1228: http://llvm.org/PR1228 and
CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll
---
Diffs of the changes: (+8 -2)
BranchFolding.cpp | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/BranchFolding.cpp
diff -u llvm/lib/CodeGen/BranchFolding.cpp:1.45
llvm/lib/CodeGen/BranchFolding.cpp:1.46
--- llvm/lib/CodeGen/BranchFolding.cpp:1.45 Tue Mar 20 16:35:06 2007
+++ llvm/lib/CodeGen/BranchFolding.cpp Mon Apr 30 18:35:00 2007
@@ -877,7 +877,7 @@
// Now we know that there was no fall-through into this block, check to
// see if it has a fall-through into its successor.
bool CurFallsThru = CanFallThrough(MBB, CurUnAnalyzable, CurTBB, CurFBB,
-CurCond);
+ CurCond);
if (!MBB-isLandingPad()) {
// Check all the predecessors of this block. If one of them has no fall
@@ -914,7 +914,13 @@
MachineBasicBlock *SuccBB = *SI;
MachineFunction::iterator SuccPrev = SuccBB; --SuccPrev;
std::vectorMachineOperand SuccPrevCond;
-if (SuccBB != MBB !CanFallThrough(SuccPrev)) {
+
+// If this block doesn't already fall-through to that successor, and if
+// the succ doesn't already have a block that can fall through into it,
+// and if the successor isn't an EH destination, we can arrange for the
+// fallthrough to happen.
+if (SuccBB != MBB !CanFallThrough(SuccPrev)
+!SuccBB-isLandingPad()) {
MBB-moveBefore(SuccBB);
MadeChange = true;
return OptimizeBlock(MBB);
___
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/ELFRelocation.h
Changes in directory llvm/include/llvm/CodeGen:
ELFRelocation.h updated: 1.1 - 1.2
---
Log message:
Implement review feedback.
---
Diffs of the changes: (+4 -1)
ELFRelocation.h |5 -
1 files changed, 4 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/CodeGen/ELFRelocation.h
diff -u llvm/include/llvm/CodeGen/ELFRelocation.h:1.1
llvm/include/llvm/CodeGen/ELFRelocation.h:1.2
--- llvm/include/llvm/CodeGen/ELFRelocation.h:1.1 Mon Apr 30 15:41:08 2007
+++ llvm/include/llvm/CodeGen/ELFRelocation.h Mon Apr 30 18:54:10 2007
@@ -14,6 +14,8 @@
#ifndef LLVM_CODEGEN_ELF_RELOCATION_H
#define LLVM_CODEGEN_ELF_RELOCATION_H
+#include llvm/Support/DataTypes.h
+
namespace llvm {
/// ELFRelocation - This class contains all the information necessary to
@@ -46,4 +48,5 @@
} // end llvm namespace
-#endif // LLVM_CODEGEN_ELF_RELOCATION_H
\ No newline at end of file
+#endif // LLVM_CODEGEN_ELF_RELOCATION_H
+
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.296 - 1.297
---
Log message:
* Only turn a load to UNDEF if all of its outputs have no uses (indexed loads
produce two results.)
* Do not touch volatile loads.
---
Diffs of the changes: (+20 -5)
DAGCombiner.cpp | 25 -
1 files changed, 20 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.296
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.297
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.296 Sun Apr 22 18:15:30 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Apr 30 19:38:21 2007
@@ -3326,11 +3326,26 @@
LoadSDNode *LD = castLoadSDNode(N);
SDOperand Chain = LD-getChain();
SDOperand Ptr = LD-getBasePtr();
-
- // If there are no uses of the loaded value, change uses of the chain value
- // into uses of the chain input (i.e. delete the dead load).
- if (N-hasNUsesOfValue(0, 0))
-return CombineTo(N, DAG.getNode(ISD::UNDEF, N-getValueType(0)), Chain);
+
+ // If load is not volatile and there are no uses of the loaded value (and
+ // the updated indexed value in case of indexed loads), change uses of the
+ // chain value into uses of the chain input (i.e. delete the dead load).
+ if (!LD-isVolatile()) {
+bool HasUses = false;
+SmallVectorMVT::ValueType, 2 VTs;
+for (unsigned i = 0, e = N-getNumValues(); i != e; ++i) {
+ if (!N-hasNUsesOfValue(0, i)) {
+HasUses = true;
+break;
+ }
+ VTs.push_back(N-getValueType(i));
+}
+if (!HasUses) {
+ SmallVectorSDOperand, 1 Ops;
+ return CombineTo(N, DAG.getNode(ISD::UNDEF, VTs[0], VTs.size(), 0, 0),
+ Chain);
+}
+ }
// If this load is directly stored, replace the load value with the stored
// value.
___
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[llvm-commits] CVS: llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll
Changes in directory llvm/test/CodeGen/ARM:
2007-04-30-CombinerCrash.ll added (r1.1)
---
Log message:
Test a dag combiner crasher.
---
Diffs of the changes: (+32 -0)
2007-04-30-CombinerCrash.ll | 32
1 files changed, 32 insertions(+)
Index: llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll
diff -c /dev/null llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll:1.1
*** /dev/null Mon Apr 30 19:40:48 2007
--- llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll Mon Apr 30 19:40:38 2007
***
*** 0
--- 1,32
+ ; RUN: llvm-as %s | llc -mtriple=arm-apple-darwin -mattr=+v6,+vfp2
+
+ target datalayout =
e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64
+ target triple = arm-apple-darwin8
+ %struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64,
i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x
i8], i8, i8, i8, i8, i8 }
+ @search = external global %struct.CHESS_POSITION;
%struct.CHESS_POSITION* [#uses=3]
+ @file_mask = external global [8 x i64] ; [8 x i64]* [#uses=1]
+ @rank_mask.1.b = external global i1 ; i1* [#uses=1]
+
+ define fastcc void @EvaluateDevelopment() {
+ entry:
+ %tmp7 = load i64* getelementptr (%struct.CHESS_POSITION* @search, i32
0, i32 7) ; i64 [#uses=1]
+ %tmp50 = load i64* getelementptr (%struct.CHESS_POSITION* @search,
i32 0, i32 0); i64 [#uses=1]
+ %tmp52 = load i64* getelementptr (%struct.CHESS_POSITION* @search,
i32 0, i32 1); i64 [#uses=1]
+ %tmp53 = or i64 %tmp52, %tmp50 ; i64 [#uses=1]
+ %tmp57.b = load i1* @rank_mask.1.b ; i1 [#uses=1]
+ %tmp57 = select i1 %tmp57.b, i64 71776119061217280, i64 0
; i64 [#uses=1]
+ %tmp58 = and i64 %tmp57, %tmp7 ; i64 [#uses=1]
+ %tmp59 = lshr i64 %tmp58, 8 ; i64 [#uses=1]
+ %tmp63 = load i64* getelementptr ([8 x i64]* @file_mask, i32 0, i32
4) ; i64 [#uses=1]
+ %tmp64 = or i64 %tmp63, 0 ; i64 [#uses=1]
+ %tmp65 = and i64 %tmp59, %tmp53 ; i64 [#uses=1]
+ %tmp66 = and i64 %tmp65, %tmp64 ; i64 [#uses=1]
+ %tmp67 = icmp eq i64 %tmp66, 0 ; i1 [#uses=1]
+ br i1 %tmp67, label %cond_next145, label %cond_true70
+
+ cond_true70:; preds = %entry
+ ret void
+
+ cond_next145: ; preds = %entry
+ ret void
+ }
___
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.107 - 1.108
---
Log message:
Added hook hasReservedCallFrame(). It returns true if the call frame is
included as part of the stack frame.
---
Diffs of the changes: (+9 -0)
MRegisterInfo.h |9 +
1 files changed, 9 insertions(+)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.107
llvm/include/llvm/Target/MRegisterInfo.h:1.108
--- llvm/include/llvm/Target/MRegisterInfo.h:1.107 Wed Apr 25 02:24:50 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hMon Apr 30 19:47:46 2007
@@ -451,6 +451,15 @@
/// variable sized allocas or if frame pointer elimination is disabled.
virtual bool hasFP(const MachineFunction MF) const = 0;
+ // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
+ // not required, we reserve argument space for call sites in the function
+ // immediately on entry to the current function. This eliminates the need for
+ // add/sub sp brackets around call sites. Returns true if the call frame is
+ // included as part of the stack frame.
+ virtual bool hasReservedCallFrame(MachineFunction MF) const {
+return !hasFP(MF);
+ }
+
/// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
/// frame setup/destroy instructions if they exist (-1 otherwise). Some
/// targets use pseudo instructions in order to abstract away the difference
___
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[llvm-commits] CVS: llvm/lib/CodeGen/PrologEpilogInserter.cpp
Changes in directory llvm/lib/CodeGen:
PrologEpilogInserter.cpp updated: 1.82 - 1.83
---
Log message:
Under normal circumstances, when a frame pointer is not required, we reserve
argument space for call sites in the function immediately on entry to the
current function. This eliminates the need for add/sub sp brackets around call
sites. However, this is not always a good idea. If the call frame is large and
the target load / store instructions have small immediate field to encode sp
offset, this can cause poor codegen. In the worst case, this can make it
impossible to scavenge a register if the reserved spill slot is pushed too far
apart from sp / fp.
---
Diffs of the changes: (+14 -17)
PrologEpilogInserter.cpp | 31 ++-
1 files changed, 14 insertions(+), 17 deletions(-)
Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp
diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.82
llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.83
--- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.82 Wed Apr 25 17:11:48 2007
+++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Mon Apr 30 19:51:28 2007
@@ -135,8 +135,9 @@
unsigned MaxCallFrameSize = 0;
bool HasCalls = false;
+ std::vectorMachineBasicBlock::iterator FrameSDOps;
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB)
-for (MachineBasicBlock::iterator I = BB-begin(); I != BB-end(); )
+for (MachineBasicBlock::iterator I = BB-begin(); I != BB-end(); ++I)
if (I-getOpcode() == FrameSetupOpcode ||
I-getOpcode() == FrameDestroyOpcode) {
assert(I-getNumOperands() = 1 Call Frame Setup/Destroy Pseudo
@@ -144,14 +145,16 @@
unsigned Size = I-getOperand(0).getImmedValue();
if (Size MaxCallFrameSize) MaxCallFrameSize = Size;
HasCalls = true;
-RegInfo-eliminateCallFramePseudoInstr(Fn, *BB, I++);
- } else {
-++I;
+FrameSDOps.push_back(I);
}
MachineFrameInfo *FFI = Fn.getFrameInfo();
FFI-setHasCalls(HasCalls);
FFI-setMaxCallFrameSize(MaxCallFrameSize);
+ for (unsigned i = 0, e = FrameSDOps.size(); i != e; ++i) {
+MachineBasicBlock::iterator I = FrameSDOps[i];
+RegInfo-eliminateCallFramePseudoInstr(Fn, *I-getParent(), I);
+ }
// Now figure out which *callee saved* registers are modified by the current
// function, thus needing to be saved and restored in the prolog/epilog.
@@ -333,10 +336,7 @@
// First assign frame offsets to stack objects that are used to spill
// callee saved registers.
if (StackGrowsDown) {
-for (unsigned i = 0, e = FFI-getObjectIndexEnd(); i != e; ++i) {
- if (i MinCSFrameIndex || i MaxCSFrameIndex)
-continue;
-
+for (unsigned i = MinCSFrameIndex; i = MaxCSFrameIndex; ++i) {
// If stack grows down, we need to add size of find the lowest
// address of the object.
Offset += FFI-getObjectSize(i);
@@ -351,10 +351,7 @@
FFI-setObjectOffset(i, -Offset);// Set the computed offset
}
} else {
-for (int i = FFI-getObjectIndexEnd()-1; i = 0; --i) {
- if ((unsigned)i MinCSFrameIndex || (unsigned)i MaxCSFrameIndex)
-continue;
-
+for (unsigned i = MaxCSFrameIndex; i = MinCSFrameIndex; --i) {
unsigned Align = FFI-getObjectAlignment(i);
// If the alignment of this object is greater than that of the stack,
then
// increase the stack alignment to match.
@@ -373,7 +370,7 @@
if (RS RegInfo-hasFP(Fn)) {
int SFI = RS-getScavengingFrameIndex();
if (SFI = 0) {
- // If stack grows down, we need to add size of find the lowest
+ // If stack grows down, we need to add size of the lowest
// address of the object.
if (StackGrowsDown)
Offset += FFI-getObjectSize(SFI);
@@ -447,10 +444,10 @@
// subroutines have their stack frames suitable aligned.
if (!RegInfo-targetHandlesStackFrameRounding()
(FFI-hasCalls() || FFI-hasVarSizedObjects())) {
-// When we have no frame pointer, we reserve argument space for call sites
-// in the function immediately on entry to the current function. This
-// eliminates the need for add/sub sp brackets around call sites.
-if (!RegInfo-hasFP(Fn))
+// If we have reserved argument space for call sites in the function
+// immediately on entry to the current function, count it as part of the
+// overall stack size.
+if (RegInfo-hasReservedCallFrame(Fn))
Offset += FFI-getMaxCallFrameSize();
unsigned AlignMask = TFI.getStackAlignment() - 1;
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp ARMRegisterInfo.h
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.90 - 1.91
ARMRegisterInfo.h updated: 1.17 - 1.18
---
Log message:
Under normal circumstances, when a frame pointer is not required, we reserve
argument space for call sites in the function immediately on entry to the
current function. This eliminates the need for add/sub sp brackets around call
sites. However, this is not always a good idea. If the call frame is large and
the target load / store instructions have small immediate field to encode sp
offset, this can cause poor codegen. In the worst case, this can make it
impossible to scavenge a register if the reserved spill slot is pushed too far
apart from sp / fp.
---
Diffs of the changes: (+29 -3)
ARMRegisterInfo.cpp | 30 +++---
ARMRegisterInfo.h |2 ++
2 files changed, 29 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.90
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.91
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.90Fri Apr 27 15:10:08 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Mon Apr 30 19:52:08 2007
@@ -386,6 +386,29 @@
return NoFramePointerElim || MF.getFrameInfo()-hasVarSizedObjects();
}
+// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
+// not required, we reserve argument space for call sites in the function
+// immediately on entry to the current function. This eliminates the need for
+// add/sub sp brackets around call sites. Returns true if the call frame is
+// included as part of the stack frame.
+bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction MF) const {
+ const MachineFrameInfo *FFI = MF.getFrameInfo();
+ unsigned CFSize = FFI-getMaxCallFrameSize();
+ ARMFunctionInfo *AFI = MF.getInfoARMFunctionInfo();
+ // It's not always a good idea to include the call frame as part of the
+ // stack frame. ARM (especially Thumb) has small immediate offset to
+ // address the stack frame. So a large call frame can cause poor codegen
+ // and may even makes it impossible to scavenge a register.
+ if (AFI-isThumbFunction()) {
+if (CFSize = ((1 8) - 1) * 4 / 2) // Half of imm8 * 4
+ return false;
+ } else {
+if (CFSize = ((1 12) - 1) / 2) // Half of imm12
+ return false;
+ }
+ return !hasFP(MF);
+}
+
/// emitARMRegPlusImmediate - Emits a series of instructions to materialize
/// a destreg = basereg + immediate in ARM code.
static
@@ -605,7 +628,7 @@
void ARMRegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction MF, MachineBasicBlock MBB,
MachineBasicBlock::iterator I) const {
- if (hasFP(MF)) {
+ if (!hasReservedCallFrame(MF)) {
// If we have alloca, convert as follows:
// ADJCALLSTACKDOWN - sub, sp, sp, amount
// ADJCALLSTACKUP - add, sp, sp, amount
@@ -1146,8 +1169,9 @@
Limit = (1 8) - 1;
goto DoneEstimating;
} else if (AddrMode == ARMII::AddrMode5) {
-Limit = ((1 8) - 1) * 4;
-goto DoneEstimating;
+unsigned ThisLimit = ((1 8) - 1) * 4;
+if (ThisLimit Limit)
+ Limit = ThisLimit;
}
}
}
Index: llvm/lib/Target/ARM/ARMRegisterInfo.h
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.17
llvm/lib/Target/ARM/ARMRegisterInfo.h:1.18
--- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.17 Tue Mar 20 03:07:04 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.h Mon Apr 30 19:52:08 2007
@@ -78,6 +78,8 @@
bool hasFP(const MachineFunction MF) const;
+ bool hasReservedCallFrame(MachineFunction MF) const;
+
void eliminateCallFramePseudoInstr(MachineFunction MF,
MachineBasicBlock MBB,
MachineBasicBlock::iterator I) const;
___
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[llvm-commits] CVS: llvm/include/llvm/Bitcode/LLVMBitCodes.h
Changes in directory llvm/include/llvm/Bitcode: LLVMBitCodes.h updated: 1.9 - 1.10 --- Log message: add missing opcode. --- Diffs of the changes: (+10 -9) LLVMBitCodes.h | 19 ++- 1 files changed, 10 insertions(+), 9 deletions(-) Index: llvm/include/llvm/Bitcode/LLVMBitCodes.h diff -u llvm/include/llvm/Bitcode/LLVMBitCodes.h:1.9 llvm/include/llvm/Bitcode/LLVMBitCodes.h:1.10 --- llvm/include/llvm/Bitcode/LLVMBitCodes.h:1.9Sun Apr 29 16:49:05 2007 +++ llvm/include/llvm/Bitcode/LLVMBitCodes.hMon Apr 30 21:12:05 2007 @@ -164,20 +164,21 @@ FUNC_CODE_INST_SHUFFLEVEC = 8, // SHUFFLEVEC: [ty, opval, opval, opval] FUNC_CODE_INST_CMP = 9, // CMP:[opty, opval, opval, pred] -FUNC_CODE_INST_RET = 10, // RET:[opvaloptional] +FUNC_CODE_INST_RET = 10, // RET:[opty,opvaloptional] FUNC_CODE_INST_BR = 11, // BR: [opval, bb#, bb#] or [bb#] FUNC_CODE_INST_SWITCH = 12, // SWITCH: [opty, opval, n, n x ops] -FUNC_CODE_INST_INVOKE = 13, // INVOKE: +FUNC_CODE_INST_INVOKE = 13, // INVOKE: [fnty, op0,op1,op2, ...] FUNC_CODE_INST_UNWIND = 14, // UNWIND FUNC_CODE_INST_UNREACHABLE = 15, // UNREACHABLE -FUNC_CODE_INST_MALLOC = 16, // MALLOC: .. -FUNC_CODE_INST_FREE= 17, // FREE: .. -FUNC_CODE_INST_ALLOCA = 18, // ALLOCA: .. -FUNC_CODE_INST_LOAD= 19, // LOAD: .. -FUNC_CODE_INST_STORE = 20, // STORE: .. -FUNC_CODE_INST_CALL= 21, // CALL: .. -FUNC_CODE_INST_VAARG = 22 // VAARG: .. +FUNC_CODE_INST_PHI = 16, // PHI:[ty, #ops, val0,bb0, ...] +FUNC_CODE_INST_MALLOC = 17, // MALLOC: [instty, op, align] +FUNC_CODE_INST_FREE= 18, // FREE: [opty, op] +FUNC_CODE_INST_ALLOCA = 19, // ALLOCA: [instty, op, align] +FUNC_CODE_INST_LOAD= 20, // LOAD: [opty, op, align, vol] +FUNC_CODE_INST_STORE = 21, // STORE: [ptrty,val,ptr, align, vol] +FUNC_CODE_INST_CALL= 22, // CALL: [fnty, fnid, arg0, arg1...] +FUNC_CODE_INST_VAARG = 23 // VAARG: [valistty, valist, instty] }; } // End bitc namespace } // End llvm namespace ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
Changes in directory llvm/lib/Bitcode/Writer:
BitcodeWriter.cpp updated: 1.16 - 1.17
---
Log message:
encode all of the instructions.
---
Diffs of the changes: (+166 -3)
BitcodeWriter.cpp | 169 +-
1 files changed, 166 insertions(+), 3 deletions(-)
Index: llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
diff -u llvm/lib/Bitcode/Writer/BitcodeWriter.cpp:1.16
llvm/lib/Bitcode/Writer/BitcodeWriter.cpp:1.17
--- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp:1.16 Sun Apr 29 15:56:48 2007
+++ llvm/lib/Bitcode/Writer/BitcodeWriter.cpp Mon Apr 30 21:13:26 2007
@@ -485,13 +485,12 @@
static void WriteInstruction(const Instruction I, ValueEnumerator VE,
BitstreamWriter Stream,
SmallVectorunsigned, 64 Vals) {
- return; // FIXME: REMOVE
unsigned Code = 0;
unsigned AbbrevToUse = 0;
switch (I.getOpcode()) {
default:
if (Instruction::isCast(I.getOpcode())) {
- Code = bitc::FUNC_CODE_INST_BINOP;
+ Code = bitc::FUNC_CODE_INST_CAST;
Vals.push_back(GetEncodedCastOpcode(I.getOpcode()));
Vals.push_back(VE.getTypeID(I.getType()));
Vals.push_back(VE.getTypeID(I.getOperand(0)-getType()));
@@ -505,15 +504,179 @@
Vals.push_back(VE.getValueID(I.getOperand(1)));
}
break;
+
+ case Instruction::GetElementPtr:
+Code = bitc::FUNC_CODE_INST_GEP;
+Vals.push_back(I.getNumOperands());
+for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
+ Vals.push_back(VE.getTypeID(I.getOperand(i)-getType()));
+ Vals.push_back(VE.getValueID(I.getOperand(i)));
+}
+break;
+ case Instruction::Select:
+Code = bitc::FUNC_CODE_INST_SELECT;
+Vals.push_back(VE.getTypeID(I.getType()));
+Vals.push_back(VE.getValueID(I.getOperand(0)));
+Vals.push_back(VE.getValueID(I.getOperand(1)));
+Vals.push_back(VE.getValueID(I.getOperand(2)));
+break;
+ case Instruction::ExtractElement:
+Code = bitc::FUNC_CODE_INST_EXTRACTELT;
+Vals.push_back(VE.getTypeID(I.getOperand(0)-getType()));
+Vals.push_back(VE.getValueID(I.getOperand(0)));
+Vals.push_back(VE.getValueID(I.getOperand(1)));
+break;
+ case Instruction::InsertElement:
+Code = bitc::FUNC_CODE_INST_INSERTELT;
+Vals.push_back(VE.getTypeID(I.getType()));
+Vals.push_back(VE.getValueID(I.getOperand(0)));
+Vals.push_back(VE.getValueID(I.getOperand(1)));
+Vals.push_back(VE.getValueID(I.getOperand(2)));
+break;
+ case Instruction::ShuffleVector:
+Code = bitc::FUNC_CODE_INST_SHUFFLEVEC;
+Vals.push_back(VE.getTypeID(I.getType()));
+Vals.push_back(VE.getValueID(I.getOperand(0)));
+Vals.push_back(VE.getValueID(I.getOperand(1)));
+Vals.push_back(VE.getValueID(I.getOperand(2)));
+break;
+ case Instruction::ICmp:
+ case Instruction::FCmp:
+Code = bitc::FUNC_CODE_INST_CMP;
+Vals.push_back(VE.getTypeID(I.getOperand(0)-getType()));
+Vals.push_back(VE.getValueID(I.getOperand(0)));
+Vals.push_back(VE.getValueID(I.getOperand(1)));
+Vals.push_back(castCmpInst(I).getPredicate());
+break;
+
+ case Instruction::Ret:
+Code = bitc::FUNC_CODE_INST_RET;
+if (I.getNumOperands()) {
+ Vals.push_back(VE.getTypeID(I.getOperand(0)-getType()));
+ Vals.push_back(VE.getValueID(I.getOperand(0)));
+}
+break;
+ case Instruction::Br:
+Code = bitc::FUNC_CODE_INST_BR;
+Vals.push_back(VE.getValueID(I.getOperand(0)));
+if (castBranchInst(I).isConditional()) {
+ Vals.push_back(VE.getValueID(I.getOperand(1)));
+ Vals.push_back(VE.getValueID(I.getOperand(2)));
+}
+break;
+ case Instruction::Switch:
+Code = bitc::FUNC_CODE_INST_SWITCH;
+Vals.push_back(VE.getTypeID(I.getOperand(0)-getType()));
+Vals.push_back(I.getNumOperands());
+for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i)
+ Vals.push_back(VE.getValueID(I.getOperand(i)));
+break;
+ case Instruction::Invoke:
+Code = bitc::FUNC_CODE_INST_INVOKE;
+// FIXME: param attrs
+Vals.push_back(VE.getTypeID(I.getOperand(0)-getType()));
+Vals.push_back(VE.getValueID(I.getOperand(0))); // callee
+Vals.push_back(VE.getValueID(I.getOperand(1))); // normal
+Vals.push_back(VE.getValueID(I.getOperand(2))); // unwind
-
+// Emit value #'s for the fixed parameters.
+const PointerType *PTy = castPointerType(I.getOperand(0)-getType());
+const FunctionType *FTy = castFunctionType(PTy-getElementType());
+for (unsigned i = 0, e = FTy-getNumParams(); i != e; ++i)
+ Vals.push_back(VE.getValueID(I.getOperand(i+3))); // fixed param.
+
+// Emit type/value pairs for varargs params.
+if (FTy-isVarArg()) {
+ unsigned NumVarargs = I.getNumOperands()-3-FTy-getNumParams();
+ Vals.push_back(NumVarargs);
+ for (unsigned i = I.getNumOperands()-NumVarargs, e = I.getNumOperands();
+ i != e; ++i) {
+
[llvm-commits] CVS: llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
Changes in directory llvm/lib/Bitcode/Writer:
BitcodeWriter.cpp updated: 1.17 - 1.18
---
Log message:
write the symbol table for function bodies
---
Diffs of the changes: (+33 -30)
BitcodeWriter.cpp | 63 --
1 files changed, 33 insertions(+), 30 deletions(-)
Index: llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
diff -u llvm/lib/Bitcode/Writer/BitcodeWriter.cpp:1.17
llvm/lib/Bitcode/Writer/BitcodeWriter.cpp:1.18
--- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp:1.17 Mon Apr 30 21:13:26 2007
+++ llvm/lib/Bitcode/Writer/BitcodeWriter.cpp Mon Apr 30 21:14:57 2007
@@ -683,6 +683,36 @@
Vals.clear();
}
+// Emit names for globals/functions etc.
+static void WriteValueSymbolTable(const ValueSymbolTable VST,
+ const ValueEnumerator VE,
+ BitstreamWriter Stream) {
+ if (VST.empty()) return;
+ Stream.EnterSubblock(bitc::VALUE_SYMTAB_BLOCK_ID, 3);
+
+ // FIXME: Set up the abbrev, we know how many values there are!
+ // FIXME: We know if the type names can use 7-bit ascii.
+ SmallVectorunsigned, 64 NameVals;
+
+ for (ValueSymbolTable::const_iterator SI = VST.begin(), SE = VST.end();
+ SI != SE; ++SI) {
+unsigned AbbrevToUse = 0;
+
+// VST_ENTRY: [valueid, namelen, namechar x N]
+NameVals.push_back(VE.getValueID(SI-getValue()));
+
+NameVals.push_back(SI-getKeyLength());
+for (const char *P = SI-getKeyData(),
+ *E = SI-getKeyData()+SI-getKeyLength(); P != E; ++P)
+ NameVals.push_back((unsigned char)*P);
+
+// Emit the finished record.
+Stream.EmitRecord(bitc::VST_CODE_ENTRY, NameVals, AbbrevToUse);
+NameVals.clear();
+ }
+ Stream.ExitBlock();
+}
+
/// WriteFunction - Emit a function body to the module stream.
static void WriteFunction(const Function F, ValueEnumerator VE,
BitstreamWriter Stream) {
@@ -709,6 +739,9 @@
for (BasicBlock::const_iterator I = BB-begin(), E = BB-end(); I != E;
++I)
WriteInstruction(*I, VE, Stream, Vals);
+ // Emit names for all the instructions etc.
+ WriteValueSymbolTable(F.getValueSymbolTable(), VE, Stream);
+
VE.purgeFunction();
Stream.ExitBlock();
}
@@ -746,36 +779,6 @@
Stream.ExitBlock();
}
-// Emit names for globals/functions etc.
-static void WriteValueSymbolTable(const ValueSymbolTable VST,
- const ValueEnumerator VE,
- BitstreamWriter Stream) {
- if (VST.empty()) return;
- Stream.EnterSubblock(bitc::VALUE_SYMTAB_BLOCK_ID, 3);
-
- // FIXME: Set up the abbrev, we know how many values there are!
- // FIXME: We know if the type names can use 7-bit ascii.
- SmallVectorunsigned, 64 NameVals;
-
- for (ValueSymbolTable::const_iterator SI = VST.begin(), SE = VST.end();
- SI != SE; ++SI) {
-unsigned AbbrevToUse = 0;
-
-// VST_ENTRY: [valueid, namelen, namechar x N]
-NameVals.push_back(VE.getValueID(SI-getValue()));
-
-NameVals.push_back(SI-getKeyLength());
-for (const char *P = SI-getKeyData(),
- *E = SI-getKeyData()+SI-getKeyLength(); P != E; ++P)
- NameVals.push_back((unsigned char)*P);
-
-// Emit the finished record.
-Stream.EmitRecord(bitc::VST_CODE_ENTRY, NameVals, AbbrevToUse);
-NameVals.clear();
- }
- Stream.ExitBlock();
-}
-
/// WriteModule - Emit the specified module to the bitstream.
static void WriteModule(const Module *M, BitstreamWriter Stream) {
___
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[llvm-commits] CVS: llvm/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
Changes in directory llvm/tools/llvm-bcanalyzer:
llvm-bcanalyzer.cpp updated: 1.15 - 1.16
---
Log message:
add phi
---
Diffs of the changes: (+5 -1)
llvm-bcanalyzer.cpp |6 +-
1 files changed, 5 insertions(+), 1 deletion(-)
Index: llvm/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
diff -u llvm/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp:1.15
llvm/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp:1.16
--- llvm/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp:1.15 Sun Apr 29 16:48:19 2007
+++ llvm/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Mon Apr 30 21:43:46 2007
@@ -167,6 +167,7 @@
case bitc::FUNC_CODE_INST_UNWIND: return INST_UNWIND;
case bitc::FUNC_CODE_INST_UNREACHABLE: return INST_UNREACHABLE;
+case bitc::FUNC_CODE_INST_PHI: return INST_PHI;
case bitc::FUNC_CODE_INST_MALLOC: return INST_MALLOC;
case bitc::FUNC_CODE_INST_FREE:return INST_FREE;
case bitc::FUNC_CODE_INST_ALLOCA: return INST_ALLOCA;
@@ -371,10 +372,11 @@
if (Dump) std::cerr \n\n;
+ uint64_t BufferSizeBits = Buffer-getBufferSize()*8;
// Print a summary of the read file.
std::cerr Summary of InputFilename :\n;
std::cerr Total size: ;
- PrintSize(Buffer-getBufferSize()*8);
+ PrintSize(BufferSizeBits);
std::cerr \n;
std::cerr Stream type: ;
switch (CurStreamType) {
@@ -402,6 +404,8 @@
std::cerr Average Size: ;
PrintSize(Stats.NumBits/(double)Stats.NumInstances);
std::cerr \n;
+std::cerr% of file:
+ Stats.NumBits/(double)BufferSizeBits*100 \n;
std::cerrTot/Avg SubBlocks: Stats.NumSubBlocks /
Stats.NumSubBlocks/(double)Stats.NumInstances \n;
std::cerr Tot/Avg Abbrevs: Stats.NumAbbrevs /
___
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[llvm-commits] CVS: llvm/test/CodeGen/X86/vector.ll
Changes in directory llvm/test/CodeGen/X86:
vector.ll added (r1.1)
---
Log message:
Split target dependent test portions to target-specific directories.
---
Diffs of the changes: (+157 -0)
vector.ll | 157 ++
1 files changed, 157 insertions(+)
Index: llvm/test/CodeGen/X86/vector.ll
diff -c /dev/null llvm/test/CodeGen/X86/vector.ll:1.1
*** /dev/null Mon Apr 30 21:56:25 2007
--- llvm/test/CodeGen/X86/vector.ll Mon Apr 30 21:56:15 2007
***
*** 0
--- 1,157
+ ; Test that vectors are scalarized/lowered correctly.
+ ; RUN: llvm-upgrade %s | llvm-as | llc -march=x86 -mcpu=i386
+ ; RUN: llvm-upgrade %s | llvm-as | llc -march=x86 -mcpu=yonah
+
+ %f1 = type 1 x float
+ %f2 = type 2 x float
+ %f4 = type 4 x float
+ %i4 = type 4 x int
+ %f8 = type 8 x float
+ %d8 = type 8 x double
+
+ implementation
+
+ ;;; TEST HANDLING OF VARIOUS VECTOR SIZES
+
+ void %test_f1(%f1 *%P, %f1* %Q, %f1 *%S) {
+ %p = load %f1 *%P
+ %q = load %f1* %Q
+ %R = add %f1 %p, %q
+ store %f1 %R, %f1 *%S
+ ret void
+ }
+
+ void %test_f2(%f2 *%P, %f2* %Q, %f2 *%S) {
+ %p = load %f2* %P
+ %q = load %f2* %Q
+ %R = add %f2 %p, %q
+ store %f2 %R, %f2 *%S
+ ret void
+ }
+
+ void %test_f4(%f4 *%P, %f4* %Q, %f4 *%S) {
+ %p = load %f4* %P
+ %q = load %f4* %Q
+ %R = add %f4 %p, %q
+ store %f4 %R, %f4 *%S
+ ret void
+ }
+
+ void %test_f8(%f8 *%P, %f8* %Q, %f8 *%S) {
+ %p = load %f8* %P
+ %q = load %f8* %Q
+ %R = add %f8 %p, %q
+ store %f8 %R, %f8 *%S
+ ret void
+ }
+
+ void %test_fmul(%f8 *%P, %f8* %Q, %f8 *%S) {
+ %p = load %f8* %P
+ %q = load %f8* %Q
+ %R = mul %f8 %p, %q
+ store %f8 %R, %f8 *%S
+ ret void
+ }
+
+ void %test_div(%f8 *%P, %f8* %Q, %f8 *%S) {
+ %p = load %f8* %P
+ %q = load %f8* %Q
+ %R = div %f8 %p, %q
+ store %f8 %R, %f8 *%S
+ ret void
+ }
+
+ ;;; TEST VECTOR CONSTRUCTS
+
+ void %test_cst(%f4 *%P, %f4 *%S) {
+ %p = load %f4* %P
+ %R = add %f4 %p, float 0.1, float 1.0, float 2.0, float 4.5
+ store %f4 %R, %f4 *%S
+ ret void
+ }
+
+ void %test_zero(%f4 *%P, %f4 *%S) {
+ %p = load %f4* %P
+ %R = add %f4 %p, zeroinitializer
+ store %f4 %R, %f4 *%S
+ ret void
+ }
+
+ void %test_undef(%f4 *%P, %f4 *%S) {
+ %p = load %f4* %P
+ %R = add %f4 %p, undef
+ store %f4 %R, %f4 *%S
+ ret void
+ }
+
+ void %test_constant_insert(%f4 *%S) {
+ %R = insertelement %f4 zeroinitializer, float 10.0, uint 0
+ store %f4 %R, %f4 *%S
+ ret void
+ }
+
+ void %test_variable_buildvector(float %F, %f4 *%S) {
+ %R = insertelement %f4 zeroinitializer, float %F, uint 0
+ store %f4 %R, %f4 *%S
+ ret void
+ }
+
+ void %test_scalar_to_vector(float %F, %f4 *%S) {
+ %R = insertelement %f4 undef, float %F, uint 0 ;; R = scalar_to_vector F
+ store %f4 %R, %f4 *%S
+ ret void
+ }
+
+ float %test_extract_elt(%f8 *%P) {
+ %p = load %f8* %P
+ %R = extractelement %f8 %p, uint 3
+ ret float %R
+ }
+
+ double %test_extract_elt2(%d8 *%P) {
+ %p = load %d8* %P
+ %R = extractelement %d8 %p, uint 3
+ ret double %R
+ }
+
+ void %test_cast_1(4 x float* %b, 4 x int* %a) {
+ %tmp = load 4 x float* %b
+ %tmp2 = add 4 x float %tmp, float 1.0, float 2.0, float 3.0, float 4.0
+ %tmp3 = cast 4 x float %tmp2 to 4 x int
+ %tmp4 = add 4 x int %tmp3, int 1, int 2, int 3, int 4
+ store 4 x int %tmp4, 4 x int* %a
+ ret void
+ }
+
+ void %test_cast_2(8 x float* %a, 8 x int* %b) {
+ %T = load 8 x float* %a
+ %T2 = cast 8 x float %T to 8 x int
+ store 8 x int %T2, 8 x int* %b
+ ret void
+ }
+
+
+ ;;; TEST IMPORTANT IDIOMS
+
+ void %splat(%f4* %P, %f4* %Q, float %X) {
+ %tmp = insertelement %f4 undef, float %X, uint 0
+ %tmp2 = insertelement %f4 %tmp, float %X, uint 1
+ %tmp4 = insertelement %f4 %tmp2, float %X, uint 2
+ %tmp6 = insertelement %f4 %tmp4, float %X, uint 3
+ %q = load %f4* %Q
+ %R = add %f4 %q, %tmp6
+ store %f4 %R, %f4* %P
+ ret void
+ }
+
+ void %splat_i4(%i4* %P, %i4* %Q, int %X) {
+ %tmp = insertelement %i4 undef, int %X, uint 0
+ %tmp2 = insertelement %i4 %tmp, int %X, uint 1
+ %tmp4 = insertelement %i4 %tmp2, int %X, uint 2
+ %tmp6 = insertelement %i4 %tmp4, int %X, uint 3
+ %q = load %i4* %Q
+ %R = add %i4 %q, %tmp6
+ store %i4 %R, %i4* %P
+ ret void
+ }
+
___
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[llvm-commits] CVS: llvm/test/CodeGen/Generic/vector.ll
Changes in directory llvm/test/CodeGen/Generic: vector.ll updated: 1.13 - 1.14 --- Log message: Split target dependent test portions to target-specific directories. --- Diffs of the changes: (+0 -4) vector.ll |4 1 files changed, 4 deletions(-) Index: llvm/test/CodeGen/Generic/vector.ll diff -u llvm/test/CodeGen/Generic/vector.ll:1.13 llvm/test/CodeGen/Generic/vector.ll:1.14 --- llvm/test/CodeGen/Generic/vector.ll:1.13Mon Apr 16 12:36:06 2007 +++ llvm/test/CodeGen/Generic/vector.ll Mon Apr 30 21:56:15 2007 @@ -1,10 +1,6 @@ ; Test that vectors are scalarized/lowered correctly. ; RUN: llvm-upgrade %s | llvm-as | llc ; RUN: llvm-upgrade %s | llvm-as | llc -mtriple a-b-c -; RUN: llvm-upgrade %s | llvm-as | llc -march=ppc32 -mcpu=g5 -; RUN: llvm-upgrade %s | llvm-as | llc -march=ppc32 -mcpu=g3 -; RUN: llvm-upgrade %s | llvm-as | llc -march=x86 -mcpu=i386 -; RUN: llvm-upgrade %s | llvm-as | llc -march=x86 -mcpu=yonah %f1 = type 1 x float %f2 = type 2 x float ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/CodeGen/PowerPC/vector.ll
Changes in directory llvm/test/CodeGen/PowerPC:
vector.ll added (r1.1)
---
Log message:
Split target dependent test portions to target-specific directories.
---
Diffs of the changes: (+157 -0)
vector.ll | 157 ++
1 files changed, 157 insertions(+)
Index: llvm/test/CodeGen/PowerPC/vector.ll
diff -c /dev/null llvm/test/CodeGen/PowerPC/vector.ll:1.1
*** /dev/null Mon Apr 30 21:56:25 2007
--- llvm/test/CodeGen/PowerPC/vector.ll Mon Apr 30 21:56:15 2007
***
*** 0
--- 1,157
+ ; Test that vectors are scalarized/lowered correctly.
+ ; RUN: llvm-upgrade %s | llvm-as | llc -march=ppc32 -mcpu=g5
+ ; RUN: llvm-upgrade %s | llvm-as | llc -march=ppc32 -mcpu=g3
+
+ %f1 = type 1 x float
+ %f2 = type 2 x float
+ %f4 = type 4 x float
+ %i4 = type 4 x int
+ %f8 = type 8 x float
+ %d8 = type 8 x double
+
+ implementation
+
+ ;;; TEST HANDLING OF VARIOUS VECTOR SIZES
+
+ void %test_f1(%f1 *%P, %f1* %Q, %f1 *%S) {
+ %p = load %f1 *%P
+ %q = load %f1* %Q
+ %R = add %f1 %p, %q
+ store %f1 %R, %f1 *%S
+ ret void
+ }
+
+ void %test_f2(%f2 *%P, %f2* %Q, %f2 *%S) {
+ %p = load %f2* %P
+ %q = load %f2* %Q
+ %R = add %f2 %p, %q
+ store %f2 %R, %f2 *%S
+ ret void
+ }
+
+ void %test_f4(%f4 *%P, %f4* %Q, %f4 *%S) {
+ %p = load %f4* %P
+ %q = load %f4* %Q
+ %R = add %f4 %p, %q
+ store %f4 %R, %f4 *%S
+ ret void
+ }
+
+ void %test_f8(%f8 *%P, %f8* %Q, %f8 *%S) {
+ %p = load %f8* %P
+ %q = load %f8* %Q
+ %R = add %f8 %p, %q
+ store %f8 %R, %f8 *%S
+ ret void
+ }
+
+ void %test_fmul(%f8 *%P, %f8* %Q, %f8 *%S) {
+ %p = load %f8* %P
+ %q = load %f8* %Q
+ %R = mul %f8 %p, %q
+ store %f8 %R, %f8 *%S
+ ret void
+ }
+
+ void %test_div(%f8 *%P, %f8* %Q, %f8 *%S) {
+ %p = load %f8* %P
+ %q = load %f8* %Q
+ %R = div %f8 %p, %q
+ store %f8 %R, %f8 *%S
+ ret void
+ }
+
+ ;;; TEST VECTOR CONSTRUCTS
+
+ void %test_cst(%f4 *%P, %f4 *%S) {
+ %p = load %f4* %P
+ %R = add %f4 %p, float 0.1, float 1.0, float 2.0, float 4.5
+ store %f4 %R, %f4 *%S
+ ret void
+ }
+
+ void %test_zero(%f4 *%P, %f4 *%S) {
+ %p = load %f4* %P
+ %R = add %f4 %p, zeroinitializer
+ store %f4 %R, %f4 *%S
+ ret void
+ }
+
+ void %test_undef(%f4 *%P, %f4 *%S) {
+ %p = load %f4* %P
+ %R = add %f4 %p, undef
+ store %f4 %R, %f4 *%S
+ ret void
+ }
+
+ void %test_constant_insert(%f4 *%S) {
+ %R = insertelement %f4 zeroinitializer, float 10.0, uint 0
+ store %f4 %R, %f4 *%S
+ ret void
+ }
+
+ void %test_variable_buildvector(float %F, %f4 *%S) {
+ %R = insertelement %f4 zeroinitializer, float %F, uint 0
+ store %f4 %R, %f4 *%S
+ ret void
+ }
+
+ void %test_scalar_to_vector(float %F, %f4 *%S) {
+ %R = insertelement %f4 undef, float %F, uint 0 ;; R = scalar_to_vector F
+ store %f4 %R, %f4 *%S
+ ret void
+ }
+
+ float %test_extract_elt(%f8 *%P) {
+ %p = load %f8* %P
+ %R = extractelement %f8 %p, uint 3
+ ret float %R
+ }
+
+ double %test_extract_elt2(%d8 *%P) {
+ %p = load %d8* %P
+ %R = extractelement %d8 %p, uint 3
+ ret double %R
+ }
+
+ void %test_cast_1(4 x float* %b, 4 x int* %a) {
+ %tmp = load 4 x float* %b
+ %tmp2 = add 4 x float %tmp, float 1.0, float 2.0, float 3.0, float 4.0
+ %tmp3 = cast 4 x float %tmp2 to 4 x int
+ %tmp4 = add 4 x int %tmp3, int 1, int 2, int 3, int 4
+ store 4 x int %tmp4, 4 x int* %a
+ ret void
+ }
+
+ void %test_cast_2(8 x float* %a, 8 x int* %b) {
+ %T = load 8 x float* %a
+ %T2 = cast 8 x float %T to 8 x int
+ store 8 x int %T2, 8 x int* %b
+ ret void
+ }
+
+
+ ;;; TEST IMPORTANT IDIOMS
+
+ void %splat(%f4* %P, %f4* %Q, float %X) {
+ %tmp = insertelement %f4 undef, float %X, uint 0
+ %tmp2 = insertelement %f4 %tmp, float %X, uint 1
+ %tmp4 = insertelement %f4 %tmp2, float %X, uint 2
+ %tmp6 = insertelement %f4 %tmp4, float %X, uint 3
+ %q = load %f4* %Q
+ %R = add %f4 %q, %tmp6
+ store %f4 %R, %f4* %P
+ ret void
+ }
+
+ void %splat_i4(%i4* %P, %i4* %Q, int %X) {
+ %tmp = insertelement %i4 undef, int %X, uint 0
+ %tmp2 = insertelement %i4 %tmp, int %X, uint 1
+ %tmp4 = insertelement %i4 %tmp2, int %X, uint 2
+ %tmp6 = insertelement %i4 %tmp4, int %X, uint 3
+ %q = load %i4* %Q
+ %R = add %i4 %q, %tmp6
+ store %i4 %R, %i4* %P
+ ret void
+ }
+
___
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Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+bool HasUses = false;
+SmallVectorMVT::ValueType, 2 VTs;
+for (unsigned i = 0, e = N-getNumValues(); i != e; ++i) {
+ if (!N-hasNUsesOfValue(0, i)) {
+HasUses = true;
+break;
+ }
+ VTs.push_back(N-getValueType(i));
+}
+if (!HasUses) {
+ SmallVectorSDOperand, 1 Ops;
+ return CombineTo(N, DAG.getNode(ISD::UNDEF, VTs[0], VTs.size
(), 0, 0),
+ Chain);
This can never trigger and isn't right if it did.
#1: This should trigger if the chain has uses but the other values do
not. If the entire node is dead, it will already have been removed.
#2. you can't create an undef with multiple results, you have to
create multiple undefs :)
I'd suggest just writing this as:
if (N-getValueType(1) == MVT::Other) {
// single result case.
} else {
assert(N-getValueType(2) == MVT::Other);
// multi result case.
}
This lets you drop the looping and smallvector.
-Chris
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[llvm-commits] CVS: llvm/include/llvm/Bitcode/BitstreamReader.h
Changes in directory llvm/include/llvm/Bitcode:
BitstreamReader.h updated: 1.9 - 1.10
---
Log message:
add JumpToBit, an explicit init method, and a default ctor.
---
Diffs of the changes: (+28 -2)
BitstreamReader.h | 30 --
1 files changed, 28 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/Bitcode/BitstreamReader.h
diff -u llvm/include/llvm/Bitcode/BitstreamReader.h:1.9
llvm/include/llvm/Bitcode/BitstreamReader.h:1.10
--- llvm/include/llvm/Bitcode/BitstreamReader.h:1.9 Sun Apr 29 16:49:05 2007
+++ llvm/include/llvm/Bitcode/BitstreamReader.h Mon Apr 30 23:59:06 2007
@@ -51,8 +51,20 @@
/// FirstChar - This remembers the first byte of the stream.
const unsigned char *FirstChar;
public:
- BitstreamReader(const unsigned char *Start, const unsigned char *End)
-: NextChar(Start), LastChar(End), FirstChar(Start) {
+ BitstreamReader() {
+NextChar = FirstChar = LastChar = 0;
+CurWord = 0;
+BitsInCurWord = 0;
+CurCodeSize = 0;
+ }
+
+ BitstreamReader(const unsigned char *Start, const unsigned char *End) {
+init(Start, End);
+ }
+
+ void init(const unsigned char *Start, const unsigned char *End) {
+NextChar = FirstChar = Start;
+LastChar = End;
assert(((End-Start) 3) == 0 Bitcode stream not a multiple of 4
bytes);
CurWord = 0;
BitsInCurWord = 0;
@@ -79,6 +91,20 @@
return (NextChar-FirstChar)*8 + (32-BitsInCurWord);
}
+ /// JumpToBit - Reset the stream to the specified bit number.
+ void JumpToBit(uint64_t BitNo) {
+unsigned WordNo = BitNo/32;
+unsigned WordBitNo = BitNo 31;
+assert(WordNo (unsigned)(LastChar-FirstChar) Invalid location);
+
+// Move the cursor to the right word.
+NextChar = FirstChar+WordNo;
+BitsInCurWord = 0;
+
+// Skip over any bits that are already consumed.
+if (WordBitNo) Read(WordBitNo);
+ }
+
/// GetAbbrevIDWidth - Return the number of bits used to encode an abbrev #.
unsigned GetAbbrevIDWidth() const { return CurCodeSize; }
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[llvm-commits] CVS: llvm/lib/Bitcode/Reader/BitcodeReader.cpp BitcodeReader.h
Changes in directory llvm/lib/Bitcode/Reader:
BitcodeReader.cpp updated: 1.17 - 1.18
BitcodeReader.h updated: 1.11 - 1.12
---
Log message:
implement scafolding for lazy deserialization of function bodies
---
Diffs of the changes: (+85 -7)
BitcodeReader.cpp | 65 --
BitcodeReader.h | 27 ++
2 files changed, 85 insertions(+), 7 deletions(-)
Index: llvm/lib/Bitcode/Reader/BitcodeReader.cpp
diff -u llvm/lib/Bitcode/Reader/BitcodeReader.cpp:1.17
llvm/lib/Bitcode/Reader/BitcodeReader.cpp:1.18
--- llvm/lib/Bitcode/Reader/BitcodeReader.cpp:1.17 Sun Apr 29 15:56:48 2007
+++ llvm/lib/Bitcode/Reader/BitcodeReader.cpp Mon Apr 30 23:59:48 2007
@@ -13,7 +13,6 @@
#include llvm/Bitcode/ReaderWriter.h
#include BitcodeReader.h
-#include llvm/Bitcode/BitstreamReader.h
#include llvm/Constants.h
#include llvm/DerivedTypes.h
#include llvm/Module.h
@@ -660,6 +659,30 @@
}
}
+/// ParseFunction - When we see the block for a function body, remember where
it
+/// is and then skip it. This lets us lazily deserialize the functions.
+bool BitcodeReader::ParseFunction(BitstreamReader Stream) {
+ // Get the function we are talking about.
+ if (FunctionsWithBodies.empty())
+return Error(Insufficient function protos);
+
+ Function *Fn = FunctionsWithBodies.back();
+ FunctionsWithBodies.pop_back();
+
+ // Save the current stream state.
+ uint64_t CurBit = Stream.GetCurrentBitNo();
+ DeferredFunctionInfo[Fn] = std::make_pair(CurBit, Fn-getLinkage());
+
+ // Set the functions linkage to GhostLinkage so we know it is lazily
+ // deserialized.
+ Fn-setLinkage(GlobalValue::GhostLinkage);
+
+ // Skip over the function block for now.
+ if (Stream.SkipBlock())
+return Error(Malformed block record);
+ return false;
+}
+
bool BitcodeReader::ParseModule(BitstreamReader Stream,
const std::string ModuleID) {
// Reject multiple MODULE_BLOCK's in a single bitstream.
@@ -682,6 +705,8 @@
ResolveGlobalAndAliasInits();
if (!GlobalInits.empty() || !AliasInits.empty())
return Error(Malformed global initializer set);
+ if (!FunctionsWithBodies.empty())
+return Error(Too few function bodies found);
if (Stream.ReadBlockEnd())
return Error(Error at end of module block);
return false;
@@ -709,6 +734,17 @@
if (ParseConstants(Stream) || ResolveGlobalAndAliasInits())
return true;
break;
+ case bitc::FUNCTION_BLOCK_ID:
+// If this is the first function body we've seen, reverse the
+// FunctionsWithBodies list.
+if (!HasReversedFunctionsWithBodies) {
+ std::reverse(FunctionsWithBodies.begin(), FunctionsWithBodies.end());
+ HasReversedFunctionsWithBodies = true;
+}
+
+if (ParseFunction(Stream))
+ return true;
+break;
}
continue;
}
@@ -819,6 +855,7 @@
, TheModule);
Func-setCallingConv(Record[1]);
+ bool isProto = Record[2];
Func-setLinkage(GetDecodedLinkage(Record[3]));
Func-setAlignment((1 Record[4]) 1);
if (Record[5]) {
@@ -829,6 +866,11 @@
Func-setVisibility(GetDecodedVisibility(Record[6]));
ValueList.push_back(Func);
+
+ // If this is a function with a body, remember the prototype we are
+ // creating now, so that we can match up the body with them later.
+ if (!isProto)
+FunctionsWithBodies.push_back(Func);
break;
}
// ALIAS: [alias type, aliasee val#, linkage]
@@ -867,7 +909,7 @@
return Error(Bitcode stream should be a multiple of 4 bytes in length);
unsigned char *BufPtr = (unsigned char *)Buffer-getBufferStart();
- BitstreamReader Stream(BufPtr, BufPtr+Buffer-getBufferSize());
+ Stream.init(BufPtr, BufPtr+Buffer-getBufferSize());
// Sniff for the signature.
if (Stream.Read(8) != 'B' ||
@@ -900,6 +942,25 @@
return false;
}
+
+bool BitcodeReader::materializeFunction(Function *F, std::string *ErrInfo) {
+ // If it already is material, ignore the request.
+ if (!F-hasNotBeenReadFromBytecode()) return false;
+
+ DenseMapFunction*, std::pairuint64_t, unsigned ::iterator DFII =
+DeferredFunctionInfo.find(F);
+ assert(DFII != DeferredFunctionInfo.end() Deferred function not found!);
+
+ // Move the bit stream to the saved position of the deferred function body
and
+ // restore the real linkage type for the function.
+ Stream.JumpToBit(DFII-second.first);
+ F-setLinkage((GlobalValue::LinkageTypes)DFII-second.second);
+ DeferredFunctionInfo.erase(DFII);
+
+ return false;
+}
+
+
//===--===//
// External interface
//===--===//
Index: llvm/lib/Bitcode/Reader/BitcodeReader.h
diff -u
[llvm-commits] CVS: llvm/lib/Bitcode/Reader/BitcodeReader.cpp BitcodeReader.h
Changes in directory llvm/lib/Bitcode/Reader:
BitcodeReader.cpp updated: 1.18 - 1.19
BitcodeReader.h updated: 1.12 - 1.13
---
Log message:
The stream to read from is now an ivar
---
Diffs of the changes: (+18 -20)
BitcodeReader.cpp | 25 -
BitcodeReader.h | 13 ++---
2 files changed, 18 insertions(+), 20 deletions(-)
Index: llvm/lib/Bitcode/Reader/BitcodeReader.cpp
diff -u llvm/lib/Bitcode/Reader/BitcodeReader.cpp:1.18
llvm/lib/Bitcode/Reader/BitcodeReader.cpp:1.19
--- llvm/lib/Bitcode/Reader/BitcodeReader.cpp:1.18 Mon Apr 30 23:59:48 2007
+++ llvm/lib/Bitcode/Reader/BitcodeReader.cpp Tue May 1 00:01:34 2007
@@ -152,7 +152,7 @@
}
-bool BitcodeReader::ParseTypeTable(BitstreamReader Stream) {
+bool BitcodeReader::ParseTypeTable() {
if (Stream.EnterSubBlock())
return Error(Malformed block record);
@@ -298,7 +298,7 @@
}
-bool BitcodeReader::ParseTypeSymbolTable(BitstreamReader Stream) {
+bool BitcodeReader::ParseTypeSymbolTable() {
if (Stream.EnterSubBlock())
return Error(Malformed block record);
@@ -346,7 +346,7 @@
}
}
-bool BitcodeReader::ParseValueSymbolTable(BitstreamReader Stream) {
+bool BitcodeReader::ParseValueSymbolTable() {
if (Stream.EnterSubBlock())
return Error(Malformed block record);
@@ -444,7 +444,7 @@
}
-bool BitcodeReader::ParseConstants(BitstreamReader Stream) {
+bool BitcodeReader::ParseConstants() {
if (Stream.EnterSubBlock())
return Error(Malformed block record);
@@ -661,7 +661,7 @@
/// ParseFunction - When we see the block for a function body, remember where
it
/// is and then skip it. This lets us lazily deserialize the functions.
-bool BitcodeReader::ParseFunction(BitstreamReader Stream) {
+bool BitcodeReader::ParseFunction() {
// Get the function we are talking about.
if (FunctionsWithBodies.empty())
return Error(Insufficient function protos);
@@ -683,8 +683,7 @@
return false;
}
-bool BitcodeReader::ParseModule(BitstreamReader Stream,
-const std::string ModuleID) {
+bool BitcodeReader::ParseModule(const std::string ModuleID) {
// Reject multiple MODULE_BLOCK's in a single bitstream.
if (TheModule)
return Error(Multiple MODULE_BLOCKs in same stream);
@@ -719,19 +718,19 @@
return Error(Malformed block record);
break;
case bitc::TYPE_BLOCK_ID:
-if (ParseTypeTable(Stream))
+if (ParseTypeTable())
return true;
break;
case bitc::TYPE_SYMTAB_BLOCK_ID:
-if (ParseTypeSymbolTable(Stream))
+if (ParseTypeSymbolTable())
return true;
break;
case bitc::VALUE_SYMTAB_BLOCK_ID:
-if (ParseValueSymbolTable(Stream))
+if (ParseValueSymbolTable())
return true;
break;
case bitc::CONSTANTS_BLOCK_ID:
-if (ParseConstants(Stream) || ResolveGlobalAndAliasInits())
+if (ParseConstants() || ResolveGlobalAndAliasInits())
return true;
break;
case bitc::FUNCTION_BLOCK_ID:
@@ -742,7 +741,7 @@
HasReversedFunctionsWithBodies = true;
}
-if (ParseFunction(Stream))
+if (ParseFunction())
return true;
break;
}
@@ -932,7 +931,7 @@
// We only know the MODULE subblock ID.
if (BlockID == bitc::MODULE_BLOCK_ID) {
- if (ParseModule(Stream, Buffer-getBufferIdentifier()))
+ if (ParseModule(Buffer-getBufferIdentifier()))
return true;
} else if (Stream.SkipBlock()) {
return Error(Malformed block record);
Index: llvm/lib/Bitcode/Reader/BitcodeReader.h
diff -u llvm/lib/Bitcode/Reader/BitcodeReader.h:1.12
llvm/lib/Bitcode/Reader/BitcodeReader.h:1.13
--- llvm/lib/Bitcode/Reader/BitcodeReader.h:1.12Mon Apr 30 23:59:48 2007
+++ llvm/lib/Bitcode/Reader/BitcodeReader.h Tue May 1 00:01:34 2007
@@ -23,7 +23,6 @@
#include vector
namespace llvm {
- class BitstreamReader;
class MemoryBuffer;
class BitcodeReaderValueList : public User {
@@ -117,12 +116,12 @@
private:
const Type *getTypeByID(unsigned ID, bool isTypeTable = false);
- bool ParseModule(BitstreamReader Stream, const std::string ModuleID);
- bool ParseTypeTable(BitstreamReader Stream);
- bool ParseTypeSymbolTable(BitstreamReader Stream);
- bool ParseValueSymbolTable(BitstreamReader Stream);
- bool ParseConstants(BitstreamReader Stream);
- bool ParseFunction(BitstreamReader Stream);
+ bool ParseModule(const std::string ModuleID);
+ bool ParseTypeTable();
+ bool ParseTypeSymbolTable();
+ bool ParseValueSymbolTable();
+ bool ParseConstants();
+ bool ParseFunction();
bool ResolveGlobalAndAliasInits();
};
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[llvm-commits] CVS: llvm/include/llvm/Bitcode/BitstreamReader.h
Changes in directory llvm/include/llvm/Bitcode:
BitstreamReader.h updated: 1.10 - 1.11
---
Log message:
several bitfixes to JumpToBit
---
Diffs of the changes: (+7 -4)
BitstreamReader.h | 11 +++
1 files changed, 7 insertions(+), 4 deletions(-)
Index: llvm/include/llvm/Bitcode/BitstreamReader.h
diff -u llvm/include/llvm/Bitcode/BitstreamReader.h:1.10
llvm/include/llvm/Bitcode/BitstreamReader.h:1.11
--- llvm/include/llvm/Bitcode/BitstreamReader.h:1.10Mon Apr 30 23:59:06 2007
+++ llvm/include/llvm/Bitcode/BitstreamReader.h Tue May 1 00:51:32 2007
@@ -93,16 +93,19 @@
/// JumpToBit - Reset the stream to the specified bit number.
void JumpToBit(uint64_t BitNo) {
-unsigned WordNo = BitNo/32;
+unsigned ByteNo = (BitNo/8) ~3;
unsigned WordBitNo = BitNo 31;
-assert(WordNo (unsigned)(LastChar-FirstChar) Invalid location);
+assert(ByteNo (unsigned)(LastChar-FirstChar) Invalid location);
// Move the cursor to the right word.
-NextChar = FirstChar+WordNo;
+NextChar = FirstChar+ByteNo;
BitsInCurWord = 0;
// Skip over any bits that are already consumed.
-if (WordBitNo) Read(WordBitNo);
+if (WordBitNo) {
+ NextChar -= 4;
+ Read(WordBitNo);
+}
}
/// GetAbbrevIDWidth - Return the number of bits used to encode an abbrev #.
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[llvm-commits] CVS: llvm/lib/Bitcode/Reader/BitcodeReader.cpp BitcodeReader.h
Changes in directory llvm/lib/Bitcode/Reader:
BitcodeReader.cpp updated: 1.19 - 1.20
BitcodeReader.h updated: 1.13 - 1.14
---
Log message:
implement materializeModule, force deallocation of vector memory when we
are done with them, start implementing ParseFunctionBody
---
Diffs of the changes: (+107 -15)
BitcodeReader.cpp | 105 ++
BitcodeReader.h | 17
2 files changed, 107 insertions(+), 15 deletions(-)
Index: llvm/lib/Bitcode/Reader/BitcodeReader.cpp
diff -u llvm/lib/Bitcode/Reader/BitcodeReader.cpp:1.19
llvm/lib/Bitcode/Reader/BitcodeReader.cpp:1.20
--- llvm/lib/Bitcode/Reader/BitcodeReader.cpp:1.19 Tue May 1 00:01:34 2007
+++ llvm/lib/Bitcode/Reader/BitcodeReader.cpp Tue May 1 00:52:21 2007
@@ -659,9 +659,10 @@
}
}
-/// ParseFunction - When we see the block for a function body, remember where
it
-/// is and then skip it. This lets us lazily deserialize the functions.
-bool BitcodeReader::ParseFunction() {
+/// RememberAndSkipFunctionBody - When we see the block for a function body,
+/// remember where it is and then skip it. This lets us lazily deserialize the
+/// functions.
+bool BitcodeReader::RememberAndSkipFunctionBody() {
// Get the function we are talking about.
if (FunctionsWithBodies.empty())
return Error(Insufficient function protos);
@@ -701,13 +702,21 @@
while (!Stream.AtEndOfStream()) {
unsigned Code = Stream.ReadCode();
if (Code == bitc::END_BLOCK) {
+ if (Stream.ReadBlockEnd())
+return Error(Error at end of module block);
+
+ // Patch the initializers for globals and aliases up.
ResolveGlobalAndAliasInits();
if (!GlobalInits.empty() || !AliasInits.empty())
return Error(Malformed global initializer set);
if (!FunctionsWithBodies.empty())
return Error(Too few function bodies found);
- if (Stream.ReadBlockEnd())
-return Error(Error at end of module block);
+
+ // Force deallocation of memory for these vectors to favor the client
that
+ // want lazy deserialization.
+ std::vectorstd::pairGlobalVariable*, unsigned ().swap(GlobalInits);
+ std::vectorstd::pairGlobalAlias*, unsigned ().swap(AliasInits);
+ std::vectorFunction*().swap(FunctionsWithBodies);
return false;
}
@@ -741,7 +750,7 @@
HasReversedFunctionsWithBodies = true;
}
-if (ParseFunction())
+if (RememberAndSkipFunctionBody())
return true;
break;
}
@@ -956,6 +965,90 @@
F-setLinkage((GlobalValue::LinkageTypes)DFII-second.second);
DeferredFunctionInfo.erase(DFII);
+ if (ParseFunctionBody(F)) {
+if (ErrInfo) *ErrInfo = ErrorString;
+return true;
+ }
+
+ return false;
+}
+
+Module *BitcodeReader::materializeModule(std::string *ErrInfo) {
+ DenseMapFunction*, std::pairuint64_t, unsigned ::iterator I =
+DeferredFunctionInfo.begin();
+ while (!DeferredFunctionInfo.empty()) {
+Function *F = (*I++).first;
+assert(F-hasNotBeenReadFromBytecode()
+ Deserialized function found in map!);
+if (materializeFunction(F, ErrInfo))
+ return 0;
+ }
+ return TheModule;
+}
+
+
+/// ParseFunctionBody - Lazily parse the specified function body block.
+bool BitcodeReader::ParseFunctionBody(Function *F) {
+ if (Stream.EnterSubBlock())
+return Error(Malformed block record);
+
+ unsigned ModuleValueListSize = ValueList.size();
+
+ // Add all the function arguments to the value table.
+ for(Function::arg_iterator I = F-arg_begin(), E = F-arg_end(); I != E; ++I)
+ValueList.push_back(I);
+
+ // Read all the records.
+ SmallVectoruint64_t, 64 Record;
+ while (1) {
+unsigned Code = Stream.ReadCode();
+if (Code == bitc::END_BLOCK) {
+ if (Stream.ReadBlockEnd())
+return Error(Error at end of function block);
+ break;
+}
+
+if (Code == bitc::ENTER_SUBBLOCK) {
+ switch (Stream.ReadSubBlockID()) {
+ default: // Skip unknown content.
+if (Stream.SkipBlock())
+ return Error(Malformed block record);
+break;
+ case bitc::CONSTANTS_BLOCK_ID:
+if (ParseConstants()) return true;
+break;
+ case bitc::VALUE_SYMTAB_BLOCK_ID:
+if (ParseValueSymbolTable()) return true;
+break;
+ }
+ continue;
+}
+
+if (Code == bitc::DEFINE_ABBREV) {
+ Stream.ReadAbbrevRecord();
+ continue;
+}
+
+// Read a record.
+Record.clear();
+switch (Stream.ReadRecord(Code, Record)) {
+default: // Default behavior: unknown constant
+case bitc::FUNC_CODE_DECLAREBLOCKS: // DECLAREBLOCKS: [nblocks]
+ if (Record.size() 1)
+return Error(Invalid FUNC_CODE_DECLAREBLOCKS record);
+ // Create all the basic blocks for the function.
+ FunctionBBs.resize(Record.size());
+ for (unsigned i = 0, e = FunctionBBs.size(); i != e; ++i)
+
[llvm-commits] CVS: llvm/lib/Target/Target.td
Changes in directory llvm/lib/Target:
Target.td updated: 1.96 - 1.97
---
Log message:
llvm bug #1350, parts 1, 2, and 3.
---
Diffs of the changes: (+9 -7)
Target.td | 16 +---
1 files changed, 9 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.96 llvm/lib/Target/Target.td:1.97
--- llvm/lib/Target/Target.td:1.96 Fri Apr 20 16:13:46 2007
+++ llvm/lib/Target/Target.td Tue May 1 00:57:02 2007
@@ -67,13 +67,15 @@
let SubRegs = subregs;
}
-// RegisterGroup - This can be used to define instances of Register which
-// need to specify aliases.
-// List aliases specifies which registers are aliased to this one. This
-// allows the code generator to be careful not to put two values with
-// overlapping live ranges into registers which alias.
-class RegisterGroupstring n, listRegister aliases : Registern {
- let Aliases = aliases;
+// SubRegSet - This can be used to define a specific mapping of registers to
+// indices, for use as named subregs of a particular physical register. Each
+// register in 'subregs' becomes an addressable subregister at index 'n' of the
+// corresponding register in 'regs'.
+class SubRegSetint n, listRegister regs, listRegister subregs {
+ int index = n;
+
+ listRegister From = regs;
+ listRegister To = subregs;
}
// RegisterClass - Now that all of the registers are defined, and aliases
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h
Changes in directory llvm/include/llvm/CodeGen:
MachineInstr.h updated: 1.217 - 1.218
---
Log message:
llvm bug #1350, parts 1, 2, and 3.
---
Diffs of the changes: (+31 -16)
MachineInstr.h | 47 +++
1 files changed, 31 insertions(+), 16 deletions(-)
Index: llvm/include/llvm/CodeGen/MachineInstr.h
diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.217
llvm/include/llvm/CodeGen/MachineInstr.h:1.218
--- llvm/include/llvm/CodeGen/MachineInstr.h:1.217 Thu Apr 26 13:59:33 2007
+++ llvm/include/llvm/CodeGen/MachineInstr.hTue May 1 00:57:01 2007
@@ -71,10 +71,17 @@
// immediately after the write. i.e. A register
// that is defined but never used.
- /// offset - Offset to address of global or external, only valid for
- /// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex
- int offset;
-
+ /// auxInfo - auxiliary information used by the MachineOperand
+ union {
+/// offset - Offset to address of global or external, only valid for
+/// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex
+int offset;
+
+/// subReg - SubRegister number, only valid for MO_Register. A value of 0
+/// indicates the MO_Register has no subReg.
+unsigned subReg;
+ } auxInfo;
+
MachineOperand() {}
void print(std::ostream os) const;
@@ -95,7 +102,7 @@
Op.IsImp = false;
Op.IsKill = false;
Op.IsDead = false;
-Op.offset = 0;
+Op.auxInfo.offset = 0;
return Op;
}
@@ -106,7 +113,7 @@
IsKill = MO.IsKill;
IsDead = MO.IsDead;
opType = MO.opType;
-offset = MO.offset;
+auxInfo = MO.auxInfo;
return *this;
}
@@ -169,7 +176,11 @@
int getOffset() const {
assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex())
Wrong MachineOperand accessor);
-return offset;
+return auxInfo.offset;
+ }
+ unsigned getSubReg() const {
+assert(isRegister() Wrong MachineOperand accessor);
+return auxInfo.subReg;
}
const char *getSymbolName() const {
assert(isExternalSymbol() Wrong MachineOperand accessor);
@@ -254,7 +265,11 @@
assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex() ||
isJumpTableIndex())
Wrong MachineOperand accessor);
-offset = Offset;
+auxInfo.offset = Offset;
+ }
+ void setSubReg(unsigned subReg) {
+assert(isRegister() Wrong MachineOperand accessor);
+auxInfo.subReg = subReg;
}
void setConstantPoolIndex(unsigned Idx) {
assert(isConstantPoolIndex() Wrong MachineOperand accessor);
@@ -433,7 +448,7 @@
Op.IsKill = IsKill;
Op.IsDead = IsDead;
Op.contents.RegNo = Reg;
-Op.offset = 0;
+Op.auxInfo.subReg = 0;
}
/// addImmOperand - Add a zero extended constant argument to the
@@ -443,14 +458,14 @@
MachineOperand Op = AddNewOperand();
Op.opType = MachineOperand::MO_Immediate;
Op.contents.immedVal = Val;
-Op.offset = 0;
+Op.auxInfo.offset = 0;
}
void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
MachineOperand Op = AddNewOperand();
Op.opType = MachineOperand::MO_MachineBasicBlock;
Op.contents.MBB = MBB;
-Op.offset = 0;
+Op.auxInfo.offset = 0;
}
/// addFrameIndexOperand - Add an abstract frame index to the instruction
@@ -459,7 +474,7 @@
MachineOperand Op = AddNewOperand();
Op.opType = MachineOperand::MO_FrameIndex;
Op.contents.immedVal = Idx;
-Op.offset = 0;
+Op.auxInfo.offset = 0;
}
/// addConstantPoolndexOperand - Add a constant pool object index to the
@@ -469,7 +484,7 @@
MachineOperand Op = AddNewOperand();
Op.opType = MachineOperand::MO_ConstantPoolIndex;
Op.contents.immedVal = Idx;
-Op.offset = Offset;
+Op.auxInfo.offset = Offset;
}
/// addJumpTableIndexOperand - Add a jump table object index to the
@@ -479,14 +494,14 @@
MachineOperand Op = AddNewOperand();
Op.opType = MachineOperand::MO_JumpTableIndex;
Op.contents.immedVal = Idx;
-Op.offset = 0;
+Op.auxInfo.offset = 0;
}
void addGlobalAddressOperand(GlobalValue *GV, int Offset) {
MachineOperand Op = AddNewOperand();
Op.opType = MachineOperand::MO_GlobalAddress;
Op.contents.GV = GV;
-Op.offset = Offset;
+Op.auxInfo.offset = Offset;
}
/// addExternalSymbolOperand - Add an external symbol operand to this instr
@@ -495,7 +510,7 @@
MachineOperand Op = AddNewOperand();
Op.opType = MachineOperand::MO_ExternalSymbol;
Op.contents.SymbolName = SymName;
-Op.offset = 0;
+Op.auxInfo.offset = 0;
}
//======//
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.td updated: 1.44 - 1.45
---
Log message:
llvm bug #1350, parts 1, 2, and 3.
---
Diffs of the changes: (+50 -1)
PPCRegisterInfo.td | 51 ++-
1 files changed, 50 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.44
llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.45
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.44 Mon Jan 29 16:57:48 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td Tue May 1 00:57:02 2007
@@ -43,10 +43,16 @@
}
// CR - One of the 8 4-bit condition registers
-class CRbits5 num, string n : PPCRegn {
+class CRbits3 num, string n : PPCRegn {
+ field bits3 Num = num;
+}
+
+// CRBIT - One of the 32 1-bit condition register fields
+class CRBITbits5 num, string n : PPCRegn {
field bits5 Num = num;
}
+
// General-purpose registers
def R0 : GPR 0, r0, DwarfRegNum0;
def R1 : GPR 1, r1, DwarfRegNum1;
@@ -193,6 +199,49 @@
def CR6 : CR6, cr6, DwarfRegNum74;
def CR7 : CR7, cr7, DwarfRegNum75;
+// Condition register bits
+def CR0LT : CRBIT 0, 0, DwarfRegNum0;
+def CR0GT : CRBIT 1, 1, DwarfRegNum0;
+def CR0EQ : CRBIT 2, 2, DwarfRegNum0;
+def CR0UN : CRBIT 3, 3, DwarfRegNum0;
+def CR1LT : CRBIT 4, 4, DwarfRegNum0;
+def CR1GT : CRBIT 5, 5, DwarfRegNum0;
+def CR1EQ : CRBIT 6, 6, DwarfRegNum0;
+def CR1UN : CRBIT 7, 7, DwarfRegNum0;
+def CR2LT : CRBIT 8, 8, DwarfRegNum0;
+def CR2GT : CRBIT 9, 9, DwarfRegNum0;
+def CR2EQ : CRBIT10, 10, DwarfRegNum0;
+def CR2UN : CRBIT11, 11, DwarfRegNum0;
+def CR3LT : CRBIT12, 12, DwarfRegNum0;
+def CR3GT : CRBIT13, 13, DwarfRegNum0;
+def CR3EQ : CRBIT14, 14, DwarfRegNum0;
+def CR3UN : CRBIT15, 15, DwarfRegNum0;
+def CR4LT : CRBIT16, 16, DwarfRegNum0;
+def CR4GT : CRBIT17, 17, DwarfRegNum0;
+def CR4EQ : CRBIT18, 18, DwarfRegNum0;
+def CR4UN : CRBIT19, 19, DwarfRegNum0;
+def CR5LT : CRBIT20, 20, DwarfRegNum0;
+def CR5GT : CRBIT21, 21, DwarfRegNum0;
+def CR5EQ : CRBIT22, 22, DwarfRegNum0;
+def CR5UN : CRBIT23, 23, DwarfRegNum0;
+def CR6LT : CRBIT24, 24, DwarfRegNum0;
+def CR6GT : CRBIT25, 25, DwarfRegNum0;
+def CR6EQ : CRBIT26, 26, DwarfRegNum0;
+def CR6UN : CRBIT27, 27, DwarfRegNum0;
+def CR7LT : CRBIT28, 28, DwarfRegNum0;
+def CR7GT : CRBIT29, 29, DwarfRegNum0;
+def CR7EQ : CRBIT30, 30, DwarfRegNum0;
+def CR7UN : CRBIT31, 31, DwarfRegNum0;
+
+def : SubRegSet1, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
+ [CR0LT, CR1LT, CR2LT, CR3LT, CR4LT, CR5LT, CR6LT, CR7LT];
+def : SubRegSet2, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
+ [CR0GT, CR1GT, CR2GT, CR3GT, CR4GT, CR5GT, CR6GT, CR7GT];
+def : SubRegSet3, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
+ [CR0EQ, CR1EQ, CR2EQ, CR3EQ, CR4EQ, CR5EQ, CR6EQ, CR7EQ];
+def : SubRegSet4, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
+ [CR0UN, CR1UN, CR2UN, CR3UN, CR4UN, CR5UN, CR6UN, CR7UN];
+
// Link register
def LR : SPR8, lr, DwarfRegNum65;
//let Aliases = [LR] in
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[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.52 - 1.53
---
Log message:
llvm bug #1350, parts 1, 2, and 3.
---
Diffs of the changes: (+36 -0)
RegisterInfoEmitter.cpp | 36
1 files changed, 36 insertions(+)
Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.52
llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.53
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.52Fri Apr 20 19:55:29 2007
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Tue May 1 00:57:02 2007
@@ -61,6 +61,7 @@
ClassName
(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n
int getDwarfRegNum(unsigned RegNum) const;\n
+unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n
};\n\n;
const std::vectorCodeGenRegisterClass RegisterClasses =
@@ -322,6 +323,7 @@
std::mapRecord*, std::setRecord* RegisterSubRegs;
std::mapRecord*, std::setRecord* RegisterSuperRegs;
std::mapRecord*, std::setRecord* RegisterAliases;
+ std::mapRecord*, std::vectorstd::pairint, Record* SubRegVectors;
const std::vectorCodeGenRegister Regs = Target.getRegisters();
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
@@ -441,6 +443,40 @@
std::string ClassName = Target.getName() + GenRegisterInfo;
+ // Calculate the mapping of subregister+index pairs to physical registers.
+ std::vectorRecord* SubRegs = Records.getAllDerivedDefinitions(SubRegSet);
+ for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
+int subRegIndex = SubRegs[i]-getValueAsInt(index);
+std::vectorRecord* From = SubRegs[i]-getValueAsListOfDefs(From);
+std::vectorRecord* To = SubRegs[i]-getValueAsListOfDefs(To);
+
+assert((From.size() == To.size())
+ SubRegSet has mismatched from/to size);
+
+// For each entry in from/to vectors, insert the to register at index
+for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
+ SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii]));
+ }
+
+ // Emit the subregister + index mapping function based on the information
+ // calculated above.
+ OS unsigned ClassName
+ ::getSubReg(unsigned RegNo, unsigned Index) const {\n
+switch (RegNo) {\n
+default: abort(); break;\n;
+ for (std::mapRecord*, std::vectorstd::pairint, Record* ::iterator
+I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
+OScase getQualifiedName(I-first) :\n;
+OS switch (Index) {\n;
+OS default: abort(); break;\n;
+for (unsigned i = 0, e = I-second.size(); i != e; ++i)
+ OS case (I-second)[i].first : return
+ getQualifiedName((I-second)[i].second) ;\n;
+OS }; break;\n;
+ }
+ OS};\n;
+ OS }\n\n;
+
// Emit the constructor of the class...
OS ClassName :: ClassName
(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n
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[llvm-commits] CVS: llvm/lib/CodeGen/MachineInstr.cpp
Changes in directory llvm/lib/CodeGen: MachineInstr.cpp updated: 1.147 - 1.148 --- Log message: llvm bug #1350, parts 1, 2, and 3. --- Diffs of the changes: (+2 -2) MachineInstr.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/MachineInstr.cpp diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.147 llvm/lib/CodeGen/MachineInstr.cpp:1.148 --- llvm/lib/CodeGen/MachineInstr.cpp:1.147 Thu Apr 26 13:59:33 2007 +++ llvm/lib/CodeGen/MachineInstr.cpp Tue May 1 00:57:02 2007 @@ -39,7 +39,7 @@ Op.IsKill = false; Op.IsDead = false; Op.contents.RegNo = *ImpDefs; - Op.offset = 0; + Op.auxInfo.subReg = 0; Operands.push_back(Op); } if (TID-ImplicitUses) @@ -51,7 +51,7 @@ Op.IsKill = false; Op.IsDead = false; Op.contents.RegNo = *ImpUses; - Op.offset = 0; + Op.auxInfo.subReg = 0; Operands.push_back(Op); } } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.108 - 1.109
---
Log message:
llvm bug #1350, parts 1, 2, and 3.
---
Diffs of the changes: (+5 -1)
MRegisterInfo.h |6 +-
1 files changed, 5 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.108
llvm/include/llvm/Target/MRegisterInfo.h:1.109
--- llvm/include/llvm/Target/MRegisterInfo.h:1.108 Mon Apr 30 19:47:46 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hTue May 1 00:57:02 2007
@@ -41,7 +41,7 @@
/// The SubRegs field is a zero terminated array of registers that are
/// sub-registers of the specific register, e.g. AL, AH are sub-registers of
AX.
/// The SuperRegs field is a zero terminated array of registers that are
-/// super-registers of the specific register, e.g. RAX, EAX, are sub-registers
+/// super-registers of the specific register, e.g. RAX, EAX, are
super-registers
/// of AX.
///
struct TargetRegisterDesc {
@@ -354,6 +354,10 @@
/// register scavenger to determine what registers are free.
virtual BitVector getReservedRegs(const MachineFunction MF) const = 0;
+ /// getSubReg - Returns the physical register number of sub-register Index
+ /// for physical register RegNo.
+ virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
+
//======//
// Register Class Information
//
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