[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.65 -> 1.66
---
Log message:
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
---
Diffs of the changes: (+13 -7)
MRegisterInfo.h | 20 +---
1 files changed, 13 insertions(+), 7 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.65
llvm/include/llvm/Target/MRegisterInfo.h:1.66
--- llvm/include/llvm/Target/MRegisterInfo.h:1.65 Sun Oct 2 22:32:39 2005
+++ llvm/include/llvm/Target/MRegisterInfo.hWed Nov 30 22:51:06 2005
@@ -45,18 +45,15 @@
typedef const unsigned* const_iterator;
private:
- const MVT::ValueType VT;
+ const MVT::ValueType* VTs;
const unsigned RegSize, Alignment;// Size & Alignment of register in
bytes
const iterator RegsBegin, RegsEnd;
public:
- TargetRegisterClass(MVT::ValueType vt, unsigned RS, unsigned Al, iterator
RB, iterator RE)
-: VT(vt), RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
+ TargetRegisterClass(const MVT::ValueType *vts, unsigned RS, unsigned Al,
+ iterator RB, iterator RE)
+: VTs(vts), RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
virtual ~TargetRegisterClass() {} // Allow subclasses
- /// getType - Return the declared value type for this register class.
- ///
- MVT::ValueType getType() const { return VT; }
-
// begin/end - Return all of the registers in this class.
iterator begin() const { return RegsBegin; }
iterator end() const { return RegsEnd; }
@@ -78,6 +75,15 @@
return false;
}
+ /// hasType - return true if this TargetRegisterClass has the ValueType vt.
+ ///
+ bool hasType(MVT::ValueType vt) const {
+for(int i = 0; VTs[i] != MVT::Other; ++i)
+ if (VTs[i] == vt)
+return true;
+return false;
+ }
+
/// allocation_order_begin/end - These methods define a range of registers
/// which specify the registers in this class that are valid to register
/// allocate, and the preferred order to allocate them in. For example,
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.66 -> 1.67
---
Log message:
add a new isStoreToStackSlot method
---
Diffs of the changes: (+10 -1)
MRegisterInfo.h | 11 ++-
1 files changed, 10 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.66
llvm/include/llvm/Target/MRegisterInfo.h:1.67
--- llvm/include/llvm/Target/MRegisterInfo.h:1.66 Wed Nov 30 22:51:06 2005
+++ llvm/include/llvm/Target/MRegisterInfo.hThu Feb 2 13:55:29 2006
@@ -262,12 +262,21 @@
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If
- /// not, return 0. This predicate must return false if the instruction has
+ /// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex)
const{
return 0;
}
+ /// isStoreToStackSlot - If the specified machine instruction is a direct
+ /// store to a stack slot, return the virtual or physical register number of
+ /// the source reg along with the FrameIndex of the loaded stack slot. If
+ /// not, return 0. This predicate must return 0 if the instruction has
+ /// any side effects other than storing to the stack slot.
+ virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const
{
+return 0;
+ }
+
/// foldMemoryOperand - Attempt to fold a load or store of the
/// specified stack slot into the specified machine instruction for
/// the specified operand. If this is possible, a new instruction
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.68 -> 1.69
---
Log message:
expose the set of values types holdable in a regclass to clients
---
Diffs of the changes: (+17 -1)
MRegisterInfo.h | 18 +-
1 files changed, 17 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.68
llvm/include/llvm/Target/MRegisterInfo.h:1.69
--- llvm/include/llvm/Target/MRegisterInfo.h:1.68 Thu Feb 2 14:11:55 2006
+++ llvm/include/llvm/Target/MRegisterInfo.hTue Feb 21 17:51:58 2006
@@ -44,8 +44,9 @@
typedef const unsigned* iterator;
typedef const unsigned* const_iterator;
+ typedef const MVT::ValueType* vt_iterator;
private:
- const MVT::ValueType* VTs;
+ const vt_iterator VTs;
const unsigned RegSize, Alignment;// Size & Alignment of register in
bytes
const iterator RegsBegin, RegsEnd;
public:
@@ -84,6 +85,21 @@
return false;
}
+ /// vt_begin - Loop over all of the value types that can be represented by
+ /// values in this register class.
+ vt_iterator vt_begin() const {
+return VTs;
+ }
+
+ /// vt_begin - Loop over all of the value types that can be represented by
+ /// values in this register class.
+ vt_iterator vt_end() const {
+vt_iterator I = VTs;
+while (*I != MVT::Other) ++I;
+return I;
+ }
+
+
/// allocation_order_begin/end - These methods define a range of registers
/// which specify the registers in this class that are valid to register
/// allocate, and the preferred order to allocate them in. For example,
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.70 -> 1.71 --- Log message: Add support to locate local variables in frames (early version.) --- Diffs of the changes: (+6 -0) MRegisterInfo.h |6 ++ 1 files changed, 6 insertions(+) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.70 llvm/include/llvm/Target/MRegisterInfo.h:1.71 --- llvm/include/llvm/Target/MRegisterInfo.h:1.70 Wed Feb 22 10:23:43 2006 +++ llvm/include/llvm/Target/MRegisterInfo.hThu Mar 23 12:12:57 2006 @@ -26,6 +26,7 @@ class Type; class MachineFunction; class MachineInstr; +class MachineLocation; class TargetRegisterClass; /// TargetRegisterDesc - This record contains all of the information known about @@ -341,6 +342,11 @@ virtual void emitPrologue(MachineFunction &MF) const = 0; virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const = 0; + + /// getLocation - This method should return the actual location of a frame + /// variable given the frame index. + virtual void getLocation(MachineFunction &MF, unsigned Index, + MachineLocation &ML) const = 0; }; // This is useful when building DenseMaps keyed on virtual registers ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.71 -> 1.72 --- Log message: Tweak a comment. --- Diffs of the changes: (+1 -1) MRegisterInfo.h |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.71 llvm/include/llvm/Target/MRegisterInfo.h:1.72 --- llvm/include/llvm/Target/MRegisterInfo.h:1.71 Thu Mar 23 12:12:57 2006 +++ llvm/include/llvm/Target/MRegisterInfo.hFri Mar 24 10:18:42 2006 @@ -344,7 +344,7 @@ MachineBasicBlock &MBB) const = 0; /// getLocation - This method should return the actual location of a frame - /// variable given the frame index. + /// variable given the frame index. The location is returned in ML. virtual void getLocation(MachineFunction &MF, unsigned Index, MachineLocation &ML) const = 0; }; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.72 -> 1.73 --- Log message: Expose base register for DwarfWriter. Refactor code accordingly. --- Diffs of the changes: (+11 -1) MRegisterInfo.h | 12 +++- 1 files changed, 11 insertions(+), 1 deletion(-) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.72 llvm/include/llvm/Target/MRegisterInfo.h:1.73 --- llvm/include/llvm/Target/MRegisterInfo.h:1.72 Fri Mar 24 10:18:42 2006 +++ llvm/include/llvm/Target/MRegisterInfo.hTue Mar 28 07:48:33 2006 @@ -343,10 +343,20 @@ virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const = 0; + //======// + /// Debug information queries. + + /// getFrameRegister - This method should return the register used as a base + /// for values allocated in the current stack frame. This value should be + /// returned as a dwarf register number (getDwarfRegNum.) + virtual unsigned getFrameRegister(MachineFunction &MF) const = 0; + /// getLocation - This method should return the actual location of a frame /// variable given the frame index. The location is returned in ML. + /// Subclasses should override this method for special handling of frame + /// variables and call MRegisterInfo::getLocation for the default action. virtual void getLocation(MachineFunction &MF, unsigned Index, - MachineLocation &ML) const = 0; + MachineLocation &ML) const; }; // This is useful when building DenseMaps keyed on virtual registers ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.73 -> 1.74 --- Log message: Foundation for call frame information. --- Diffs of the changes: (+20 -2) MRegisterInfo.h | 22 -- 1 files changed, 20 insertions(+), 2 deletions(-) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.73 llvm/include/llvm/Target/MRegisterInfo.h:1.74 --- llvm/include/llvm/Target/MRegisterInfo.h:1.73 Tue Mar 28 07:48:33 2006 +++ llvm/include/llvm/Target/MRegisterInfo.hFri Apr 7 11:34:45 2006 @@ -27,6 +27,7 @@ class MachineFunction; class MachineInstr; class MachineLocation; +class MachineMove; class TargetRegisterClass; /// TargetRegisterDesc - This record contains all of the information known about @@ -345,18 +346,35 @@ //======// /// Debug information queries. + + /// getDwarfRegNum - Map a target register to an equivalent dwarf register + /// number. Returns -1 if there is no equivalent value. + virtual int getDwarfRegNum(unsigned RegNum) const = 0; /// getFrameRegister - This method should return the register used as a base - /// for values allocated in the current stack frame. This value should be - /// returned as a dwarf register number (getDwarfRegNum.) + /// for values allocated in the current stack frame. virtual unsigned getFrameRegister(MachineFunction &MF) const = 0; + + /// getRARegister - This method should return the register where the return + /// address can be found. + virtual unsigned getRARegister() const = 0; + /// getStackDirection - This method should return the factor by which stacks + /// grow. The tyical value is -4 which is the grows negatively in 4 byte + /// increments. + virtual int getStackDirection() const; + /// getLocation - This method should return the actual location of a frame /// variable given the frame index. The location is returned in ML. /// Subclasses should override this method for special handling of frame /// variables and call MRegisterInfo::getLocation for the default action. virtual void getLocation(MachineFunction &MF, unsigned Index, MachineLocation &ML) const; + + /// getInitialFrameState - Returns a list of machine moves that are assumed + /// on entry to all functions. Note that LabelID is ignored (assumed to be + /// the beginning of the function.) + virtual void getInitialFrameState(std::vector &Moves) const; }; // This is useful when building DenseMaps keyed on virtual registers ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.74 -> 1.75 --- Log message: Use existing information. --- Diffs of the changes: (+0 -5) MRegisterInfo.h |5 - 1 files changed, 5 deletions(-) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.74 llvm/include/llvm/Target/MRegisterInfo.h:1.75 --- llvm/include/llvm/Target/MRegisterInfo.h:1.74 Fri Apr 7 11:34:45 2006 +++ llvm/include/llvm/Target/MRegisterInfo.hMon Apr 10 18:09:19 2006 @@ -359,11 +359,6 @@ /// address can be found. virtual unsigned getRARegister() const = 0; - /// getStackDirection - This method should return the factor by which stacks - /// grow. The tyical value is -4 which is the grows negatively in 4 byte - /// increments. - virtual int getStackDirection() const; - /// getLocation - This method should return the actual location of a frame /// variable given the frame index. The location is returned in ML. /// Subclasses should override this method for special handling of frame ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.84 -> 1.85
---
Log message:
Add virtual method spillCalleeSaveRegisters() and restoreCalleeSaveRegisters()
to MRegisterInfo. These allow the target to issue instructions to spill and
restore callee saved registers in case where individual stores / loads aren't
the correct / profitable choice.
---
Diffs of the changes: (+21 -0)
MRegisterInfo.h | 21 +
1 files changed, 21 insertions(+)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.84
llvm/include/llvm/Target/MRegisterInfo.h:1.85
--- llvm/include/llvm/Target/MRegisterInfo.h:1.84 Wed Sep 27 19:07:19 2006
+++ llvm/include/llvm/Target/MRegisterInfo.hTue Jan 2 14:55:17 2007
@@ -29,6 +29,7 @@
class MachineLocation;
class MachineMove;
class TargetRegisterClass;
+class CalleeSavedInfo;
/// TargetRegisterDesc - This record contains all of the information known
about
/// a particular register. The AliasSet field (if not null) contains a pointer
@@ -319,6 +320,26 @@
// immediates and memory. FIXME: Move these to TargetInstrInfo.h.
//
+ /// spillCalleeSaveRegisters - Issues instruction(s) to spill all callee
saved
+ /// registers and returns true if it isn't possible / profitable to do so by
+ /// issuing a series of store instructions via storeRegToStackSlot(). Returns
+ /// false otherwise.
+ virtual bool spillCalleeSaveRegisters(MachineBasicBlock &MBB,
+MachineBasicBlock::iterator MI,
+const std::vector &CSI) const
{
+return false;
+ }
+
+ /// restoreCalleeSaveRegisters - Issues instruction(s) to restore all callee
+ /// saved registers and returns true if it isn't possible / profitable to do
+ /// so by issuing a series of load instructions via loadRegToStackSlot().
+ /// Returns false otherwise.
+ virtual bool restoreCalleeSaveRegisters(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+const std::vector &CSI) const
{
+return false;
+ }
+
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIndex,
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.86 -> 1.87 --- Log message: hasFP() is now a virtual method of MRegisterInfo. --- Diffs of the changes: (+5 -0) MRegisterInfo.h |5 + 1 files changed, 5 insertions(+) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.86 llvm/include/llvm/Target/MRegisterInfo.h:1.87 --- llvm/include/llvm/Target/MRegisterInfo.h:1.86 Tue Jan 2 15:30:17 2007 +++ llvm/include/llvm/Target/MRegisterInfo.hMon Jan 22 18:51:23 2007 @@ -367,6 +367,11 @@ return 0; } + /// hasFP - Return true if the specified function should have a dedicated frame + /// pointer register. For most targets this is true only if the function has + /// variable sized allocas or if frame pointer elimination is disabled. + virtual bool hasFP(const MachineFunction &MF) const = 0; + /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the /// frame setup/destroy instructions if they exist (-1 otherwise). Some /// targets use pseudo instructions in order to abstract away the difference ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.87 -> 1.88 --- Log message: Repair debug frames as a prelude to eh_frames. Switched to using MachineMoves by value so that clean up is less confusing (these vectors tend to be small.) --- Diffs of the changes: (+1 -1) MRegisterInfo.h |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.87 llvm/include/llvm/Target/MRegisterInfo.h:1.88 --- llvm/include/llvm/Target/MRegisterInfo.h:1.87 Mon Jan 22 18:51:23 2007 +++ llvm/include/llvm/Target/MRegisterInfo.hWed Jan 24 12:45:12 2007 @@ -456,7 +456,7 @@ /// getInitialFrameState - Returns a list of machine moves that are assumed /// on entry to all functions. Note that LabelID is ignored (assumed to be /// the beginning of the function.) - virtual void getInitialFrameState(std::vector &Moves) const; + virtual void getInitialFrameState(std::vector &Moves) const; }; // This is useful when building DenseMaps keyed on virtual registers ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.88 -> 1.89
---
Log message:
Added a MRegisterInfo hook that tells PEI the target is responsible for
rounding the stack frame to a multiple of stack alignment.
---
Diffs of the changes: (+6 -0)
MRegisterInfo.h |6 ++
1 files changed, 6 insertions(+)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.88
llvm/include/llvm/Target/MRegisterInfo.h:1.89
--- llvm/include/llvm/Target/MRegisterInfo.h:1.88 Wed Jan 24 12:45:12 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hThu Jan 25 16:12:41 2007
@@ -367,6 +367,12 @@
return 0;
}
+ /// targetHandlesStackFrameRounding - Returns true if the target is
responsible
+ /// for rounding up the stack frame (probably at emitPrologue time).
+ virtual bool targetHandlesStackFrameRounding() const {
+return false;
+ }
+
/// hasFP - Return true if the specified function should have a dedicated
frame
/// pointer register. For most targets this is true only if the function has
/// variable sized allocas or if frame pointer elimination is disabled.
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.89 -> 1.90
---
Log message:
rename DenseMap to IndexedMap.
---
Diffs of the changes: (+1 -1)
MRegisterInfo.h |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.89
llvm/include/llvm/Target/MRegisterInfo.h:1.90
--- llvm/include/llvm/Target/MRegisterInfo.h:1.89 Thu Jan 25 16:12:41 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hWed Jan 31 23:32:05 2007
@@ -465,7 +465,7 @@
virtual void getInitialFrameState(std::vector &Moves) const;
};
-// This is useful when building DenseMaps keyed on virtual registers
+// This is useful when building IndexedMaps keyed on virtual registers
struct VirtReg2IndexFunctor : std::unary_function {
unsigned operator()(unsigned Reg) const {
return Reg - MRegisterInfo::FirstVirtualRegister;
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.90 -> 1.91
---
Log message:
Use BitVector instead of vector which can be extremely slow.
---
Diffs of the changes: (+2 -1)
MRegisterInfo.h |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.90
llvm/include/llvm/Target/MRegisterInfo.h:1.91
--- llvm/include/llvm/Target/MRegisterInfo.h:1.90 Wed Jan 31 23:32:05 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hWed Feb 14 23:57:14 2007
@@ -30,6 +30,7 @@
class MachineMove;
class TargetRegisterClass;
class CalleeSavedInfo;
+class BitVector;
/// TargetRegisterDesc - This record contains all of the information known
about
/// a particular register. The AliasSet field (if not null) contains a pointer
@@ -240,7 +241,7 @@
/// getAllocatableSet - Returns a bitset indexed by register number
/// indicating if a register is allocatable or not.
- std::vector getAllocatableSet(MachineFunction &MF) const;
+ BitVector getAllocatableSet(MachineFunction &MF) const;
const TargetRegisterDesc &operator[](unsigned RegNo) const {
assert(RegNo < NumRegs &&
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.91 -> 1.92
---
Log message:
- Added regsOverlap() to test if two registers overlap. Or in case they are
virtual registers, test if they the same.
- Added a virtual method to return target specific reserved registers, e.g. SP.
---
Diffs of the changes: (+17 -0)
MRegisterInfo.h | 17 +
1 files changed, 17 insertions(+)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.91
llvm/include/llvm/Target/MRegisterInfo.h:1.92
--- llvm/include/llvm/Target/MRegisterInfo.h:1.91 Wed Feb 14 23:57:14 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hSat Feb 17 05:04:35 2007
@@ -284,6 +284,17 @@
return false;
}
+ /// regsOverlap - Returns true if the two registers are equal or alias
+ /// each other. The registers may be virtual register.
+ bool regsOverlap(unsigned regA, unsigned regB) const {
+if (regA == regB)
+ return true;
+
+if (isVirtualRegister(regA) || isVirtualRegister(regB))
+ return false;
+return areAliases(regA, regB);
+ }
+
/// getCalleeSavedRegs - Return a null-terminated list of all of the
/// callee saved registers on this target. The register should be in the
/// order of desired callee-save stack frame offset. The first register is
@@ -295,6 +306,12 @@
/// length of this list match the getCalleeSaveRegs() list.
virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const
=0;
+ /// getReservedRegs - Returns a bitset indexed by physical register number
+ /// indicating if a register is a special register that has particular uses
and
+ /// should be considered unavailable at all times, e.g. SP, RA. This is used
by
+ /// register scavenger to determine what registers are free.
+ virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
+
//======//
// Register Class Information
//
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.92 -> 1.93
---
Log message:
For PR1207: http://llvm.org/PR1207 :
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.
---
Diffs of the changes: (+0 -17)
MRegisterInfo.h | 17 -
1 files changed, 17 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.92
llvm/include/llvm/Target/MRegisterInfo.h:1.93
--- llvm/include/llvm/Target/MRegisterInfo.h:1.92 Sat Feb 17 05:04:35 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hSun Feb 18 21:20:00 2007
@@ -284,17 +284,6 @@
return false;
}
- /// regsOverlap - Returns true if the two registers are equal or alias
- /// each other. The registers may be virtual register.
- bool regsOverlap(unsigned regA, unsigned regB) const {
-if (regA == regB)
- return true;
-
-if (isVirtualRegister(regA) || isVirtualRegister(regB))
- return false;
-return areAliases(regA, regB);
- }
-
/// getCalleeSavedRegs - Return a null-terminated list of all of the
/// callee saved registers on this target. The register should be in the
/// order of desired callee-save stack frame offset. The first register is
@@ -306,12 +295,6 @@
/// length of this list match the getCalleeSaveRegs() list.
virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const
=0;
- /// getReservedRegs - Returns a bitset indexed by physical register number
- /// indicating if a register is a special register that has particular uses
and
- /// should be considered unavailable at all times, e.g. SP, RA. This is used
by
- /// register scavenger to determine what registers are free.
- virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
-
//======//
// Register Class Information
//
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.93 -> 1.94
---
Log message:
Re-apply my liveintervalanalysis changes. Now with PR1207:
http://llvm.org/PR1207 fixes.
---
Diffs of the changes: (+17 -0)
MRegisterInfo.h | 17 +
1 files changed, 17 insertions(+)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.93
llvm/include/llvm/Target/MRegisterInfo.h:1.94
--- llvm/include/llvm/Target/MRegisterInfo.h:1.93 Sun Feb 18 21:20:00 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hMon Feb 19 15:49:53 2007
@@ -284,6 +284,17 @@
return false;
}
+ /// regsOverlap - Returns true if the two registers are equal or alias
+ /// each other. The registers may be virtual register.
+ bool regsOverlap(unsigned regA, unsigned regB) const {
+if (regA == regB)
+ return true;
+
+if (isVirtualRegister(regA) || isVirtualRegister(regB))
+ return false;
+return areAliases(regA, regB);
+ }
+
/// getCalleeSavedRegs - Return a null-terminated list of all of the
/// callee saved registers on this target. The register should be in the
/// order of desired callee-save stack frame offset. The first register is
@@ -295,6 +306,12 @@
/// length of this list match the getCalleeSaveRegs() list.
virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const
=0;
+ /// getReservedRegs - Returns a bitset indexed by physical register number
+ /// indicating if a register is a special register that has particular uses
and
+ /// should be considered unavailable at all times, e.g. SP, RA. This is used
by
+ /// register scavenger to determine what registers are free.
+ virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
+
//======//
// Register Class Information
//
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.94 -> 1.95 --- Log message: Support to provide exception and selector registers. --- Diffs of the changes: (+9 -1) MRegisterInfo.h | 10 +- 1 files changed, 9 insertions(+), 1 deletion(-) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.94 llvm/include/llvm/Target/MRegisterInfo.h:1.95 --- llvm/include/llvm/Target/MRegisterInfo.h:1.94 Mon Feb 19 15:49:53 2007 +++ llvm/include/llvm/Target/MRegisterInfo.hWed Feb 21 16:54:50 2007 @@ -469,7 +469,15 @@ /// getRARegister - This method should return the register where the return /// address can be found. virtual unsigned getRARegister() const = 0; - + + /// getEHExceptionRegister - This method should return the register containing + /// the address of the exception info on entry to a landing pad. + virtual unsigned getEHExceptionRegister() const = 0; + + /// getEHHandlerRegister - This method should return the register containing + /// the switch table selection on entry to an landing pad. + virtual unsigned getEHHandlerRegister() const = 0; + /// getLocation - This method should return the actual location of a frame /// variable given the frame index. The location is returned in ML. /// Subclasses should override this method for special handling of frame ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.95 -> 1.96 --- Log message: Simplify lowering and selection of exception ops. --- Diffs of the changes: (+0 -8) MRegisterInfo.h |8 1 files changed, 8 deletions(-) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.95 llvm/include/llvm/Target/MRegisterInfo.h:1.96 --- llvm/include/llvm/Target/MRegisterInfo.h:1.95 Wed Feb 21 16:54:50 2007 +++ llvm/include/llvm/Target/MRegisterInfo.hThu Feb 22 08:56:35 2007 @@ -470,14 +470,6 @@ /// address can be found. virtual unsigned getRARegister() const = 0; - /// getEHExceptionRegister - This method should return the register containing - /// the address of the exception info on entry to a landing pad. - virtual unsigned getEHExceptionRegister() const = 0; - - /// getEHHandlerRegister - This method should return the register containing - /// the switch table selection on entry to an landing pad. - virtual unsigned getEHHandlerRegister() const = 0; - /// getLocation - This method should return the actual location of a frame /// variable given the frame index. The location is returned in ML. /// Subclasses should override this method for special handling of frame ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.96 -> 1.97
---
Log message:
Temporay hook to enable register scavening for specific targets only.
---
Diffs of the changes: (+6 -0)
MRegisterInfo.h |6 ++
1 files changed, 6 insertions(+)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.96
llvm/include/llvm/Target/MRegisterInfo.h:1.97
--- llvm/include/llvm/Target/MRegisterInfo.h:1.96 Thu Feb 22 08:56:35 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hThu Feb 22 19:07:04 2007
@@ -391,6 +391,12 @@
return false;
}
+ /// requiresRegisterScavenging - returns true if the target requires (and
+ /// can make use of) the register scavenger.
+ virtual bool requiresRegisterScavenging() const {
+return false;
+ }
+
/// hasFP - Return true if the specified function should have a dedicated
frame
/// pointer register. For most targets this is true only if the function has
/// variable sized allocas or if frame pointer elimination is disabled.
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.97 -> 1.98
---
Log message:
Let MRegisterInfo owns RegScavenger.
---
Diffs of the changes: (+10 -9)
MRegisterInfo.h | 19 ++-
1 files changed, 10 insertions(+), 9 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.97
llvm/include/llvm/Target/MRegisterInfo.h:1.98
--- llvm/include/llvm/Target/MRegisterInfo.h:1.97 Thu Feb 22 19:07:04 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hTue Feb 27 15:08:07 2007
@@ -23,14 +23,15 @@
namespace llvm {
-class Type;
+class BitVector;
+class CalleeSavedInfo;
class MachineFunction;
class MachineInstr;
class MachineLocation;
class MachineMove;
+class RegScavenger;
class TargetRegisterClass;
-class CalleeSavedInfo;
-class BitVector;
+class Type;
/// TargetRegisterDesc - This record contains all of the information known
about
/// a particular register. The AliasSet field (if not null) contains a pointer
@@ -213,6 +214,12 @@
virtual ~MRegisterInfo();
public:
+ /// getRegScavenger - Returns pointer to an instance of register scavenger it
+ /// the specific target is making use of one.
+ virtual RegScavenger *getRegScavenger() const {
+return NULL;
+ }
+
enum {// Define some target independent constants
/// NoRegister - This physical register is not a real target register. It
/// is useful as a sentinal.
@@ -391,12 +398,6 @@
return false;
}
- /// requiresRegisterScavenging - returns true if the target requires (and
- /// can make use of) the register scavenger.
- virtual bool requiresRegisterScavenging() const {
-return false;
- }
-
/// hasFP - Return true if the specified function should have a dedicated
frame
/// pointer register. For most targets this is true only if the function has
/// variable sized allocas or if frame pointer elimination is disabled.
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.98 -> 1.99
---
Log message:
MRegisterInfo disowns RegScavenger. It's immutable.
---
Diffs of the changes: (+8 -7)
MRegisterInfo.h | 15 ---
1 files changed, 8 insertions(+), 7 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.98
llvm/include/llvm/Target/MRegisterInfo.h:1.99
--- llvm/include/llvm/Target/MRegisterInfo.h:1.98 Tue Feb 27 15:08:07 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hTue Feb 27 18:16:54 2007
@@ -214,12 +214,6 @@
virtual ~MRegisterInfo();
public:
- /// getRegScavenger - Returns pointer to an instance of register scavenger it
- /// the specific target is making use of one.
- virtual RegScavenger *getRegScavenger() const {
-return NULL;
- }
-
enum {// Define some target independent constants
/// NoRegister - This physical register is not a real target register. It
/// is useful as a sentinal.
@@ -398,6 +392,12 @@
return false;
}
+ /// requiresRegisterScavenging - returns true if the target requires (and
+ /// can make use of) the register scavenger.
+ virtual bool requiresRegisterScavenging() const {
+return false;
+ }
+
/// hasFP - Return true if the specified function should have a dedicated
frame
/// pointer register. For most targets this is true only if the function has
/// variable sized allocas or if frame pointer elimination is disabled.
@@ -452,7 +452,8 @@
/// finished product. The return value is the number of instructions
/// added to (negative if removed from) the basic block.
///
- virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
+ virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
+ RegScavenger *RS = NULL) const = 0;
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function. The return value is the number of instructions
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.99 -> 1.100
---
Log message:
Make requiresRegisterScavenging determination on a per MachineFunction basis.
---
Diffs of the changes: (+1 -1)
MRegisterInfo.h |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.99
llvm/include/llvm/Target/MRegisterInfo.h:1.100
--- llvm/include/llvm/Target/MRegisterInfo.h:1.99 Tue Feb 27 18:16:54 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hTue Feb 27 18:57:39 2007
@@ -394,7 +394,7 @@
/// requiresRegisterScavenging - returns true if the target requires (and
/// can make use of) the register scavenger.
- virtual bool requiresRegisterScavenging() const {
+ virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
return false;
}
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.100 -> 1.101
---
Log message:
Minor interface change.
---
Diffs of the changes: (+3 -1)
MRegisterInfo.h |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.100
llvm/include/llvm/Target/MRegisterInfo.h:1.101
--- llvm/include/llvm/Target/MRegisterInfo.h:1.100 Tue Feb 27 18:57:39 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hTue Mar 6 04:04:38 2007
@@ -433,7 +433,9 @@
/// processFunctionBeforeCalleeSavedScan - This method is called immediately
/// before PrologEpilogInserter scans the physical registers used to
determine
/// what callee saved registers should be spilled. This method is optional.
- virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const
{
+ virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
+RegScavenger *RS = NULL) const
{
+
}
/// processFunctionBeforeFrameFinalized - This method is called immediately
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.101 -> 1.102 --- Log message: Added MRegisterInfo hook to re-materialize an instruction. --- Diffs of the changes: (+7 -0) MRegisterInfo.h |7 +++ 1 files changed, 7 insertions(+) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.101 llvm/include/llvm/Target/MRegisterInfo.h:1.102 --- llvm/include/llvm/Target/MRegisterInfo.h:1.101 Tue Mar 6 04:04:38 2007 +++ llvm/include/llvm/Target/MRegisterInfo.hTue Mar 20 03:05:54 2007 @@ -374,6 +374,13 @@ unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *RC) const = 0; + /// reMaterialize - Re-issue the specified 'original' instruction at the + /// specific location targeting a new destination register. + virtual void reMaterialize(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, + const MachineInstr *Orig) const = 0; + /// foldMemoryOperand - Attempt to fold a load or store of the /// specified stack slot into the specified machine instruction for /// the specified operand. If this is possible, a new instruction ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.102 -> 1.103
---
Log message:
Change getAllocatableSet() so it returns allocatable registers for a specific
register class.
---
Diffs of the changes: (+4 -2)
MRegisterInfo.h |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.102
llvm/include/llvm/Target/MRegisterInfo.h:1.103
--- llvm/include/llvm/Target/MRegisterInfo.h:1.102 Tue Mar 20 03:05:54 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hTue Apr 17 15:23:34 2007
@@ -241,8 +241,10 @@
}
/// getAllocatableSet - Returns a bitset indexed by register number
- /// indicating if a register is allocatable or not.
- BitVector getAllocatableSet(MachineFunction &MF) const;
+ /// indicating if a register is allocatable or not. If a register class is
+ /// specified, returns the subset for the class.
+ BitVector getAllocatableSet(MachineFunction &MF,
+ const TargetRegisterClass *RC = NULL) const;
const TargetRegisterDesc &operator[](unsigned RegNo) const {
assert(RegNo < NumRegs &&
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.104 -> 1.105
---
Log message:
Add sub-registers set accessor.
---
Diffs of the changes: (+8 -0)
MRegisterInfo.h |8
1 files changed, 8 insertions(+)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.104
llvm/include/llvm/Target/MRegisterInfo.h:1.105
--- llvm/include/llvm/Target/MRegisterInfo.h:1.104 Fri Apr 20 16:11:22 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hFri Apr 20 16:28:05 2007
@@ -270,6 +270,14 @@
return get(RegNo).AliasSet;
}
+ /// getSubRegisters - Return the set of registers that are sub-registers of
+ // the specified register, or a null list of there are none. The list
+ /// returned is zero terminated.
+ ///
+ const unsigned *getSubRegisters(unsigned RegNo) const {
+return get(RegNo).SubRegs;
+ }
+
/// getName - Return the symbolic target specific name for the specified
/// physical register.
const char *getName(unsigned RegNo) const {
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.103 -> 1.104
---
Log message:
Add sub-register sets.
---
Diffs of the changes: (+3 -0)
MRegisterInfo.h |3 +++
1 files changed, 3 insertions(+)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.103
llvm/include/llvm/Target/MRegisterInfo.h:1.104
--- llvm/include/llvm/Target/MRegisterInfo.h:1.103 Tue Apr 17 15:23:34 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hFri Apr 20 16:11:22 2007
@@ -38,10 +38,13 @@
/// to a Zero terminated array of registers that this register aliases. This
is
/// needed for architectures like X86 which have AL alias AX alias EAX.
/// Registers that this does not apply to simply should set this to null.
+/// The SubRegs field is a zero terminated array of registers that are
+/// sub-registers of the specific register, e.g. AL, AH are sub-registers of
AX.
///
struct TargetRegisterDesc {
const char *Name; // Assembly language name for the register
const unsigned *AliasSet; // Register Alias Set, described above
+ const unsigned *SubRegs; // Sub-register set, described above
};
class TargetRegisterClass {
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.105 -> 1.106
---
Log message:
Add super-register set.
---
Diffs of the changes: (+13 -1)
MRegisterInfo.h | 14 +-
1 files changed, 13 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.105
llvm/include/llvm/Target/MRegisterInfo.h:1.106
--- llvm/include/llvm/Target/MRegisterInfo.h:1.105 Fri Apr 20 16:28:05 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hFri Apr 20 19:54:06 2007
@@ -40,11 +40,15 @@
/// Registers that this does not apply to simply should set this to null.
/// The SubRegs field is a zero terminated array of registers that are
/// sub-registers of the specific register, e.g. AL, AH are sub-registers of
AX.
+/// The SuperRegs field is a zero terminated array of registers that are
+/// super-registers of the specific register, e.g. RAX, EAX, are sub-registers
+/// of AX.
///
struct TargetRegisterDesc {
const char *Name; // Assembly language name for the register
const unsigned *AliasSet; // Register Alias Set, described above
const unsigned *SubRegs; // Sub-register set, described above
+ const unsigned *SuperRegs;// Super-register set, described above
};
class TargetRegisterClass {
@@ -271,13 +275,21 @@
}
/// getSubRegisters - Return the set of registers that are sub-registers of
- // the specified register, or a null list of there are none. The list
+ /// the specified register, or a null list of there are none. The list
/// returned is zero terminated.
///
const unsigned *getSubRegisters(unsigned RegNo) const {
return get(RegNo).SubRegs;
}
+ /// getSuperRegisters - Return the set of registers that are super-registers
+ /// of the specified register, or a null list of there are none. The list
+ /// returned is zero terminated.
+ ///
+ const unsigned *getSuperRegisters(unsigned RegNo) const {
+return get(RegNo).SuperRegs;
+ }
+
/// getName - Return the symbolic target specific name for the specified
/// physical register.
const char *getName(unsigned RegNo) const {
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.75 -> 1.76
---
Log message:
Added sub- register classes information.
---
Diffs of the changes: (+29 -7)
MRegisterInfo.h | 36 +---
1 files changed, 29 insertions(+), 7 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.75
llvm/include/llvm/Target/MRegisterInfo.h:1.76
--- llvm/include/llvm/Target/MRegisterInfo.h:1.75 Mon Apr 10 18:09:19 2006
+++ llvm/include/llvm/Target/MRegisterInfo.hTue May 9 01:35:30 2006
@@ -47,14 +47,18 @@
typedef const unsigned* const_iterator;
typedef const MVT::ValueType* vt_iterator;
+ typedef const TargetRegisterClass** sc_iterator;
private:
const vt_iterator VTs;
+ const sc_iterator SubClasses;
const unsigned RegSize, Alignment;// Size & Alignment of register in
bytes
const iterator RegsBegin, RegsEnd;
public:
- TargetRegisterClass(const MVT::ValueType *vts, unsigned RS, unsigned Al,
- iterator RB, iterator RE)
-: VTs(vts), RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
+ TargetRegisterClass(const MVT::ValueType *vts,
+ const TargetRegisterClass **scs,
+ unsigned RS, unsigned Al, iterator RB, iterator RE)
+: VTs(vts), SubClasses(scs),
+RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
virtual ~TargetRegisterClass() {} // Allow subclasses
// begin/end - Return all of the registers in this class.
@@ -87,20 +91,38 @@
return false;
}
- /// vt_begin - Loop over all of the value types that can be represented by
- /// values in this register class.
+ /// vt_begin / vt_end - Loop over all of the value types that can be
+ /// represented by values in this register class.
vt_iterator vt_begin() const {
return VTs;
}
- /// vt_begin - Loop over all of the value types that can be represented by
- /// values in this register class.
vt_iterator vt_end() const {
vt_iterator I = VTs;
while (*I != MVT::Other) ++I;
return I;
}
+
+ /// hasSubRegClass - return true if the specified TargetRegisterClass is a
+ /// sub-register class of this TargetRegisterClass.
+ bool hasSubRegClass(const TargetRegisterClass *cs) const {
+for (int i = 0; SubClasses[i] != NULL; ++i)
+ if (SubClasses[i] == cs)
+return true;
+return false;
+ }
+
+ /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
+ /// this register class.
+ sc_iterator subclasses_begin() const {
+return SubClasses;
+ }
+ sc_iterator subclasses_end() const {
+sc_iterator I = SubClasses;
+while (*I != NULL) ++I;
+return I;
+ }
/// allocation_order_begin/end - These methods define a range of registers
/// which specify the registers in this class that are valid to register
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.76 -> 1.77
---
Log message:
Also add super- register class info.
---
Diffs of the changes: (+26 -2)
MRegisterInfo.h | 28 ++--
1 files changed, 26 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.76
llvm/include/llvm/Target/MRegisterInfo.h:1.77
--- llvm/include/llvm/Target/MRegisterInfo.h:1.76 Tue May 9 01:35:30 2006
+++ llvm/include/llvm/Target/MRegisterInfo.hThu May 11 02:31:44 2006
@@ -49,15 +49,18 @@
typedef const MVT::ValueType* vt_iterator;
typedef const TargetRegisterClass** sc_iterator;
private:
+ bool isSubClass;
const vt_iterator VTs;
const sc_iterator SubClasses;
+ const sc_iterator SuperClasses;
const unsigned RegSize, Alignment;// Size & Alignment of register in
bytes
const iterator RegsBegin, RegsEnd;
public:
TargetRegisterClass(const MVT::ValueType *vts,
- const TargetRegisterClass **scs,
+ const TargetRegisterClass **subcs,
+ const TargetRegisterClass **supcs,
unsigned RS, unsigned Al, iterator RB, iterator RE)
-: VTs(vts), SubClasses(scs),
+: VTs(vts), SubClasses(subcs), SuperClasses(supcs),
RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
virtual ~TargetRegisterClass() {} // Allow subclasses
@@ -124,6 +127,27 @@
return I;
}
+ /// hasSuperRegClass - return true if the specified TargetRegisterClass is a
+ /// super-register class of this TargetRegisterClass.
+ bool hasSuperRegClass(const TargetRegisterClass *cs) const {
+for (int i = 0; SuperClasses[i] != NULL; ++i)
+ if (SuperClasses[i] == cs)
+return true;
+return false;
+ }
+
+ /// superclasses_begin / superclasses_end - Loop over all of the
super-classes
+ /// of this register class.
+ sc_iterator superclasses_begin() const {
+return SuperClasses;
+ }
+
+ sc_iterator superclasses_end() const {
+sc_iterator I = SuperClasses;
+while (*I != NULL) ++I;
+return I;
+ }
+
/// allocation_order_begin/end - These methods define a range of registers
/// which specify the registers in this class that are valid to register
/// allocate, and the preferred order to allocate them in. For example,
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.77 -> 1.78
---
Log message:
Make sub- and super- register classes const.
---
Diffs of the changes: (+3 -3)
MRegisterInfo.h |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.77
llvm/include/llvm/Target/MRegisterInfo.h:1.78
--- llvm/include/llvm/Target/MRegisterInfo.h:1.77 Thu May 11 02:31:44 2006
+++ llvm/include/llvm/Target/MRegisterInfo.hWed Jul 19 00:58:18 2006
@@ -47,7 +47,7 @@
typedef const unsigned* const_iterator;
typedef const MVT::ValueType* vt_iterator;
- typedef const TargetRegisterClass** sc_iterator;
+ typedef const TargetRegisterClass* const * sc_iterator;
private:
bool isSubClass;
const vt_iterator VTs;
@@ -57,8 +57,8 @@
const iterator RegsBegin, RegsEnd;
public:
TargetRegisterClass(const MVT::ValueType *vts,
- const TargetRegisterClass **subcs,
- const TargetRegisterClass **supcs,
+ const TargetRegisterClass * const *subcs,
+ const TargetRegisterClass * const *supcs,
unsigned RS, unsigned Al, iterator RB, iterator RE)
: VTs(vts), SubClasses(subcs), SuperClasses(supcs),
RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
___
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.79 -> 1.80
---
Log message:
update comment
---
Diffs of the changes: (+2 -8)
MRegisterInfo.h | 10 ++
1 files changed, 2 insertions(+), 8 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.79
llvm/include/llvm/Target/MRegisterInfo.h:1.80
--- llvm/include/llvm/Target/MRegisterInfo.h:1.79 Fri Jul 21 15:57:35 2006
+++ llvm/include/llvm/Target/MRegisterInfo.hThu Aug 3 13:57:28 2006
@@ -208,20 +208,14 @@
public:
enum {// Define some target independent constants
-/// NoRegister - This 'hard' register is a 'noop' register for all
backends.
-/// This is used as the destination register for instructions that do not
-/// produce a value. Some frontends may use this as an operand register to
-/// mean special things, for example, the Sparc backend uses R0 to mean %g0
-/// which always PRODUCES the value 0. The X86 backend does not use this
-/// value as an operand register, except for memory references.
-///
+/// NoRegister - This physical register is not a real target register. It
+/// is useful as a sentinal.
NoRegister = 0,
/// FirstVirtualRegister - This is the first register number that is
/// considered to be a 'virtual' register, which is part of the SSA
/// namespace. This must be the same for all targets, which means that
each
/// target is limited to 1024 registers.
-///
FirstVirtualRegister = 1024
};
___
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.80 -> 1.81
---
Log message:
Doxygenify some methods.
---
Diffs of the changes: (+8 -4)
MRegisterInfo.h | 12
1 files changed, 8 insertions(+), 4 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.80
llvm/include/llvm/Target/MRegisterInfo.h:1.81
--- llvm/include/llvm/Target/MRegisterInfo.h:1.80 Thu Aug 3 13:57:28 2006
+++ llvm/include/llvm/Target/MRegisterInfo.hThu Aug 10 01:00:40 2006
@@ -66,17 +66,21 @@
RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
virtual ~TargetRegisterClass() {} // Allow subclasses
- // getID() - Return the register class ID number.
+ /// getID() - Return the register class ID number.
+ ///
unsigned getID() const { return ID; }
- // begin/end - Return all of the registers in this class.
+ /// begin/end - Return all of the registers in this class.
+ ///
iterator begin() const { return RegsBegin; }
iterator end() const { return RegsEnd; }
- // getNumRegs - Return the number of registers in this class
+ /// getNumRegs - Return the number of registers in this class.
+ ///
unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
- // getRegister - Return the specified register in the class
+ /// getRegister - Return the specified register in the class.
+ ///
unsigned getRegister(unsigned i) const {
assert(i < getNumRegs() && "Register number out of range!");
return RegsBegin[i];
___
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.81 -> 1.82
---
Log message:
Constify some methods. Patch provided by Anton Vayvod, thanks!
---
Diffs of the changes: (+2 -2)
MRegisterInfo.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.81
llvm/include/llvm/Target/MRegisterInfo.h:1.82
--- llvm/include/llvm/Target/MRegisterInfo.h:1.81 Thu Aug 10 01:00:40 2006
+++ llvm/include/llvm/Target/MRegisterInfo.hThu Aug 17 17:00:07 2006
@@ -170,10 +170,10 @@
///
/// By default, these methods return all registers in the class.
///
- virtual iterator allocation_order_begin(MachineFunction &MF) const {
+ virtual iterator allocation_order_begin(const MachineFunction &MF) const {
return begin();
}
- virtual iterator allocation_order_end(MachineFunction &MF) const {
+ virtual iterator allocation_order_end(const MachineFunction &MF) const {
return end();
}
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.82 -> 1.83 --- Log message: update some comments --- Diffs of the changes: (+1 -2) MRegisterInfo.h |3 +-- 1 files changed, 1 insertion(+), 2 deletions(-) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.82 llvm/include/llvm/Target/MRegisterInfo.h:1.83 --- llvm/include/llvm/Target/MRegisterInfo.h:1.82 Thu Aug 17 17:00:07 2006 +++ llvm/include/llvm/Target/MRegisterInfo.hWed Aug 23 19:21:32 2006 @@ -314,8 +314,7 @@ //======// // Interfaces used by the register allocator and stack frame // manipulation passes to move data around between registers, - // immediates and memory. The return value is the number of - // instructions added to (negative if removed from) the basic block. + // immediates and memory. FIXME: Move these to TargetInstrInfo.h. // virtual void storeRegToStackSlot(MachineBasicBlock &MBB, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.83 -> 1.84
---
Log message:
- Added a hook processFunctionBeforeCalleeSaveScn(). This is called by PEI just
before it determines which callee-save registers are to be spilled. This allows
the target to make changes such as forcing certain physical registers to be
spilled.
- Modified comments. It's important to note the order of registers in the array
returns by getCalleeSaveRegs() determines the order of callee save spill code.
---
Diffs of the changes: (+10 -4)
MRegisterInfo.h | 14 ++
1 files changed, 10 insertions(+), 4 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.83
llvm/include/llvm/Target/MRegisterInfo.h:1.84
--- llvm/include/llvm/Target/MRegisterInfo.h:1.83 Wed Aug 23 19:21:32 2006
+++ llvm/include/llvm/Target/MRegisterInfo.hWed Sep 27 19:07:19 2006
@@ -283,7 +283,9 @@
}
/// getCalleeSaveRegs - Return a null-terminated list of all of the
- /// callee-save registers on this target.
+ /// callee-save registers on this target. The register should be in the
+ /// order of desired callee-save stack frame offset. The first register is
+ /// closed to the incoming stack pointer if stack grows down, and vice versa.
virtual const unsigned* getCalleeSaveRegs() const = 0;
/// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
@@ -371,12 +373,16 @@
assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
}
+ /// processFunctionBeforeCalleeSaveScan - This method is called immediately
+ /// before PrologEpilogInserter scans the physical registers used to
determine
+ /// what callee-save registers should be spilled. This method is optional.
+ virtual void processFunctionBeforeCalleeSaveScan(MachineFunction &MF) const {
+ }
+
/// processFunctionBeforeFrameFinalized - This method is called immediately
/// before the specified functions frame layout (MF.getFrameInfo()) is
/// finalized. Once the frame is finalized, MO_FrameIndex operands are
- /// replaced with direct constants. This method is optional. The return
value
- /// is the number of instructions added to (negative if removed from) the
- /// basic block
+ /// replaced with direct constants. This method is optional.
///
virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
}
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.106 -> 1.107
---
Log message:
Test if a register is sub- or super-register of another.
---
Diffs of the changes: (+16 -0)
MRegisterInfo.h | 16
1 files changed, 16 insertions(+)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.106
llvm/include/llvm/Target/MRegisterInfo.h:1.107
--- llvm/include/llvm/Target/MRegisterInfo.h:1.106 Fri Apr 20 19:54:06 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hWed Apr 25 02:24:50 2007
@@ -321,6 +321,22 @@
return areAliases(regA, regB);
}
+ /// isSubRegister - Returns true if regB is a sub-register of regA.
+ ///
+ bool isSubRegister(unsigned regA, unsigned regB) const {
+for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR)
+ if (*SR == regB) return true;
+return false;
+ }
+
+ /// isSuperRegister - Returns true if regB is a super-register of regA.
+ ///
+ bool isSuperRegister(unsigned regA, unsigned regB) const {
+for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
+ if (*SR == regB) return true;
+return false;
+ }
+
/// getCalleeSavedRegs - Return a null-terminated list of all of the
/// callee saved registers on this target. The register should be in the
/// order of desired callee-save stack frame offset. The first register is
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.107 -> 1.108
---
Log message:
Added hook hasReservedCallFrame(). It returns true if the call frame is
included as part of the stack frame.
---
Diffs of the changes: (+9 -0)
MRegisterInfo.h |9 +
1 files changed, 9 insertions(+)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.107
llvm/include/llvm/Target/MRegisterInfo.h:1.108
--- llvm/include/llvm/Target/MRegisterInfo.h:1.107 Wed Apr 25 02:24:50 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hMon Apr 30 19:47:46 2007
@@ -451,6 +451,15 @@
/// variable sized allocas or if frame pointer elimination is disabled.
virtual bool hasFP(const MachineFunction &MF) const = 0;
+ // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
+ // not required, we reserve argument space for call sites in the function
+ // immediately on entry to the current function. This eliminates the need for
+ // add/sub sp brackets around call sites. Returns true if the call frame is
+ // included as part of the stack frame.
+ virtual bool hasReservedCallFrame(MachineFunction &MF) const {
+return !hasFP(MF);
+ }
+
/// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
/// frame setup/destroy instructions if they exist (-1 otherwise). Some
/// targets use pseudo instructions in order to abstract away the difference
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.108 -> 1.109
---
Log message:
llvm bug #1350, parts 1, 2, and 3.
---
Diffs of the changes: (+5 -1)
MRegisterInfo.h |6 +-
1 files changed, 5 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.108
llvm/include/llvm/Target/MRegisterInfo.h:1.109
--- llvm/include/llvm/Target/MRegisterInfo.h:1.108 Mon Apr 30 19:47:46 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hTue May 1 00:57:02 2007
@@ -41,7 +41,7 @@
/// The SubRegs field is a zero terminated array of registers that are
/// sub-registers of the specific register, e.g. AL, AH are sub-registers of
AX.
/// The SuperRegs field is a zero terminated array of registers that are
-/// super-registers of the specific register, e.g. RAX, EAX, are sub-registers
+/// super-registers of the specific register, e.g. RAX, EAX, are
super-registers
/// of AX.
///
struct TargetRegisterDesc {
@@ -354,6 +354,10 @@
/// register scavenger to determine what registers are free.
virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
+ /// getSubReg - Returns the physical register number of sub-register "Index"
+ /// for physical register RegNo.
+ virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
+
//======//
// Register Class Information
//
___
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.109 -> 1.110 --- Log message: Add SPAdj parameter to account for call frame setup SP adjustment. --- Diffs of the changes: (+4 -3) MRegisterInfo.h |7 --- 1 files changed, 4 insertions(+), 3 deletions(-) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.109 llvm/include/llvm/Target/MRegisterInfo.h:1.110 --- llvm/include/llvm/Target/MRegisterInfo.h:1.109 Tue May 1 00:57:02 2007 +++ llvm/include/llvm/Target/MRegisterInfo.hTue May 1 03:58:27 2007 @@ -512,11 +512,12 @@ /// referenced by the iterator contains an MO_FrameIndex operand which must be /// eliminated by this method. This method may modify or replace the /// specified instruction, as long as it keeps the iterator pointing the the - /// finished product. The return value is the number of instructions - /// added to (negative if removed from) the basic block. + /// finished product. SPAdj is the SP adjustment due to call frame setup + /// instruction. The return value is the number of instructions added to + /// (negative if removed from) the basic block. /// virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, - RegScavenger *RS = NULL) const = 0; + int SPAdj, RegScavenger *RS=NULL) const = 0; /// emitProlog/emitEpilog - These methods insert prolog and epilog code into /// the function. The return value is the number of instructions ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.110 -> 1.111
---
Log message:
Add support to tablegen for specifying subregister classes on a per register
class basis.
---
Diffs of the changes: (+44 -0)
MRegisterInfo.h | 44
1 files changed, 44 insertions(+)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.110
llvm/include/llvm/Target/MRegisterInfo.h:1.111
--- llvm/include/llvm/Target/MRegisterInfo.h:1.110 Tue May 1 03:58:27 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hWed Jun 13 17:20:15 2007
@@ -64,6 +64,7 @@
const vt_iterator VTs;
const sc_iterator SubClasses;
const sc_iterator SuperClasses;
+ const sc_iterator SubRegClasses;
const unsigned RegSize, Alignment;// Size & Alignment of register in
bytes
const iterator RegsBegin, RegsEnd;
public:
@@ -71,8 +72,10 @@
const MVT::ValueType *vts,
const TargetRegisterClass * const *subcs,
const TargetRegisterClass * const *supcs,
+ const TargetRegisterClass * const *subregcs,
unsigned RS, unsigned Al, iterator RB, iterator RE)
: ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
+SubRegClasses(subregcs),
RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
virtual ~TargetRegisterClass() {} // Allow subclasses
@@ -167,6 +170,47 @@
return I;
}
+ /// hasSubRegForClass - return true if the specified TargetRegisterClass is a
+ /// class of a sub-register class for this TargetRegisterClass.
+ bool hasSubRegForClass(const TargetRegisterClass *cs) const {
+for (int i = 0; SubRegClasses[i] != NULL; ++i)
+ if (SubRegClasses[i] == cs)
+return true;
+return false;
+ }
+
+ /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
+ /// class of a sub-register class for this TargetRegisterClass.
+ bool hasClassForSubReg(unsigned SubReg) const {
+--SubReg;
+for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
+ if (i == SubReg)
+return true;
+return false;
+ }
+
+ /// getClassForSubReg - return theTargetRegisterClass for the sub-register
+ /// at idx for this TargetRegisterClass.
+ sc_iterator getClassForSubReg(unsigned SubReg) const {
+--SubReg;
+for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
+ if (i == SubReg)
+return &SubRegClasses[i];
+return NULL;
+ }
+
+ /// subregclasses_begin / subregclasses_end - Loop over all of
+ /// the subregister classes of this register class.
+ sc_iterator subregclasses_begin() const {
+return SubRegClasses;
+ }
+
+ sc_iterator subregclasses_end() const {
+sc_iterator I = SubRegClasses;
+while (*I != NULL) ++I;
+return I;
+ }
+
/// allocation_order_begin/end - These methods define a range of registers
/// which specify the registers in this class that are valid to register
/// allocate, and the preferred order to allocate them in. For example,
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.111 -> 1.112
---
Log message:
Add immediate sub-registers.
---
Diffs of the changes: (+9 -0)
MRegisterInfo.h |9 +
1 files changed, 9 insertions(+)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.111
llvm/include/llvm/Target/MRegisterInfo.h:1.112
--- llvm/include/llvm/Target/MRegisterInfo.h:1.111 Wed Jun 13 17:20:15 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hTue Jun 26 15:59:16 2007
@@ -48,6 +48,7 @@
const char *Name; // Assembly language name for the register
const unsigned *AliasSet; // Register Alias Set, described above
const unsigned *SubRegs; // Sub-register set, described above
+ const unsigned *ImmSubRegs; // Immediate sub-register set, described above
const unsigned *SuperRegs;// Super-register set, described above
};
@@ -326,6 +327,14 @@
return get(RegNo).SubRegs;
}
+ /// getImmediateSubRegisters - Return the set of registers that are immediate
+ /// sub-registers of the specified register, or a null list of there are
none.
+ /// The list returned is zero terminated.
+ ///
+ const unsigned *getImmediateSubRegisters(unsigned RegNo) const {
+return get(RegNo).ImmSubRegs;
+ }
+
/// getSuperRegisters - Return the set of registers that are super-registers
/// of the specified register, or a null list of there are none. The list
/// returned is zero terminated.
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.112 -> 1.113
---
Log message:
Add comment.
---
Diffs of the changes: (+5 -3)
MRegisterInfo.h |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.112
llvm/include/llvm/Target/MRegisterInfo.h:1.113
--- llvm/include/llvm/Target/MRegisterInfo.h:1.112 Tue Jun 26 15:59:16 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hTue Jun 26 16:19:07 2007
@@ -40,9 +40,11 @@
/// Registers that this does not apply to simply should set this to null.
/// The SubRegs field is a zero terminated array of registers that are
/// sub-registers of the specific register, e.g. AL, AH are sub-registers of
AX.
-/// The SuperRegs field is a zero terminated array of registers that are
-/// super-registers of the specific register, e.g. RAX, EAX, are
super-registers
-/// of AX.
+/// The ImmsubRegs field is a subset of SubRegs. It includes only the immediate
+/// sub-registers. e.g. EAX has only one immediate sub-register of AX, not AH,
+/// AL which are immediate sub-registers of AX. The SuperRegs field is a zero
+/// terminated array of registers that are super-registers of the specific
+/// register, e.g. RAX, EAX, are super-registers of AX.
///
struct TargetRegisterDesc {
const char *Name; // Assembly language name for the register
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h TargetInstrInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.67 -> 1.68
TargetInstrInfo.h updated: 1.82 -> 1.83
---
Log message:
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,
a far more logical place. Other methods should also be moved if anyone
is interested. :)
---
Diffs of the changes: (+18 -18)
MRegisterInfo.h | 18 --
TargetInstrInfo.h | 18 ++
2 files changed, 18 insertions(+), 18 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.67
llvm/include/llvm/Target/MRegisterInfo.h:1.68
--- llvm/include/llvm/Target/MRegisterInfo.h:1.67 Thu Feb 2 13:55:29 2006
+++ llvm/include/llvm/Target/MRegisterInfo.hThu Feb 2 14:11:55 2006
@@ -259,24 +259,6 @@
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const = 0;
- /// isLoadFromStackSlot - If the specified machine instruction is a direct
- /// load from a stack slot, return the virtual or physical register number of
- /// the destination along with the FrameIndex of the loaded stack slot. If
- /// not, return 0. This predicate must return 0 if the instruction has
- /// any side effects other than loading from the stack slot.
- virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex)
const{
-return 0;
- }
-
- /// isStoreToStackSlot - If the specified machine instruction is a direct
- /// store to a stack slot, return the virtual or physical register number of
- /// the source reg along with the FrameIndex of the loaded stack slot. If
- /// not, return 0. This predicate must return 0 if the instruction has
- /// any side effects other than storing to the stack slot.
- virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const
{
-return 0;
- }
-
/// foldMemoryOperand - Attempt to fold a load or store of the
/// specified stack slot into the specified machine instruction for
/// the specified operand. If this is possible, a new instruction
Index: llvm/include/llvm/Target/TargetInstrInfo.h
diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.82
llvm/include/llvm/Target/TargetInstrInfo.h:1.83
--- llvm/include/llvm/Target/TargetInstrInfo.h:1.82 Thu Jan 26 17:27:02 2006
+++ llvm/include/llvm/Target/TargetInstrInfo.h Thu Feb 2 14:11:55 2006
@@ -212,6 +212,24 @@
unsigned& destReg) const {
return false;
}
+
+ /// isLoadFromStackSlot - If the specified machine instruction is a direct
+ /// load from a stack slot, return the virtual or physical register number of
+ /// the destination along with the FrameIndex of the loaded stack slot. If
+ /// not, return 0. This predicate must return 0 if the instruction has
+ /// any side effects other than loading from the stack slot.
+ virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex)
const{
+return 0;
+ }
+
+ /// isStoreToStackSlot - If the specified machine instruction is a direct
+ /// store to a stack slot, return the virtual or physical register number of
+ /// the source reg along with the FrameIndex of the loaded stack slot. If
+ /// not, return 0. This predicate must return 0 if the instruction has
+ /// any side effects other than storing to the stack slot.
+ virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const
{
+return 0;
+ }
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h TargetLowering.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.69 -> 1.70
TargetLowering.h updated: 1.53 -> 1.54
---
Log message:
Make the LLVM headers "-ansi -pedantic -Wno-long-long" clean.
Patch by Martin Partel!
---
Diffs of the changes: (+5 -5)
MRegisterInfo.h |2 +-
TargetLowering.h |8
2 files changed, 5 insertions(+), 5 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.69
llvm/include/llvm/Target/MRegisterInfo.h:1.70
--- llvm/include/llvm/Target/MRegisterInfo.h:1.69 Tue Feb 21 17:51:58 2006
+++ llvm/include/llvm/Target/MRegisterInfo.hWed Feb 22 10:23:43 2006
@@ -169,7 +169,7 @@
/// namespace. This must be the same for all targets, which means that
each
/// target is limited to 1024 registers.
///
-FirstVirtualRegister = 1024,
+FirstVirtualRegister = 1024
};
/// isPhysicalRegister - Return true if the specified register number is in
Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.53
llvm/include/llvm/Target/TargetLowering.h:1.54
--- llvm/include/llvm/Target/TargetLowering.h:1.53 Tue Feb 21 18:56:01 2006
+++ llvm/include/llvm/Target/TargetLowering.h Wed Feb 22 10:23:43 2006
@@ -56,24 +56,24 @@
Legal, // The target natively supports this operation.
Promote,// This operation should be executed in a larger type.
Expand, // Try to expand this to other ops, otherwise use a libcall.
-Custom, // Use the LowerOperation hook to implement custom lowering.
+Custom // Use the LowerOperation hook to implement custom lowering.
};
enum OutOfRangeShiftAmount {
Undefined, // Oversized shift amounts are undefined (default).
Mask, // Shift amounts are auto masked (anded) to value size.
-Extend, // Oversized shift pulls in zeros or sign bits.
+Extend // Oversized shift pulls in zeros or sign bits.
};
enum SetCCResultValue {
UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
-ZeroOrNegativeOneSetCCResult, // SetCC returns a sign extended result.
+ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result.
};
enum SchedPreference {
SchedulingForLatency, // Scheduling for shortest total latency.
-SchedulingForRegPressure, // Scheduling for lowest register pressure.
+SchedulingForRegPressure // Scheduling for lowest register pressure.
};
TargetLowering(TargetMachine &TM);
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h TargetFrameInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.85 -> 1.86
TargetFrameInfo.h updated: 1.21 -> 1.22
---
Log message:
Fix naming inconsistency: calleesave -> calleesaved.
---
Diffs of the changes: (+18 -18)
MRegisterInfo.h | 30 +++---
TargetFrameInfo.h |6 +++---
2 files changed, 18 insertions(+), 18 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.85
llvm/include/llvm/Target/MRegisterInfo.h:1.86
--- llvm/include/llvm/Target/MRegisterInfo.h:1.85 Tue Jan 2 14:55:17 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hTue Jan 2 15:30:17 2007
@@ -283,16 +283,16 @@
return false;
}
- /// getCalleeSaveRegs - Return a null-terminated list of all of the
- /// callee-save registers on this target. The register should be in the
+ /// getCalleeSavedRegs - Return a null-terminated list of all of the
+ /// callee saved registers on this target. The register should be in the
/// order of desired callee-save stack frame offset. The first register is
/// closed to the incoming stack pointer if stack grows down, and vice versa.
- virtual const unsigned* getCalleeSaveRegs() const = 0;
+ virtual const unsigned* getCalleeSavedRegs() const = 0;
- /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
- /// register classes to spill each callee-saved register with. The order and
+ /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
+ /// register classes to spill each callee saved register with. The order and
/// length of this list match the getCalleeSaveRegs() list.
- virtual const TargetRegisterClass* const *getCalleeSaveRegClasses() const =
0;
+ virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const
=0;
//======//
// Register Class Information
@@ -320,22 +320,22 @@
// immediates and memory. FIXME: Move these to TargetInstrInfo.h.
//
- /// spillCalleeSaveRegisters - Issues instruction(s) to spill all callee
saved
+ /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
saved
/// registers and returns true if it isn't possible / profitable to do so by
/// issuing a series of store instructions via storeRegToStackSlot(). Returns
/// false otherwise.
- virtual bool spillCalleeSaveRegisters(MachineBasicBlock &MBB,
-MachineBasicBlock::iterator MI,
+ virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
const std::vector &CSI) const
{
return false;
}
- /// restoreCalleeSaveRegisters - Issues instruction(s) to restore all callee
+ /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
/// saved registers and returns true if it isn't possible / profitable to do
/// so by issuing a series of load instructions via loadRegToStackSlot().
/// Returns false otherwise.
- virtual bool restoreCalleeSaveRegisters(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
+ virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
const std::vector &CSI) const
{
return false;
}
@@ -394,10 +394,10 @@
assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
}
- /// processFunctionBeforeCalleeSaveScan - This method is called immediately
+ /// processFunctionBeforeCalleeSavedScan - This method is called immediately
/// before PrologEpilogInserter scans the physical registers used to
determine
- /// what callee-save registers should be spilled. This method is optional.
- virtual void processFunctionBeforeCalleeSaveScan(MachineFunction &MF) const {
+ /// what callee saved registers should be spilled. This method is optional.
+ virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const
{
}
/// processFunctionBeforeFrameFinalized - This method is called immediately
Index: llvm/include/llvm/Target/TargetFrameInfo.h
diff -u llvm/include/llvm/Target/TargetFrameInfo.h:1.21
llvm/include/llvm/Target/TargetFrameInfo.h:1.22
--- llvm/include/llvm/Target/TargetFrameInfo.h:1.21 Thu Aug 3 13:55:44 2006
+++ llvm/include/llvm/Target/TargetFrameInfo.h Tue Jan 2 15:30:17 2007
@@ -61,8 +61,8 @@
///
int getOffsetOfLocalArea() const { return LocalAreaOffset; }
- /// getCalleeSaveSpillSlots - This method returns a pointer to an array of
- /// pairs, that contains an entry for each callee save register that must be
+ /// getCalleeSavedSpillSlots - This method returns a pointer to an array of
+ /// pairs, that contains an entry for each callee saved register that must
[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h TargetInstrInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.78 -> 1.79
TargetInstrInfo.h updated: 1.90 -> 1.91
---
Log message:
Use an enumeration to eliminate data relocations.
---
Diffs of the changes: (+19 -18)
MRegisterInfo.h | 18 +++---
TargetInstrInfo.h | 19 ---
2 files changed, 19 insertions(+), 18 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.78
llvm/include/llvm/Target/MRegisterInfo.h:1.79
--- llvm/include/llvm/Target/MRegisterInfo.h:1.78 Wed Jul 19 00:58:18 2006
+++ llvm/include/llvm/Target/MRegisterInfo.hFri Jul 21 15:57:35 2006
@@ -49,6 +49,7 @@
typedef const MVT::ValueType* vt_iterator;
typedef const TargetRegisterClass* const * sc_iterator;
private:
+ unsigned ID;
bool isSubClass;
const vt_iterator VTs;
const sc_iterator SubClasses;
@@ -56,14 +57,18 @@
const unsigned RegSize, Alignment;// Size & Alignment of register in
bytes
const iterator RegsBegin, RegsEnd;
public:
- TargetRegisterClass(const MVT::ValueType *vts,
+ TargetRegisterClass(unsigned id,
+ const MVT::ValueType *vts,
const TargetRegisterClass * const *subcs,
const TargetRegisterClass * const *supcs,
unsigned RS, unsigned Al, iterator RB, iterator RE)
-: VTs(vts), SubClasses(subcs), SuperClasses(supcs),
+: ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
virtual ~TargetRegisterClass() {} // Allow subclasses
-
+
+ // getID() - Return the register class ID number.
+ unsigned getID() const { return ID; }
+
// begin/end - Return all of the registers in this class.
iterator begin() const { return RegsBegin; }
iterator end() const { return RegsEnd; }
@@ -300,6 +305,13 @@
unsigned getNumRegClasses() const {
return regclass_end()-regclass_begin();
}
+
+ /// getRegClass - Returns the register class associated with the enumeration
+ /// value. See class TargetOperandInfo.
+ const TargetRegisterClass *getRegClass(unsigned i) const {
+assert(i <= getNumRegClasses() && "Register Class ID out of range");
+return i ? RegClassBegin[i - 1] : NULL;
+ }
//======//
// Interfaces used by the register allocator and stack frame
Index: llvm/include/llvm/Target/TargetInstrInfo.h
diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.90
llvm/include/llvm/Target/TargetInstrInfo.h:1.91
--- llvm/include/llvm/Target/TargetInstrInfo.h:1.90 Fri Jun 16 20:42:20 2006
+++ llvm/include/llvm/Target/TargetInstrInfo.h Fri Jul 21 15:57:35 2006
@@ -90,10 +90,10 @@
///
class TargetOperandInfo {
public:
- /// RegClass - This specifies the register class of the operand if the
- /// operand is a register. If not, this contains null.
- const TargetRegisterClass *RegClass;
- unsigned Flags;
+ /// RegClass - This specifies the register class enumeration of the operand
+ /// if the operand is a register. If not, this contains 0.
+ unsigned short RegClass;
+ unsigned short Flags;
/// Currently no other information.
};
@@ -146,17 +146,6 @@
return get(Opcode).Name;
}
- const TargetRegisterClass
- *getInstrOperandRegClass(const TargetInstrDescriptor *II, unsigned Op) const
{
-if (Op >= II->numOperands) {
- assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of
instruction");
- return NULL;
-}
-const TargetOperandInfo &toi = II->OpInfo[Op];
-return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS)
- ? getPointerRegClass() : toi.RegClass;
- }
-
int getNumOperands(MachineOpCode Opcode) const {
return get(Opcode).numOperands;
}
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