[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrVFP.td
Changes in directory llvm/lib/Target/ARM:
ARMInstrVFP.td updated: 1.6 - 1.7
---
Log message:
For VFP2 fldm, fstm instructions, the condition code is printed after the
address mode and size specifier. e.g. fstmiaseq, not fstmeqias.
---
Diffs of the changes: (+4 -4)
ARMInstrVFP.td |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/ARM/ARMInstrVFP.td
diff -u llvm/lib/Target/ARM/ARMInstrVFP.td:1.6
llvm/lib/Target/ARM/ARMInstrVFP.td:1.7
--- llvm/lib/Target/ARM/ARMInstrVFP.td:1.6 Mon May 14 20:29:07 2007
+++ llvm/lib/Target/ARM/ARMInstrVFP.td Tue May 29 18:34:19 2007
@@ -108,21 +108,21 @@
let isLoad = 1 in {
def FLDMD : AXDI5(ops addrmode5:$addr, pred:$p, reglist:$dst1, variable_ops),
- fldm${p}${addr:submode}d ${addr:base}, $dst1,
+ fldm${addr:submode}d${p} ${addr:base}, $dst1,
[];
def FLDMS : AXSI5(ops addrmode5:$addr, pred:$p, reglist:$dst1, variable_ops),
- fldm${p}${addr:submode}s ${addr:base}, $dst1,
+ fldm${addr:submode}s${p} ${addr:base}, $dst1,
[];
} // isLoad
let isStore = 1 in {
def FSTMD : AXDI5(ops addrmode5:$addr, pred:$p, reglist:$src1, variable_ops),
- fstm${p}${addr:submode}d ${addr:base}, $src1,
+ fstm${addr:submode}d${p} ${addr:base}, $src1,
[];
def FSTMS : AXSI5(ops addrmode5:$addr, pred:$p, reglist:$src1, variable_ops),
- fstm${p}${addr:submode}s ${addr:base}, $src1,
+ fstm${addr:submode}s${p} ${addr:base}, $src1,
[];
} // isStore
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrVFP.td
Changes in directory llvm/lib/Target/ARM: ARMInstrVFP.td updated: 1.3 - 1.4 --- Log message: This is no longer needed after enabling the DAG combiner xform. --- Diffs of the changes: (+0 -5) ARMInstrVFP.td |5 - 1 files changed, 5 deletions(-) Index: llvm/lib/Target/ARM/ARMInstrVFP.td diff -u llvm/lib/Target/ARM/ARMInstrVFP.td:1.3 llvm/lib/Target/ARM/ARMInstrVFP.td:1.4 --- llvm/lib/Target/ARM/ARMInstrVFP.td:1.3 Thu May 3 15:54:42 2007 +++ llvm/lib/Target/ARM/ARMInstrVFP.td Mon May 7 16:29:41 2007 @@ -78,11 +78,6 @@ [(store SPR:$src, addrmode5:$addr)]; } // isStore -// avoid copying result of FTOUIZ to int reg when we're just storing it -let AddedComplexity = 1 in -def : ARMPat(store (i32 (bitconvert SPR:$src)), addrmode5:$addr), - (FSTS SPR:$src, addrmode5:$addr); - //===--===// // Load / store multiple Instructions. // ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrVFP.td
Changes in directory llvm/lib/Target/ARM: ARMInstrVFP.td updated: 1.2 - 1.3 --- Log message: Evan's patch to avoid FPreg-intreg copy for cvt; store to mem --- Diffs of the changes: (+5 -0) ARMInstrVFP.td |5 + 1 files changed, 5 insertions(+) Index: llvm/lib/Target/ARM/ARMInstrVFP.td diff -u llvm/lib/Target/ARM/ARMInstrVFP.td:1.2 llvm/lib/Target/ARM/ARMInstrVFP.td:1.3 --- llvm/lib/Target/ARM/ARMInstrVFP.td:1.2 Wed May 2 19:32:00 2007 +++ llvm/lib/Target/ARM/ARMInstrVFP.td Thu May 3 15:54:42 2007 @@ -78,6 +78,11 @@ [(store SPR:$src, addrmode5:$addr)]; } // isStore +// avoid copying result of FTOUIZ to int reg when we're just storing it +let AddedComplexity = 1 in +def : ARMPat(store (i32 (bitconvert SPR:$src)), addrmode5:$addr), + (FSTS SPR:$src, addrmode5:$addr); + //===--===// // Load / store multiple Instructions. // ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrVFP.td
Evan's patch to avoid FPreg-intreg copy for cvt; store to mem +// avoid copying result of FTOUIZ to int reg when we're just storing it +let AddedComplexity = 1 in +def : ARMPat(store (i32 (bitconvert SPR:$src)), addrmode5:$addr), + (FSTS SPR:$src, addrmode5:$addr); + // ===--- ---===// // Load / store multiple Instructions. // Interesting approach. Instead of adding this to one target's .td file, can you please investigate whether we can enable the dag combine xform at DAGCombiner.cpp:3412 now? The primary thing blocking that xform was that we need to know (in this case) that an f32 store doesn't require greater alignment than an i32 store has. -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
