[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp ARMRegisterInfo.h
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.91 - 1.92
ARMRegisterInfo.h updated: 1.18 - 1.19
---
Log message:
eliminateFrameIndex() change.
---
Diffs of the changes: (+5 -4)
ARMRegisterInfo.cpp |7 ---
ARMRegisterInfo.h |2 +-
2 files changed, 5 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.91
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.92
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.91Mon Apr 30 19:52:08 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Tue May 1 04:13:03 2007
@@ -689,7 +689,7 @@
}
void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
- RegScavenger *RS) const{
+ int SPAdj, RegScavenger *RS) const{
unsigned i = 0;
MachineInstr MI = *II;
MachineBasicBlock MBB = *MI.getParent();
@@ -705,7 +705,7 @@
unsigned FrameReg = ARM::SP;
int FrameIndex = MI.getOperand(i).getFrameIndex();
int Offset = MF.getFrameInfo()-getObjectOffset(FrameIndex) +
- MF.getFrameInfo()-getStackSize();
+ MF.getFrameInfo()-getStackSize() + SPAdj;
if (AFI-isGPRCalleeSavedArea1Frame(FrameIndex))
Offset -= AFI-getGPRCalleeSavedArea1Offset();
@@ -714,6 +714,7 @@
else if (AFI-isDPRCalleeSavedAreaFrame(FrameIndex))
Offset -= AFI-getDPRCalleeSavedAreaOffset();
else if (hasFP(MF)) {
+assert(SPAdj == 0 Unexpected);
// There is alloca()'s in this function, must reference off the frame
// pointer instead.
FrameReg = getFrameRegister(MF);
@@ -988,7 +989,7 @@
unsigned ScratchReg = findScratchRegister(RS, ARM::GPRRegClass, AFI);
if (ScratchReg == 0)
// No register is free. Scavenge a register.
- ScratchReg = RS-scavengeRegister(ARM::GPRRegClass, II);
+ ScratchReg = RS-scavengeRegister(ARM::GPRRegClass, II, SPAdj);
emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
isSub ? -Offset : Offset, TII);
MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
Index: llvm/lib/Target/ARM/ARMRegisterInfo.h
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.18
llvm/lib/Target/ARM/ARMRegisterInfo.h:1.19
--- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.18 Mon Apr 30 19:52:08 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.h Tue May 1 04:13:03 2007
@@ -85,7 +85,7 @@
MachineBasicBlock::iterator I) const;
void eliminateFrameIndex(MachineBasicBlock::iterator II,
- RegScavenger *RS = NULL) const;
+ int SPAdj, RegScavenger *RS = NULL) const;
void processFunctionBeforeCalleeSavedScan(MachineFunction MF,
RegScavenger *RS = NULL) const;
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp ARMRegisterInfo.h
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.90 - 1.91
ARMRegisterInfo.h updated: 1.17 - 1.18
---
Log message:
Under normal circumstances, when a frame pointer is not required, we reserve
argument space for call sites in the function immediately on entry to the
current function. This eliminates the need for add/sub sp brackets around call
sites. However, this is not always a good idea. If the call frame is large and
the target load / store instructions have small immediate field to encode sp
offset, this can cause poor codegen. In the worst case, this can make it
impossible to scavenge a register if the reserved spill slot is pushed too far
apart from sp / fp.
---
Diffs of the changes: (+29 -3)
ARMRegisterInfo.cpp | 30 +++---
ARMRegisterInfo.h |2 ++
2 files changed, 29 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.90
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.91
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.90Fri Apr 27 15:10:08 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Mon Apr 30 19:52:08 2007
@@ -386,6 +386,29 @@
return NoFramePointerElim || MF.getFrameInfo()-hasVarSizedObjects();
}
+// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
+// not required, we reserve argument space for call sites in the function
+// immediately on entry to the current function. This eliminates the need for
+// add/sub sp brackets around call sites. Returns true if the call frame is
+// included as part of the stack frame.
+bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction MF) const {
+ const MachineFrameInfo *FFI = MF.getFrameInfo();
+ unsigned CFSize = FFI-getMaxCallFrameSize();
+ ARMFunctionInfo *AFI = MF.getInfoARMFunctionInfo();
+ // It's not always a good idea to include the call frame as part of the
+ // stack frame. ARM (especially Thumb) has small immediate offset to
+ // address the stack frame. So a large call frame can cause poor codegen
+ // and may even makes it impossible to scavenge a register.
+ if (AFI-isThumbFunction()) {
+if (CFSize = ((1 8) - 1) * 4 / 2) // Half of imm8 * 4
+ return false;
+ } else {
+if (CFSize = ((1 12) - 1) / 2) // Half of imm12
+ return false;
+ }
+ return !hasFP(MF);
+}
+
/// emitARMRegPlusImmediate - Emits a series of instructions to materialize
/// a destreg = basereg + immediate in ARM code.
static
@@ -605,7 +628,7 @@
void ARMRegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction MF, MachineBasicBlock MBB,
MachineBasicBlock::iterator I) const {
- if (hasFP(MF)) {
+ if (!hasReservedCallFrame(MF)) {
// If we have alloca, convert as follows:
// ADJCALLSTACKDOWN - sub, sp, sp, amount
// ADJCALLSTACKUP - add, sp, sp, amount
@@ -1146,8 +1169,9 @@
Limit = (1 8) - 1;
goto DoneEstimating;
} else if (AddrMode == ARMII::AddrMode5) {
-Limit = ((1 8) - 1) * 4;
-goto DoneEstimating;
+unsigned ThisLimit = ((1 8) - 1) * 4;
+if (ThisLimit Limit)
+ Limit = ThisLimit;
}
}
}
Index: llvm/lib/Target/ARM/ARMRegisterInfo.h
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.17
llvm/lib/Target/ARM/ARMRegisterInfo.h:1.18
--- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.17 Tue Mar 20 03:07:04 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.h Mon Apr 30 19:52:08 2007
@@ -78,6 +78,8 @@
bool hasFP(const MachineFunction MF) const;
+ bool hasReservedCallFrame(MachineFunction MF) const;
+
void eliminateCallFramePseudoInstr(MachineFunction MF,
MachineBasicBlock MBB,
MachineBasicBlock::iterator I) const;
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp ARMRegisterInfo.h
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.79 - 1.80
ARMRegisterInfo.h updated: 1.15 - 1.16
---
Log message:
Scavenge a register using the register scavenger when needed.
---
Diffs of the changes: (+111 -14)
ARMRegisterInfo.cpp | 115
ARMRegisterInfo.h | 10 +---
2 files changed, 111 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.79
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.80
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.79Thu Mar 1 19:17:17 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Tue Mar 6 04:03:56 2007
@@ -85,11 +85,6 @@
: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
TII(tii), STI(sti),
FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) {
- RS = (EnableScavenging) ? new RegScavenger() : NULL;
-}
-
-ARMRegisterInfo::~ARMRegisterInfo() {
- delete RS;
}
bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock MBB,
@@ -329,6 +324,25 @@
}
bool
+ARMRegisterInfo::isReservedReg(const MachineFunction MF, unsigned Reg) const {
+ switch (Reg) {
+ default: break;
+ case ARM::SP:
+ case ARM::PC:
+return true;
+ case ARM::R7:
+ case ARM::R11:
+if (FramePtr == Reg (STI.isTargetDarwin() || hasFP(MF)))
+ return true;
+break;
+ case ARM::R9:
+return STI.isR9Reserved();
+ }
+
+ return false;
+}
+
+bool
ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction MF) const {
const ARMFunctionInfo *AFI = MF.getInfoARMFunctionInfo();
return EnableScavenging !AFI-isThumbFunction();
@@ -918,15 +932,34 @@
// to form it with a series of ADDri's. Do this by taking 8-bit chunks
// out of 'Offset'.
unsigned ScratchReg = findScratchRegister(RS, ARM::GPRRegClass, AFI);
-assert(ScratchReg Unable to find a free register!);
+if (ScratchReg == 0)
+ // No register is free. Scavenge a register.
+ ScratchReg = RS-scavengeRegister(ARM::GPRRegClass, II);
emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
isSub ? -Offset : Offset, TII);
MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
}
}
-void ARMRegisterInfo::
-processFunctionBeforeCalleeSavedScan(MachineFunction MF) const {
+static unsigned estimateStackSize(MachineFunction MF, MachineFrameInfo *MFI) {
+ const MachineFrameInfo *FFI = MF.getFrameInfo();
+ int Offset = 0;
+ for (int i = FFI-getObjectIndexBegin(); i != 0; ++i) {
+int FixedOff = -FFI-getObjectOffset(i);
+if (FixedOff Offset) Offset = FixedOff;
+ }
+ for (unsigned i = 0, e = FFI-getObjectIndexEnd(); i != e; ++i) {
+Offset += FFI-getObjectSize(i);
+unsigned Align = FFI-getObjectAlignment(i);
+// Adjust to alignment boundary
+Offset = (Offset+Align-1)/Align*Align;
+ }
+ return (unsigned)Offset;
+}
+
+void
+ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction MF,
+ RegScavenger *RS) const {
// This tells PEI to spill the FP as if it is any other callee-save register
// to take advantage the eliminateFrameIndex machinery. This also ensures it
// is spilled in the order specified by getCalleeSavedRegs() to make it
easier
@@ -1020,6 +1053,7 @@
}
}
+ bool ExtraCSSpill = false;
if (!CanEliminateFrame || hasFP(MF)) {
AFI-setHasStackFrame(true);
@@ -1032,6 +1066,7 @@
UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
UnspilledCS1GPRs.end(),
(unsigned)ARM::LR));
ForceLRSpill = false;
+ ExtraCSSpill = true;
}
// Darwin ABI requires FP to point to the stack slot that contains the
@@ -1050,10 +1085,74 @@
unsigned Reg = UnspilledCS1GPRs.front();
MF.changePhyRegUsed(Reg, true);
AFI-setCSRegisterIsSpilled(Reg);
+if (!isReservedReg(MF, Reg))
+ ExtraCSSpill = true;
} else if (!UnspilledCS2GPRs.empty()) {
unsigned Reg = UnspilledCS2GPRs.front();
MF.changePhyRegUsed(Reg, true);
AFI-setCSRegisterIsSpilled(Reg);
+if (!isReservedReg(MF, Reg))
+ ExtraCSSpill = true;
+ }
+}
+
+// Estimate if we might need to scavenge a register at some point in order
+// to materialize a stack offset. If so, either spill one additiona
+// callee-saved register or reserve a special spill slot to facilitate
+// register scavenging.
+if (RS !ExtraCSSpill !AFI-isThumbFunction()) {
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+ unsigned Size = estimateStackSize(MF, MFI);
+ unsigned Limit = (1 12) - 1;
+ for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E;
++BB)
+for (MachineBasicBlock::iterator I= BB-begin(); I != BB-end(); ++I) {
+ for (unsigned i = 0, e = I-getNumOperands(); i != e; ++i)
+
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp ARMRegisterInfo.h
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.72 - 1.73
ARMRegisterInfo.h updated: 1.12 - 1.13
---
Log message:
Let MRegisterInfo now owns RegScavenger; eliminateFrameIndex must preserve
register kill info.
---
Diffs of the changes: (+51 -30)
ARMRegisterInfo.cpp | 70 +++-
ARMRegisterInfo.h | 11 +---
2 files changed, 51 insertions(+), 30 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.72
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.73
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.72Fri Feb 23 15:53:48 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Tue Feb 27 15:12:35 2007
@@ -25,6 +25,7 @@
#include llvm/CodeGen/MachineFunction.h
#include llvm/CodeGen/MachineInstrBuilder.h
#include llvm/CodeGen/MachineLocation.h
+#include llvm/CodeGen/RegisterScavenging.h
#include llvm/Target/TargetFrameInfo.h
#include llvm/Target/TargetMachine.h
#include llvm/Target/TargetOptions.h
@@ -84,6 +85,15 @@
: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
TII(tii), STI(sti),
FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) {
+ RS = new RegScavenger();
+}
+
+ARMRegisterInfo::~ARMRegisterInfo() {
+ delete RS;
+}
+
+RegScavenger *ARMRegisterInfo::getRegScavenger() const {
+ return EnableScavenging ? RS : NULL;
}
bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock MBB,
@@ -328,10 +338,6 @@
return NoFramePointerElim || MF.getFrameInfo()-hasVarSizedObjects();
}
-bool ARMRegisterInfo::requiresRegisterScavenging() const {
- return EnableScavenging;
-}
-
/// emitARMRegPlusImmediate - Emits a series of instructions to materialize
/// a destreg = basereg + immediate in ARM code.
static
@@ -356,7 +362,7 @@
// Build the new ADD / SUB.
BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
- .addReg(BaseReg).addImm(SOImmVal);
+ .addReg(BaseReg, false, false, true).addImm(SOImmVal);
BaseReg = DestReg;
}
}
@@ -423,28 +429,29 @@
if (DestReg == ARM::SP) {
assert(BaseReg == ARM::SP Unexpected!);
LdReg = ARM::R3;
- BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3);
+ BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12)
+.addReg(ARM::R3, false, false, true);
}
if (NumBytes = 255 NumBytes = 0)
BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes);
else if (NumBytes 0 NumBytes = -255) {
BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes);
- BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg).addReg(LdReg);
+ BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
+.addReg(LdReg, false, false, true);
} else
emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII);
// Emit add / sub.
int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
-if (DestReg == ARM::SP)
- MIB.addReg(BaseReg).addReg(LdReg);
-else if (isSub)
- MIB.addReg(BaseReg).addReg(LdReg);
+if (DestReg == ARM::SP || isSub)
+ MIB.addReg(BaseReg).addReg(LdReg, false, false, true);
else
- MIB.addReg(LdReg).addReg(BaseReg);
+ MIB.addReg(LdReg).addReg(BaseReg, false, false, true);
if (DestReg == ARM::SP)
- BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3).addReg(ARM::R12);
+ BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3)
+.addReg(ARM::R12, false, false, true);
}
/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
@@ -510,9 +517,10 @@
unsigned ThisVal = (Bytes Chunk) ? Chunk : Bytes;
Bytes -= ThisVal;
BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
-.addReg(BaseReg).addImm(ThisVal);
+.addReg(BaseReg, false, false, true).addImm(ThisVal);
} else {
- BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg).addReg(BaseReg);
+ BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg)
+.addReg(BaseReg, false, false, true);
}
BaseReg = DestReg;
}
@@ -526,7 +534,9 @@
if (isTwoAddr)
BuildMI(MBB, MBBI, TII.get(Opc),
DestReg).addReg(DestReg).addImm(ThisVal);
else {
- BuildMI(MBB, MBBI, TII.get(Opc),
DestReg).addReg(BaseReg).addImm(ThisVal);
+ bool isKill = BaseReg != ARM::SP;
+ BuildMI(MBB, MBBI, TII.get(Opc), DestReg)
+.addReg(BaseReg, false, false, isKill).addImm(ThisVal);
BaseReg = DestReg;
if (Opc == ARM::tADDrSPi) {
@@ -543,7 +553,8 @@
}
if (ExtraOpc)
-BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg).addReg(DestReg)
+BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg)
+ .addReg(DestReg, false, false, true)
.addImm(((unsigned)NumBytes) 3);
}
@@ -601,7 +612,8 @@
if (Imm 0)
emitThumbRegPlusImmediate(MBB, MBBI, DestReg,
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp ARMRegisterInfo.h ARMRegisterInfo.td
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.74 - 1.75
ARMRegisterInfo.h updated: 1.14 - 1.15
ARMRegisterInfo.td updated: 1.12 - 1.13
---
Log message:
Make requiresRegisterScavenging determination on a per MachineFunction basis.
---
Diffs of the changes: (+13 -11)
ARMRegisterInfo.cpp |6 --
ARMRegisterInfo.h |2 +-
ARMRegisterInfo.td | 16
3 files changed, 13 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.74
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.75
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.74Tue Feb 27 18:21:58 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Tue Feb 27 18:59:19 2007
@@ -326,8 +326,10 @@
return Reserved;
}
-bool ARMRegisterInfo::requiresRegisterScavenging() const {
- return EnableScavenging;
+bool
+ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction MF) const {
+ const ARMFunctionInfo *AFI = MF.getInfoARMFunctionInfo();
+ return EnableScavenging !AFI-isThumbFunction();
}
/// hasFP - Return true if the specified function should have a dedicated frame
Index: llvm/lib/Target/ARM/ARMRegisterInfo.h
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.14
llvm/lib/Target/ARM/ARMRegisterInfo.h:1.15
--- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.14 Tue Feb 27 18:21:17 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.h Tue Feb 27 18:59:19 2007
@@ -74,7 +74,7 @@
BitVector getReservedRegs(const MachineFunction MF) const;
- bool requiresRegisterScavenging() const;
+ bool requiresRegisterScavenging(const MachineFunction MF) const;
bool hasFP(const MachineFunction MF) const;
Index: llvm/lib/Target/ARM/ARMRegisterInfo.td
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.td:1.12
llvm/lib/Target/ARM/ARMRegisterInfo.td:1.13
--- llvm/lib/Target/ARM/ARMRegisterInfo.td:1.12 Tue Feb 27 18:22:44 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.td Tue Feb 27 18:59:19 2007
@@ -163,14 +163,14 @@
return THUMB_GPR_AO;
if (Subtarget.useThumbBacktraces()) {
if (Subtarget.isR9Reserved())
- return RI-requiresRegisterScavenging() ? ARM_GPR_AO_8 :
ARM_GPR_AO_4;
+ return RI-requiresRegisterScavenging(MF) ?
ARM_GPR_AO_8:ARM_GPR_AO_4;
else
- return RI-requiresRegisterScavenging() ? ARM_GPR_AO_7 :
ARM_GPR_AO_3;
+ return RI-requiresRegisterScavenging(MF) ?
ARM_GPR_AO_7:ARM_GPR_AO_3;
} else {
if (Subtarget.isR9Reserved())
- return RI-requiresRegisterScavenging() ? ARM_GPR_AO_6 :
ARM_GPR_AO_2;
+ return RI-requiresRegisterScavenging(MF) ?
ARM_GPR_AO_6:ARM_GPR_AO_2;
else
- return RI-requiresRegisterScavenging() ? ARM_GPR_AO_5 :
ARM_GPR_AO_1;
+ return RI-requiresRegisterScavenging(MF) ?
ARM_GPR_AO_5:ARM_GPR_AO_1;
}
}
@@ -184,24 +184,24 @@
I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
else if (Subtarget.useThumbBacktraces()) {
if (Subtarget.isR9Reserved()) {
- if (RI-requiresRegisterScavenging())
+ if (RI-requiresRegisterScavenging(MF))
I = ARM_GPR_AO_8 + (sizeof(ARM_GPR_AO_8)/sizeof(unsigned));
else
I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
} else {
- if (RI-requiresRegisterScavenging())
+ if (RI-requiresRegisterScavenging(MF))
I = ARM_GPR_AO_7 + (sizeof(ARM_GPR_AO_7)/sizeof(unsigned));
else
I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned));
}
} else {
if (Subtarget.isR9Reserved()) {
- if (RI-requiresRegisterScavenging())
+ if (RI-requiresRegisterScavenging(MF))
I = ARM_GPR_AO_6 + (sizeof(ARM_GPR_AO_6)/sizeof(unsigned));
else
I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
} else {
- if (RI-requiresRegisterScavenging())
+ if (RI-requiresRegisterScavenging(MF))
I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned));
else
I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp ARMRegisterInfo.h
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.70 - 1.71
ARMRegisterInfo.h updated: 1.11 - 1.12
---
Log message:
Add option to turn on register scavenger; By default, spills kills the register
being stored.
---
Diffs of the changes: (+20 -6)
ARMRegisterInfo.cpp | 24 ++--
ARMRegisterInfo.h |2 ++
2 files changed, 20 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.70
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.71
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.70Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Thu Feb 22 19:09:11 2007
@@ -31,9 +31,13 @@
#include llvm/ADT/BitVector.h
#include llvm/ADT/SmallVector.h
#include llvm/ADT/STLExtras.h
+#include llvm/Support/CommandLine.h
#include algorithm
using namespace llvm;
+static cl::optbool EnableScavenging(enable-arm-reg-scavenging, cl::Hidden,
+ cl::desc(Enable register scavenging on
ARM));
+
unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
using namespace ARM;
switch (RegEnum) {
@@ -91,8 +95,12 @@
return false;
MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH));
- for (unsigned i = CSI.size(); i != 0; --i)
-MIB.addReg(CSI[i-1].getReg());
+ for (unsigned i = CSI.size(); i != 0; --i) {
+unsigned Reg = CSI[i-1].getReg();
+// Add the callee-saved register as live-in. It's killed at the spill.
+MBB.addLiveIn(Reg);
+MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
+ }
return true;
}
@@ -130,17 +138,17 @@
MachineFunction MF = *MBB.getParent();
ARMFunctionInfo *AFI = MF.getInfoARMFunctionInfo();
if (AFI-isThumbFunction())
- BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg)
+ BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true)
.addFrameIndex(FI).addImm(0);
else
- BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg)
+ BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true)
.addFrameIndex(FI).addReg(0).addImm(0);
} else if (RC == ARM::DPRRegisterClass) {
-BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg)
+BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true)
.addFrameIndex(FI).addImm(0);
} else {
assert(RC == ARM::SPRRegisterClass Unknown regclass!);
-BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg)
+BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true)
.addFrameIndex(FI).addImm(0);
}
}
@@ -320,6 +328,10 @@
return NoFramePointerElim || MF.getFrameInfo()-hasVarSizedObjects();
}
+bool ARMRegisterInfo::requiresRegisterScavenging() const {
+ return EnableScavenging;
+}
+
/// emitARMRegPlusImmediate - Emits a series of instructions to materialize
/// a destreg = basereg + immediate in ARM code.
static
Index: llvm/lib/Target/ARM/ARMRegisterInfo.h
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.11
llvm/lib/Target/ARM/ARMRegisterInfo.h:1.12
--- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.11 Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.h Thu Feb 22 19:09:11 2007
@@ -69,6 +69,8 @@
BitVector getReservedRegs(const MachineFunction MF) const;
+ bool requiresRegisterScavenging() const;
+
bool hasFP(const MachineFunction MF) const;
void eliminateCallFramePseudoInstr(MachineFunction MF,
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp ARMRegisterInfo.h
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.68 - 1.69
ARMRegisterInfo.h updated: 1.9 - 1.10
---
Log message:
Re-apply my liveintervalanalysis changes. Now with PR1207:
http://llvm.org/PR1207 fixes.
---
Diffs of the changes: (+17 -0)
ARMRegisterInfo.cpp | 15 +++
ARMRegisterInfo.h |2 ++
2 files changed, 17 insertions(+)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.68
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.69
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.68Sun Feb 18 21:20:00 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Mon Feb 19 15:49:53 2007
@@ -28,6 +28,7 @@
#include llvm/Target/TargetFrameInfo.h
#include llvm/Target/TargetMachine.h
#include llvm/Target/TargetOptions.h
+#include llvm/ADT/BitVector.h
#include llvm/ADT/SmallVector.h
#include llvm/ADT/STLExtras.h
#include algorithm
@@ -297,6 +298,20 @@
return CalleeSavedRegClasses;
}
+BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction MF) const {
+ BitVector Reserved(getNumRegs());
+ Reserved.set(ARM::SP);
+ if (STI.isTargetDarwin() || hasFP(MF))
+Reserved.set(FramePtr);
+ // Some targets reserve R9.
+ if (STI.isR9Reserved())
+Reserved.set(ARM::R9);
+ // At PEI time, if LR is used, it will be spilled upon entry.
+ if (MF.getUsedPhysregs() !MF.isPhysRegUsed((unsigned)ARM::LR))
+Reserved.set(ARM::LR);
+ return Reserved;
+}
+
/// hasFP - Return true if the specified function should have a dedicated frame
/// pointer register. This is true if the function has variable sized allocas
/// or if frame pointer elimination is disabled.
Index: llvm/lib/Target/ARM/ARMRegisterInfo.h
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.9
llvm/lib/Target/ARM/ARMRegisterInfo.h:1.10
--- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.9 Sun Feb 18 21:20:00 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.h Mon Feb 19 15:49:53 2007
@@ -67,6 +67,8 @@
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
+ BitVector getReservedRegs(const MachineFunction MF) const;
+
bool hasFP(const MachineFunction MF) const;
void eliminateCallFramePseudoInstr(MachineFunction MF,
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp ARMRegisterInfo.h
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.67 - 1.68
ARMRegisterInfo.h updated: 1.8 - 1.9
---
Log message:
For PR1207: http://llvm.org/PR1207 :
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.
---
Diffs of the changes: (+0 -17)
ARMRegisterInfo.cpp | 15 ---
ARMRegisterInfo.h |2 --
2 files changed, 17 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.67
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.68
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.67Sat Feb 17 05:06:00 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Sun Feb 18 21:20:00 2007
@@ -28,7 +28,6 @@
#include llvm/Target/TargetFrameInfo.h
#include llvm/Target/TargetMachine.h
#include llvm/Target/TargetOptions.h
-#include llvm/ADT/BitVector.h
#include llvm/ADT/SmallVector.h
#include llvm/ADT/STLExtras.h
#include algorithm
@@ -298,20 +297,6 @@
return CalleeSavedRegClasses;
}
-BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction MF) const {
- BitVector Reserved(getNumRegs());
- Reserved.set(ARM::SP);
- if (STI.isTargetDarwin() || hasFP(MF))
-Reserved.set(FramePtr);
- // Some targets reserve R9.
- if (STI.isR9Reserved())
-Reserved.set(ARM::R9);
- // At PEI time, if LR is used, it will be spilled upon entry.
- if (MF.getUsedPhysregs() !MF.isPhysRegUsed((unsigned)ARM::LR))
-Reserved.set(ARM::LR);
- return Reserved;
-}
-
/// hasFP - Return true if the specified function should have a dedicated frame
/// pointer register. This is true if the function has variable sized allocas
/// or if frame pointer elimination is disabled.
Index: llvm/lib/Target/ARM/ARMRegisterInfo.h
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.8
llvm/lib/Target/ARM/ARMRegisterInfo.h:1.9
--- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.8 Sat Feb 17 05:06:00 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.h Sun Feb 18 21:20:00 2007
@@ -67,8 +67,6 @@
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
- BitVector getReservedRegs(const MachineFunction MF) const;
-
bool hasFP(const MachineFunction MF) const;
void eliminateCallFramePseudoInstr(MachineFunction MF,
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp ARMRegisterInfo.h
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.66 - 1.67
ARMRegisterInfo.h updated: 1.7 - 1.8
---
Log message:
Added getReservedRegs().
---
Diffs of the changes: (+17 -0)
ARMRegisterInfo.cpp | 15 +++
ARMRegisterInfo.h |2 ++
2 files changed, 17 insertions(+)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.66
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.67
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.66Wed Feb 7 15:44:33 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Sat Feb 17 05:06:00 2007
@@ -28,6 +28,7 @@
#include llvm/Target/TargetFrameInfo.h
#include llvm/Target/TargetMachine.h
#include llvm/Target/TargetOptions.h
+#include llvm/ADT/BitVector.h
#include llvm/ADT/SmallVector.h
#include llvm/ADT/STLExtras.h
#include algorithm
@@ -297,6 +298,20 @@
return CalleeSavedRegClasses;
}
+BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction MF) const {
+ BitVector Reserved(getNumRegs());
+ Reserved.set(ARM::SP);
+ if (STI.isTargetDarwin() || hasFP(MF))
+Reserved.set(FramePtr);
+ // Some targets reserve R9.
+ if (STI.isR9Reserved())
+Reserved.set(ARM::R9);
+ // At PEI time, if LR is used, it will be spilled upon entry.
+ if (MF.getUsedPhysregs() !MF.isPhysRegUsed((unsigned)ARM::LR))
+Reserved.set(ARM::LR);
+ return Reserved;
+}
+
/// hasFP - Return true if the specified function should have a dedicated frame
/// pointer register. This is true if the function has variable sized allocas
/// or if frame pointer elimination is disabled.
Index: llvm/lib/Target/ARM/ARMRegisterInfo.h
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.7
llvm/lib/Target/ARM/ARMRegisterInfo.h:1.8
--- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.7 Wed Jan 24 21:07:27 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.h Sat Feb 17 05:06:00 2007
@@ -67,6 +67,8 @@
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
+ BitVector getReservedRegs(const MachineFunction MF) const;
+
bool hasFP(const MachineFunction MF) const;
void eliminateCallFramePseudoInstr(MachineFunction MF,
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp ARMRegisterInfo.h ARMRegisterInfo.td
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.38 - 1.39
ARMRegisterInfo.h updated: 1.5 - 1.6
ARMRegisterInfo.td updated: 1.8 - 1.9
---
Log message:
hasFP() is now a virtual method of MRegisterInfo.
---
Diffs of the changes: (+5 -2)
ARMRegisterInfo.cpp |2 +-
ARMRegisterInfo.h |2 ++
ARMRegisterInfo.td |3 ++-
3 files changed, 5 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.38
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.39
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.38Sat Jan 20 04:22:33 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Mon Jan 22 18:52:44 2007
@@ -277,7 +277,7 @@
/// pointer register. This is true if the function has variable sized allocas
/// or if frame pointer elimination is disabled.
///
-static bool hasFP(const MachineFunction MF) {
+bool ARMRegisterInfo::hasFP(const MachineFunction MF) const {
return NoFramePointerElim || MF.getFrameInfo()-hasVarSizedObjects();
}
Index: llvm/lib/Target/ARM/ARMRegisterInfo.h
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.5
llvm/lib/Target/ARM/ARMRegisterInfo.h:1.6
--- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.5 Fri Jan 19 01:51:42 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.h Mon Jan 22 18:52:44 2007
@@ -68,6 +68,8 @@
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
+ bool hasFP(const MachineFunction MF) const;
+
void eliminateCallFramePseudoInstr(MachineFunction MF,
MachineBasicBlock MBB,
MachineBasicBlock::iterator I) const;
Index: llvm/lib/Target/ARM/ARMRegisterInfo.td
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.td:1.8
llvm/lib/Target/ARM/ARMRegisterInfo.td:1.9
--- llvm/lib/Target/ARM/ARMRegisterInfo.td:1.8 Fri Jan 19 20:09:25 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.td Mon Jan 22 18:52:44 2007
@@ -150,6 +150,7 @@
GPRClass::iterator
GPRClass::allocation_order_end(const MachineFunction MF) const {
const TargetMachine TM = MF.getTarget();
+ const MRegisterInfo *RI = TM.getRegisterInfo();
const ARMSubtarget Subtarget = TM.getSubtargetARMSubtarget();
GPRClass::iterator I;
if (Subtarget.isThumb())
@@ -167,7 +168,7 @@
}
// Mac OS X requires FP not to be clobbered for backtracing purpose.
- return (Subtarget.isTargetDarwin() || hasFP(MF)) ? I-1 : I;
+ return (Subtarget.isTargetDarwin() || RI-hasFP(MF)) ? I-1 : I;
}
}];
}
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp ARMRegisterInfo.h
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.30 - 1.31
ARMRegisterInfo.h updated: 1.3 - 1.4
---
Log message:
Fix naming inconsistency.
---
Diffs of the changes: (+8 -8)
ARMRegisterInfo.cpp | 12 ++--
ARMRegisterInfo.h |4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.30
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.31
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.30Mon Dec 18 05:07:09 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Tue Jan 2 15:31:55 2007
@@ -157,23 +157,23 @@
return NULL;
}
-const unsigned* ARMRegisterInfo::getCalleeSaveRegs() const {
- static const unsigned CalleeSaveRegs[] = {
+const unsigned* ARMRegisterInfo::getCalleeSavedRegs() const {
+ static const unsigned CalleeSavedRegs[] = {
ARM::R4, ARM::R5, ARM::R6, ARM::R7,
ARM::R8, ARM::R9, ARM::R10, ARM::R11,
ARM::R14, 0
};
- return CalleeSaveRegs;
+ return CalleeSavedRegs;
}
const TargetRegisterClass* const *
-ARMRegisterInfo::getCalleeSaveRegClasses() const {
- static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
+ARMRegisterInfo::getCalleeSavedRegClasses() const {
+ static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
ARM::IntRegsRegClass, ARM::IntRegsRegClass, ARM::IntRegsRegClass,
ARM::IntRegsRegClass,
ARM::IntRegsRegClass, ARM::IntRegsRegClass, ARM::IntRegsRegClass,
ARM::IntRegsRegClass,
ARM::IntRegsRegClass, 0
};
- return CalleeSaveRegClasses;
+ return CalleeSavedRegClasses;
}
void ARMRegisterInfo::
Index: llvm/lib/Target/ARM/ARMRegisterInfo.h
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.3
llvm/lib/Target/ARM/ARMRegisterInfo.h:1.4
--- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.3 Mon Nov 27 17:37:22 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.h Tue Jan 2 15:31:55 2007
@@ -47,9 +47,9 @@
unsigned OpNum,
int FrameIndex) const;
- const unsigned *getCalleeSaveRegs() const;
+ const unsigned *getCalleeSavedRegs() const;
- const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
+ const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction MF,
MachineBasicBlock MBB,
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