[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.65 -> 1.66
---
Log message:
Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration
for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.
---
Diffs of the changes: (+1 -1)
IA64ISelDAGToDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.65
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.66
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.65 Mon Apr 16 13:10:23 2007
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Tue Jun 19 09:13:56 2007
@@ -470,7 +470,7 @@
switch (TypeBeingLoaded) {
default:
#ifndef NDEBUG
- N->dump();
+ N->dump(CurDAG);
#endif
assert(0 && "Cannot load this type!");
case MVT::i1: { // this is a bool
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.60 -> 1.61 IA64InstrInfo.td updated: 1.48 -> 1.49 --- Log message: fix storing bools to mem and unordered FP ops --- Diffs of the changes: (+5 -5) IA64ISelDAGToDAG.cpp |2 +- IA64InstrInfo.td |8 2 files changed, 5 insertions(+), 5 deletions(-) Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.60 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.61 --- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.60 Thu Nov 2 14:25:49 2006 +++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sat Nov 25 22:34:26 2006 @@ -515,7 +515,7 @@ SDOperand Tmp = ST->getValue(); AddToISelQueue(Tmp); Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial, - CurDAG->getConstant(1, MVT::i64), + CurDAG->getTargetConstant(1, MVT::i64), Tmp), 0); return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain); } Index: llvm/lib/Target/IA64/IA64InstrInfo.td diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.48 llvm/lib/Target/IA64/IA64InstrInfo.td:1.49 --- llvm/lib/Target/IA64/IA64InstrInfo.td:1.48 Mon Jul 31 13:43:10 2006 +++ llvm/lib/Target/IA64/IA64InstrInfo.td Sat Nov 25 22:34:26 2006 @@ -307,16 +307,16 @@ "fcmp.neq $dst, p0 = $src1, $src2", [(set PR:$dst, (setne FP:$src1, FP:$src2))]>, isF; def FCMPLTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), - "fcmp.ltu $dst, p0 = $src1, $src2", + "fcmp.lt $dst, p0 = $src1, $src2", [(set PR:$dst, (setult FP:$src1, FP:$src2))]>, isF; def FCMPGTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), - "fcmp.gtu $dst, p0 = $src1, $src2", + "fcmp.gt $dst, p0 = $src1, $src2", [(set PR:$dst, (setugt FP:$src1, FP:$src2))]>, isF; def FCMPLEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), - "fcmp.leu $dst, p0 = $src1, $src2", + "fcmp.le $dst, p0 = $src1, $src2", [(set PR:$dst, (setule FP:$src1, FP:$src2))]>, isF; def FCMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), - "fcmp.geu $dst, p0 = $src1, $src2", + "fcmp.ge $dst, p0 = $src1, $src2", [(set PR:$dst, (setuge FP:$src1, FP:$src2))]>, isF; def PCMPEQUNCR0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$qp), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.59 -> 1.60
---
Log message:
For PR786: http://llvm.org/PR786 :
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
---
Diffs of the changes: (+3 -5)
IA64ISelDAGToDAG.cpp |8 +++-
1 files changed, 3 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.59
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.60
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.59 Tue Oct 24 12:09:43 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Thu Nov 2 14:25:49 2006
@@ -337,11 +337,9 @@
dyn_cast(N->getOperand(1))) {
CallOpcode = IA64::BRCALL_IPREL_GA;
CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(),
MVT::i64);
-} else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
-// case for correctness, to avoid
-// "non-pic code with imm reloc.n
-// against dynamic symbol" errors
- dyn_cast(N->getOperand(1))) {
+} else if (isa(N->getOperand(1))) {
+ // FIXME: we currently NEED this case for correctness, to avoid
+ // "non-pic code with imm reloc.n against dynamic symbol" errors
CallOpcode = IA64::BRCALL_IPREL_ES;
CallOperand = N->getOperand(1);
} else {
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.58 -> 1.59
---
Log message:
Fix CodeGen/IA64/ret-0.ll, which has apparently been broken since some of the
isel changes happened months ago.
---
Diffs of the changes: (+6 -2)
IA64ISelDAGToDAG.cpp |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.58
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.59
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.58 Fri Oct 13 16:14:26 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Tue Oct 24 12:09:43 2006
@@ -408,12 +408,16 @@
case ISD::TargetConstantFP: {
SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
+SDOperand V;
if (cast(N)->isExactlyValue(+0.0)) {
- return CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64).Val;
+ V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
} else if (cast(N)->isExactlyValue(+1.0)) {
- return CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64).Val;
+ V = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
} else
assert(0 && "Unexpected FP constant!");
+
+ReplaceUses(SDOperand(N, 0), V);
+return 0;
}
case ISD::FrameIndex: { // TODO: reduce creepyness
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.57 -> 1.58
IA64ISelLowering.cpp updated: 1.46 -> 1.47
---
Log message:
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
---
Diffs of the changes: (+12 -12)
IA64ISelDAGToDAG.cpp | 14 +++---
IA64ISelLowering.cpp | 10 +-
2 files changed, 12 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.57
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.58
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.57 Wed Oct 11 02:10:22 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Fri Oct 13 16:14:26 2006
@@ -493,15 +493,15 @@
Address, Chain);
}
- case ISD::TRUNCSTORE:
case ISD::STORE: {
-SDOperand Address = N->getOperand(2);
-SDOperand Chain = N->getOperand(0);
+StoreSDNode *ST = cast(N);
+SDOperand Address = ST->getBasePtr();
+SDOperand Chain = ST->getChain();
AddToISelQueue(Address);
AddToISelQueue(Chain);
unsigned Opc;
-if (N->getOpcode() == ISD::STORE) {
+if (ISD::isNON_TRUNCStore(N)) {
switch (N->getOperand(1).getValueType()) {
default: assert(0 && "unknown type in store");
case MVT::i1: { // this is a bool
@@ -510,7 +510,7 @@
SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
Chain = Initial.getValue(1);
// then load 1 into the same reg iff the predicate to store is 1
-SDOperand Tmp = N->getOperand(1);
+SDOperand Tmp = ST->getValue();
AddToISelQueue(Tmp);
Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
CurDAG->getConstant(1, MVT::i64),
@@ -520,8 +520,8 @@
case MVT::i64: Opc = IA64::ST8; break;
case MVT::f64: Opc = IA64::STF8; break;
}
-} else { //ISD::TRUNCSTORE
- switch(cast(N->getOperand(4))->getVT()) {
+} else { // Truncating store
+ switch(ST->getStoredVT()) {
default: assert(0 && "unknown type in truncstore");
case MVT::i8: Opc = IA64::ST1; break;
case MVT::i16: Opc = IA64::ST2; break;
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.46
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.47
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.46 Mon Oct 9 15:57:25 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Fri Oct 13 16:14:26 2006
@@ -331,7 +331,7 @@
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
getPointerTy()));
- SDOperand StackPtr, NullSV;
+ SDOperand StackPtr;
std::vector Stores;
std::vector Converts;
std::vector RegValuesToPass;
@@ -383,11 +383,10 @@
if(ValToStore.Val) {
if(!StackPtr.Val) {
StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
- NullSV = DAG.getSrcValue(NULL);
}
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
-Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NullSV));
+Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
ArgOffset += ObjSize;
}
@@ -592,7 +591,7 @@
VT));
// Store the incremented VAList to the legalized pointer
VAIncr = DAG.getStore(VAList.getValue(1), VAIncr,
- Op.getOperand(1), Op.getOperand(2));
+ Op.getOperand(1), SV->getValue(), SV->getOffset());
// Load the actual argument out of the pointer VAList
return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0);
}
@@ -600,8 +599,9 @@
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
+SrcValueSDNode *SV = cast(Op.getOperand(2));
return DAG.getStore(Op.getOperand(0), FR,
-Op.getOperand(1), Op.getOperand(2));
+Op.getOperand(1), SV->getValue(), SV->getOffset());
}
}
}
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.56 -> 1.57
---
Log message:
Naming consistency.
---
Diffs of the changes: (+1 -1)
IA64ISelDAGToDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.56
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.57
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.56 Mon Oct 9 15:57:24 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Wed Oct 11 02:10:22 2006
@@ -460,7 +460,7 @@
AddToISelQueue(Chain);
AddToISelQueue(Address);
-MVT::ValueType TypeBeingLoaded = LD->getLoadVT();
+MVT::ValueType TypeBeingLoaded = LD->getLoadedVT();
unsigned Opc;
switch (TypeBeingLoaded) {
default:
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.55 -> 1.56
IA64ISelLowering.cpp updated: 1.45 -> 1.46
---
Log message:
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
---
Diffs of the changes: (+10 -10)
IA64ISelDAGToDAG.cpp | 11 +--
IA64ISelLowering.cpp |9 +
2 files changed, 10 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.55
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.56
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.55 Tue Oct 3 19:55:13 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Oct 9 15:57:24 2006
@@ -453,15 +453,14 @@
}
*/
- case ISD::LOAD:
- case ISD::LOADX: { // FIXME: load -1, not 1, for bools?
-SDOperand Chain = N->getOperand(0);
-SDOperand Address = N->getOperand(1);
+ case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
+LoadSDNode *LD = cast(N);
+SDOperand Chain = LD->getChain();
+SDOperand Address = LD->getBasePtr();
AddToISelQueue(Chain);
AddToISelQueue(Address);
-MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
- N->getValueType(0) : cast(N->getOperand(3))->getVT();
+MVT::ValueType TypeBeingLoaded = LD->getLoadVT();
unsigned Opc;
switch (TypeBeingLoaded) {
default:
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.45
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.46
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.45 Thu Oct 5 18:00:04 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Mon Oct 9 15:57:25 2006
@@ -133,7 +133,7 @@
static bool isFloatingPointZero(SDOperand Op) {
if (ConstantFPSDNode *CFP = dyn_cast(Op))
return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
- else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
+ else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
// Maybe this has already been legalized into the constant pool?
if (ConstantPoolSDNode *CP =
dyn_cast(Op.getOperand(1)))
if (ConstantFP *CFP = dyn_cast(CP->getConstVal()))
@@ -226,7 +226,7 @@
//from this parameter
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
argt = newroot = DAG.getLoad(getValueType(I->getType()),
- DAG.getEntryNode(), FIN,
DAG.getSrcValue(NULL));
+ DAG.getEntryNode(), FIN, NULL, 0);
}
++count;
DAG.setRoot(newroot.getValue(1));
@@ -583,8 +583,9 @@
}
case ISD::VAARG: {
MVT::ValueType VT = getPointerTy();
+SrcValueSDNode *SV = cast(Op.getOperand(2));
SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1),
- Op.getOperand(2));
+ SV->getValue(), SV->getOffset());
// Increment the pointer, VAList, to the next vaarg
SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList,
DAG.getConstant(MVT::getSizeInBits(VT)/8,
@@ -593,7 +594,7 @@
VAIncr = DAG.getStore(VAList.getValue(1), VAIncr,
Op.getOperand(1), Op.getOperand(2));
// Load the actual argument out of the pointer VAList
-return DAG.getLoad(Op.getValueType(), VAIncr, VAList, DAG.getSrcValue(0));
+return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0);
}
case ISD::VASTART: {
// vastart just stores the address of the VarArgsFrameIndex slot into the
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.54 -> 1.55
IA64ISelLowering.cpp updated: 1.43 -> 1.44
---
Log message:
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.
---
Diffs of the changes: (+10 -11)
IA64ISelDAGToDAG.cpp |3 +--
IA64ISelLowering.cpp | 18 +-
2 files changed, 10 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.54
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.55
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.54 Tue Sep 12 16:02:20 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Tue Oct 3 19:55:13 2006
@@ -454,8 +454,7 @@
*/
case ISD::LOAD:
- case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools?
- case ISD::ZEXTLOAD: {
+ case ISD::LOADX: { // FIXME: load -1, not 1, for bools?
SDOperand Chain = N->getOperand(0);
SDOperand Address = N->getOperand(1);
AddToISelQueue(Chain);
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.43
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.44
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.43 Tue Sep 12 16:02:20 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Tue Oct 3 19:55:13 2006
@@ -35,6 +35,15 @@
// register class for predicate registers
addRegisterClass(MVT::i1, IA64::PRRegisterClass);
+ setLoadXAction(ISD::EXTLOAD , MVT::i1 , Promote);
+
+ setLoadXAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
+
+ setLoadXAction(ISD::SEXTLOAD , MVT::i1 , Expand);
+ setLoadXAction(ISD::SEXTLOAD , MVT::i8 , Expand);
+ setLoadXAction(ISD::SEXTLOAD , MVT::i16 , Expand);
+ setLoadXAction(ISD::SEXTLOAD , MVT::i32 , Expand);
+
setOperationAction(ISD::BRIND, MVT::i64, Expand);
setOperationAction(ISD::BR_CC, MVT::Other, Expand);
setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
@@ -50,15 +59,6 @@
setSetCCResultType(MVT::i1);
setShiftAmountType(MVT::i64);
- setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
-
- setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
-
- setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
- setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand);
- setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
- setOperationAction(ISD::SEXTLOAD , MVT::i32 , Expand);
-
setOperationAction(ISD::FREM , MVT::f32 , Expand);
setOperationAction(ISD::FREM , MVT::f64 , Expand);
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.53 -> 1.54
IA64ISelLowering.cpp updated: 1.42 -> 1.43
---
Log message:
Reflects MachineConstantPoolEntry changes.
---
Diffs of the changes: (+2 -2)
IA64ISelDAGToDAG.cpp |2 +-
IA64ISelLowering.cpp |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.53
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.54
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.53 Sun Aug 27 03:12:51 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Tue Sep 12 16:02:20 2006
@@ -429,7 +429,7 @@
case ISD::ConstantPool: { // TODO: nuke the constant pool
// (ia64 doesn't need one)
ConstantPoolSDNode *CP = cast(N);
-Constant *C = CP->get();
+Constant *C = CP->getConstVal();
SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
CP->getAlignment());
return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.42
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.43
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.42 Mon Sep 4 01:21:35 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Tue Sep 12 16:02:20 2006
@@ -136,7 +136,7 @@
else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
// Maybe this has already been legalized into the constant pool?
if (ConstantPoolSDNode *CP =
dyn_cast(Op.getOperand(1)))
- if (ConstantFP *CFP = dyn_cast(CP->get()))
+ if (ConstantFP *CFP = dyn_cast(CP->getConstVal()))
return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
}
return false;
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.52 -> 1.53
---
Log message:
Do not use getTargetNode() and SelectNodeTo() which takes more than 3
SDOperand arguments. Use the variants which take an array and number instead.
---
Diffs of the changes: (+27 -15)
IA64ISelDAGToDAG.cpp | 42 +++---
1 files changed, 27 insertions(+), 15 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.52
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.53
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.52 Sat Aug 26 02:57:56 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sun Aug 27 03:12:51 2006
@@ -204,18 +204,22 @@
}
SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
-
+
+SDOperand OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
-TmpF4, TmpF5, F1, TmpPR), 0);
+OpsE0, 4), 0);
Chain = TmpE0.getValue(1);
+SDOperand OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
-TmpF5, TmpE0, TmpF5, TmpPR), 0);
+OpsY1, 4), 0);
Chain = TmpY1.getValue(1);
+SDOperand OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
-TmpE0, TmpE0, F0, TmpPR), 0);
+OpsE1, 4), 0);
Chain = TmpE1.getValue(1);
+SDOperand OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
-TmpY1, TmpE1, TmpY1, TmpPR), 0);
+OpsY2, 4), 0);
Chain = TmpY2.getValue(1);
if(isFP) { // if this is an FP divide, we finish up here and exit early
@@ -223,45 +227,53 @@
assert(0 && "Sorry, try another FORTRAN compiler.");
SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
-
+
+ SDOperand OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpE1, TmpE1, F0, TmpPR), 0);
+ OpsE2, 4), 0);
Chain = TmpE2.getValue(1);
+ SDOperand OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpY2, TmpE2, TmpY2, TmpPR), 0);
+ OpsY3, 4), 0);
Chain = TmpY3.getValue(1);
+ SDOperand OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
TmpQ0 =
SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double
prec!
-Tmp1, TmpY3, F0, TmpPR), 0);
+OpsQ0, 4), 0);
Chain = TmpQ0.getValue(1);
+ SDOperand OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
TmpR0 =
SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double
prec!
-Tmp2, TmpQ0, Tmp1, TmpPR), 0);
+OpsR0, 4), 0);
Chain = TmpR0.getValue(1);
// we want Result to have the same target register as the frcpa, so
// we two-address hack it. See the comment "for this to work..." on
// page 48 of Intel application note #245415
+ SDOperand Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
- TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR);
+ Ops, 5);
Chain = SDOperand(Result, 1);
return Result; // XXX: early exit!
} else { // this is *not* an FP divide, so there's a bit left to do:
SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
-
+
+ SDOperand OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpF3, TmpY2, F0, TmpPR), 0);
+ OpsQ2, 4), 0);
Chain = TmpQ2.getValue(1);
+ SDOperand OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
- TmpF4, TmpQ2, TmpF3, TmpPR), 0);
+ OpsR2, 4), 0);
Chain = TmpR2.getValue(1);
// we want TmpQ3 to have the same target register as the frcpa? maybe we
// should two-address hack it. See the comment "for this to work..." on page
// 48 of Intel application note #245415
+ SDOperand OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
TmpQ3
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.51 -> 1.52
---
Log message:
SelectNodeTo now returns a SDNode*.
---
Diffs of the changes: (+10 -10)
IA64ISelDAGToDAG.cpp | 20 ++--
1 files changed, 10 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.51
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.52
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.51 Sat Aug 26 00:33:15 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sat Aug 26 02:57:56 2006
@@ -408,10 +408,10 @@
int FI = cast(N)->getIndex();
if (N->hasOneUse())
return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
- CurDAG->getTargetFrameIndex(FI,
MVT::i64)).Val;
+ CurDAG->getTargetFrameIndex(FI, MVT::i64));
else
- return SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64,
- CurDAG->getTargetFrameIndex(FI, MVT::i64)),
0).Val;
+ return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
+ CurDAG->getTargetFrameIndex(FI, MVT::i64));
}
case ISD::ConstantPool: { // TODO: nuke the constant pool
@@ -464,7 +464,7 @@
return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address),
0),
CurDAG->getRegister(IA64::r0, MVT::i64),
-Chain).getValue(Op.ResNo).Val;
+Chain);
}
/* otherwise, we want to load a bool into something bigger: LD1
will do that for us, so we just fall through */
@@ -480,7 +480,7 @@
// TODO: comment this
return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
-Address, Chain).getValue(Op.ResNo).Val;
+Address, Chain);
}
case ISD::TRUNCSTORE:
@@ -505,7 +505,7 @@
Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
CurDAG->getConstant(1, MVT::i64),
Tmp), 0);
-return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp,
Chain).Val;
+return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
}
case MVT::i64: Opc = IA64::ST8; break;
case MVT::f64: Opc = IA64::STF8; break;
@@ -524,7 +524,7 @@
SDOperand N2 = N->getOperand(2);
AddToISelQueue(N1);
AddToISelQueue(N2);
-return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain).Val;
+return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
}
case ISD::BRCOND: {
@@ -536,7 +536,7 @@
cast(N->getOperand(2))->getBasicBlock();
//FIXME - we do NOT need long branches all the time
return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
-CurDAG->getBasicBlock(Dest), Chain).Val;
+CurDAG->getBasicBlock(Dest), Chain);
}
case ISD::CALLSEQ_START:
@@ -546,7 +546,7 @@
IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
SDOperand N0 = N->getOperand(0);
AddToISelQueue(N0);
-return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0).Val;
+return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
}
case ISD::BR:
@@ -554,7 +554,7 @@
SDOperand N0 = N->getOperand(0);
AddToISelQueue(N0);
return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
-N->getOperand(1), N0).Val;
+N->getOperand(1), N0);
}
return SelectCode(Op);
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.50 -> 1.51
---
Log message:
Select() no longer require Result operand by reference.
---
Diffs of the changes: (+13 -20)
IA64ISelDAGToDAG.cpp | 33 +
1 files changed, 13 insertions(+), 20 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.50
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.51
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.50 Fri Aug 25 20:07:16 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sat Aug 26 00:33:15 2006
@@ -65,7 +65,7 @@
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
-SDNode *Select(SDOperand &Result, SDOperand N);
+SDNode *Select(SDOperand N);
SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
unsigned OCHi, unsigned OCLo,
@@ -94,7 +94,7 @@
#include "IA64GenDAGISel.inc"
private:
-SDOperand SelectDIV(SDOperand Op);
+SDNode *SelectDIV(SDOperand Op);
};
}
@@ -111,7 +111,7 @@
ScheduleAndEmitDAG(DAG);
}
-SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
+SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
SDNode *N = Op.Val;
SDOperand Chain = N->getOperand(0);
SDOperand Tmp1 = N->getOperand(0);
@@ -245,7 +245,7 @@
Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR);
Chain = SDOperand(Result, 1);
- return SDOperand(Result, 0); // XXX: early exit!
+ return Result; // XXX: early exit!
} else { // this is *not* an FP divide, so there's a bit left to do:
SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
@@ -292,19 +292,17 @@
Chain = SDOperand(Result, 1);
}
- return SDOperand(Result, 0);
+ return Result;
} // wasn't an FP divide
}
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
-SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
+SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
SDNode *N = Op.Val;
if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
- N->getOpcode() < IA64ISD::FIRST_NUMBER) {
-Result = Op;
+ N->getOpcode() < IA64ISD::FIRST_NUMBER)
return NULL; // Already selected.
- }
switch (N->getOpcode()) {
default: break;
@@ -379,15 +377,13 @@
for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
ReplaceUses(Op.getValue(i), CallResults[i]);
- Result = CallResults[Op.ResNo];
return NULL;
}
case IA64ISD::GETFD: {
SDOperand Input = N->getOperand(0);
AddToISelQueue(Input);
-Result = SDOperand(CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input), 0);
-return Result.Val;
+return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
}
case ISD::FDIV:
@@ -395,8 +391,7 @@
case ISD::UDIV:
case ISD::SREM:
case ISD::UREM:
-Result = SelectDIV(Op);
-return Result.Val;
+return SelectDIV(Op);
case ISD::TargetConstantFP: {
SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
@@ -425,9 +420,8 @@
Constant *C = CP->get();
SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
CP->getAlignment());
-Result = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
- CurDAG->getRegister(IA64::r1, MVT::i64), CPI), 0);
-return Result.Val;
+return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
+ CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
}
case ISD::GlobalAddress: {
@@ -435,8 +429,7 @@
SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
CurDAG->getRegister(IA64::r1, MVT::i64), GA),
0);
-Result = SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp), 0);
-return Result.Val;
+return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
}
/* XXX case ISD::ExternalSymbol: {
@@ -564,7 +557,7 @@
N->getOperand(1), N0).Val;
}
- return SelectCode(Result, Op);
+ return SelectCode(Op);
}
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.49 -> 1.50
---
Log message:
Match tblgen changes.
---
Diffs of the changes: (+38 -30)
IA64ISelDAGToDAG.cpp | 68 ---
1 files changed, 38 insertions(+), 30 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.49
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.50
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.49 Wed Aug 16 02:29:13 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Fri Aug 25 20:07:16 2006
@@ -113,11 +113,13 @@
SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
SDNode *N = Op.Val;
- SDOperand Chain, Tmp1, Tmp2;
- AddToQueue(Chain, N->getOperand(0));
+ SDOperand Chain = N->getOperand(0);
+ SDOperand Tmp1 = N->getOperand(0);
+ SDOperand Tmp2 = N->getOperand(1);
+ AddToISelQueue(Chain);
- AddToQueue(Tmp1, N->getOperand(0));
- AddToQueue(Tmp2, N->getOperand(1));
+ AddToISelQueue(Tmp1);
+ AddToISelQueue(Tmp2);
bool isFP=false;
@@ -308,12 +310,14 @@
default: break;
case IA64ISD::BRCALL: { // XXX: this is also a hack!
-SDOperand Chain;
+SDOperand Chain = N->getOperand(0);
SDOperand InFlag; // Null incoming flag value.
-AddToQueue(Chain, N->getOperand(0));
-if(N->getNumOperands()==3) // we have an incoming chain, callee and flag
- AddToQueue(InFlag, N->getOperand(2));
+AddToISelQueue(Chain);
+if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
+ InFlag = N->getOperand(2);
+ AddToISelQueue(InFlag);
+}
unsigned CallOpcode;
SDOperand CallOperand;
@@ -334,8 +338,8 @@
// otherwise we need to load the function descriptor,
// load the branch target (function)'s entry point and GP,
// branch (call) then restore the GP
-SDOperand FnDescriptor;
-AddToQueue(FnDescriptor, N->getOperand(1));
+SDOperand FnDescriptor = N->getOperand(1);
+AddToISelQueue(FnDescriptor);
// load the branch target's entry point [mem] and
// GP value [mem+8]
@@ -380,8 +384,8 @@
}
case IA64ISD::GETFD: {
-SDOperand Input;
-AddToQueue(Input, N->getOperand(0));
+SDOperand Input = N->getOperand(0);
+AddToISelQueue(Input);
Result = SDOperand(CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input), 0);
return Result.Val;
}
@@ -447,9 +451,10 @@
case ISD::LOAD:
case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools?
case ISD::ZEXTLOAD: {
-SDOperand Chain, Address;
-AddToQueue(Chain, N->getOperand(0));
-AddToQueue(Address, N->getOperand(1));
+SDOperand Chain = N->getOperand(0);
+SDOperand Address = N->getOperand(1);
+AddToISelQueue(Chain);
+AddToISelQueue(Address);
MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
N->getValueType(0) : cast(N->getOperand(3))->getVT();
@@ -487,9 +492,10 @@
case ISD::TRUNCSTORE:
case ISD::STORE: {
-SDOperand Address, Chain;
-AddToQueue(Address, N->getOperand(2));
-AddToQueue(Chain, N->getOperand(0));
+SDOperand Address = N->getOperand(2);
+SDOperand Chain = N->getOperand(0);
+AddToISelQueue(Address);
+AddToISelQueue(Chain);
unsigned Opc;
if (N->getOpcode() == ISD::STORE) {
@@ -501,8 +507,8 @@
SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
Chain = Initial.getValue(1);
// then load 1 into the same reg iff the predicate to store is 1
-SDOperand Tmp;
-AddToQueue(Tmp, N->getOperand(1));
+SDOperand Tmp = N->getOperand(1);
+AddToISelQueue(Tmp);
Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
CurDAG->getConstant(1, MVT::i64),
Tmp), 0);
@@ -521,16 +527,18 @@
}
}
-SDOperand N1, N2;
-AddToQueue(N1, N->getOperand(1));
-AddToQueue(N2, N->getOperand(2));
+SDOperand N1 = N->getOperand(1);
+SDOperand N2 = N->getOperand(2);
+AddToISelQueue(N1);
+AddToISelQueue(N2);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain).Val;
}
case ISD::BRCOND: {
-SDOperand Chain, CC;
-AddToQueue(Chain, N->getOperand(0));
-AddToQueue(CC, N->getOperand(1));
+SDOperand Chain = N->getOperand(0);
+SDOperand CC = N->getOperand(1);
+AddToISelQueue(Chain);
+AddToISelQueue(CC);
MachineBasicBlock *Dest =
cast(N->getOperand(2))->getBasicBlock();
//FIXME - we do NOT need long branches all the time
@@ -543,15 +551,15 @@
int64_t Amt = cast(N->getOperand(1))->getValue();
unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
-SDOperand N0;
-AddToQueue(N0, N->getOperand(0));
+SDOperand N0 = N->getOperand(0);
+AddToISelQueue(N0);
ret
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.48 -> 1.49
---
Log message:
SelectNodeTo() may return a SDOperand that is different from the input.
---
Diffs of the changes: (+20 -31)
IA64ISelDAGToDAG.cpp | 51 ---
1 files changed, 20 insertions(+), 31 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.48
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.49
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.48 Fri Aug 11 04:07:25 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Wed Aug 16 02:29:13 2006
@@ -398,25 +398,21 @@
SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
if (cast(N)->isExactlyValue(+0.0)) {
- Result = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
+ return CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64).Val;
} else if (cast(N)->isExactlyValue(+1.0)) {
- Result = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
+ return CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64).Val;
} else
assert(0 && "Unexpected FP constant!");
-return Result.Val;
}
case ISD::FrameIndex: { // TODO: reduce creepyness
int FI = cast(N)->getIndex();
-if (N->hasOneUse()) {
- Result = CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
- CurDAG->getTargetFrameIndex(FI, MVT::i64));
- return NULL;
-} else {
- Result = SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64,
-CurDAG->getTargetFrameIndex(FI, MVT::i64)), 0);
- return Result.Val;
-}
+if (N->hasOneUse())
+ return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
+ CurDAG->getTargetFrameIndex(FI,
MVT::i64)).Val;
+else
+ return SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64,
+ CurDAG->getTargetFrameIndex(FI, MVT::i64)),
0).Val;
}
case ISD::ConstantPool: { // TODO: nuke the constant pool
@@ -467,11 +463,10 @@
case MVT::i1: { // this is a bool
Opc = IA64::LD1; // first we load a byte, then compare for != 0
if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
-Result = CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
+return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address),
0),
- CurDAG->getRegister(IA64::r0, MVT::i64),
- Chain).getValue(Op.ResNo);
-return NULL;
+CurDAG->getRegister(IA64::r0, MVT::i64),
+Chain).getValue(Op.ResNo).Val;
}
/* otherwise, we want to load a bool into something bigger: LD1
will do that for us, so we just fall through */
@@ -486,9 +481,8 @@
}
// TODO: comment this
-Result = CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
-Address, Chain).getValue(Op.ResNo);
-return NULL;
+return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
+Address, Chain).getValue(Op.ResNo).Val;
}
case ISD::TRUNCSTORE:
@@ -512,8 +506,7 @@
Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
CurDAG->getConstant(1, MVT::i64),
Tmp), 0);
-Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
-return NULL;
+return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp,
Chain).Val;
}
case MVT::i64: Opc = IA64::ST8; break;
case MVT::f64: Opc = IA64::STF8; break;
@@ -531,8 +524,7 @@
SDOperand N1, N2;
AddToQueue(N1, N->getOperand(1));
AddToQueue(N2, N->getOperand(2));
-Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
-return NULL;
+return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain).Val;
}
case ISD::BRCOND: {
@@ -542,9 +534,8 @@
MachineBasicBlock *Dest =
cast(N->getOperand(2))->getBasicBlock();
//FIXME - we do NOT need long branches all the time
-Result = CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
-CurDAG->getBasicBlock(Dest), Chain);
-return NULL;
+return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
+CurDAG->getBasicBlock(Dest), Chain).Val;
}
case ISD::CALLSEQ_START:
@@ -554,17 +545,15 @@
IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
SDOperand N0;
AddToQueue(N0, N->getOperand(0));
-Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
-return NULL;
+return CurDAG->SelectNodeTo(N, Opc, MVT::
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.47 -> 1.48
---
Log message:
Match tablegen changes.
---
Diffs of the changes: (+21 -25)
IA64ISelDAGToDAG.cpp | 46 +-
1 files changed, 21 insertions(+), 25 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.47
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.48
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.47 Mon Aug 7 17:23:40 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Fri Aug 11 04:07:25 2006
@@ -65,7 +65,7 @@
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
-void Select(SDOperand &Result, SDOperand N);
+SDNode *Select(SDOperand &Result, SDOperand N);
SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
unsigned OCHi, unsigned OCLo,
@@ -296,12 +296,12 @@
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
-void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
+SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
SDNode *N = Op.Val;
if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
N->getOpcode() < IA64ISD::FIRST_NUMBER) {
Result = Op;
-return; // Already selected.
+return NULL; // Already selected.
}
switch (N->getOpcode()) {
@@ -376,15 +376,14 @@
for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
ReplaceUses(Op.getValue(i), CallResults[i]);
Result = CallResults[Op.ResNo];
- return;
+ return NULL;
}
case IA64ISD::GETFD: {
SDOperand Input;
AddToQueue(Input, N->getOperand(0));
Result = SDOperand(CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input), 0);
-ReplaceUses(Op, Result);
-return;
+return Result.Val;
}
case ISD::FDIV:
@@ -393,8 +392,7 @@
case ISD::SREM:
case ISD::UREM:
Result = SelectDIV(Op);
-ReplaceUses(Op, Result);
-return;
+return Result.Val;
case ISD::TargetConstantFP: {
SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
@@ -405,20 +403,20 @@
Result = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
} else
assert(0 && "Unexpected FP constant!");
-return;
+return Result.Val;
}
case ISD::FrameIndex: { // TODO: reduce creepyness
int FI = cast(N)->getIndex();
-if (N->hasOneUse())
+if (N->hasOneUse()) {
Result = CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
CurDAG->getTargetFrameIndex(FI, MVT::i64));
-else {
+ return NULL;
+} else {
Result = SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64,
CurDAG->getTargetFrameIndex(FI, MVT::i64)), 0);
- ReplaceUses(Op, Result);
+ return Result.Val;
}
-return;
}
case ISD::ConstantPool: { // TODO: nuke the constant pool
@@ -429,8 +427,7 @@
CP->getAlignment());
Result = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
CurDAG->getRegister(IA64::r1, MVT::i64), CPI), 0);
-ReplaceUses(Op, Result);
-return;
+return Result.Val;
}
case ISD::GlobalAddress: {
@@ -439,8 +436,7 @@
SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
CurDAG->getRegister(IA64::r1, MVT::i64), GA),
0);
Result = SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp), 0);
-ReplaceUses(Op, Result);
-return;
+return Result.Val;
}
/* XXX case ISD::ExternalSymbol: {
@@ -475,7 +471,7 @@
SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address),
0),
CurDAG->getRegister(IA64::r0, MVT::i64),
Chain).getValue(Op.ResNo);
-return;
+return NULL;
}
/* otherwise, we want to load a bool into something bigger: LD1
will do that for us, so we just fall through */
@@ -492,7 +488,7 @@
// TODO: comment this
Result = CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
Address, Chain).getValue(Op.ResNo);
-return;
+return NULL;
}
case ISD::TRUNCSTORE:
@@ -517,7 +513,7 @@
CurDAG->getConstant(1, MVT::i64),
Tmp), 0);
Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
-return;
+return NULL;
}
case MVT::i64: Opc = IA64::ST8; break;
case MVT::f64: Opc = IA64::STF8; break;
@@ -536,7 +532,7 @@
AddToQueue(N1, N->getOperand(1));
AddToQueue(N2, N->getOperand(2));
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.46 -> 1.47
---
Log message:
Match tablegen isel changes.
---
Diffs of the changes: (+28 -70)
IA64ISelDAGToDAG.cpp | 98 ++-
1 files changed, 28 insertions(+), 70 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.46
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.47
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.46 Thu Jul 27 19:46:44 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Aug 7 17:23:40 2006
@@ -28,6 +28,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include
+#include
#include
using namespace llvm;
@@ -101,50 +102,9 @@
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
DEBUG(BB->dump());
-
- // The selection process is inherently a bottom-up recursive process (users
- // select their uses before themselves). Given infinite stack space, we
- // could just start selecting on the root and traverse the whole graph. In
- // practice however, this causes us to run out of stack space on large basic
- // blocks. To avoid this problem, select the entry node, then all its uses,
- // iteratively instead of recursively.
- std::vector Worklist;
- Worklist.push_back(DAG.getEntryNode());
-
- // Note that we can do this in the IA64 target (scanning forward across token
- // chain edges) because no nodes ever get folded across these edges. On a
- // target like X86 which supports load/modify/store operations, this would
- // have to be more careful.
- while (!Worklist.empty()) {
-SDOperand Node = Worklist.back();
-Worklist.pop_back();
-
-if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
- Node.Val->getOpcode() < IA64ISD::FIRST_NUMBER) ||
-CodeGenMap.count(Node)) continue;
-
-for (SDNode::use_iterator UI = Node.Val->use_begin(),
- E = Node.Val->use_end(); UI != E; ++UI) {
- // Scan the values. If this use has a value that is a token chain, add
it
- // to the worklist.
- SDNode *User = *UI;
- for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
-if (User->getValueType(i) == MVT::Other) {
- Worklist.push_back(SDOperand(User, i));
- break;
-}
-}
-// Finally, legalize this node.
-SDOperand Dummy;
-Select(Dummy, Node);
- }
-
// Select target instructions for the DAG.
DAG.setRoot(SelectRoot(DAG.getRoot()));
- CodeGenMap.clear();
- HandleMap.clear();
- ReplaceMap.clear();
DAG.RemoveDeadNodes();
// Emit machine code to BB.
@@ -154,10 +114,10 @@
SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
SDNode *N = Op.Val;
SDOperand Chain, Tmp1, Tmp2;
- Select(Chain, N->getOperand(0));
+ AddToQueue(Chain, N->getOperand(0));
- Select(Tmp1, N->getOperand(0));
- Select(Tmp2, N->getOperand(1));
+ AddToQueue(Tmp1, N->getOperand(0));
+ AddToQueue(Tmp2, N->getOperand(1));
bool isFP=false;
@@ -344,13 +304,6 @@
return; // Already selected.
}
- // If this has already been converted, use it.
- std::map::iterator CGMI = CodeGenMap.find(Op);
- if (CGMI != CodeGenMap.end()) {
-Result = CGMI->second;
-return;
- }
-
switch (N->getOpcode()) {
default: break;
@@ -358,9 +311,9 @@
SDOperand Chain;
SDOperand InFlag; // Null incoming flag value.
-Select(Chain, N->getOperand(0));
+AddToQueue(Chain, N->getOperand(0));
if(N->getNumOperands()==3) // we have an incoming chain, callee and flag
- Select(InFlag, N->getOperand(2));
+ AddToQueue(InFlag, N->getOperand(2));
unsigned CallOpcode;
SDOperand CallOperand;
@@ -382,7 +335,7 @@
// load the branch target (function)'s entry point and GP,
// branch (call) then restore the GP
SDOperand FnDescriptor;
-Select(FnDescriptor, N->getOperand(1));
+AddToQueue(FnDescriptor, N->getOperand(1));
// load the branch target's entry point [mem] and
// GP value [mem+8]
@@ -421,16 +374,16 @@
CallResults.push_back(InFlag);
for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
- CodeGenMap[Op.getValue(i)] = CallResults[i];
+ ReplaceUses(Op.getValue(i), CallResults[i]);
Result = CallResults[Op.ResNo];
return;
}
case IA64ISD::GETFD: {
SDOperand Input;
-Select(Input, N->getOperand(0));
+AddToQueue(Input, N->getOperand(0));
Result = SDOperand(CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input), 0);
-CodeGenMap[Op] = Result;
+ReplaceUses(Op, Result);
return;
}
@@ -440,6 +393,7 @@
case ISD::SREM:
case ISD::UREM:
Result = SelectDIV(Op);
+ReplaceUses(Op, Result);
return;
case ISD::TargetConstantFP: {
@@ -459,9 +413,11 @@
if (N->hasOneUse())
Result = CurDAG->Select
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.45 -> 1.46 --- Log message: Remove InFlightSet hack. No longer needed. --- Diffs of the changes: (+0 -1) IA64ISelDAGToDAG.cpp |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.45 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.46 --- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.45 Thu Jul 27 01:39:46 2006 +++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Thu Jul 27 19:46:44 2006 @@ -142,7 +142,6 @@ // Select target instructions for the DAG. DAG.setRoot(SelectRoot(DAG.getRoot())); - assert(InFlightSet.empty() && "ISel InFlightSet has not been emptied!"); CodeGenMap.clear(); HandleMap.clear(); ReplaceMap.clear(); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.44 -> 1.45
---
Log message:
Remove NodeDepth
---
Diffs of the changes: (+1 -6)
IA64ISelDAGToDAG.cpp |7 +--
1 files changed, 1 insertion(+), 6 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.44
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.45
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.44 Tue Jul 11 13:25:13 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Thu Jul 27 01:39:46 2006
@@ -118,12 +118,7 @@
while (!Worklist.empty()) {
SDOperand Node = Worklist.back();
Worklist.pop_back();
-
-// Chose from the least deep of the top two nodes.
-if (!Worklist.empty() &&
-Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
- std::swap(Worklist.back(), Node);
-
+
if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
Node.Val->getOpcode() < IA64ISD::FIRST_NUMBER) ||
CodeGenMap.count(Node)) continue;
___
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llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.43 -> 1.44
---
Log message:
It was pointed out that DEBUG() is only available with -debug.
---
Diffs of the changes: (+5 -1)
IA64ISelDAGToDAG.cpp |6 +-
1 files changed, 5 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.43
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.44
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.43 Tue Jul 11 12:58:07 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Tue Jul 11 13:25:13 2006
@@ -511,7 +511,11 @@
N->getValueType(0) : cast(N->getOperand(3))->getVT();
unsigned Opc;
switch (TypeBeingLoaded) {
-default: DEBUG(N->dump()); assert(0 && "Cannot load this type!");
+default:
+#ifndef NDEBUG
+ N->dump();
+#endif
+ assert(0 && "Cannot load this type!");
case MVT::i1: { // this is a bool
Opc = IA64::LD1; // first we load a byte, then compare for != 0
if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.42 -> 1.43
---
Log message:
Ensure that dump calls that are associated with asserts are removed from
non-debug build.
---
Diffs of the changes: (+1 -1)
IA64ISelDAGToDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.42
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.43
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.42 Wed May 24 19:24:28 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Tue Jul 11 12:58:07 2006
@@ -511,7 +511,7 @@
N->getValueType(0) : cast(N->getOperand(3))->getVT();
unsigned Opc;
switch (TypeBeingLoaded) {
-default: N->dump(); assert(0 && "Cannot load this type!");
+default: DEBUG(N->dump()); assert(0 && "Cannot load this type!");
case MVT::i1: { // this is a bool
Opc = IA64::LD1; // first we load a byte, then compare for != 0
if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.41 -> 1.42 --- Log message: Assert if InflightSet is not cleared after instruction selecting a BB. --- Diffs of the changes: (+1 -0) IA64ISelDAGToDAG.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.41 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.42 --- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.41 Wed May 24 15:46:25 2006 +++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Wed May 24 19:24:28 2006 @@ -147,6 +147,7 @@ // Select target instructions for the DAG. DAG.setRoot(SelectRoot(DAG.getRoot())); + assert(InFlightSet.empty() && "ISel InFlightSet has not been emptied!"); CodeGenMap.clear(); HandleMap.clear(); ReplaceMap.clear(); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.40 -> 1.41 --- Log message: Clear HandleMap and ReplaceMap after instruction selection. Or it may cause non-deterministic behavior. --- Diffs of the changes: (+2 -0) IA64ISelDAGToDAG.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.40 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.41 --- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.40 Tue May 16 12:42:15 2006 +++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Wed May 24 15:46:25 2006 @@ -148,6 +148,8 @@ // Select target instructions for the DAG. DAG.setRoot(SelectRoot(DAG.getRoot())); CodeGenMap.clear(); + HandleMap.clear(); + ReplaceMap.clear(); DAG.RemoveDeadNodes(); // Emit machine code to BB. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.39 -> 1.40 --- Log message: Move this code to a common place --- Diffs of the changes: (+0 -3) IA64ISelDAGToDAG.cpp |3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.39 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.40 --- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.39 Sat Mar 25 00:47:10 2006 +++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Tue May 16 12:42:15 2006 @@ -81,9 +81,6 @@ /// operation. bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2); -SDOperand BuildSDIVSequence(SDNode *N); -SDOperand BuildUDIVSequence(SDNode *N); - /// InstructionSelectBasicBlock - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.38 -> 1.39 --- Log message: #include Intrinsics.h into all dag isels --- Diffs of the changes: (+1 -0) IA64ISelDAGToDAG.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.38 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.39 --- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.38 Mon Mar 13 17:20:37 2006 +++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sat Mar 25 00:47:10 2006 @@ -24,6 +24,7 @@ #include "llvm/ADT/Statistic.h" #include "llvm/Constants.h" #include "llvm/GlobalValue.h" +#include "llvm/Intrinsics.h" #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" #include ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.36 -> 1.37 --- Log message: fix storing booleans (grawp missed this one) --- Diffs of the changes: (+3 -3) IA64ISelDAGToDAG.cpp |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.36 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.37 --- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.36 Thu Feb 9 01:17:49 2006 +++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sat Feb 11 01:33:17 2006 @@ -556,9 +556,9 @@ // then load 1 into the same reg iff the predicate to store is 1 SDOperand Tmp; Select(Tmp, N->getOperand(1)); -CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial, - CurDAG->getConstant(1, MVT::i64), - Tmp); +Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial, + CurDAG->getConstant(1, MVT::i64), + Tmp), 0); Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain); return; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.35 -> 1.36
---
Log message:
Match getTargetNode() changes (now return SDNode* instead of SDOperand).
---
Diffs of the changes: (+78 -64)
IA64ISelDAGToDAG.cpp | 142 ---
1 files changed, 78 insertions(+), 64 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.35
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.36
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.35 Wed Feb 8 18:37:58 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Thu Feb 9 01:17:49 2006
@@ -186,7 +186,7 @@
SDOperand TmpPR, TmpPR2;
SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
-SDOperand Result;
+SDNode *Result;
// we'll need copies of F0 and F1
SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
@@ -196,21 +196,27 @@
if(!isFP) {
// first, load the inputs into FP regs.
- TmpF1 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1);
+ TmpF1 =
+SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
Chain = TmpF1.getValue(1);
- TmpF2 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2);
+ TmpF2 =
+SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
Chain = TmpF2.getValue(1);
// next, convert the inputs to FP
if(isSigned) {
-TmpF3 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1);
+TmpF3 =
+ SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
Chain = TmpF3.getValue(1);
-TmpF4 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2);
+TmpF4 =
+ SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
Chain = TmpF4.getValue(1);
} else { // is unsigned
-TmpF3 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
+TmpF3 =
+ SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1),
0);
Chain = TmpF3.getValue(1);
-TmpF4 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
+TmpF4 =
+ SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2),
0);
Chain = TmpF4.getValue(1);
}
@@ -223,11 +229,11 @@
// we start by computing an approximate reciprocal (good to 9 bits?)
// note, this instruction writes _both_ TmpF5 (answer) and TmpPR
(predicate)
if(isFP)
- TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
- TmpF3, TmpF4);
+ TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
+ TmpF3, TmpF4), 0);
else
- TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
- TmpF3, TmpF4);
+ TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
+ TmpF3, TmpF4), 0);
TmpPR = TmpF5.getValue(1);
Chain = TmpF5.getValue(2);
@@ -235,24 +241,24 @@
SDOperand minusB;
if(isModulus) { // for remainders, it'll be handy to have
// copies of -input_b
- minusB = CurDAG->getTargetNode(IA64::SUB, MVT::i64,
- CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2);
+ minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
+ CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
Chain = minusB.getValue(1);
}
SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
-TmpE0 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
- TmpF4, TmpF5, F1, TmpPR);
+TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
+TmpF4, TmpF5, F1, TmpPR), 0);
Chain = TmpE0.getValue(1);
-TmpY1 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpF5, TmpE0, TmpF5, TmpPR);
+TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+TmpF5, TmpE0, TmpF5, TmpPR), 0);
Chain = TmpY1.getValue(1);
-TmpE1 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpE0, TmpE0, F0, TmpPR);
+TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+TmpE0, TmpE0, F0, TmpPR), 0);
Chain = TmpE1.getValue(1);
-TmpY2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpY1, TmpE1, TmpY1, TmpPR);
+TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+TmpY1, TmpE1, TmpY1, TmpPR), 0);
Chain = TmpY2.getValue(1);
if(isFP) { // if this is an FP divide, we finish up here and exit early
@@ -261,42 +267,44 @@
SDOperand TmpE2, TmpY3, Tmp
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.34 -> 1.35
---
Log message:
Change Select() from
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
---
Diffs of the changes: (+82 -48)
IA64ISelDAGToDAG.cpp | 130 ---
1 files changed, 82 insertions(+), 48 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.34
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.35
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.34 Sun Feb 5 00:46:41 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Wed Feb 8 18:37:58 2006
@@ -63,7 +63,7 @@
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
-SDOperand Select(SDOperand Op);
+void Select(SDOperand &Result, SDOperand N);
SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
unsigned OCHi, unsigned OCLo,
@@ -143,7 +143,8 @@
}
// Finally, legalize this node.
-Select(Node);
+SDOperand Dummy;
+Select(Dummy, Node);
}
// Select target instructions for the DAG.
@@ -157,10 +158,11 @@
SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
SDNode *N = Op.Val;
- SDOperand Chain = Select(N->getOperand(0));
+ SDOperand Chain, Tmp1, Tmp2;
+ Select(Chain, N->getOperand(0));
- SDOperand Tmp1 = Select(N->getOperand(0));
- SDOperand Tmp2 = Select(N->getOperand(1));
+ Select(Tmp1, N->getOperand(0));
+ Select(Tmp2, N->getOperand(1));
bool isFP=false;
@@ -328,25 +330,31 @@
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
-SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
+void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
SDNode *N = Op.Val;
if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
- N->getOpcode() < IA64ISD::FIRST_NUMBER)
-return Op; // Already selected.
+ N->getOpcode() < IA64ISD::FIRST_NUMBER) {
+Result = Op;
+return; // Already selected.
+ }
// If this has already been converted, use it.
std::map::iterator CGMI = CodeGenMap.find(Op);
- if (CGMI != CodeGenMap.end()) return CGMI->second;
+ if (CGMI != CodeGenMap.end()) {
+Result = CGMI->second;
+return;
+ }
switch (N->getOpcode()) {
default: break;
case IA64ISD::BRCALL: { // XXX: this is also a hack!
-SDOperand Chain = Select(N->getOperand(0));
+SDOperand Chain;
SDOperand InFlag; // Null incoming flag value.
+Select(Chain, N->getOperand(0));
if(N->getNumOperands()==3) // we have an incoming chain, callee and flag
- InFlag = Select(N->getOperand(2));
+ Select(InFlag, N->getOperand(2));
unsigned CallOpcode;
SDOperand CallOperand;
@@ -367,7 +375,8 @@
// otherwise we need to load the function descriptor,
// load the branch target (function)'s entry point and GP,
// branch (call) then restore the GP
-SDOperand FnDescriptor = Select(N->getOperand(1));
+SDOperand FnDescriptor;
+Select(FnDescriptor, N->getOperand(1));
// load the branch target's entry point [mem] and
// GP value [mem+8]
@@ -404,41 +413,47 @@
for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
CodeGenMap[Op.getValue(i)] = CallResults[i];
- return CallResults[Op.ResNo];
+ Result = CallResults[Op.ResNo];
+ return;
}
case IA64ISD::GETFD: {
-SDOperand Input = Select(N->getOperand(0));
-SDOperand Result = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
+SDOperand Input;
+Select(Input, N->getOperand(0));
+Result = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
CodeGenMap[Op] = Result;
-return Result;
+return;
}
case ISD::FDIV:
case ISD::SDIV:
case ISD::UDIV:
case ISD::SREM:
- case ISD::UREM: return SelectDIV(Op);
+ case ISD::UREM:
+Result = SelectDIV(Op);
+return;
case ISD::TargetConstantFP: {
SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
-if (cast(N)->isExactlyValue(+0.0))
- return CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
-else if (cast(N)->isExactlyValue(+1.0))
- return CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
-else
+if (cast(N)->isExactlyValue(+0.0)) {
+ Result = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
+} else if (cast(N)->isExactlyValue(+1.0)) {
+ Result = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
+} else
assert(0 && "Unexpected FP constant!");
+return;
}
case ISD::FrameIndex: { // TODO: reduce creepyness
int FI = cast(N)->getIndex();
if (N->hasOneUse())
- return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
+ Result = CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.33 -> 1.34
---
Log message:
Use SelectRoot() as entry of any tblgen based isel.
---
Diffs of the changes: (+2 -1)
IA64ISelDAGToDAG.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.33
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.34
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.33 Tue Jan 31 16:21:34 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sun Feb 5 00:46:41 2006
@@ -27,6 +27,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include
+#include
using namespace llvm;
namespace {
@@ -146,7 +147,7 @@
}
// Select target instructions for the DAG.
- DAG.setRoot(Select(DAG.getRoot()));
+ DAG.setRoot(SelectRoot(DAG.getRoot()));
CodeGenMap.clear();
DAG.RemoveDeadNodes();
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.32 -> 1.33
---
Log message:
Allow the specification of explicit alignments for constant pool entries.
---
Diffs of the changes: (+4 -2)
IA64ISelDAGToDAG.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.32
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.33
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.32 Sun Jan 29 00:26:07 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Tue Jan 31 16:21:34 2006
@@ -442,8 +442,10 @@
case ISD::ConstantPool: { // TODO: nuke the constant pool
// (ia64 doesn't need one)
-Constant *C = cast(N)->get();
-SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
+ConstantPoolSDNode *CP = cast(N);
+Constant *C = CP->get();
+SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
+ CP->getAlignment());
return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
}
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.31 -> 1.32
IA64ISelLowering.cpp updated: 1.31 -> 1.32
---
Log message:
Targets all now request ConstantFP to be legalized into TargetConstantFP.
'fpimm' in .td files is now TargetConstantFP.
---
Diffs of the changes: (+2 -1)
IA64ISelDAGToDAG.cpp |2 +-
IA64ISelLowering.cpp |1 +
2 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.31
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.32
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.31 Fri Jan 27 18:02:51 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sun Jan 29 00:26:07 2006
@@ -419,7 +419,7 @@
case ISD::SREM:
case ISD::UREM: return SelectDIV(Op);
- case ISD::ConstantFP: {
+ case ISD::TargetConstantFP: {
SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
if (cast(N)->isExactlyValue(+0.0))
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.31
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.32
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.31 Fri Jan 27 21:14:31 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Sun Jan 29 00:26:07 2006
@@ -104,6 +104,7 @@
computeRegisterProperties();
+ setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
addLegalFPImmediate(+0.0);
addLegalFPImmediate(+1.0);
}
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.30 -> 1.31
IA64ISelLowering.cpp updated: 1.29 -> 1.30
---
Log message:
Remove some dead code
---
Diffs of the changes: (+0 -35)
IA64ISelDAGToDAG.cpp | 30 --
IA64ISelLowering.cpp |5 -
2 files changed, 35 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.30
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.31
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.30 Sun Jan 22 17:37:17 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Fri Jan 27 18:02:51 2006
@@ -413,36 +413,6 @@
return Result;
}
- case ISD::CALL:
- case ISD::TAILCALL: { {
-// FIXME: This is a workaround for a bug in tblgen.
-// Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
-// Emits: (CALL:void (tglobaladdr:i32):$dst)
-// Pattern complexity = 2 cost = 1
-SDOperand N1 = N->getOperand(1);
-if (N1.getOpcode() != ISD::TargetGlobalAddress &&
-N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail;
-SDOperand InFlag = SDOperand(0, 0);
-SDOperand Chain = N->getOperand(0);
-SDOperand Tmp0 = N1;
-Chain = Select(Chain);
-SDOperand Result;
-if (N->getNumOperands() == 3) {
- InFlag = Select(N->getOperand(2));
- Result = CurDAG->getTargetNode(IA64::BRCALL, MVT::Other, MVT::Flag,
Tmp0,
- Chain, InFlag);
-} else {
- Result = CurDAG->getTargetNode(IA64::BRCALL, MVT::Other, MVT::Flag,
Tmp0,
- Chain);
-}
-Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
-CodeGenMap[SDOperand(N, 1)] = Result.getValue(1);
-return Result.getValue(Op.ResNo);
- }
-P47Fail:;
-
- }
-
case ISD::FDIV:
case ISD::SDIV:
case ISD::UDIV:
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.29
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.30
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.29 Fri Jan 27 15:09:22 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Fri Jan 27 18:02:51 2006
@@ -461,11 +461,6 @@
else
assert(0 && "this should never happen!\n");
-/* out with the old...
-Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0);
- else
-Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0);
-*/
// to make way for a hack:
Chain = DAG.getNode(IA64ISD::BRCALL, NodeTys, CallOperands);
InFlag = Chain.getValue(1);
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.28 -> 1.29 --- Log message: insignificant, but next up is proper stack frame layout! --- Diffs of the changes: (+2 -1) IA64ISelDAGToDAG.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.28 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.29 --- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.28 Fri Jan 20 14:24:31 2006 +++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sat Jan 21 08:27:19 2006 @@ -464,7 +464,8 @@ if (N->hasOneUse()) return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64, CurDAG->getTargetFrameIndex(FI, MVT::i64)); -return CurDAG->getTargetNode(IA64::MOV, MVT::i64, +else + return CodeGenMap[Op] = CurDAG->getTargetNode(IA64::MOV, MVT::i64, CurDAG->getTargetFrameIndex(FI, MVT::i64)); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp IA64ISelLowering.h IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.27 -> 1.28
IA64ISelLowering.cpp updated: 1.24 -> 1.25
IA64ISelLowering.h updated: 1.4 -> 1.5
IA64InstrInfo.td updated: 1.41 -> 1.42
---
Log message:
remove RET hack, add proper support for rets (watching out for ret voids)
---
Diffs of the changes: (+89 -56)
IA64ISelDAGToDAG.cpp | 51 ---
IA64ISelLowering.cpp | 66 +++
IA64ISelLowering.h | 16 ++--
IA64InstrInfo.td | 12 ++---
4 files changed, 89 insertions(+), 56 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.27
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.28
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.27 Fri Jan 20 10:10:05 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Fri Jan 20 14:24:31 2006
@@ -585,57 +585,6 @@
getI64Imm(Amt), Select(N->getOperand(0)));
}
- case ISD::RET: {
-SDOperand Chain = Select(N->getOperand(0)); // Token chain.
-SDOperand InFlag;
-
-switch (N->getNumOperands()) {
-default:
- assert(0 && "Unknown return instruction!");
-case 2: {
- SDOperand RetVal = Select(N->getOperand(1));
- switch (RetVal.getValueType()) {
- default: assert(0 && "I don't know how to return this type! (promote?)");
- // FIXME: do I need to add support for bools here?
- // (return '0' or '1' in r8, basically...)
- //
- // FIXME: need to round floats - 80 bits is bad, the tester
- // told me so
- case MVT::i64:
-// we mark r8 as live on exit up above in LowerArguments()
-// BuildMI(BB, IA64::MOV, 1, IA64::r8).addReg(Tmp1);
-Chain = CurDAG->getCopyToReg(Chain, IA64::r8, RetVal);
- InFlag = Chain.getValue(1);
- break;
- case MVT::f64:
-// we mark F8 as live on exit up above in LowerArguments()
-// BuildMI(BB, IA64::FMOV, 1, IA64::F8).addReg(Tmp1);
-Chain = CurDAG->getCopyToReg(Chain, IA64::F8, RetVal);
- InFlag = Chain.getValue(1);
-break;
- }
- break;
- }
-case 1:
- break;
-}
-
-// we need to copy VirtGPR (the vreg (to become a real reg)) that holds
-// the output of this function's alloc instruction back into ar.pfs
-// before we return. this copy must not float up above the last
-// outgoing call in this function!!!
-SDOperand AR_PFSVal = CurDAG->getCopyFromReg(Chain, IA64Lowering.VirtGPR,
- MVT::i64);
-Chain = AR_PFSVal.getValue(1);
-Chain = CurDAG->getCopyToReg(Chain, IA64::AR_PFS, AR_PFSVal);
-
-// and then just emit a 'ret' instruction
-// before returning, restore the ar.pfs register (set by the 'alloc' up
top)
-// BuildMI(BB, IA64::MOV,
1).addReg(IA64::AR_PFS).addReg(IA64Lowering.VirtGPR);
-//
-return CurDAG->SelectNodeTo(N, IA64::RET, MVT::Other, Chain);
- }
-
case ISD::BR:
// FIXME: we don't need long branches all the time!
return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.24
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.25
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.24 Fri Jan 20 10:10:05 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Fri Jan 20 14:24:31 2006
@@ -39,6 +39,11 @@
setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
+ // We need to handle ISD::RET for void functions ourselves,
+ // so we get a chance to restore ar.pfs before adding a
+ // br.ret insn
+ setOperationAction(ISD::RET, MVT::Other, Custom);
+
setSetCCResultType(MVT::i1);
setShiftAmountType(MVT::i64);
@@ -101,6 +106,7 @@
default: return 0;
case IA64ISD::GETFD: return "IA64ISD::GETFD";
case IA64ISD::BRCALL: return "IA64ISD::BRCALL";
+ case IA64ISD::RET_FLAG: return "IA64ISD::RET_FLAG";
}
}
@@ -524,6 +530,44 @@
return std::make_pair(RetVal, Chain);
}
+SDOperand IA64TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
+ SelectionDAG &DAG) {
+ SDOperand Copy, InFlag;
+ SDOperand AR_PFSVal = DAG.getCopyFromReg(Chain, this->VirtGPR,
+ MVT::i64);
+ Chain = AR_PFSVal.getValue(1);
+
+ switch (Op.getValueType()) {
+ default: assert(0 && "Unknown type to return! (promote?)");
+ case MVT::i64:
+Copy = DAG.getCopyToReg(Chain, IA64::r8, Op, InFlag);
+break;
+ case MVT::f64:
+Copy = DAG.getCopyToReg(Chain, IA64::F8, Op, InFlag);
+break;
+ }
+
+ Chain = Copy.getValue(0);
+ InFlag = Copy.getValue(1);
+ // we need to copy VirtGPR (the
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.26 -> 1.27
IA64ISelLowering.cpp updated: 1.23 -> 1.24
---
Log message:
fix sext breakage: now we correctly deal with functions that return
int vs uint
---
Diffs of the changes: (+5 -1)
IA64ISelDAGToDAG.cpp |2 +-
IA64ISelLowering.cpp |4
2 files changed, 5 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.26
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.27
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.26 Thu Jan 19 21:40:25 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Fri Jan 20 10:10:05 2006
@@ -494,7 +494,7 @@
*/
case ISD::LOAD:
- case ISD::EXTLOAD:
+ case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools?
case ISD::ZEXTLOAD: {
SDOperand Chain = Select(N->getOperand(0));
SDOperand Address = Select(N->getOperand(1));
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.23
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.24
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.23 Thu Jan 19 02:31:51 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Fri Jan 20 10:10:05 2006
@@ -475,6 +475,8 @@
switch (RetTyVT) {
default: assert(0 && "Unknown value type to return!");
case MVT::i1: { // bools are just like other integers (returned in r8)
+ // we *could* fall through to the truncate below, but this saves a
+ // few redundant predicate ops
SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,
InFlag);
InFlag = boolInR8.getValue(2);
Chain = boolInR8.getValue(1);
@@ -492,8 +494,10 @@
Chain = RetVal.getValue(1);
// keep track of whether it is sign or zero extended (todo: bools?)
+/* XXX
RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext
:ISD::AssertZext,
MVT::i64, RetVal, DAG.getValueType(RetTyVT));
+*/
RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
break;
case MVT::i64:
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.25 -> 1.26 IA64InstrInfo.td updated: 1.40 -> 1.41 --- Log message: fix storing bools! eek! --- Diffs of the changes: (+5 -8) IA64ISelDAGToDAG.cpp |4 ++-- IA64InstrInfo.td |9 +++-- 2 files changed, 5 insertions(+), 8 deletions(-) Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.25 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.26 --- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.25 Mon Jan 16 21:09:48 2006 +++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Thu Jan 19 21:40:25 2006 @@ -542,9 +542,9 @@ // first load zero! SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64); Chain = Initial.getValue(1); - // then load 1 iff the predicate to store is 1 + // then load 1 into the same reg iff the predicate to store is 1 SDOperand Tmp = - CurDAG->getTargetNode(IA64::PADDS, MVT::i64, Initial, + CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial, CurDAG->getConstant(1, MVT::i64), Select(N->getOperand(1))); return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain); Index: llvm/lib/Target/IA64/IA64InstrInfo.td diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.40 llvm/lib/Target/IA64/IA64InstrInfo.td:1.41 --- llvm/lib/Target/IA64/IA64InstrInfo.td:1.40 Thu Jan 19 09:18:56 2006 +++ llvm/lib/Target/IA64/IA64InstrInfo.td Thu Jan 19 21:40:25 2006 @@ -113,10 +113,6 @@ "adds $dst = $imm, $src1;;", [(set GR:$dst, (add GR:$src1, immSExt14:$imm))]>; -def PADDS: AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm, PR:$qp), - "($qp) adds $dst = $imm, $src1;;", - []>; - def MOVL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, s64imm:$imm), "movl $dst = $imm;;", [(set GR:$dst, imm64:$imm)]>; @@ -142,9 +138,10 @@ def TPCADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp), "($qp) add $dst = $imm, $dst;;">; -def TPCADDS : AForm<0x03, 0x0b, +def TPCADDS : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm, PR:$qp), -"($qp) adds $dst = $imm, $dst;;">; +"($qp) adds $dst = $imm, $dst;;", +[]>; def TPCMPIMM8NE : AForm<0x03, 0x0b, (ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp), "($qp) cmp.ne $dst , p0 = $imm, $src2;;">; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.24 -> 1.25
---
Log message:
oops, this shouldn't have gotten in
---
Diffs of the changes: (+0 -2)
IA64ISelDAGToDAG.cpp |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.24
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.25
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.24 Mon Jan 16 19:19:49 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Jan 16 21:09:48 2006
@@ -228,8 +228,6 @@
TmpPR = TmpF5.getValue(1);
Chain = TmpF5.getValue(2);
-Chain = CurDAG->getCopyToReg(Chain, IA64::F8, TmpF5);
-
SDOperand minusB;
if(isModulus) { // for remainders, it'll be handy to have
// copies of -input_b
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.23 -> 1.24
---
Log message:
fixing divides
---
Diffs of the changes: (+9 -12)
IA64ISelDAGToDAG.cpp | 21 +
1 files changed, 9 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.23
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.24
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.23 Mon Jan 16 08:33:04 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Jan 16 19:19:49 2006
@@ -228,6 +228,8 @@
TmpPR = TmpF5.getValue(1);
Chain = TmpF5.getValue(2);
+Chain = CurDAG->getCopyToReg(Chain, IA64::F8, TmpF5);
+
SDOperand minusB;
if(isModulus) { // for remainders, it'll be handy to have
// copies of -input_b
@@ -287,23 +289,18 @@
TmpR2 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
TmpF4, TmpQ2, TmpF3, TmpPR);
Chain = TmpR2.getValue(1);
-
+
// we want TmpQ3 to have the same target register as the frcpa? maybe we
// should two-address hack it. See the comment "for this to work..." on page
// 48 of Intel application note #245415
- TmpQ3 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
-TmpR2, TmpY2, TmpQ2, TmpPR);
+ TmpQ3 = CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
+TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR);
Chain = TmpQ3.getValue(1);
- // FIXME: this is unfortunate :(
- // the story is that the dest reg of the fnma above and the fma below it
- // (and therefore the src of the fcvt.fx[u] below as well) cannot
- // be the same register, or this code breaks if the first argument is
- // zero. (e.g. without this hack, 0%8 yields -64, not 0.)
-/* XXX: these two lines do nothing */
- SDOperand bogus = CurDAG->getTargetNode(IA64::IUSE, MVT::Other, TmpR2);
- Chain = bogus.getValue(0);
-
+ // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
+ // the FPSWA won't be able to help out in the case of large/tiny
+ // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
+
if(isSigned)
TmpQ = CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, MVT::f64, TmpQ3);
else
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.22 -> 1.23
---
Log message:
fixing divides: FP should now be 100%, and integers are fine too
unless you try to div/mod 0 by anything, in which case you will
get some cute number, and not 0, which is bad.
---
Diffs of the changes: (+24 -17)
IA64ISelDAGToDAG.cpp | 41 -
1 files changed, 24 insertions(+), 17 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.22
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.23
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.22 Mon Jan 16 00:33:38 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Jan 16 08:33:04 2006
@@ -183,6 +183,10 @@
SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
SDOperand Result;
+
+// we'll need copies of F0 and F1
+SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
+SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
// OK, emit some code:
@@ -200,12 +204,10 @@
TmpF4 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2);
Chain = TmpF4.getValue(1);
} else { // is unsigned
-if(isModulus) { /* unsigned integer divides do not need any fcvt.x*f*
insns */
- TmpF3 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
- Chain = TmpF3.getValue(1);
- TmpF4 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
- Chain = TmpF4.getValue(1);
-}
+TmpF3 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
+Chain = TmpF3.getValue(1);
+TmpF4 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
+Chain = TmpF4.getValue(1);
}
} else { // this is an FP divide/remainder, so we 'leak' some temp
@@ -226,10 +228,6 @@
TmpPR = TmpF5.getValue(1);
Chain = TmpF5.getValue(2);
-// we'll need copies of F0 and F1
-SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
-SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
-
SDOperand minusB;
if(isModulus) { // for remainders, it'll be handy to have
// copies of -input_b
@@ -276,7 +274,7 @@
// we two-address hack it. See the comment "for this to work..." on
// page 48 of Intel application note #245415
Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
-TmpY3, TmpR0, TmpQ0, TmpPR);
+TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR);
Chain = Result.getValue(1);
return Result; // XXX: early exit!
} else { // this is *not* an FP divide, so there's a bit left to do:
@@ -290,13 +288,22 @@
TmpF4, TmpQ2, TmpF3, TmpPR);
Chain = TmpR2.getValue(1);
-// we want TmpQ3 to have the same target register as the frcpa, so
-// we two-address hack it. See the comment "for this to work..." on
-// page 48 of Intel application note #245415
- TmpQ3 = CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
-TmpR2, TmpR2, TmpY2, TmpQ2, TmpPR);
+// we want TmpQ3 to have the same target register as the frcpa? maybe we
+// should two-address hack it. See the comment "for this to work..." on page
+// 48 of Intel application note #245415
+ TmpQ3 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+TmpR2, TmpY2, TmpQ2, TmpPR);
Chain = TmpQ3.getValue(1);
-
+
+ // FIXME: this is unfortunate :(
+ // the story is that the dest reg of the fnma above and the fma below it
+ // (and therefore the src of the fcvt.fx[u] below as well) cannot
+ // be the same register, or this code breaks if the first argument is
+ // zero. (e.g. without this hack, 0%8 yields -64, not 0.)
+/* XXX: these two lines do nothing */
+ SDOperand bogus = CurDAG->getTargetNode(IA64::IUSE, MVT::Other, TmpR2);
+ Chain = bogus.getValue(0);
+
if(isSigned)
TmpQ = CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, MVT::f64, TmpQ3);
else
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.21 -> 1.22
IA64InstrInfo.td updated: 1.37 -> 1.38
---
Log message:
fix division! again!! pattern isel, prepare to die.
---
Diffs of the changes: (+118 -101)
IA64ISelDAGToDAG.cpp | 198 ---
IA64InstrInfo.td | 21 +
2 files changed, 118 insertions(+), 101 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.21
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.22
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.21 Sun Jan 15 03:45:22 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Jan 16 00:33:38 2006
@@ -199,11 +199,13 @@
Chain = TmpF3.getValue(1);
TmpF4 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2);
Chain = TmpF4.getValue(1);
- } else {
-TmpF3 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
-Chain = TmpF3.getValue(1);
-TmpF4 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
-Chain = TmpF4.getValue(1);
+ } else { // is unsigned
+if(isModulus) { /* unsigned integer divides do not need any fcvt.x*f*
insns */
+ TmpF3 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
+ Chain = TmpF3.getValue(1);
+ TmpF4 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
+ Chain = TmpF4.getValue(1);
+}
}
} else { // this is an FP divide/remainder, so we 'leak' some temp
@@ -214,116 +216,110 @@
// we start by computing an approximate reciprocal (good to 9 bits?)
// note, this instruction writes _both_ TmpF5 (answer) and TmpPR
(predicate)
-TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
+if(isFP)
+ TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
TmpF3, TmpF4);
+else
+ TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
+ TmpF3, TmpF4);
+
TmpPR = TmpF5.getValue(1);
Chain = TmpF5.getValue(2);
-if(!isModulus) { // if this is a divide, we worry about div-by-zero
-SDOperand bogusPR = CurDAG->getTargetNode(IA64::CMPEQ, MVT::i1,
- CurDAG->getRegister(IA64::r0, MVT::i64),
- CurDAG->getRegister(IA64::r0, MVT::i64));
-Chain = bogusPR.getValue(1);
-TmpPR2 = CurDAG->getTargetNode(IA64::TPCMPNE, MVT::i1, bogusPR,
- CurDAG->getRegister(IA64::r0, MVT::i64),
- CurDAG->getRegister(IA64::r0, MVT::i64), TmpPR);
-Chain = TmpPR2.getValue(1);
-}
-
+// we'll need copies of F0 and F1
SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
-// now we apply newton's method, thrice! (FIXME: this is ~72 bits of
-// precision, don't need this much for f32/i32)
-TmpF6 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
- TmpF4, TmpF5, F1, TmpPR);
-Chain = TmpF6.getValue(1);
-TmpF7 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpF3, TmpF5, F0, TmpPR);
-Chain = TmpF7.getValue(1);
-TmpF8 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpF6, TmpF6, F0, TmpPR);
-Chain = TmpF8.getValue(1);
-TmpF9 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpF6, TmpF7, TmpF7, TmpPR);
-Chain = TmpF9.getValue(1);
-TmpF10 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpF6, TmpF5, TmpF5, TmpPR);
-Chain = TmpF10.getValue(1);
-TmpF11 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpF8, TmpF9, TmpF9, TmpPR);
-Chain = TmpF11.getValue(1);
-TmpF12 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpF8, TmpF10, TmpF10, TmpPR);
-Chain = TmpF12.getValue(1);
-TmpF13 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
- TmpF4, TmpF11, TmpF3, TmpPR);
-Chain = TmpF13.getValue(1);
+SDOperand minusB;
+if(isModulus) { // for remainders, it'll be handy to have
+ // copies of -input_b
+ minusB = CurDAG->getTargetNode(IA64::SUB, MVT::i64,
+ CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2);
+ Chain = minusB.getValue(1);
+}
- // FIXME: this is unfortunate :(
- // the story is that the dest reg of the fnma above and the fma below
- // (and therefore possibly the src of the fcvt.fx[u] as well) cannot
- // be the same register, or this code breaks if the first argument is
- // zero. (e.g. without this hack, 0%8 yields -64, not 0.)
-TmpF14 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
- TmpF13, TmpF12, TmpF11, TmpPR);
-Chain = TmpF14.getValue(1);
+SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
-if(isModulus) { // XXX: fragile! fixes _only_ mod, *breaks* div! !
- SDOperand bogus = CurDAG->getTargetNode(IA64::IUSE, MVT::Other, TmpF13);
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.20 -> 1.21
IA64ISelLowering.cpp updated: 1.21 -> 1.22
---
Log message:
explain that r12 is the stack pointer reg
---
Diffs of the changes: (+5 -33)
IA64ISelDAGToDAG.cpp | 34 ++
IA64ISelLowering.cpp |4 +++-
2 files changed, 5 insertions(+), 33 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.20
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.21
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.20 Fri Jan 13 04:28:25 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sun Jan 15 03:45:22 2006
@@ -450,37 +450,6 @@
case ISD::SREM:
case ISD::UREM: return SelectDIV(Op);
- case ISD::DYNAMIC_STACKALLOC: {
-if (!isa(N->getOperand(2)) ||
-cast(N->getOperand(2))->getValue() != 0) {
- std::cerr << "Cannot allocate stack object with greater alignment than"
-<< " the stack alignment yet!";
- abort();
-}
-
-SDOperand Chain = Select(N->getOperand(0));
-SDOperand Amt = Select(N->getOperand(1));
-SDOperand Reg = CurDAG->getRegister(IA64::r12, MVT::i64);
-SDOperand Val = CurDAG->getCopyFromReg(Chain, IA64::r12, MVT::i64);
-Chain = Val.getValue(1);
-
-// Subtract the amount (guaranteed to be a multiple of the stack alignment)
-// from the stack pointer, giving us the result pointer.
-SDOperand Result = Select(CurDAG->getNode(ISD::SUB, MVT::i64, Val, Amt));
-
-// Copy this result back into r12.
-Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, Reg, Result);
-
-// Copy this result back out of r12 to make sure we're not using the stack
-// space without decrementing the stack pointer.
-Result = CurDAG->getCopyFromReg(Chain, IA64::r12, MVT::i64);
-
-// Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
-CodeGenMap[Op.getValue(0)] = Result;
-CodeGenMap[Op.getValue(1)] = Result.getValue(1);
-return SDOperand(Result.Val, Op.ResNo);
- }
-
case ISD::ConstantFP: {
SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
@@ -501,7 +470,8 @@
CurDAG->getTargetFrameIndex(FI, MVT::i64));
}
- case ISD::ConstantPool: {
+ case ISD::ConstantPool: { // TODO: nuke the constant pool
+ // (ia64 doesn't need one)
Constant *C = cast(N)->get();
SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.21
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.22
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.21 Sat Jan 14 16:27:21 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Sun Jan 15 03:45:23 2006
@@ -84,9 +84,11 @@
setOperationAction(ISD::ROTR , MVT::i64 , Expand);
setOperationAction(ISD::BSWAP, MVT::i64 , Expand); // mux @rev
- // Not implemented yet.
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
+
+ setStackPointerRegisterToSaveRestore(IA64::r12);
computeRegisterProperties();
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.19 -> 1.20
---
Log message:
don't be a doofus - this fixes storing bools
---
Diffs of the changes: (+5 -2)
IA64ISelDAGToDAG.cpp |7 +--
1 files changed, 5 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.19
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.20
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.19 Wed Jan 11 13:53:22 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Fri Jan 13 04:28:25 2006
@@ -571,9 +571,12 @@
default: assert(0 && "unknown type in store");
case MVT::i1: { // this is a bool
Opc = IA64::ST1; // we store either 0 or 1 as a byte
+ // first load zero!
+ SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
+ Chain = Initial.getValue(1);
+ // then load 1 iff the predicate to store is 1
SDOperand Tmp =
- CurDAG->getTargetNode(IA64::PADDS, MVT::i64,
-CurDAG->getRegister(IA64::r0, MVT::i64),
+ CurDAG->getTargetNode(IA64::PADDS, MVT::i64, Initial,
CurDAG->getConstant(1, MVT::i64),
Select(N->getOperand(1)));
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.18 -> 1.19
---
Log message:
tblgen does this now
---
Diffs of the changes: (+0 -2)
IA64ISelDAGToDAG.cpp |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.18
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.19
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.18 Tue Jan 10 21:50:40 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Wed Jan 11 13:53:22 2006
@@ -341,8 +341,6 @@
switch (N->getOpcode()) {
default: break;
- case ISD::Register: return Op; // XXX: this is a hack, tblgen one day?
-
case IA64ISD::BRCALL: { // XXX: this is also a hack!
SDOperand Chain = Select(N->getOperand(0));
SDOperand InFlag; // Null incoming flag value.
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.17 -> 1.18
---
Log message:
cleanup GETFD
---
Diffs of the changes: (+3 -4)
IA64ISelDAGToDAG.cpp |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.17
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.18
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.17 Sun Dec 25 08:09:08 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Tue Jan 10 21:50:40 2006
@@ -411,10 +411,9 @@
case IA64ISD::GETFD: {
SDOperand Input = Select(N->getOperand(0));
-SDOperand Result = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, MVT::Flag,
Input);
-CodeGenMap[Op.getValue(0)] = Result;
-CodeGenMap[Op.getValue(1)] = Result.getValue(1);
-return Result.getValue(Op.ResNo);
+SDOperand Result = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
+CodeGenMap[Op] = Result;
+return Result;
}
case ISD::CALL:
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.16 -> 1.17 --- Log message: unbreak calls, a few more tests should run. Tomorrow: bugpoint! --- Diffs of the changes: (+1 -2) IA64ISelDAGToDAG.cpp |3 +-- 1 files changed, 1 insertion(+), 2 deletions(-) Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.16 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.17 --- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.16 Thu Dec 22 07:29:14 2005 +++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sun Dec 25 08:09:08 2005 @@ -352,7 +352,6 @@ unsigned CallOpcode; SDOperand CallOperand; -std::vector TypeOperands; // if we can call directly, do so if (GlobalAddressSDNode *GASD = @@ -395,7 +394,7 @@ // Finally, once everything is setup, emit the call itself if(InFlag.Val) - Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, Chain, InFlag); + Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, InFlag); else // there might be no arguments Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, Chain); InFlag = Chain.getValue(1); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.14 -> 1.15
---
Log message:
we can't do this directly in lowering, so we need this case
---
Diffs of the changes: (+8 -0)
IA64ISelDAGToDAG.cpp |8
1 files changed, 8 insertions(+)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.14
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.15
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.14 Wed Dec 21 21:58:17 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Thu Dec 22 01:14:45 2005
@@ -343,6 +343,14 @@
case ISD::Register: return Op; // XXX: this is a hack, tblgen one day?
+ case IA64ISD::GETFD: {
+SDOperand Input = Select(N->getOperand(0));
+SDOperand Result = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, MVT::Flag,
Input);
+CodeGenMap[Op.getValue(0)] = Result;
+CodeGenMap[Op.getValue(1)] = Result.getValue(1);
+return Result.getValue(Op.ResNo);
+ }
+
case ISD::CALL:
case ISD::TAILCALL: { {
// FIXME: This is a workaround for a bug in tblgen.
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.13 -> 1.14
---
Log message:
kill SelectCALL() in the DAG isel, we handle this in lowering now, like
SPARCv8. (we copy sparcv8's workaround for tablegen not being nice about
ISD::CALL/TAILCALL)
---
Diffs of the changes: (+47 -189)
IA64ISelDAGToDAG.cpp | 236 ++-
1 files changed, 47 insertions(+), 189 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.13
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.14
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.13 Wed Nov 30 17:02:08 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Wed Dec 21 21:58:17 2005
@@ -94,7 +94,6 @@
private:
SDOperand SelectDIV(SDOperand Op);
-SDOperand SelectCALL(SDOperand Op);
};
}
@@ -327,191 +326,6 @@
return Result;
}
-
-SDOperand IA64DAGToDAGISel::SelectCALL(SDOperand Op) {
- SDNode *N = Op.Val;
- SDOperand Chain = Select(N->getOperand(0));
-
- unsigned CallOpcode;
- std::vector CallOperands;
-
- // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
- SDOperand GPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::r1, MVT::i64);
- Chain = GPBeforeCall.getValue(1);
- SDOperand SPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::r12, MVT::i64);
- Chain = SPBeforeCall.getValue(1);
- SDOperand RPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::rp, MVT::i64);
- Chain = RPBeforeCall.getValue(1);
-
- // if we can call directly, do so
- if (GlobalAddressSDNode *GASD =
- dyn_cast(N->getOperand(1))) {
-CallOpcode = IA64::BRCALL_IPREL;
-CallOperands.push_back(CurDAG->getTargetGlobalAddress(GASD->getGlobal(),
- MVT::i64));
- } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
-// case for correctness, to avoid
-// "non-pic code with imm reloc.n
-// against dynamic symbol" errors
- dyn_cast(N->getOperand(1))) {
-CallOpcode = IA64::BRCALL_IPREL;
-CallOperands.push_back(N->getOperand(1));
- } else {
-// otherwise we need to load the function descriptor,
-// load the branch target (function)'s entry point and GP,
-// branch (call) then restore the GP
-
-SDOperand FnDescriptor = Select(N->getOperand(1));
-
-// load the branch target's entry point [mem] and
-// GP value [mem+8]
-SDOperand targetEntryPoint=CurDAG->getTargetNode(IA64::LD8, MVT::i64,
- FnDescriptor);
-Chain = targetEntryPoint.getValue(1);
-SDOperand targetGPAddr=CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
- FnDescriptor, CurDAG->getConstant(8, MVT::i64));
-Chain = targetGPAddr.getValue(1);
-SDOperand targetGP=CurDAG->getTargetNode(IA64::LD8, MVT::i64,
- targetGPAddr);
-Chain = targetGP.getValue(1);
-
-/* FIXME? (methcall still fails)
-SDOperand targetEntryPoint=CurDAG->getLoad(MVT::i64, Chain, FnDescriptor,
- CurDAG->getSrcValue(0));
-SDOperand targetGPAddr=CurDAG->getNode(ISD::ADD, MVT::i64, FnDescriptor,
- CurDAG->getConstant(8, MVT::i64));
-SDOperand targetGP=CurDAG->getLoad(MVT::i64, Chain, targetGPAddr,
- CurDAG->getSrcValue(0));
-*/
-
-/* this is just the long way of writing the two lines below?
-// Copy the callee GP into r1
-SDOperand r1 = CurDAG->getRegister(IA64::r1, MVT::i64);
-Chain = CurDAG->getNode(ISD::CopyToReg, MVT::i64, Chain, r1,
-targetGP);
-
-
-// Copy the callee address into the b6 branch register
-SDOperand B6 = CurDAG->getRegister(IA64::B6, MVT::i64);
-Chain = CurDAG->getNode(ISD::CopyToReg, MVT::i64, Chain, B6,
-targetEntryPoint);
-*/
-
-Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP);
-Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint);
-
-CallOperands.push_back(CurDAG->getRegister(IA64::B6, MVT::i64));
-CallOpcode = IA64::BRCALL_INDIRECT;
- }
-
- // see section 8.5.8 of "Itanium Software Conventions and
- // Runtime Architecture Guide to see some examples of what's going
- // on here. (in short: int args get mapped 1:1 'slot-wise' to out0->out7,
- // while FP args get mapped to F8->F15 as needed)
-
- // TODO: support in-memory arguments
-
- unsigned used_FPArgs=0; // how many FP args have been used so far?
-
- unsigned intArgs[] = {IA64::out0, IA64::out1, IA64::out2, IA64::out3,
-IA64::out4, IA64::out5, IA64::out6, IA64::out7 };
- unsigned FPArgs[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
- IA64::F12, IA64::F13, IA64::F14, IA64::F15 };
-
- SDOperand InFlag; // Null incoming f
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.12 -> 1.13
---
Log message:
Pay attn to the node returned by SelectNodeTo
---
Diffs of the changes: (+28 -37)
IA64ISelDAGToDAG.cpp | 65 +--
1 files changed, 28 insertions(+), 37 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.12
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.13
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.12 Fri Nov 25 01:49:25 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Wed Nov 30 17:02:08 2005
@@ -580,11 +580,9 @@
case ISD::FrameIndex: { // TODO: reduce creepyness
int FI = cast(N)->getIndex();
-if (N->hasOneUse()) {
- CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
- CurDAG->getTargetFrameIndex(FI, MVT::i64));
- return SDOperand(N, 0);
-}
+if (N->hasOneUse())
+ return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
+ CurDAG->getTargetFrameIndex(FI, MVT::i64));
return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
CurDAG->getTargetFrameIndex(FI, MVT::i64));
}
@@ -617,11 +615,11 @@
default: N->dump(); assert(0 && "Cannot load this type!");
case MVT::i1: { // this is a bool
Opc = IA64::LD1; // first we load a byte, then compare for != 0
- CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
- CurDAG->getTargetNode(Opc, MVT::i64, Address),
- CurDAG->getRegister(IA64::r0, MVT::i64), Chain);
- return SDOperand(N, Op.ResNo); // XXX: early exit
- }
+ return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
+ CurDAG->getTargetNode(Opc, MVT::i64,
Address),
+ CurDAG->getRegister(IA64::r0, MVT::i64),
+ Chain).getValue(Op.ResNo);
+}
case MVT::i8: Opc = IA64::LD1; break;
case MVT::i16: Opc = IA64::LD2; break;
case MVT::i32: Opc = IA64::LD4; break;
@@ -631,10 +629,9 @@
case MVT::f64: Opc = IA64::LDF8; break;
}
-CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
- Address, Chain); // TODO: comment this
-
-return SDOperand(N, Op.ResNo);
+// TODO: comment this
+return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
+Address, Chain).getValue(Op.ResNo);
}
case ISD::TRUNCSTORE:
@@ -648,14 +645,13 @@
default: assert(0 && "unknown type in store");
case MVT::i1: { // this is a bool
Opc = IA64::ST1; // we store either 0 or 1 as a byte
-CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address,
- CurDAG->getTargetNode(IA64::PADDS, MVT::i64,
- CurDAG->getRegister(IA64::r0, MVT::i64),
- CurDAG->getConstant(1, MVT::i64),
- Select(N->getOperand(1))),
- Chain);
-return SDOperand(N, 0); // XXX: early exit
-}
+SDOperand Tmp =
+ CurDAG->getTargetNode(IA64::PADDS, MVT::i64,
+CurDAG->getRegister(IA64::r0, MVT::i64),
+CurDAG->getConstant(1, MVT::i64),
+Select(N->getOperand(1)));
+return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
+ }
case MVT::i64: Opc = IA64::ST8; break;
case MVT::f64: Opc = IA64::STF8; break;
}
@@ -669,9 +665,8 @@
}
}
-CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(2)),
- Select(N->getOperand(1)), Chain);
-return SDOperand(N, 0);
+return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(2)),
+Select(N->getOperand(1)), Chain);
}
case ISD::BRCOND: {
@@ -680,8 +675,8 @@
MachineBasicBlock *Dest =
cast(N->getOperand(2))->getBasicBlock();
//FIXME - we do NOT need long branches all the time
-CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
CurDAG->getBasicBlock(Dest), Chain);
-return SDOperand(N, 0);
+return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
+CurDAG->getBasicBlock(Dest), Chain);
}
case ISD::CALLSEQ_START:
@@ -689,9 +684,8 @@
int64_t Amt = cast(N->getOperand(1))->getValue();
unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
-CurDAG->SelectNodeTo(N, Opc, MVT::Other,
- getI64Imm(Amt), Select(N->getOperand(0)));
-return SDOperand(N, 0);
+return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
+getI64Imm(Amt), Select(N->getOperand(0)));
}
case ISD::RET: {
@@ -735,20 +729,17 @@
Chain = AR_PFSVal.getValue(1);
Chain = CurDA
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.11 -> 1.12
---
Log message:
add support for dynamic_stackalloc to the dag isel (thanks andrew ;)
next up: support argument passing in memory, not just registers
---
Diffs of the changes: (+31 -3)
IA64ISelDAGToDAG.cpp | 34 +++---
1 files changed, 31 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.11
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.12
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.11 Mon Nov 21 08:14:54 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Fri Nov 25 01:49:25 2005
@@ -536,9 +536,37 @@
case ISD::SREM:
case ISD::UREM: return SelectDIV(Op);
-/* todo:
- * case ISD::DYNAMIC_STACKALLOC:
-*/
+ case ISD::DYNAMIC_STACKALLOC: {
+if (!isa(N->getOperand(2)) ||
+cast(N->getOperand(2))->getValue() != 0) {
+ std::cerr << "Cannot allocate stack object with greater alignment than"
+<< " the stack alignment yet!";
+ abort();
+}
+
+SDOperand Chain = Select(N->getOperand(0));
+SDOperand Amt = Select(N->getOperand(1));
+SDOperand Reg = CurDAG->getRegister(IA64::r12, MVT::i64);
+SDOperand Val = CurDAG->getCopyFromReg(Chain, IA64::r12, MVT::i64);
+Chain = Val.getValue(1);
+
+// Subtract the amount (guaranteed to be a multiple of the stack alignment)
+// from the stack pointer, giving us the result pointer.
+SDOperand Result = Select(CurDAG->getNode(ISD::SUB, MVT::i64, Val, Amt));
+
+// Copy this result back into r12.
+Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, Reg, Result);
+
+// Copy this result back out of r12 to make sure we're not using the stack
+// space without decrementing the stack pointer.
+Result = CurDAG->getCopyFromReg(Chain, IA64::r12, MVT::i64);
+
+// Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
+CodeGenMap[Op.getValue(0)] = Result;
+CodeGenMap[Op.getValue(1)] = Result.getValue(1);
+return SDOperand(Result.Val, Op.ResNo);
+ }
+
case ISD::ConstantFP: {
SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.10 -> 1.11
---
Log message:
add support for div/rem to the dag->dag isel. yay.
---
Diffs of the changes: (+180 -0)
IA64ISelDAGToDAG.cpp | 180 +++
1 files changed, 180 insertions(+)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.10
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.11
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.10 Sun Nov 6 21:11:03 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Nov 21 08:14:54 2005
@@ -93,6 +93,7 @@
#include "IA64GenDAGISel.inc"
private:
+SDOperand SelectDIV(SDOperand Op);
SDOperand SelectCALL(SDOperand Op);
};
}
@@ -153,6 +154,179 @@
ScheduleAndEmitDAG(DAG);
}
+SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
+ SDNode *N = Op.Val;
+ SDOperand Chain = Select(N->getOperand(0));
+
+ SDOperand Tmp1 = Select(N->getOperand(0));
+ SDOperand Tmp2 = Select(N->getOperand(1));
+
+ bool isFP=false;
+
+ if(MVT::isFloatingPoint(Tmp1.getValueType()))
+isFP=true;
+
+ bool isModulus=false; // is it a division or a modulus?
+ bool isSigned=false;
+
+ switch(N->getOpcode()) {
+case ISD::FDIV:
+case ISD::SDIV: isModulus=false; isSigned=true; break;
+case ISD::UDIV: isModulus=false; isSigned=false; break;
+case ISD::FREM:
+case ISD::SREM: isModulus=true; isSigned=true; break;
+case ISD::UREM: isModulus=true; isSigned=false; break;
+ }
+
+ // TODO: check for integer divides by powers of 2 (or other simple patterns?)
+
+SDOperand TmpPR, TmpPR2;
+SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
+SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
+SDOperand Result;
+
+// OK, emit some code:
+
+if(!isFP) {
+ // first, load the inputs into FP regs.
+ TmpF1 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1);
+ Chain = TmpF1.getValue(1);
+ TmpF2 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2);
+ Chain = TmpF2.getValue(1);
+
+ // next, convert the inputs to FP
+ if(isSigned) {
+TmpF3 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1);
+Chain = TmpF3.getValue(1);
+TmpF4 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2);
+Chain = TmpF4.getValue(1);
+ } else {
+TmpF3 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
+Chain = TmpF3.getValue(1);
+TmpF4 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
+Chain = TmpF4.getValue(1);
+ }
+
+} else { // this is an FP divide/remainder, so we 'leak' some temp
+ // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
+ TmpF3=Tmp1;
+ TmpF4=Tmp2;
+}
+
+// we start by computing an approximate reciprocal (good to 9 bits?)
+// note, this instruction writes _both_ TmpF5 (answer) and TmpPR
(predicate)
+TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
+ TmpF3, TmpF4);
+TmpPR = TmpF5.getValue(1);
+Chain = TmpF5.getValue(2);
+
+if(!isModulus) { // if this is a divide, we worry about div-by-zero
+SDOperand bogusPR = CurDAG->getTargetNode(IA64::CMPEQ, MVT::i1,
+ CurDAG->getRegister(IA64::r0, MVT::i64),
+ CurDAG->getRegister(IA64::r0, MVT::i64));
+Chain = bogusPR.getValue(1);
+TmpPR2 = CurDAG->getTargetNode(IA64::TPCMPNE, MVT::i1, bogusPR,
+ CurDAG->getRegister(IA64::r0, MVT::i64),
+ CurDAG->getRegister(IA64::r0, MVT::i64), TmpPR);
+Chain = TmpPR2.getValue(1);
+}
+
+SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
+SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
+
+// now we apply newton's method, thrice! (FIXME: this is ~72 bits of
+// precision, don't need this much for f32/i32)
+TmpF6 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
+ TmpF4, TmpF5, F1, TmpPR);
+Chain = TmpF6.getValue(1);
+TmpF7 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpF3, TmpF5, F0, TmpPR);
+Chain = TmpF7.getValue(1);
+TmpF8 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpF6, TmpF6, F0, TmpPR);
+Chain = TmpF8.getValue(1);
+TmpF9 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpF6, TmpF7, TmpF7, TmpPR);
+Chain = TmpF9.getValue(1);
+TmpF10 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpF6, TmpF5, TmpF5, TmpPR);
+Chain = TmpF10.getValue(1);
+TmpF11 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpF8, TmpF9, TmpF9, TmpPR);
+Chain = TmpF11.getValue(1);
+TmpF12 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpF8, TmpF10, TmpF10, TmpPR);
+Chain = TmpF12.getValue(1);
+TmpF13 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
+ TmpF4, TmpF11, TmpF3, TmpPR);
+Chain = TmpF13.getValue(1);
+
+ // FIXME
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.9 -> 1.10
---
Log message:
add support for storing and returning bools
---
Diffs of the changes: (+26 -5)
IA64ISelDAGToDAG.cpp | 31 ++-
1 files changed, 26 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.9
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.10
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.9 Sun Nov 6 07:43:30 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sun Nov 6 21:11:03 2005
@@ -301,6 +301,16 @@
switch (N->getValueType(0)) {
default: assert(0 && "Unexpected ret value!");
case MVT::Other: break;
+case MVT::i1: {
+// bools are returned as bytes 0/1 in r8
+ SDOperand byteval = CurDAG->getCopyFromReg(Chain, IA64::r8, MVT::i64,
+ Chain.getValue(1));
+Chain = byteval.getValue(1);
+ Chain = CurDAG->getTargetNode(IA64::CMPNE, MVT::i1, MVT::Other,
+ byteval, CurDAG->getRegister(IA64::r0, MVT::i64)).getValue(1);
+ CallResults.push_back(Chain.getValue(0));
+ break;
+ }
case MVT::i64:
Chain = CurDAG->getCopyFromReg(Chain, IA64::r8, MVT::i64,
Chain.getValue(1)).getValue(1);
@@ -422,17 +432,28 @@
case ISD::TRUNCSTORE:
case ISD::STORE: {
SDOperand Address = Select(N->getOperand(2));
-
+SDOperand Chain = Select(N->getOperand(0));
+
unsigned Opc;
if (N->getOpcode() == ISD::STORE) {
switch (N->getOperand(1).getValueType()) {
- default: assert(0 && "unknown Type in store");
+ default: assert(0 && "unknown type in store");
+ case MVT::i1: { // this is a bool
+Opc = IA64::ST1; // we store either 0 or 1 as a byte
+CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address,
+ CurDAG->getTargetNode(IA64::PADDS, MVT::i64,
+ CurDAG->getRegister(IA64::r0, MVT::i64),
+ CurDAG->getConstant(1, MVT::i64),
+ Select(N->getOperand(1))),
+ Chain);
+return SDOperand(N, 0); // XXX: early exit
+}
case MVT::i64: Opc = IA64::ST8; break;
case MVT::f64: Opc = IA64::STF8; break;
- }
+ }
} else { //ISD::TRUNCSTORE
switch(cast(N->getOperand(4))->getVT()) {
- default: assert(0 && "unknown Type in store");
+ default: assert(0 && "unknown type in truncstore");
case MVT::i8: Opc = IA64::ST1; break;
case MVT::i16: Opc = IA64::ST2; break;
case MVT::i32: Opc = IA64::ST4; break;
@@ -441,7 +462,7 @@
}
CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(2)),
- Select(N->getOperand(1)), Select(N->getOperand(0)));
+ Select(N->getOperand(1)), Chain);
return SDOperand(N, 0);
}
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.8 -> 1.9
---
Log message:
just some random hacking - calls (particularly indirect) need a lot of
love (especially with -sched=simple)
---
Diffs of the changes: (+25 -14)
IA64ISelDAGToDAG.cpp | 39 +--
1 files changed, 25 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.8
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.9
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.8 Fri Nov 4 11:55:53 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sun Nov 6 07:43:30 2005
@@ -201,7 +201,7 @@
targetGPAddr);
Chain = targetGP.getValue(1);
-/* FIXME! (methcall still fails)
+/* FIXME? (methcall still fails)
SDOperand targetEntryPoint=CurDAG->getLoad(MVT::i64, Chain, FnDescriptor,
CurDAG->getSrcValue(0));
SDOperand targetGPAddr=CurDAG->getNode(ISD::ADD, MVT::i64, FnDescriptor,
@@ -209,7 +209,8 @@
SDOperand targetGP=CurDAG->getLoad(MVT::i64, Chain, targetGPAddr,
CurDAG->getSrcValue(0));
*/
-
+
+/* this is just the long way of writing the two lines below?
// Copy the callee GP into r1
SDOperand r1 = CurDAG->getRegister(IA64::r1, MVT::i64);
Chain = CurDAG->getNode(ISD::CopyToReg, MVT::i64, Chain, r1,
@@ -220,8 +221,12 @@
SDOperand B6 = CurDAG->getRegister(IA64::B6, MVT::i64);
Chain = CurDAG->getNode(ISD::CopyToReg, MVT::i64, Chain, B6,
targetEntryPoint);
+*/
+
+Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP);
+Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint);
-CallOperands.push_back(B6);
+CallOperands.push_back(CurDAG->getRegister(IA64::B6, MVT::i64));
CallOpcode = IA64::BRCALL_INDIRECT;
}
@@ -256,18 +261,23 @@
if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
SDOperand Val = Select(N->getOperand(i));
- Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
- InFlag = Chain.getValue(1);
- CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
+ if(MVT::isInteger(N->getOperand(i).getValueType())) {
+Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
+InFlag = Chain.getValue(1);
+CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
+ }
// some functions (e.g. printf) want floating point arguments
// *also* passed as in-memory representations in integer registers
// this is FORTRAN legacy junk which we don't _always_ need
// to do, but to be on the safe side, we do.
- if(MVT::isFloatingPoint(N->getOperand(i).getValueType())) {
+ else if(MVT::isFloatingPoint(N->getOperand(i).getValueType())) {
assert((i-2) < 8 && "FP args alone would fit, but no int regs left");
- DestReg = intArgs[i-2]; // this FP arg goes in an int reg
+ // first copy into the appropriate FP reg
+Chain = CurDAG->getCopyToReg(Chain, DestReg, Val);
+ // then copy into the appropriate integer reg
+ DestReg = intArgs[i-2];
// GETFD takes an FP reg and writes a GP reg
- Chain = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Val, InFlag);
+ Chain = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Val);
// FIXME: this next line is a bit unfortunate
Chain = CurDAG->getCopyToReg(Chain, DestReg, Chain, InFlag);
InFlag = Chain.getValue(1);
@@ -285,8 +295,6 @@
Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
CallOperands);
-// return Chain; // HACK: err, this means that functions never return
anything. need to intergrate this with the code immediately below FIXME XXX
-
std::vector CallResults;
// If the call has results, copy the values out of the ret val registers.
@@ -304,12 +312,15 @@
CallResults.push_back(Chain.getValue(0));
break;
}
- // restore GP, SP and RP
+
+ // restore GP, SP and RP - FIXME: this doesn't quite work (e.g.
+ // methcall / objinst both segfault on exit) and it *really*
+ // doesn't work unless you have -sched=none
Chain = CurDAG->getCopyToReg(Chain, IA64::r1, GPBeforeCall);
Chain = CurDAG->getCopyToReg(Chain, IA64::r12, SPBeforeCall);
Chain = CurDAG->getCopyToReg(Chain, IA64::rp, RPBeforeCall);
-
- CallResults.push_back(Chain);
+ CallResults.push_back(Chain); // llc segfaults w/o this,
+ // ary3(e.g.) SIGILLs with 3
for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
CodeGenMap[Op.getValue(i)] = CallResults[i];
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.7 -> 1.8
---
Log message:
oops, forgot to load GP for indirect calls, though the old code now commented
out failed (e.g. methcall) - now the code compiles, though it's not quite
right just yet (tm) ;)
would fix this but it's 3am! :O
---
Diffs of the changes: (+21 -4)
IA64ISelDAGToDAG.cpp | 25 +
1 files changed, 21 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.7
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.8
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.7 Fri Nov 4 03:59:06 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Fri Nov 4 11:55:53 2005
@@ -185,23 +185,40 @@
} else {
// otherwise we need to load the function descriptor,
// load the branch target (function)'s entry point and GP,
-// branch (call) then restore the
-// GP
+// branch (call) then restore the GP
SDOperand FnDescriptor = Select(N->getOperand(1));
// load the branch target's entry point [mem] and
// GP value [mem+8]
+SDOperand targetEntryPoint=CurDAG->getTargetNode(IA64::LD8, MVT::i64,
+ FnDescriptor);
+Chain = targetEntryPoint.getValue(1);
+SDOperand targetGPAddr=CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
+ FnDescriptor, CurDAG->getConstant(8, MVT::i64));
+Chain = targetGPAddr.getValue(1);
+SDOperand targetGP=CurDAG->getTargetNode(IA64::LD8, MVT::i64,
+ targetGPAddr);
+Chain = targetGP.getValue(1);
+
+/* FIXME! (methcall still fails)
SDOperand targetEntryPoint=CurDAG->getLoad(MVT::i64, Chain, FnDescriptor,
CurDAG->getSrcValue(0));
SDOperand targetGPAddr=CurDAG->getNode(ISD::ADD, MVT::i64, FnDescriptor,
CurDAG->getConstant(8, MVT::i64));
SDOperand targetGP=CurDAG->getLoad(MVT::i64, Chain, targetGPAddr,
- CurDAG->getSrcValue(0));
+ CurDAG->getSrcValue(0));
+*/
+
+// Copy the callee GP into r1
+SDOperand r1 = CurDAG->getRegister(IA64::r1, MVT::i64);
+Chain = CurDAG->getNode(ISD::CopyToReg, MVT::i64, Chain, r1,
+targetGP);
+
// Copy the callee address into the b6 branch register
SDOperand B6 = CurDAG->getRegister(IA64::B6, MVT::i64);
-Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, B6,
+Chain = CurDAG->getNode(ISD::CopyToReg, MVT::i64, Chain, B6,
targetEntryPoint);
CallOperands.push_back(B6);
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.6 -> 1.7
---
Log message:
add support for loading bools
---
Diffs of the changes: (+7 -1)
IA64ISelDAGToDAG.cpp |8 +++-
1 files changed, 7 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.6
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.7
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.6 Wed Nov 2 01:32:59 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Fri Nov 4 03:59:06 2005
@@ -369,7 +369,13 @@
unsigned Opc;
switch (TypeBeingLoaded) {
default: N->dump(); assert(0 && "Cannot load this type!");
-// FIXME: bools? case MVT::i1:
+case MVT::i1: { // this is a bool
+ Opc = IA64::LD1; // first we load a byte, then compare for != 0
+ CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
+ CurDAG->getTargetNode(Opc, MVT::i64, Address),
+ CurDAG->getRegister(IA64::r0, MVT::i64), Chain);
+ return SDOperand(N, Op.ResNo); // XXX: early exit
+ }
case MVT::i8: Opc = IA64::LD1; break;
case MVT::i16: Opc = IA64::LD2; break;
case MVT::i32: Opc = IA64::LD4; break;
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.5 -> 1.6
---
Log message:
"fix" support for FP constants (this code asserts in the scheduler,
though)
---
Diffs of the changes: (+4 -2)
IA64ISelDAGToDAG.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.5
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.6
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.5 Tue Nov 1 20:35:04 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Wed Nov 2 01:32:59 2005
@@ -322,10 +322,12 @@
* case ISD::DYNAMIC_STACKALLOC:
*/
case ISD::ConstantFP: {
+SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
+
if (cast(N)->isExactlyValue(+0.0))
- return CurDAG->getRegister(IA64::F0, MVT::f64); // load 0.0
+ return CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
else if (cast(N)->isExactlyValue(+1.0))
- return CurDAG->getRegister(IA64::F1, MVT::f64); // load 1.0
+ return CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
else
assert(0 && "Unexpected FP constant!");
}
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.4 -> 1.5
IA64ISelLowering.cpp updated: 1.1 -> 1.2
---
Log message:
add support for loading FP constants +0.0 and +1.0 to the dag isel,
stop pretending -0.0 and -1.0 are machine constants
---
Diffs of the changes: (+8 -3)
IA64ISelDAGToDAG.cpp |8
IA64ISelLowering.cpp |3 ---
2 files changed, 8 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.4
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.5
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.4 Mon Oct 31 23:46:16 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Tue Nov 1 20:35:04 2005
@@ -321,6 +321,14 @@
/* todo:
* case ISD::DYNAMIC_STACKALLOC:
*/
+ case ISD::ConstantFP: {
+if (cast(N)->isExactlyValue(+0.0))
+ return CurDAG->getRegister(IA64::F0, MVT::f64); // load 0.0
+else if (cast(N)->isExactlyValue(+1.0))
+ return CurDAG->getRegister(IA64::F1, MVT::f64); // load 1.0
+else
+ assert(0 && "Unexpected FP constant!");
+ }
case ISD::FrameIndex: { // TODO: reduce creepyness
int FI = cast(N)->getIndex();
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.1
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.2
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.1 Fri Oct 28 12:46:36 2005
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Tue Nov 1 20:35:04 2005
@@ -80,9 +80,6 @@
addLegalFPImmediate(+0.0);
addLegalFPImmediate(+1.0);
- addLegalFPImmediate(-0.0);
- addLegalFPImmediate(-1.0);
-
}
/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.3 -> 1.4
---
Log message:
FORTRAN!!! :( and other similarly unfortunate things mean that on ia64
one sometimes needs to pass FP args in both FP *and* integer registers.
---
Diffs of the changes: (+20 -0)
IA64ISelDAGToDAG.cpp | 20
1 files changed, 20 insertions(+)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.3
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.4
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.3 Sat Oct 29 11:08:30 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Oct 31 23:46:16 2005
@@ -208,7 +208,13 @@
CallOpcode = IA64::BRCALL_INDIRECT;
}
+ // see section 8.5.8 of "Itanium Software Conventions and
+ // Runtime Architecture Guide to see some examples of what's going
+ // on here. (in short: int args get mapped 1:1 'slot-wise' to out0->out7,
+ // while FP args get mapped to F8->F15 as needed)
+
// TODO: support in-memory arguments
+
unsigned used_FPArgs=0; // how many FP args have been used so far?
unsigned intArgs[] = {IA64::out0, IA64::out1, IA64::out2, IA64::out3,
@@ -236,6 +242,20 @@
Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
InFlag = Chain.getValue(1);
CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
+ // some functions (e.g. printf) want floating point arguments
+ // *also* passed as in-memory representations in integer registers
+ // this is FORTRAN legacy junk which we don't _always_ need
+ // to do, but to be on the safe side, we do.
+ if(MVT::isFloatingPoint(N->getOperand(i).getValueType())) {
+assert((i-2) < 8 && "FP args alone would fit, but no int regs left");
+ DestReg = intArgs[i-2]; // this FP arg goes in an int reg
+// GETFD takes an FP reg and writes a GP reg
+ Chain = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Val, InFlag);
+// FIXME: this next line is a bit unfortunate
+ Chain = CurDAG->getCopyToReg(Chain, DestReg, Chain, InFlag);
+InFlag = Chain.getValue(1);
+CallOperands.push_back(CurDAG->getRegister(DestReg, MVT::i64));
+ }
}
}
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.2 -> 1.3
IA64InstrInfo.td updated: 1.17 -> 1.18
---
Log message:
add some FP stuff, some mix.* stuff, and constant pool support to the
DAG instruction selector, which should be destroyed one day (in the pattern
isel also) since ia64 can pack any constant in the instruction stream
---
Diffs of the changes: (+131 -61)
IA64ISelDAGToDAG.cpp |7 +
IA64InstrInfo.td | 185 ++-
2 files changed, 131 insertions(+), 61 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.2
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.3
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.2 Fri Oct 28 13:26:52 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sat Oct 29 11:08:30 2005
@@ -313,6 +313,13 @@
CurDAG->getTargetFrameIndex(FI, MVT::i64));
}
+ case ISD::ConstantPool: {
+Constant *C = cast(N)->get();
+SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
+return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
+ CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
+ }
+
case ISD::GlobalAddress: {
GlobalValue *GV = cast(N)->getGlobal();
SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.17
llvm/lib/Target/IA64/IA64InstrInfo.td:1.18
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.17 Fri Oct 28 23:13:40 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Sat Oct 29 11:08:30 2005
@@ -45,10 +45,33 @@
def is32ones : PatLeaf<(i64 imm), [{
// is32ones predicate - True if the immediate is 0x
// Used to create ZXT4s appropriately
- int64_t v = (int64_t)N->getValue();
+ uint64_t v = (uint64_t)N->getValue();
return (v == 0xLL);
}]>;
+// isMIXable predicates - True if the immediate is
+// 0xFF00FF00FF00FF00, 0x00FF00FF00FF00FF
+// etc, through 0x
+// Used to test for the suitability of mix*
+def isMIX1Lable: PatLeaf<(i64 imm), [{
+ return((uint64_t)N->getValue()==0xFF00FF00FF00FF00LL);
+}]>;
+def isMIX1Rable: PatLeaf<(i64 imm), [{
+ return((uint64_t)N->getValue()==0x00FF00FF00FF00FFLL);
+}]>;
+def isMIX2Lable: PatLeaf<(i64 imm), [{
+ return((uint64_t)N->getValue()==0xLL);
+}]>;
+def isMIX2Rable: PatLeaf<(i64 imm), [{
+ return((uint64_t)N->getValue()==0xLL);
+}]>;
+def isMIX4Lable: PatLeaf<(i64 imm), [{
+ return((uint64_t)N->getValue()==0xLL);
+}]>;
+def isMIX4Rable: PatLeaf<(i64 imm), [{
+ return((uint64_t)N->getValue()==0xLL);
+}]>;
+
def isSHLADDimm: PatLeaf<(i64 imm), [{
// isSHLADDimm predicate - True if the immediate is exactly 1, 2, 3 or 4
// - 0 is *not* okay.
@@ -83,6 +106,37 @@
def ZXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src;;",
[(set GR:$dst, (and GR:$src, is32ones))]>;
+// fixme: shrs vs shru?
+def MIX1L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ "mix1.l $dst = $src1, $src2;;",
+ [(set GR:$dst, (or (and GR:$src1, isMIX1Lable),
+(and (srl GR:$src2, 8), isMIX1Lable)))]>;
+
+def MIX2L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ "mix2.l $dst = $src1, $src2;;",
+ [(set GR:$dst, (or (and GR:$src1, isMIX2Lable),
+(and (srl GR:$src2, 16), isMIX2Lable)))]>;
+
+def MIX4L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ "mix4.l $dst = $src1, $src2;;",
+ [(set GR:$dst, (or (and GR:$src1, isMIX4Lable),
+(and (srl GR:$src2, 32), isMIX4Lable)))]>;
+
+def MIX1R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ "mix1.r $dst = $src1, $src2;;",
+ [(set GR:$dst, (or (and (shl GR:$src1, 8), isMIX1Rable),
+(and GR:$src2, isMIX1Rable)))]>;
+
+def MIX2R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ "mix2.r $dst = $src1, $src2;;",
+ [(set GR:$dst, (or (and (shl GR:$src1, 16), isMIX2Rable),
+(and GR:$src2, isMIX2Rable)))]>;
+
+def MIX4R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ "mix4.r $dst = $src1, $src2;;",
+ [(set GR:$dst, (or (and (shl GR:$src1, 32), isMIX4Rable),
+(and GR:$src2, isMIX4Rable)))]>;
+
def ADD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
"add $dst = $src1, $src2;;",
[(set GR:$dst, (add GR:$src1, GR:$src2))]>;
@@ -122,10 +176,20 @@
def XMALD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
"xma.l $dst = $src1, $src2, $src3;;",
[]>;
+def XMAHD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
+ "xma.h $dst = $src1, $s
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.1 -> 1.2
---
Log message:
These are autogenerated
---
Diffs of the changes: (+0 -33)
IA64ISelDAGToDAG.cpp | 33 -
1 files changed, 33 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.1
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.2
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.1 Fri Oct 28 12:46:36 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Fri Oct 28 13:26:52 2005
@@ -313,39 +313,6 @@
CurDAG->getTargetFrameIndex(FI, MVT::i64));
}
- case ISD::TokenFactor: {
-SDOperand New;
-if (N->getNumOperands() == 2) {
- SDOperand Op0 = Select(N->getOperand(0));
- SDOperand Op1 = Select(N->getOperand(1));
- New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
-} else {
- std::vector Ops;
- for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-Ops.push_back(Select(N->getOperand(i)));
- New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
-}
-
-CodeGenMap[Op] = New;
-return New;
- }
- case ISD::CopyFromReg: {
-SDOperand Chain = Select(N->getOperand(0));
-if (Chain == N->getOperand(0)) return Op; // No change
-SDOperand New = CurDAG->getCopyFromReg(Chain,
- cast(N->getOperand(1))->getReg(), N->getValueType(0));
-return New.getValue(Op.ResNo);
- }
- case ISD::CopyToReg: {
-SDOperand Chain = Select(N->getOperand(0));
-SDOperand Reg = N->getOperand(1);
-SDOperand Val = Select(N->getOperand(2));
-SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
-Chain, Reg, Val);
-CodeGenMap[Op] = New;
-return New;
- }
-
case ISD::GlobalAddress: {
GlobalValue *GV = cast(N)->getGlobal();
SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
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