[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstr64Bit.td updated: 1.44 - 1.45 --- Log message: add support for 128-bit add/sub on ppc64 --- Diffs of the changes: (+34 -0) PPCInstr64Bit.td | 34 ++ 1 files changed, 34 insertions(+) Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.44 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.45 --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.44 Tue Apr 3 07:35:28 2007 +++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdThu May 17 01:52:46 2007 @@ -212,6 +212,15 @@ def ADD8 : XOForm_131, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), add $rT, $rA, $rB, IntGeneral, [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]; + +def ADDC8 : XOForm_131, 10, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), + addc $rT, $rA, $rB, IntGeneral, + [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))], + PPC970_DGroup_Cracked; +def ADDE8 : XOForm_131, 138, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), + adde $rT, $rA, $rB, IntGeneral, + [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]; + def ADDI8 : DForm_214, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm), addi $rD, $rA, $imm, IntGeneral, [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]; @@ -226,6 +235,31 @@ subf $rT, $rA, $rB, IntGeneral, [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]; +def SUBFC8 : XOForm_131, 8, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), + subfc $rT, $rA, $rB, IntGeneral, + [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))], + PPC970_DGroup_Cracked; + +def SUBFE8 : XOForm_131, 136, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), + subfe $rT, $rA, $rB, IntGeneral, + [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]; +def ADDME8 : XOForm_331, 234, 0, (ops G8RC:$rT, G8RC:$rA), + addme $rT, $rA, IntGeneral, + [(set G8RC:$rT, (adde G8RC:$rA, immAllOnes))]; +def ADDZE8 : XOForm_331, 202, 0, (ops G8RC:$rT, G8RC:$rA), + addze $rT, $rA, IntGeneral, + [(set G8RC:$rT, (adde G8RC:$rA, 0))]; +def NEG8: XOForm_331, 104, 0, (ops G8RC:$rT, G8RC:$rA), + neg $rT, $rA, IntGeneral, + [(set G8RC:$rT, (ineg G8RC:$rA))]; +def SUBFME8 : XOForm_331, 232, 0, (ops G8RC:$rT, G8RC:$rA), + subfme $rT, $rA, IntGeneral, + [(set G8RC:$rT, (sube immAllOnes, G8RC:$rA))]; +def SUBFZE8 : XOForm_331, 200, 0, (ops G8RC:$rT, G8RC:$rA), + subfze $rT, $rA, IntGeneral, + [(set G8RC:$rT, (sube 0, G8RC:$rA))]; + + def MULHD : XOForm_131, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), mulhd $rT, $rA, $rB, IntMulHW, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstr64Bit.td updated: 1.41 - 1.42 --- Log message: Fix CodeGen/PowerPC/2007-03-24-cntlzd.ll --- Diffs of the changes: (+4 -1) PPCInstr64Bit.td |5 - 1 files changed, 4 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.41 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.42 --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.41 Tue Feb 27 07:01:19 2007 +++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdSat Mar 24 23:44:03 2007 @@ -273,7 +273,10 @@ def SRADI : XSForm_131, 413, (ops G8RC:$rA, G8RC:$rS, u6imm:$SH), sradi $rA, $rS, $SH, IntRotateD, [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))], isPPC64; - +def CNTLZD : XForm_1131, 58, (ops G8RC:$rA, G8RC:$rS), + cntlzd $rA, $rS, IntGeneral, + [(set G8RC:$rA, (ctlz G8RC:$rS))]; + def DIVD : XOForm_131, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), divd $rT, $rA, $rB, IntDivD, [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))], isPPC64, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstr64Bit.td updated: 1.39 - 1.40 PPCInstrInfo.td updated: 1.273 - 1.274 --- Log message: one important bugfix: PPC32 didn't have both elf and macho support for external symbols and global addresses. Add the missing ones. one important workaround: PPCISD::CALL is matched by both PPCcall_ELF and PPCcall_Macho, disable the _ELF patterns for now. --- Diffs of the changes: (+10 -6) PPCInstr64Bit.td |6 +++--- PPCInstrInfo.td | 10 +++--- 2 files changed, 10 insertions(+), 6 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.39 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.40 --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.39 Sat Feb 24 23:34:32 2007 +++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdSun Feb 25 13:20:53 2007 @@ -102,7 +102,7 @@ def BLA8_ELF : IForm18, 1, 1, (ops aaddr:$func, variable_ops), - bla $func, BrB, [(PPCcall_ELF (i64 imm:$func))]; + bla $func, BrB, [/*(PPCcall_ELF (i64 imm:$func))*/]; } @@ -111,12 +111,12 @@ (BL8_Macho tglobaladdr:$dst); def : Pat(PPCcall_Macho (i64 texternalsym:$dst)), (BL8_Macho texternalsym:$dst); - +/* def : Pat(PPCcall_ELF (i64 tglobaladdr:$dst)), (BL8_ELF tglobaladdr:$dst); def : Pat(PPCcall_ELF (i64 texternalsym:$dst)), (BL8_ELF texternalsym:$dst); - +*/ //===--===// // 64-bit SPR manipulation instrs. Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.273 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.274 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.273 Sat Feb 24 23:34:32 2007 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Sun Feb 25 13:20:53 2007 @@ -407,11 +407,11 @@ def BLA_ELF : IForm18, 1, 1, (ops aaddr:$func, variable_ops), bla $func, BrB, - [(PPCcall_ELF (i32 imm:$func))]; + [/*(PPCcall_ELF (i32 imm:$func))*/]; def BCTRL_ELF : XLForm_2_ext19, 528, 20, 0, 1, (ops variable_ops), bctrl, BrB, - [(PPCbctrl_ELF)]; + [/*(PPCbctrl_ELF)*/]; } // DCB* instructions. @@ -1102,8 +1102,12 @@ // Calls def : Pat(PPCcall_Macho (i32 tglobaladdr:$dst)), (BL_Macho tglobaladdr:$dst); +def : Pat(PPCcall_Macho (i32 texternalsym:$dst)), + (BL_Macho texternalsym:$dst); +/*def : Pat(PPCcall_ELF (i32 tglobaladdr:$dst)), + (BL_ELF tglobaladdr:$dst); def : Pat(PPCcall_ELF (i32 texternalsym:$dst)), - (BL_ELF texternalsym:$dst); + (BL_ELF texternalsym:$dst);*/ // Hi and Lo for Darwin Global Addresses. def : Pat(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstr64Bit.td updated: 1.34 - 1.35 --- Log message: Provide 64-bit support for i64 sextloadi8. --- Diffs of the changes: (+4 -0) PPCInstr64Bit.td |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.34 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.35 --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.34 Tue Dec 12 07:23:43 2006 +++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdFri Dec 15 08:34:11 2006 @@ -491,6 +491,10 @@ (LBZ8 iaddr:$src); def : Pat(extloadi1 xaddr:$src), (LBZX8 xaddr:$src); +def : Pat(sextloadi8 iaddr:$src), + (EXTSB8 (LBZ8 iaddr:$src)); +def : Pat(sextloadi8 xaddr:$src), + (EXTSB8 (LBZX8 xaddr:$src)); def : Pat(extloadi8 iaddr:$src), (LBZ8 iaddr:$src); def : Pat(extloadi8 xaddr:$src), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstr64Bit.td updated: 1.36 - 1.37 --- Log message: Not all test cases are created equal. This fix is needed. --- Diffs of the changes: (+4 -0) PPCInstr64Bit.td |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.36 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.37 --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.36 Fri Dec 15 12:45:32 2006 +++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdFri Dec 15 12:51:01 2006 @@ -491,6 +491,10 @@ (LBZ8 iaddr:$src); def : Pat(extloadi1 xaddr:$src), (LBZX8 xaddr:$src); +def : Pat(sextloadi8 iaddr:$src), + (EXTSB8 (LBZ8 iaddr:$src)); +def : Pat(sextloadi8 xaddr:$src), + (EXTSB8 (LBZX8 xaddr:$src)); def : Pat(extloadi8 iaddr:$src), (LBZ8 iaddr:$src); def : Pat(extloadi8 xaddr:$src), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstr64Bit.td updated: 1.35 - 1.36 --- Log message: Not needed. Misinterpreted error message from other bug (Missing load/store relocations.) --- Diffs of the changes: (+0 -4) PPCInstr64Bit.td |4 1 files changed, 4 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.35 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.36 --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.35 Fri Dec 15 08:34:11 2006 +++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdFri Dec 15 12:45:32 2006 @@ -491,10 +491,6 @@ (LBZ8 iaddr:$src); def : Pat(extloadi1 xaddr:$src), (LBZX8 xaddr:$src); -def : Pat(sextloadi8 iaddr:$src), - (EXTSB8 (LBZ8 iaddr:$src)); -def : Pat(sextloadi8 xaddr:$src), - (EXTSB8 (LBZX8 xaddr:$src)); def : Pat(extloadi8 iaddr:$src), (LBZ8 iaddr:$src); def : Pat(extloadi8 xaddr:$src), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstr64Bit.td updated: 1.37 - 1.38 --- Log message: Patterns no longer needed due to fix in the DAG combiner. --- Diffs of the changes: (+0 -4) PPCInstr64Bit.td |4 1 files changed, 4 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.37 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.38 --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.37 Fri Dec 15 12:51:01 2006 +++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdFri Dec 15 15:39:31 2006 @@ -491,10 +491,6 @@ (LBZ8 iaddr:$src); def : Pat(extloadi1 xaddr:$src), (LBZX8 xaddr:$src); -def : Pat(sextloadi8 iaddr:$src), - (EXTSB8 (LBZ8 iaddr:$src)); -def : Pat(sextloadi8 xaddr:$src), - (EXTSB8 (LBZX8 xaddr:$src)); def : Pat(extloadi8 iaddr:$src), (LBZ8 iaddr:$src); def : Pat(extloadi8 xaddr:$src), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstr64Bit.td updated: 1.32 - 1.33 --- Log message: implement sextinreg i8-i64 and i16-i64 --- Diffs of the changes: (+8 -0) PPCInstr64Bit.td |8 1 files changed, 8 insertions(+) Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.32 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.33 --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.32 Thu Nov 16 16:43:37 2006 +++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdWed Dec 6 15:46:13 2006 @@ -224,6 +224,14 @@ def SRAD : XForm_631, 794, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB), srad $rA, $rS, $rB, IntRotateD, [(set G8RC:$rA, (sra G8RC:$rS, GPRC:$rB))], isPPC64; + +def EXTSB8 : XForm_1131, 954, (ops G8RC:$rA, G8RC:$rS), + extsb $rA, $rS, IntGeneral, + [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]; +def EXTSH8 : XForm_1131, 922, (ops G8RC:$rA, G8RC:$rS), + extsh $rA, $rS, IntGeneral, + [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]; + def EXTSW : XForm_1131, 986, (ops G8RC:$rA, G8RC:$rS), extsw $rA, $rS, IntGeneral, [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))], isPPC64; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCInstr64Bit.td updated: 1.24 - 1.25
PPCRegisterInfo.cpp updated: 1.78 - 1.79
---
Log message:
implement proper PPC64 prolog/epilog codegen.
---
Diffs of the changes: (+81 -30)
PPCInstr64Bit.td|5 ++
PPCRegisterInfo.cpp | 106 +---
2 files changed, 81 insertions(+), 30 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.24
llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.25
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.24 Fri Nov 10 22:51:36 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdSat Nov 11 13:05:28 2006
@@ -322,6 +322,10 @@
stdx $rS, $dst, LdStSTD,
[(store G8RC:$rS, xaddr:$dst)], isPPC64,
PPC970_DGroup_Cracked;
+
+def STDU : DSForm_162, 1, (ops G8RC:$rS, memrix:$dst),
+stdu $rS, $dst, LdStSTD,
+[], isPPC64;
def STDUX : XForm_831, 181, (ops G8RC:$rS, memrr:$dst),
stdux $rS, $dst, LdStSTD,
[], isPPC64;
@@ -335,6 +339,7 @@
[(PPCstd_32 GPRC:$rT, xaddr:$dst)], isPPC64,
PPC970_DGroup_Cracked;
+
// Truncating stores.
def STB8 : DForm_338, (ops G8RC:$rS, memri:$src),
stb $rS, $src, LdStGeneral,
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.78
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.79
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.78Sat Nov 11 04:21:58 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Sat Nov 11 13:05:28 2006
@@ -636,7 +636,7 @@
// Add the size of R1 to NumBytes size for the store of R1 to the bottom
// of the stack and round the size to a multiple of the alignment.
unsigned Align = std::max(TargetAlign, MaxAlign);
- unsigned GPRSize = 4;
+ unsigned GPRSize = Subtarget.isPPC64() ? 8 : 4;
unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize;
NumBytes = (NumBytes+Size+Align-1)/Align*Align;
@@ -646,24 +646,47 @@
// Adjust stack pointer: r1 -= numbytes.
// If there is a preferred stack alignment, align R1 now
- if (MaxAlign TargetAlign) {
-assert(isPowerOf2_32(MaxAlign) MaxAlign 32767 Invalid
alignment!);
-assert(isInt16(0-NumBytes) Unhandled stack size and alignment!);
-BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
- .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
-BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
- .addImm(0-NumBytes);
-BuildMI(MBB, MBBI, PPC::STWUX, 3)
- .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
- } else if (NumBytes = 32768) {
-BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes)
- .addReg(PPC::R1);
- } else {
-BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes 16);
-BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
- .addImm(NegNumbytes 0x);
-BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
- .addReg(PPC::R0);
+ if (!Subtarget.isPPC64()) {
+// PPC32.
+if (MaxAlign TargetAlign) {
+ assert(isPowerOf2_32(MaxAlign) MaxAlign 32767Invalid
alignment!);
+ assert(isInt16(0-NumBytes) Unhandled stack size and alignment!);
+ BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
+.addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
+ BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
+.addImm(0-NumBytes);
+ BuildMI(MBB, MBBI, PPC::STWUX, 3)
+.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
+} else if (NumBytes = 32768) {
+ BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes)
+.addReg(PPC::R1);
+} else {
+ BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes 16);
+ BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
+.addImm(NegNumbytes 0x);
+ BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
+.addReg(PPC::R0);
+}
+ } else {// PPC64.
+if (MaxAlign TargetAlign) {
+ assert(isPowerOf2_32(MaxAlign) MaxAlign 32767Invalid
alignment!);
+ assert(isInt16(0-NumBytes) Unhandled stack size and alignment!);
+ BuildMI(MBB, MBBI, PPC::RLDICL, 3, PPC::X0)
+.addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign));
+ BuildMI(MBB, MBBI, PPC::SUBFIC8, 2, PPC::X0).addReg(PPC::X0)
+.addImm(0-NumBytes);
+ BuildMI(MBB, MBBI, PPC::STDUX, 3)
+.addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
+} else if (NumBytes = 32768*4) {
+ BuildMI(MBB, MBBI, PPC::STDU, 3).addReg(PPC::X1).addImm(NegNumbytes/4)
+ .addReg(PPC::X1);
+} else {
+ BuildMI(MBB, MBBI, PPC::LIS8, 1, PPC::X0).addImm(NegNumbytes 16);
+ BuildMI(MBB, MBBI, PPC::ORI8, 2, PPC::X0).addReg(PPC::X0)
+
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstr64Bit.td updated: 1.23 - 1.24 PPCInstrInfo.td updated: 1.256 - 1.257 --- Log message: Mark operands as symbol lo instead of imm32 so that they print lo(x) around globals. --- Diffs of the changes: (+11 -11) PPCInstr64Bit.td | 10 +- PPCInstrInfo.td | 12 ++-- 2 files changed, 11 insertions(+), 11 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.23 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.24 --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.23 Fri Nov 10 17:58:45 2006 +++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdFri Nov 10 22:51:36 2006 @@ -249,7 +249,7 @@ PPC970_DGroup_Cracked; // Update forms. -def LHAU8 : DForm_143, (ops G8RC:$rD, ptr_rc:$rA_result, i32imm:$disp, +def LHAU8 : DForm_143, (ops G8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp, ptr_rc:$rA), lhau $rD, $disp($rA), LdStGeneral, [], RegConstraint$rA = $rA_result; @@ -281,15 +281,15 @@ // Update forms. -def LBZU8 : DForm_135, (ops G8RC:$rD, ptr_rc:$rA_result, i32imm:$disp, +def LBZU8 : DForm_135, (ops G8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp, ptr_rc:$rA), lbzu $rD, $disp($rA), LdStGeneral, [], RegConstraint$rA = $rA_result; -def LHZU8 : DForm_141, (ops G8RC:$rD, ptr_rc:$rA_result, i32imm:$disp, +def LHZU8 : DForm_141, (ops G8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp, ptr_rc:$rA), lhzu $rD, $disp($rA), LdStGeneral, [], RegConstraint$rA = $rA_result; -def LWZU8 : DForm_133, (ops G8RC:$rD, ptr_rc:$rA_result, i32imm:$disp, +def LWZU8 : DForm_133, (ops G8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp, ptr_rc:$rA), lwzu $rD, $disp($rA), LdStGeneral, [], RegConstraint$rA = $rA_result; @@ -306,7 +306,7 @@ ldx $rD, $src, LdStLD, [(set G8RC:$rD, (load xaddr:$src))], isPPC64; -def LDU : DSForm_158, 1, (ops G8RC:$rD, ptr_rc:$rA_result, i32imm:$disp, +def LDU : DSForm_158, 1, (ops G8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp, ptr_rc:$rA), ldu $rD, $disp($rA), LdStLD, [], RegConstraint$rA = $rA_result, isPPC64; Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.256 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.257 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.256 Fri Nov 10 11:51:02 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Fri Nov 10 22:51:36 2006 @@ -432,31 +432,31 @@ // FIXME: PTRRC for Pointer regs for ppc64. // 'Update' load forms. -def LBZU : DForm_135, (ops GPRC:$rD, ptr_rc:$rA_result, i32imm:$disp, +def LBZU : DForm_135, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp, ptr_rc:$rA), lbzu $rD, $disp($rA), LdStGeneral, [], RegConstraint$rA = $rA_result; -def LHAU : DForm_143, (ops GPRC:$rD, ptr_rc:$rA_result, i32imm:$disp, +def LHAU : DForm_143, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp, ptr_rc:$rA), lhau $rD, $disp($rA), LdStGeneral, [], RegConstraint$rA = $rA_result; -def LHZU : DForm_141, (ops GPRC:$rD, ptr_rc:$rA_result, i32imm:$disp, +def LHZU : DForm_141, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp, ptr_rc:$rA), lhzu $rD, $disp($rA), LdStGeneral, [], RegConstraint$rA = $rA_result; -def LWZU : DForm_133, (ops GPRC:$rD, ptr_rc:$rA_result, i32imm:$disp, +def LWZU : DForm_133, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp, ptr_rc:$rA), lwzu $rD, $disp($rA), LdStGeneral, [], RegConstraint$rA = $rA_result; -def LFSU : DForm_149, (ops F4RC:$rD, ptr_rc:$rA_result, i32imm:$disp, +def LFSU : DForm_149, (ops F4RC:$rD, ptr_rc:$rA_result, symbolLo:$disp, ptr_rc:$rA), lfs $rD, $disp($rA), LdStLFDU, [], RegConstraint$rA = $rA_result; -def LFDU : DForm_151, (ops F8RC:$rD, ptr_rc:$rA_result, i32imm:$disp, +def LFDU : DForm_151, (ops F8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp, ptr_rc:$rA), lfd $rD, $disp($rA), LdStLFD, [], RegConstraint$rA = $rA_result; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstr64Bit.td updated: 1.19 - 1.20 --- Log message: Shift amounts are always 32-bits, even in 64-bit mode. This fixes CodeGen/PowerPC/2006-09-28-shift_64.ll --- Diffs of the changes: (+6 -6) PPCInstr64Bit.td | 12 ++-- 1 files changed, 6 insertions(+), 6 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.19 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.20 --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.19 Tue Jul 18 11:33:26 2006 +++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdThu Sep 28 15:48:45 2006 @@ -168,15 +168,15 @@ def CMPLDI : DForm_6_ext10, (ops CRRC:$dst, G8RC:$src1, u16imm:$src2), cmpldi $dst, $src1, $src2, IntCompare, isPPC64; -def SLD : XForm_631, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), +def SLD : XForm_631, 27, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB), sld $rA, $rS, $rB, IntRotateD, - [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))], isPPC64; -def SRD : XForm_631, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), + [(set G8RC:$rA, (shl G8RC:$rS, GPRC:$rB))], isPPC64; +def SRD : XForm_631, 539, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB), srd $rA, $rS, $rB, IntRotateD, - [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))], isPPC64; -def SRAD : XForm_631, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), + [(set G8RC:$rA, (srl G8RC:$rS, GPRC:$rB))], isPPC64; +def SRAD : XForm_631, 794, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB), srad $rA, $rS, $rB, IntRotateD, - [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))], isPPC64; + [(set G8RC:$rA, (sra G8RC:$rS, GPRC:$rB))], isPPC64; def EXTSW : XForm_1131, 986, (ops G8RC:$rA, G8RC:$rS), extsw $rA, $rS, IntGeneral, [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))], isPPC64; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td PPCInstrAltivec.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstr64Bit.td updated: 1.18 - 1.19
PPCInstrAltivec.td updated: 1.54 - 1.55
PPCInstrInfo.td updated: 1.238 - 1.239
---
Log message:
Make the implicit def instructions look like other instrs.
---
Diffs of the changes: (+5 -5)
PPCInstr64Bit.td |2 +-
PPCInstrAltivec.td |2 +-
PPCInstrInfo.td|6 +++---
3 files changed, 5 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.18
llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.19
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.18 Thu Jul 13 23:42:02 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdTue Jul 18 11:33:26 2006
@@ -57,7 +57,7 @@
// Pseudo instructions.
//
-def IMPLICIT_DEF_G8RC : Pseudo(ops G8RC:$rD), ; $rD = IMPLICIT_DEF_G8RC,
+def IMPLICIT_DEF_G8RC : Pseudo(ops G8RC:$rD), ; IMPLICIT_DEF_G8RC $rD,
[(set G8RC:$rD, (undef))];
let Pattern = [(PPCmtctr G8RC:$rS)] in {
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.54
llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.55
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.54 Mon Jun 19 19:39:56 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Tue Jul 18 11:33:26 2006
@@ -157,7 +157,7 @@
//===--===//
// Instruction Definitions.
-def IMPLICIT_DEF_VRRC : Pseudo(ops VRRC:$rD), ; $rD = IMPLICIT_DEF_VRRC,
+def IMPLICIT_DEF_VRRC : Pseudo(ops VRRC:$rD), ; IMPLICIT_DEF_VRRC $rD,
[(set VRRC:$rD, (v4i32 (undef)))];
let noResults = 1 in {
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.238
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.239
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.238 Mon Jul 10 15:56:58 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Jul 18 11:33:26 2006
@@ -262,11 +262,11 @@
def UPDATE_VRSAVE: Pseudo(ops GPRC:$rD, GPRC:$rS),
UPDATE_VRSAVE $rD, $rS, [];
}
-def IMPLICIT_DEF_GPRC: Pseudo(ops GPRC:$rD), ; $rD = IMPLICIT_DEF_GPRC,
+def IMPLICIT_DEF_GPRC: Pseudo(ops GPRC:$rD), ; IMPLICIT_DEF_GPRC $rD,
[(set GPRC:$rD, (undef))];
-def IMPLICIT_DEF_F8 : Pseudo(ops F8RC:$rD), ; $rD = IMPLICIT_DEF_F8,
+def IMPLICIT_DEF_F8 : Pseudo(ops F8RC:$rD), ; IMPLICIT_DEF_F8 $rD,
[(set F8RC:$rD, (undef))];
-def IMPLICIT_DEF_F4 : Pseudo(ops F4RC:$rD), ; $rD = IMPLICIT_DEF_F4,
+def IMPLICIT_DEF_F4 : Pseudo(ops F4RC:$rD), ; IMPLICIT_DEF_F4 $rD,
[(set F4RC:$rD, (undef))];
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by
the
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstr64Bit.td updated: 1.11 - 1.12
---
Log message:
Add zextload from i32 - i64, with this, perimeter works.
---
Diffs of the changes: (+3 -0)
PPCInstr64Bit.td |3 +++
1 files changed, 3 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.11
llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.12
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.11 Mon Jun 26 18:53:10 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdTue Jun 27 12:30:08 2006
@@ -228,6 +228,9 @@
def LDX : XForm_131, 21, (ops G8RC:$rD, memrr:$src),
ldx $rD, $src, LdStLD,
[(set G8RC:$rD, (load xaddr:$src))], isPPC64;
+def LWZ8 : DForm_132, (ops G8RC:$rD, memri:$src),
+ lwz $rD, $src, LdStGeneral,
+ [(set G8RC:$rD, (zextload iaddr:$src, i32))], isPPC64;
}
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
def STD : DSForm_262, 0, (ops G8RC:$rS, memrix:$dst),
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC: PPCInstr64Bit.td updated: 1.13 - 1.14 --- Log message: Fix an incorrect store pattern. This fixes em3d. --- Diffs of the changes: (+1 -1) PPCInstr64Bit.td |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.13 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.14 --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.13 Tue Jun 27 13:18:41 2006 +++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdTue Jun 27 13:22:50 2006 @@ -251,7 +251,7 @@ [(store G8RC:$rS, ixaddr:$dst)], isPPC64; def STDX : XForm_831, 149, (ops G8RC:$rS, memrr:$dst), stdx $rS, $dst, LdStSTD, - [(store G8RC:$rS, iaddr:$dst)], isPPC64, + [(store G8RC:$rS, xaddr:$dst)], isPPC64, PPC970_DGroup_Cracked; def STDUX : XForm_831, 181, (ops G8RC:$rS, memrr:$dst), stdux $rS, $dst, LdStSTD, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstr64Bit.td updated: 1.14 - 1.15
PPCInstrInfo.td updated: 1.236 - 1.237
---
Log message:
Add 64-bit MTCTR so that indirect calls work.
---
Diffs of the changes: (+6 -2)
PPCInstr64Bit.td |4
PPCInstrInfo.td |4 ++--
2 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.14
llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.15
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.14 Tue Jun 27 13:22:50 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdTue Jun 27 13:36:44 2006
@@ -60,6 +60,10 @@
def IMPLICIT_DEF_G8RC : Pseudo(ops G8RC:$rD), ; $rD = IMPLICIT_DEF_G8RC,
[(set G8RC:$rD, (undef))];
+let Pattern = [(PPCmtctr G8RC:$rS)] in {
+def MTCTR8 : XFXForm_7_ext31, 467, 9, (ops G8RC:$rS), mtctr $rS, SprMTSPR,
+PPC970_DGroup_First, PPC970_Unit_FXU;
+}
//===--===//
// Fixed point instructions.
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.236
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.237
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.236 Tue Jun 27 13:18:41 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Jun 27 13:36:44 2006
@@ -71,7 +71,7 @@
def callseq_start : SDNodeISD::CALLSEQ_START,
SDT_PPCCallSeq,[SDNPHasChain];
def callseq_end : SDNodeISD::CALLSEQ_END,
SDT_PPCCallSeq,[SDNPHasChain];
-def SDT_PPCCall : SDTypeProfile0, -1, [SDTCisVT0, i32];
+def SDT_PPCCall : SDTypeProfile0, -1, [SDTCisInt0];
def PPCcall : SDNodePPCISD::CALL, SDT_PPCCall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag];
def PPCmtctr : SDNodePPCISD::MTCTR, SDT_PPCCall,
@@ -323,7 +323,7 @@
def BL : IForm18, 0, 1, (ops calltarget:$func, variable_ops),
bl $func, BrB, []; // See Pat patterns below.
def BLA : IForm18, 1, 1, (ops aaddr:$func, variable_ops),
-bla $func, BrB, [(PPCcall imm:$func)];
+bla $func, BrB, [(PPCcall (i32 imm:$func))];
def BCTRL : XLForm_2_ext19, 528, 20, 0, 1, (ops variable_ops), bctrl, BrB,
[(PPCbctrl)];
}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstr64Bit.td updated: 1.4 - 1.5
---
Log message:
Add some patterns for globals, so we can now compile this:
static unsigned long long X, Y;
void test1() {
X = Y;
}
into:
_test1:
lis r2, ha16(_Y)
lis r3, ha16(_X)
ld r2, lo16(_Y)(r2)
std r2, lo16(_X)(r3)
blr
---
Diffs of the changes: (+37 -1)
PPCInstr64Bit.td | 38 +-
1 files changed, 37 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.4
llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.5
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.4Mon Jun 19 19:38:36 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdTue Jun 20 16:23:06 2006
@@ -12,6 +12,18 @@
//
//===--===//
+//===--===//
+// 64-bit operands.
+//
+def symbolHi64 : Operandi64 {
+ let PrintMethod = printSymbolHi;
+}
+def symbolLo64 : Operandi64 {
+ let PrintMethod = printSymbolLo;
+}
+
+
+
//===--===//
// Fixed point instructions.
@@ -19,6 +31,13 @@
let PPC970_Unit = 1 in { // FXU Operations.
+def LI8 : DForm_2_r014, (ops G8RC:$rD, symbolLo64:$imm),
+ li $rD, $imm, IntGeneral,
+ [(set G8RC:$rD, immSExt16:$imm)];
+def LIS8 : DForm_2_r015, (ops G8RC:$rD, symbolHi64:$imm),
+ lis $rD, $imm, IntGeneral,
+ [(set G8RC:$rD, imm16Shifted:$imm)];
+
def OR8 : XForm_631, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
or $rA, $rS, $rB, IntGeneral,
[(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))];
@@ -32,6 +51,10 @@
def ADD8 : XOForm_131, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
add $rT, $rA, $rB, IntGeneral,
[(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))];
+def ADDIS8 : DForm_215, (ops G8RC:$rD, G8RC:$rA, symbolHi64:$imm),
+ addis $rD, $rA, $imm, IntGeneral,
+ [(set G8RC:$rD, (add G8RC:$rA, imm16Shifted:$imm))];
+
def MULHD : XOForm_131, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
mulhd $rT, $rA, $rB, IntMulHW,
[(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))];
@@ -163,7 +186,6 @@
//===--===//
// Instruction Patterns
//
-
// Extensions and truncates to/from 32-bit regs.
def : Pat(i64 (zext GPRC:$in)),
(RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32);
@@ -177,3 +199,17 @@
(RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm));
def : Pat(srl G8RC:$in, (i64 imm:$imm)),
(RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm);
+
+// Hi and Lo for Darwin Global Addresses.
+def : Pat(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in);
+def : Pat(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in);
+def : Pat(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in);
+def : Pat(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in);
+def : Pat(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in);
+def : Pat(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in);
+def : Pat(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
+ (ADDIS8 G8RC:$in, tglobaladdr:$g);
+def : Pat(add G8RC:$in, (PPChi tconstpool:$g, 0)),
+ (ADDIS8 G8RC:$in, tconstpool:$g);
+def : Pat(add G8RC:$in, (PPChi tjumptable:$g, 0)),
+ (ADDIS8 G8RC:$in, tjumptable:$g);
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstr64Bit.td updated: 1.5 - 1.6
PPCInstrInfo.td updated: 1.227 - 1.228
---
Log message:
Add some 64-bit logical ops.
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
---
Diffs of the changes: (+78 -16)
PPCInstr64Bit.td | 66 ---
PPCInstrInfo.td | 28 ---
2 files changed, 78 insertions(+), 16 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.5
llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.6
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.5Tue Jun 20 16:23:06 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdTue Jun 20 17:34:10 2006
@@ -31,13 +31,7 @@
let PPC970_Unit = 1 in { // FXU Operations.
-def LI8 : DForm_2_r014, (ops G8RC:$rD, symbolLo64:$imm),
- li $rD, $imm, IntGeneral,
- [(set G8RC:$rD, immSExt16:$imm)];
-def LIS8 : DForm_2_r015, (ops G8RC:$rD, symbolHi64:$imm),
- lis $rD, $imm, IntGeneral,
- [(set G8RC:$rD, imm16Shifted:$imm)];
-
+// Copies, extends, truncates.
def OR8 : XForm_631, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
or $rA, $rS, $rB, IntGeneral,
[(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))];
@@ -47,13 +41,47 @@
def OR8To4 : XForm_631, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
or $rA, $rS, $rB, IntGeneral,
[];
+
+def LI8 : DForm_2_r014, (ops G8RC:$rD, symbolLo64:$imm),
+ li $rD, $imm, IntGeneral,
+ [(set G8RC:$rD, immSExt16:$imm)];
+def LIS8 : DForm_2_r015, (ops G8RC:$rD, symbolHi64:$imm),
+ lis $rD, $imm, IntGeneral,
+ [(set G8RC:$rD, imm16ShiftedSExt:$imm)];
+
+// Logical ops.
+def ANDIo8 : DForm_428, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
+ andi. $dst, $src1, $src2, IntGeneral,
+ [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))],
+ isDOT;
+def ANDISo8 : DForm_429, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
+ andis. $dst, $src1, $src2, IntGeneral,
+[(set G8RC:$dst, (and
G8RC:$src1,imm16ShiftedZExt:$src2))],
+ isDOT;
+def ORI8: DForm_424, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
+ ori $dst, $src1, $src2, IntGeneral,
+ [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))];
+def ORIS8 : DForm_425, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
+ oris $dst, $src1, $src2, IntGeneral,
+[(set G8RC:$dst, (or G8RC:$src1,
imm16ShiftedZExt:$src2))];
+def XORI8 : DForm_426, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
+ xori $dst, $src1, $src2, IntGeneral,
+ [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))];
+def XORIS8 : DForm_427, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
+ xoris $dst, $src1, $src2, IntGeneral,
+ [(set G8RC:$dst, (xor G8RC:$src1,
imm16ShiftedZExt:$src2))];
+
+
def ADD8 : XOForm_131, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
add $rT, $rA, $rB, IntGeneral,
[(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))];
def ADDIS8 : DForm_215, (ops G8RC:$rD, G8RC:$rA, symbolHi64:$imm),
addis $rD, $rA, $imm, IntGeneral,
- [(set G8RC:$rD, (add G8RC:$rA, imm16Shifted:$imm))];
+ [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))];
+
+
+
def MULHD : XOForm_131, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
mulhd $rT, $rA, $rB, IntMulHW,
@@ -186,6 +214,28 @@
//===--===//
// Instruction Patterns
//
+
+// Immediate support.
+// Handled above:
+// sext(0x___, i8) - li imm
+// sext(0x___, i16) - lis imm16
+
+// sext(0x___, i16) - lis + ori
+def sext_0x____i16 : PatLeaf(imm), [{
+ return N-getValue() == (uint64_t)(int32_t)N-getValue();
+}];
+def : Pat(i64 sext_0x____i16:$imm),
+ (ORI8 (LIS8 (HI16 imm:$imm)), (LO16 imm:$imm));
+
+// zext(0x___, i16) - xoris (li lo16(imm)), imm16
+def zext_0x____i16 : PatLeaf(imm), [{
+ return (N-getValue()
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstr64Bit.td updated: 1.6 - 1.7
---
Log message:
Instead of li/xoris use li/oris. Note that this doesn't work if bit 15 is
set, so disable the pattern in that case.
---
Diffs of the changes: (+5 -5)
PPCInstr64Bit.td | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.6
llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.7
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.6Tue Jun 20 17:34:10 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdTue Jun 20 17:38:59 2006
@@ -227,12 +227,12 @@
def : Pat(i64 sext_0x____i16:$imm),
(ORI8 (LIS8 (HI16 imm:$imm)), (LO16 imm:$imm));
-// zext(0x___, i16) - xoris (li lo16(imm)), imm16
-def zext_0x____i16 : PatLeaf(imm), [{
- return (N-getValue() 0xULL) == 0;
+// zext(0x___7FFF, i16) - oris (li lo16(imm)), imm16
+def zext_0x___7FFF_i16 : PatLeaf(imm), [{
+ return (N-getValue() 0x8000ULL) == 0;
}];
-def : Pat(i64 zext_0x____i16:$imm),
- (XORIS8 (LI8 (LO16 imm:$imm)), (HI16 imm:$imm));
+def : Pat(i64 zext_0x___7FFF_i16:$imm),
+ (ORIS8 (LI8 (LO16 imm:$imm)), (HI16 imm:$imm));
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstr64Bit.td updated: 1.8 - 1.9
---
Log message:
add some logical ops
---
Diffs of the changes: (+28 -3)
PPCInstr64Bit.td | 31 ---
1 files changed, 28 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.8
llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.9
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.8Tue Jun 20 18:03:01 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdTue Jun 20 18:11:59 2006
@@ -32,9 +32,6 @@
let PPC970_Unit = 1 in { // FXU Operations.
// Copies, extends, truncates.
-def OR8 : XForm_631, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
- or $rA, $rS, $rB, IntGeneral,
- [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))];
def OR4To8 : XForm_631, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
or $rA, $rS, $rB, IntGeneral,
[];
@@ -50,6 +47,32 @@
[(set G8RC:$rD, imm16ShiftedSExt:$imm)];
// Logical ops.
+def NAND8: XForm_631, 476, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
+ nand $rA, $rS, $rB, IntGeneral,
+ [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))];
+def AND8 : XForm_631, 28, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
+ and $rA, $rS, $rB, IntGeneral,
+ [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))];
+def ANDC8: XForm_631, 60, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
+ andc $rA, $rS, $rB, IntGeneral,
+ [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))];
+def OR8 : XForm_631, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
+ or $rA, $rS, $rB, IntGeneral,
+ [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))];
+def NOR8 : XForm_631, 124, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
+ nor $rA, $rS, $rB, IntGeneral,
+ [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))];
+def ORC8 : XForm_631, 412, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
+ orc $rA, $rS, $rB, IntGeneral,
+ [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))];
+def EQV8 : XForm_631, 284, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
+ eqv $rA, $rS, $rB, IntGeneral,
+ [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))];
+def XOR8 : XForm_631, 316, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
+ xor $rA, $rS, $rB, IntGeneral,
+ [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))];
+
+// Logical ops with immediate.
def ANDIo8 : DForm_428, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
andi. $dst, $src1, $src2, IntGeneral,
[(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))],
@@ -252,6 +275,8 @@
def : Pat(i64 zext_0x____i16:$imm),
(ORIS8 (ORI8 (LI8 0), (LO16 imm:$imm)), (HI16 imm:$imm));
+// FIXME: Handle smart forms where the top 32-bits are set. Right now, stuff
+// like 0xABCD0123BCDE hits the case below, which produces ORI R, R, 0's!
// Fully general (and most expensive: 6 instructions!) immediate pattern.
def : Pat(i64 imm:$imm),
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstr64Bit.td updated: 1.3 - 1.4
---
Log message:
Add some patterns for ppc64
---
Diffs of the changes: (+14 -13)
PPCInstr64Bit.td | 27 ++-
1 files changed, 14 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.3
llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.4
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.3Fri Jun 16 16:29:41 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdMon Jun 19 19:38:36 2006
@@ -105,12 +105,13 @@
let isLoad = 1, PPC970_Unit = 2 in {
-def LWA : DSForm_158, 2, (ops G8RC:$rT, memrix:$src),
-lwa $rT, $src, LdStLWA,
-[], isPPC64, PPC970_DGroup_Cracked;
-def LD : DSForm_258, 0, (ops G8RC:$rT, memrix:$src),
-ld $rT, $src, LdStLD,
-[], isPPC64;
+def LWA : DSForm_158, 2, (ops G8RC:$rD, memrix:$src),
+lwa $rD, $src, LdStLWA,
+[(set G8RC:$rD, (sextload ixaddr:$src, i32))], isPPC64,
+PPC970_DGroup_Cracked;
+def LD : DSForm_258, 0, (ops G8RC:$rD, memrix:$src),
+ld $rD, $src, LdStLD,
+[(set G8RC:$rD, (load ixaddr:$src))], isPPC64;
def LWAX : XForm_131, 341, (ops G8RC:$rD, memrr:$src),
lwax $rD, $src, LdStLHA,
@@ -121,14 +122,14 @@
[(set G8RC:$rD, (load xaddr:$src))], isPPC64;
}
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
-def STD : DSForm_262, 0, (ops G8RC:$rT, memrix:$src),
-std $rT, $src, LdStSTD,
-[], isPPC64;
-
-def STDX : XForm_831, 149, (ops GPRC:$rS, memrr:$dst),
+def STD : DSForm_262, 0, (ops G8RC:$rS, memrix:$dst),
+std $rS, $dst, LdStSTD,
+[(store G8RC:$rS, ixaddr:$dst)], isPPC64;
+def STDX : XForm_831, 149, (ops G8RC:$rS, memrr:$dst),
stdx $rS, $dst, LdStSTD,
- [], isPPC64, PPC970_DGroup_Cracked;
-def STDUX : XForm_831, 181, (ops GPRC:$rS, memrr:$dst),
+ [(store G8RC:$rS, iaddr:$dst)], isPPC64,
+ PPC970_DGroup_Cracked;
+def STDUX : XForm_831, 181, (ops G8RC:$rS, memrr:$dst),
stdux $rS, $dst, LdStSTD,
[], isPPC64;
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstr64Bit.td added (r1.1)
PPCInstrInfo.td updated: 1.222 - 1.223
---
Log message:
Split 64-bit instructions out into a separate .td file
---
Diffs of the changes: (+185 -130)
PPCInstr64Bit.td | 183 +++
PPCInstrInfo.td | 132 ---
2 files changed, 185 insertions(+), 130 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -c /dev/null llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.1
*** /dev/null Fri Jun 16 15:22:11 2006
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.tdFri Jun 16 15:22:01 2006
***
*** 0
--- 1,183
+ //===- PPCInstr64Bit.td - The PowerPC 64-bit Support ---*- tablegen
-*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Chris Lattner and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for
details.
+ //
+
//===--===//
+ //
+ // This file describes the PowerPC 64-bit instructions. These patterns are
used
+ // both when in ppc64 mode and when in use 64-bit extensions in 32-bit mode.
+ //
+
//===--===//
+
+
+
//===--===//
+ // Fixed point instructions.
+ //
+
+ let PPC970_Unit = 1 in { // FXU Operations.
+
+ def OR8 : XForm_631, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
+or $rA, $rS, $rB, IntGeneral,
+[(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))];
+ def OR4To8 : XForm_631, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
+or $rA, $rS, $rB, IntGeneral,
+[];
+ def OR8To4 : XForm_631, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
+or $rA, $rS, $rB, IntGeneral,
+[];
+
+ def ADD8 : XOForm_131, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
+ add $rT, $rA, $rB, IntGeneral,
+ [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))];
+ def MULHD : XOForm_131, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
+ mulhd $rT, $rA, $rB, IntMulHW,
+ [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))];
+ def MULHDU : XOForm_131, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
+ mulhdu $rT, $rA, $rB, IntMulHWU,
+ [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))];
+
+ def CMPDI : DForm_5_ext11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
+ cmpdi $crD, $rA, $imm, IntCompare, isPPC64;
+
+ def CMPLDI : DForm_6_ext10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
+ cmpldi $dst, $src1, $src2, IntCompare, isPPC64;
+ def CMPD : XForm_16_ext31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
+ cmpd $crD, $rA, $rB, IntCompare, isPPC64;
+ def CMPLD : XForm_16_ext31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
+ cmpld $crD, $rA, $rB, IntCompare, isPPC64;
+
+ def SLD : XForm_631, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
+sld $rA, $rS, $rB, IntRotateD,
+[(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))], isPPC64;
+ def SRD : XForm_631, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
+srd $rA, $rS, $rB, IntRotateD,
+[(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))], isPPC64;
+ def SRAD : XForm_631, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
+srad $rA, $rS, $rB, IntRotateD,
+[(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))], isPPC64;
+ def EXTSW : XForm_1131, 986, (ops G8RC:$rA, G8RC:$rS),
+ extsw $rA, $rS, IntGeneral,
+ [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))], isPPC64;
+ /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
+ def EXTSW_32 : XForm_1131, 986, (ops GPRC:$rA, GPRC:$rS),
+ extsw $rA, $rS, IntGeneral,
+ [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))], isPPC64;
+
+ def SRADI : XSForm_131, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
+ sradi $rA, $rS, $SH, IntRotateD, isPPC64;
+ def DIVD : XOForm_131, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
+ divd $rT, $rA, $rB, IntDivD,
+ [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))], isPPC64,
+ PPC970_DGroup_First, PPC970_DGroup_Cracked;
+ def DIVDU : XOForm_131, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
+ divdu $rT, $rA, $rB, IntDivD,
+ [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))], isPPC64,
+ PPC970_DGroup_First, PPC970_DGroup_Cracked;
+ def MULLD : XOForm_131, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
+ mulld $rT, $rA, $rB, IntMulHD,
+
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstr64Bit.td updated: 1.2 - 1.3
---
Log message:
Upgrade some load/store instructions to use the proper addressing mode stuff.
---
Diffs of the changes: (+10 -10)
PPCInstr64Bit.td | 20 ++--
1 files changed, 10 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.2
llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.3
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.2Fri Jun 16 16:01:35 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdFri Jun 16 16:29:41 2006
@@ -105,11 +105,11 @@
let isLoad = 1, PPC970_Unit = 2 in {
-def LWA : DSForm_158, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
-lwa $rT, $DS($rA), LdStLWA,
+def LWA : DSForm_158, 2, (ops G8RC:$rT, memrix:$src),
+lwa $rT, $src, LdStLWA,
[], isPPC64, PPC970_DGroup_Cracked;
-def LD : DSForm_258, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
-ld $rT, $DS($rA), LdStLD,
+def LD : DSForm_258, 0, (ops G8RC:$rT, memrix:$src),
+ld $rT, $src, LdStLD,
[], isPPC64;
def LWAX : XForm_131, 341, (ops G8RC:$rD, memrr:$src),
@@ -121,15 +121,15 @@
[(set G8RC:$rD, (load xaddr:$src))], isPPC64;
}
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
-def STD : DSForm_262, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
-std $rT, $DS($rA), LdStSTD,
+def STD : DSForm_262, 0, (ops G8RC:$rT, memrix:$src),
+std $rT, $src, LdStSTD,
[], isPPC64;
-def STDX : XForm_831, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
- stdx $rS, $rA, $rB, LdStSTD,
+def STDX : XForm_831, 149, (ops GPRC:$rS, memrr:$dst),
+ stdx $rS, $dst, LdStSTD,
[], isPPC64, PPC970_DGroup_Cracked;
-def STDUX : XForm_831, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
- stdux $rS, $rA, $rB, LdStSTD,
+def STDUX : XForm_831, 181, (ops GPRC:$rS, memrr:$dst),
+ stdux $rS, $dst, LdStSTD,
[], isPPC64;
// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
___
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