[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.54 -> 1.55
PPCInstrInfo.td updated: 1.135 -> 1.136
---
Log message:
Allow pseudos to have patterns, no functionality change
---
Diffs of the changes: (+13 -13)
PPCInstrFormats.td |4 ++--
PPCInstrInfo.td| 22 +++---
2 files changed, 13 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.54
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.55
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.54 Wed Oct 19 14:51:16 2005
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Tue Oct 25 15:58:43 2005
@@ -550,10 +550,10 @@
//===--===//
def NoItin : InstrItinClass;
-class Pseudo
+class Pseudo pattern>
: I<0, OL, asmstr, NoItin> {
let PPC64 = 0;
let VMX = 0;
-
+ let Pattern = pattern;
let Inst{31-0} = 0;
}
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.135
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.136
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.135 Tue Oct 25 15:55:47 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Oct 25 15:58:43 2005
@@ -147,25 +147,25 @@
// PowerPC Instruction Definitions.
// Pseudo-instructions:
-def PHI : Pseudo<(ops variable_ops), "; PHI">;
+def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
let isLoad = 1 in {
-def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN">;
-def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP">;
+def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN", []>;
+def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP", []>;
}
-def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
-def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8">;
-def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4">;
+def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC", []>;
+def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8", []>;
+def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4", []>;
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by
the
// scheduler into a branch sequence.
let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
- i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
+ i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
- i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
+ i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
- i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
+ i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
}
@@ -176,12 +176,12 @@
}
let Defs = [LR] in
- def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
+ def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>;
let isBranch = 1, isTerminator = 1 in {
def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
target:$true, target:$false),
- "; COND_BRANCH">;
+ "; COND_BRANCH", []>;
def B : IForm<18, 0, 0, (ops target:$func), "b $func", BrB>;
//def BA : IForm<18, 1, 0, (ops target:$func), "ba $func", BrB>;
def BL : IForm<18, 0, 1, (ops target:$func), "bl $func", BrB>;
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.57 -> 1.58
PPCInstrInfo.td updated: 1.145 -> 1.146
---
Log message:
Add the remainder of the AltiVec 4 x float instructions. Further
enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.
---
Diffs of the changes: (+61 -14)
PPCInstrFormats.td | 14
PPCInstrInfo.td| 61 -
2 files changed, 61 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.57
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.58
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.57 Sat Nov 26 16:39:34 2005
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Tue Nov 29 02:04:45 2005
@@ -582,6 +582,20 @@
let Inst{21-31} = xo;
}
+class VXForm_2 xo, dag OL, string asmstr,
+ InstrItinClass itin, list pattern>
+: I<4, OL, asmstr, itin> {
+ bits<5> VD;
+ bits<5> VB;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = VD;
+ let Inst{11-15} = 0;
+ let Inst{16-20} = VB;
+ let Inst{21-31} = xo;
+}
+
// E-4 VXR-Form
class VXRForm_1 xo, bit rc, dag OL, string asmstr,
InstrItinClass itin, list pattern>
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.145
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.146
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.145 Sat Nov 26 16:39:34 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Nov 29 02:04:45 2005
@@ -767,32 +767,65 @@
[]>, isPPC64;
// VA-Form instructions. 3-input AltiVec ops.
-def VMADDFP: VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
- "vmaddfp $vD, $vA, $vB, $vC", VecFP,
- []>;
+def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
+ "vmaddfp $vD, $vA, $vC, $vB", VecFP,
+ [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
+ VRRC:$vB))]>;
+def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
+ "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
+ [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA,
+VRRC:$vC),
+ VRRC:$vB)))]>;
// VX-Form instructions. AltiVec arithmetic ops.
def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
"vaddfp $vD, $vA, $vB", VecFP,
- []>;
-def VADDUWM: VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
- "vadduwm $vD, $vA, $vB", VecGeneral,
- []>;
-def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
- "vand $vD, $vA, $vB", VecGeneral,
- []>;
+ [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
"vcfsx $vD, $vB, $UIMM", VecFP,
[]>;
def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
"vcfux $vD, $vB, $UIMM", VecFP,
[]>;
-def VOR: VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
- "vor $vD, $vA, $vB", VecGeneral,
+def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
+ "vctsxs $vD, $vB, $UIMM", VecFP,
[]>;
-def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
- "vxor $vD, $vA, $vB", VecGeneral,
+def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
+ "vctuxs $vD, $vB, $UIMM", VecFP,
[]>;
+def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
+"vexptefp $vD, $vB", VecFP,
+[]>;
+def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
+"vlogefp $vD, $vB", VecFP,
+[]>;
+def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vmaxfp $vD, $vA, $vB", VecFP,
+ []>;
+def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vminfp $vD, $vA, $vB", VecFP,
+ []>;
+def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
+ "vrefp $vD, $vB", VecFP,
+ []>;
+def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
+ "vrfim $vD, $vB", VecFP,
+ []>;
+def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
+ "vrfin $vD, $vB", VecFP,
+ []>;
+def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
+ "vrfip $vD, $vB", VecFP,
+
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.58 -> 1.59
PPCInstrInfo.td updated: 1.146 -> 1.147
---
Log message:
Represent the encoding of the SPR instructions as they actually are, so
that we can use the correct SPR numbers in the InstrInfo.td file. This is
necessary to support VRsave.
---
Diffs of the changes: (+18 -8)
PPCInstrFormats.td | 12 ++--
PPCInstrInfo.td| 14 --
2 files changed, 18 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.58
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.59
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.58 Tue Nov 29 02:04:45 2005
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Tue Nov 29 16:42:50 2005
@@ -361,7 +361,16 @@
bits<10> SPR;
let Inst{6-10} = RT;
- let Inst{11-20} = SPR;
+ let Inst{11}= SPR{4};
+ let Inst{12}= SPR{3};
+ let Inst{13}= SPR{2};
+ let Inst{14}= SPR{1};
+ let Inst{15}= SPR{0};
+ let Inst{16}= SPR{9};
+ let Inst{17}= SPR{8};
+ let Inst{18}= SPR{7};
+ let Inst{19}= SPR{6};
+ let Inst{20}= SPR{5};
let Inst{21-30} = xo;
let Inst{31}= 0;
}
@@ -411,7 +420,6 @@
let Inst{31}= 0;
}
-
class XFXForm_7 opcode, bits<10> xo, dag OL, string asmstr,
InstrItinClass itin>
: XFXForm_1;
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.146
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.147
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.146 Tue Nov 29 02:04:45 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Nov 29 16:42:50 2005
@@ -560,15 +560,17 @@
// Note that although LR should be listed as `8' and CTR as `9' in the SPR
// field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
// which means the SPR value needs to be multiplied by a factor of 32.
-def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
-def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
+def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
+def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
"mtcrf $FXM, $rS", BrMCRX>;
-def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
-"mfcr $rT, $FXM", SprMFCR>;
-def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
-def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
+def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
+ "mfcr $rT, $FXM", SprMFCR>;
+def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
+def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
+def MTSPR : XFXForm_7<31, 467, (ops GPRC:$rS, u16imm:$UIMM), "mtspr $UIMM,
$rS",
+ SprMTSPR>;
// XS-Form instructions. Just 'sradi'
//
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.59 -> 1.60
PPCInstrInfo.td updated: 1.147 -> 1.148
---
Log message:
Define BR in the .td file now that Evan made tblgen smarter.
---
Diffs of the changes: (+10 -5)
PPCInstrFormats.td |3 ++-
PPCInstrInfo.td| 12
2 files changed, 10 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.59
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.60
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.59 Tue Nov 29 16:42:50 2005
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Sun Dec 4 12:42:54 2005
@@ -31,8 +31,9 @@
// 1.7.1 I-Form
class IForm opcode, bit aa, bit lk, dag OL, string asmstr,
-InstrItinClass itin>
+InstrItinClass itin, list pattern>
: I {
+ let Pattern = pattern;
bits<24> LI;
let Inst{6-29} = LI;
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.147
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.148
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.147 Tue Nov 29 16:42:50 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Sun Dec 4 12:42:54 2005
@@ -128,7 +128,7 @@
def s16immX4 : Operand { // Multiply imm by 4 before printing.
let PrintMethod = "printS16X4ImmOperand";
}
-def target : Operand {
+def target : Operand {
let PrintMethod = "printBranchOperand";
}
def calltarget : Operand {
@@ -194,7 +194,9 @@
def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
target:$true, target:$false),
"; COND_BRANCH", []>;
- def B : IForm<18, 0, 0, (ops target:$func), "b $func", BrB>;
+ def B : IForm<18, 0, 0, (ops target:$dst),
+ "b $dst", BrB,
+ [(br bb:$dst)]>;
// FIXME: 4*CR# needs to be added to the BI field!
// This will only work for CR0 as it stands now
@@ -223,8 +225,10 @@
LR,CTR,
CR0,CR1,CR5,CR6,CR7] in {
// Convenient aliases for call instructions
- def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops), "bl $func",
BrB>;
- def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops), "bla $func", BrB>;
+ def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
+"bl $func", BrB, []>;
+ def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
+"bla $func", BrB, []>;
def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl",
BrB>;
}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.60 -> 1.61
PPCInstrInfo.td updated: 1.152 -> 1.153
---
Log message:
Add support patterns to many load and store instructions which will
hopefully use patterns in the near future.
---
Diffs of the changes: (+133 -76)
PPCInstrFormats.td | 69 +++---
PPCInstrInfo.td| 140 +++--
2 files changed, 133 insertions(+), 76 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.60
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.61
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.60 Sun Dec 4 12:42:54 2005
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Fri Dec 9 17:54:17 2005
@@ -58,23 +58,27 @@
// 1.7.4 D-Form
class DForm_base opcode, dag OL, string asmstr, InstrItinClass itin,
- list pattern>
- : I {
- let Pattern = pattern;
+ list pattern>
+ : I {
bits<5> A;
bits<5> B;
bits<16> C;
+
+ let Pattern = pattern;
let Inst{6-10} = A;
let Inst{11-15} = B;
let Inst{16-31} = C;
}
-class DForm_1 opcode, dag OL, string asmstr, InstrItinClass itin>
- : I {
+class DForm_1 opcode, dag OL, string asmstr, InstrItinClass itin,
+ list pattern>
+ : I {
bits<5> A;
bits<16> C;
bits<5> B;
+
+ let Pattern = pattern;
let Inst{6-10} = A;
let Inst{11-15} = B;
@@ -99,12 +103,13 @@
}
// Currently we make the use/def reg distinction in ISel, not tablegen
-class DForm_3 opcode, dag OL, string asmstr, InstrItinClass itin>
- : DForm_1;
+class DForm_3 opcode, dag OL, string asmstr, InstrItinClass itin,
+ list pattern>
+ : DForm_1;
class DForm_4 opcode, dag OL, string asmstr, InstrItinClass itin,
list pattern>
- : I {
+ : I {
bits<5> B;
bits<5> A;
bits<16> C;
@@ -116,8 +121,9 @@
let Inst{16-31} = C;
}
-class DForm_4_zero opcode, dag OL, string asmstr, InstrItinClass itin>
- : DForm_1 {
+class DForm_4_zero opcode, dag OL, string asmstr, InstrItinClass itin,
+ list pattern>
+ : DForm_1 {
let A = 0;
let B = 0;
let C = 0;
@@ -150,22 +156,26 @@
let L = PPC64;
}
-class DForm_8 opcode, dag OL, string asmstr, InstrItinClass itin>
- : DForm_1 {
+class DForm_8 opcode, dag OL, string asmstr, InstrItinClass itin,
+ list pattern>
+ : DForm_1 {
}
-class DForm_9 opcode, dag OL, string asmstr, InstrItinClass itin>
- : DForm_1 {
+class DForm_9 opcode, dag OL, string asmstr, InstrItinClass itin,
+ list pattern>
+ : DForm_1 {
}
// 1.7.5 DS-Form
class DSForm_1 opcode, bits<2> xo, dag OL, string asmstr,
- InstrItinClass itin>
+ InstrItinClass itin, list pattern>
: I {
bits<5> RST;
bits<14> DS;
bits<5> RA;
+ let Pattern = pattern;
+
let Inst{6-10} = RST;
let Inst{11-15} = RA;
let Inst{16-29} = DS;
@@ -173,17 +183,19 @@
}
class DSForm_2 opcode, bits<2> xo, dag OL, string asmstr,
- InstrItinClass itin>
- : DSForm_1;
+ InstrItinClass itin, list pattern>
+ : DSForm_1;
// 1.7.6 X-Form
-class XForm_base_r3xo opcode, bits<10> xo,
- dag OL, string asmstr, InstrItinClass itin>
+class XForm_base_r3xo opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin, list pattern>
: I {
bits<5> RST;
bits<5> A;
bits<5> B;
+ let Pattern = pattern;
+
bit RC = 0;// set by isDOT
let Inst{6-10} = RST;
@@ -214,8 +226,8 @@
class XForm_1 opcode, bits<10> xo, dag OL, string asmstr,
- InstrItinClass itin>
- : XForm_base_r3xo;
+ InstrItinClass itin, list pattern>
+ : XForm_base_r3xo;
class XForm_6 opcode, bits<10> xo, dag OL, string asmstr,
InstrItinClass itin, list pattern>
@@ -224,8 +236,8 @@
}
class XForm_8 opcode, bits<10> xo, dag OL, string asmstr,
- InstrItinClass itin>
- : XForm_base_r3xo;
+ InstrItinClass itin, list pattern>
+ : XForm_base_r3xo;
class XForm_10 opcode, bits<10> xo, dag OL, string asmstr,
InstrItinClass itin, list pattern>
@@ -279,20 +291,19 @@
}
class XForm_25 opcode, bits<10> xo, dag OL, string asmstr,
- InstrItinClass itin>
- : XForm_base_r3xo {
+ InstrItinClass itin, list pattern>
+ : XForm_base_r3xo {
}
class XForm_26 opcode, bits<10> xo, dag OL, string asmstr,
InstrItinClass itin, list pattern>
- : XForm_base_r3xo {
+ : XForm_base_r3xo {
let A = 0;
- let Pattern = pattern;
}
class XForm_28 opcode, bits<10> xo, dag OL, string asmstr,
- InstrItinClass itin>
- : XForm_base_r3xo {
+ InstrItinClass itin, list pattern>
+ : XForm_base_r3xo {
}
// 1.7.7 XL-Form
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/T
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.61 -> 1.62
PPCInstrInfo.td updated: 1.156 -> 1.157
---
Log message:
Add support for fmul node of type v4f32.
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
Is selected to:
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v0, v0, v0, v1
stvx v0, r2, r3
blr
---
Diffs of the changes: (+21 -0)
PPCInstrFormats.td |8
PPCInstrInfo.td| 13 +
2 files changed, 21 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.61
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.62
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.61 Fri Dec 9 17:54:17 2005
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Tue Dec 13 18:34:09 2005
@@ -602,6 +602,14 @@
let Inst{21-31} = xo;
}
+class VXForm_setzero xo, dag OL, string asmstr,
+ InstrItinClass itin, list pattern>
+: VXForm_1 {
+ let VA = VD;
+ let VB = VD;
+}
+
+
class VXForm_2 xo, dag OL, string asmstr,
InstrItinClass itin, list pattern>
: I<4, OL, asmstr, itin> {
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.156
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.157
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.156 Tue Dec 13 16:55:22 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Dec 13 18:34:09 2005
@@ -897,6 +897,16 @@
def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
"vsubfp $vD, $vA, $vB", VecFP,
[(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
+def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vxor $vD, $vA, $vB", VecFP,
+ []>;
+
+// VX-Form Pseudo Instructions
+
+def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
+ "vxor $vD, $vD, $vD", VecFP,
+ []>;
+
//===--===//
// PowerPC Instruction Patterns
@@ -951,6 +961,9 @@
def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
(ADDIS GPRC:$in, tconstpool:$g)>;
+def : Pat<(fmul VRRC:$vA, VRRC:$vB),
+ (VMADDFP VRRC:$vA, (V_SET0), VRRC:$vB)>;
+
// Fused multiply add and multiply sub for packed float. These are represented
// separately from the real instructions above, for operations that must have
// the additional precision, such as Newton-Rhapson (used by divide, sqrt)
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.63 -> 1.64
PPCInstrInfo.td updated: 1.174 -> 1.175
---
Log message:
PHI and INLINEASM are now built-in instructions provided by Target.td
---
Diffs of the changes: (+1 -5)
PPCInstrFormats.td |3 +--
PPCInstrInfo.td|3 ---
2 files changed, 1 insertion(+), 5 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.63
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.64
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.63 Mon Dec 19 18:26:01 2005
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Thu Jan 26 19:46:15 2006
@@ -644,9 +644,8 @@
}
//===--===//
-def NoItin : InstrItinClass;
class Pseudo pattern>
-: I<0, OL, asmstr, NoItin> {
+: I<0, OL, asmstr, NoItinerary> {
let PPC64 = 0;
let VMX = 0;
let Pattern = pattern;
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.174
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.175
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.174 Wed Jan 11 20:05:36 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Thu Jan 26 19:46:15 2006
@@ -194,7 +194,6 @@
// PowerPC Instruction Definitions.
// Pseudo-instructions:
-def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
let isLoad = 1, hasCtrlDep = 1 in {
def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
@@ -1087,8 +1086,6 @@
// PowerPCInstrInfo Definition
//
def PowerPCInstrInfo : InstrInfo {
- let PHIInst = PHI;
-
let TSFlagsFields = [ "VMX", "PPC64" ];
let TSFlagsShifts = [ 0, 1 ];
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.66 -> 1.67
PPCInstrInfo.td updated: 1.201 -> 1.202
---
Log message:
Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
---
Diffs of the changes: (+8 -9)
PPCInstrFormats.td |2 +-
PPCInstrInfo.td| 15 +++
2 files changed, 8 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.66
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.67
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.66 Sun Mar 12 23:15:10 2006
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Tue Mar 21 19:44:36 2006
@@ -595,8 +595,8 @@
: I<4, OL, asmstr, itin> {
bits<5> VD;
bits<5> VA;
- bits<5> VB;
bits<5> VC;
+ bits<5> VB;
let Pattern = pattern;
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.201
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.202
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.201 Mon Mar 20 18:51:38 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Mar 21 19:44:36 2006
@@ -948,22 +948,21 @@
let PPC970_Unit = 5 in { // VALU Operations.
// VA-Form instructions. 3-input AltiVec ops.
-def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
+def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
"vmaddfp $vD, $vA, $vC, $vB", VecFP,
[(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
VRRC:$vB))]>,
Requires<[FPContractions]>;
-def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
+def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
"vnmsubfp $vD, $vA, $vC, $vB", VecFP,
- [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA,
- VRRC:$vC),
- VRRC:$vB)))]>,
+ [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
+ VRRC:$vB)))]>,
Requires<[FPContractions]>;
-def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
- "vperm $vD, $vA, $vB, $vC", VecPerm,
+def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
+ "vperm $vD, $vA, $vC, $vB", VecPerm,
[(set VRRC:$vD,
- (PPCvperm (v4f32 VRRC:$vA), VRRC:$vB,
VRRC:$vC))]>;
+ (PPCvperm (v4f32 VRRC:$vA), VRRC:$vC,
VRRC:$vB))]>;
// VX-Form instructions. AltiVec arithmetic ops.
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.81 -> 1.82
PPCInstrInfo.td updated: 1.255 -> 1.256
---
Log message:
dform 8/9 are identical to dform 1
---
Diffs of the changes: (+6 -15)
PPCInstrFormats.td |9 -
PPCInstrInfo.td| 12 ++--
2 files changed, 6 insertions(+), 15 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.81
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.82
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.81 Mon Nov 6 19:51:50 2006
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Fri Nov 10 11:51:02 2006
@@ -174,15 +174,6 @@
let L = PPC64;
}
-class DForm_8 opcode, dag OL, string asmstr, InstrItinClass itin,
- list pattern>
- : DForm_1 {
-}
-
-class DForm_9 opcode, dag OL, string asmstr, InstrItinClass itin,
- list pattern>
- : DForm_1 {
-}
// 1.7.5 DS-Form
class DSForm_1 opcode, bits<2> xo, dag OL, string asmstr,
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.255
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.256
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.255 Thu Nov 9 20:08:47 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Fri Nov 10 11:51:02 2006
@@ -422,10 +422,10 @@
"lwz $rD, $src", LdStGeneral,
[(set GPRC:$rD, (load iaddr:$src))]>;
-def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src),
+def LFS : DForm_1<48, (ops F4RC:$rD, memri:$src),
"lfs $rD, $src", LdStLFDU,
[(set F4RC:$rD, (load iaddr:$src))]>;
-def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src),
+def LFD : DForm_1<50, (ops F8RC:$rD, memri:$src),
"lfd $rD, $src", LdStLFD,
[(set F8RC:$rD, (load iaddr:$src))]>;
@@ -452,11 +452,11 @@
"lwzu $rD, $disp($rA)", LdStGeneral,
[]>, RegConstraint<"$rA = $rA_result">;
-def LFSU : DForm_8<49, (ops F4RC:$rD, ptr_rc:$rA_result, i32imm:$disp,
+def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$rA_result, i32imm:$disp,
ptr_rc:$rA),
"lfs $rD, $disp($rA)", LdStLFDU,
[]>, RegConstraint<"$rA = $rA_result">;
-def LFDU : DForm_8<51, (ops F8RC:$rD, ptr_rc:$rA_result, i32imm:$disp,
+def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$rA_result, i32imm:$disp,
ptr_rc:$rA),
"lfd $rD, $disp($rA)", LdStLFD,
[]>, RegConstraint<"$rA = $rA_result">;
@@ -537,10 +537,10 @@
"cmplwi $dst, $src1, $src2", IntCompare>;
}
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
-def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst),
+def STFS : DForm_1<52, (ops F4RC:$rS, memri:$dst),
"stfs $rS, $dst", LdStUX,
[(store F4RC:$rS, iaddr:$dst)]>;
-def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst),
+def STFD : DForm_1<54, (ops F8RC:$rS, memri:$dst),
"stfd $rS, $dst", LdStUX,
[(store F8RC:$rS, iaddr:$dst)]>;
}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.73 -> 1.74
PPCInstrInfo.td updated: 1.220 -> 1.221
---
Log message:
Add PowerPC intrinsics to support dcbz[l]
---
Diffs of the changes: (+25 -0)
PPCInstrFormats.td | 17 +
PPCInstrInfo.td|8
2 files changed, 25 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.73
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.74
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.73 Wed Apr 5 17:27:14 2006
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Tue Jun 6 16:29:23 2006
@@ -325,6 +325,23 @@
: XForm_base_r3xo {
}
+// DCB_Form - Form X instruction, used for dcb* instructions.
+class DCB_Form xo, bits<5> immfield, dag OL, string asmstr,
+ InstrItinClass itin, list pattern>
+ : I<31, OL, asmstr, itin> {
+ bits<5> A;
+ bits<5> B;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = immfield;
+ let Inst{11-15} = A;
+ let Inst{16-20} = B;
+ let Inst{21-30} = xo;
+ let Inst{31}= 0;
+}
+
+
// DSS_Form - Form X instruction, used for altivec dss* instructions.
class DSS_Form xo, dag OL, string asmstr,
InstrItinClass itin, list pattern>
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.220
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.221
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.220 Wed May 17 14:00:46 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Jun 6 16:29:23 2006
@@ -318,6 +318,14 @@
[(PPCbctrl)]>;
}
+// DCB* instructions.
+def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst),
+"dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
+PPC970_DGroup_Single;
+def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
+ "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
+ PPC970_DGroup_Single;
+
// D-Form instructions. Most instructions that perform an operation on a
// register and an immediate are of this type.
//
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.74 -> 1.75
PPCInstrInfo.td updated: 1.229 -> 1.230
---
Log message:
remove unused flag
---
Diffs of the changes: (+0 -2)
PPCInstrFormats.td |1 -
PPCInstrInfo.td|1 -
2 files changed, 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.74
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.75
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.74 Tue Jun 6 16:29:23 2006
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Tue Jun 20 18:15:07 2006
@@ -16,7 +16,6 @@
field bits<32> Inst;
bit PPC64 = 0; // Default value, override with isPPC64
- bit VMX = 0;// Default value, override with isVMX
let Name = "";
let Namespace = "PPC";
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.229
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.230
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.229 Tue Jun 20 18:11:36 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Jun 20 18:15:07 2006
@@ -167,7 +167,6 @@
// PowerPC Flag Definitions.
class isPPC64 { bit PPC64 = 1; }
-class isVMX { bit VMX = 1; }
class isDOT {
list Defs = [CR0];
bit RC = 1;
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td PPCRegisterInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrFormats.td updated: 1.55 -> 1.56
PPCInstrInfo.td updated: 1.143 -> 1.144
PPCRegisterInfo.td updated: 1.20 -> 1.21
---
Log message:
Some first bits of AltiVec stuff: Instruction Formats, Encodings, and
Registers. Apologies to Jim if the scheduling info so far isn't accurate.
There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.
---
Diffs of the changes: (+123 -1)
PPCInstrFormats.td | 45 +
PPCInstrInfo.td| 49 +
PPCRegisterInfo.td | 30 +-
3 files changed, 123 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.55
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.56
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.55 Tue Oct 25 15:58:43 2005
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Tue Nov 22 23:29:52 2005
@@ -548,6 +548,51 @@
let Inst{31}= RC;
}
+// E-1 VA-Form
+class VAForm_1 xo, dag OL, string asmstr,
+ InstrItinClass itin, list pattern>
+: I<4, OL, asmstr, itin> {
+ bits<5> VD;
+ bits<5> VA;
+ bits<5> VB;
+ bits<5> VC;
+
+ let Inst{6-10} = VD;
+ let Inst{11-15} = VA;
+ let Inst{16-20} = VB;
+ let Inst{21-25} = VC;
+ let Inst{26-31} = xo;
+}
+
+// E-2 VX-Form
+class VXForm_1 xo, dag OL, string asmstr,
+ InstrItinClass itin, list pattern>
+: I<4, OL, asmstr, itin> {
+ bits<5> VD;
+ bits<5> VA;
+ bits<5> VB;
+
+ let Inst{6-10} = VD;
+ let Inst{11-15} = VA;
+ let Inst{16-20} = VB;
+ let Inst{21-31} = xo;
+}
+
+// E-4 VXR-Form
+class VXRForm_1 xo, bit rc, dag OL, string asmstr,
+ InstrItinClass itin, list pattern>
+: I<4, OL, asmstr, itin> {
+ bits<5> VD;
+ bits<5> VA;
+ bits<5> VB;
+
+ let Inst{6-10} = VD;
+ let Inst{11-15} = VA;
+ let Inst{16-20} = VB;
+ let Inst{21}= rc;
+ let Inst{22-31} = xo;
+}
+
//===--===//
def NoItin : InstrItinClass;
class Pseudo pattern>
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.143
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.144
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.143 Thu Nov 17 13:16:08 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Nov 22 23:29:52 2005
@@ -360,6 +360,18 @@
"lwzx $dst, $base, $index", LdStGeneral>;
def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
"ldx $dst, $base, $index", LdStLD>, isPPC64;
+def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
+ "lvebx $vD, $base, $rA", LdStGeneral>;
+def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
+ "lvehx $vD, $base, $rA", LdStGeneral>;
+def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
+ "lvewx $vD, $base, $rA", LdStGeneral>;
+def LVX : XForm_1<31, 103, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
+ "lvx $vD, $base, $rA", LdStGeneral>;
+def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
+ "lvsl $vD, $base, $rA", LdStGeneral>;
+def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
+ "lvsl $vD, $base, $rA", LdStGeneral>;
}
def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"nand $rA, $rS, $rB", IntGeneral,
@@ -431,6 +443,14 @@
"stdx $rS, $rA, $rB", LdStSTD>, isPPC64;
def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
"stdux $rS, $rA, $rB", LdStSTD>, isPPC64;
+def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
+ "stvebx $rS, $rA, $rB", LdStGeneral>;
+def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
+ "stvehx $rS, $rA, $rB", LdStGeneral>;
+def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
+ "stvewx $rS, $rA, $rB", LdStGeneral>;
+def STVX : XForm_8<31, 231, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
+ "stvx $rS, $rA, $rB", LdStGeneral>;
}
def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
"srawi $rA, $rS, $SH", IntShift,
@@ -746,6 +766,35 @@
"rldicr $rA, $rS, $SH, $ME", IntRotateD,
[]>, isPPC64;
+// VA-Form instructions. 3-input AltiVec ops.
+def VMADDFP: VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
+ "vmaddfp $vD, $vA, $vB, $vC", VecFP,
+ []>;
+
+// VX-Form instructions. AltiVec arithmetic ops.
+def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+
