[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.122 - 1.123
PPCRegisterInfo.h updated: 1.34 - 1.35
---
Log message:
eliminateFrameIndex() change.
---
Diffs of the changes: (+4 -2)
PPCRegisterInfo.cpp |4 +++-
PPCRegisterInfo.h |2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.122
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.123
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.122 Wed Apr 25 17:13:27 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue May 1 04:13:03 2007
@@ -589,7 +589,9 @@
}
void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
- RegScavenger *RS) const {
+ int SPAdj, RegScavenger *RS) const {
+ assert(SPAdj == 0 Unexpected);
+
// Get the instruction.
MachineInstr MI = *II;
// Get the instruction's basic block.
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.34
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.35
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.34 Tue Mar 20 03:08:30 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Tue May 1 04:13:03 2007
@@ -80,7 +80,7 @@
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
void eliminateFrameIndex(MachineBasicBlock::iterator II,
- RegScavenger *RS = NULL) const;
+ int SPAdj, RegScavenger *RS = NULL) const;
/// determineFrameLayout - Determine the size of the frame and maximum call
/// frame size.
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.121 - 1.122
---
Log message:
Match MachineFunction::UsedPhysRegs changes.
---
Diffs of the changes: (+6 -7)
PPCRegisterInfo.cpp | 13 ++---
1 files changed, 6 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.121
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.122
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.121 Tue Apr 3 07:35:28 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed Apr 25 17:13:27 2007
@@ -739,16 +739,16 @@
// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
// instruction selector. Based on the vector registers that have been used,
// transform this into the appropriate ORI instruction.
-static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs,
- const TargetInstrInfo TII) {
+static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo TII) {
+ MachineFunction *MF = MI-getParent()-getParent();
+
unsigned UsedRegMask = 0;
for (unsigned i = 0; i != 32; ++i)
-if (UsedRegs[VRRegNo[i]])
+if (MF-isPhysRegUsed(VRRegNo[i]))
UsedRegMask |= 1 (31-i);
// Live in and live out values already must be in the mask, so don't bother
// marking them.
- MachineFunction *MF = MI-getParent()-getParent();
for (MachineFunction::livein_iterator I =
MF-livein_begin(), E = MF-livein_end(); I != E; ++I) {
unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I-first);
@@ -846,8 +846,7 @@
PPCFunctionInfo *FI = MF.getInfoPPCFunctionInfo();
unsigned LR = getRARegister();
FI-setUsesLR(MF.isPhysRegUsed(LR));
- MF.changePhyRegUsed(LR, false);
-
+ MF.setPhysRegUnused(LR);
// Save R31 if necessary
int FPSI = FI-getFramePointerSaveIndex();
@@ -883,7 +882,7 @@
// process it.
for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
if (MBBI-getOpcode() == PPC::UPDATE_VRSAVE) {
- HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs(), TII);
+ HandleVRSaveUpdate(MBBI, TII);
break;
}
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.117 - 1.118
---
Log message:
Protect R31's frame offset from being used by callee-saved registers, when R31
is the frame pointer.
---
Diffs of the changes: (+20 -0)
PPCRegisterInfo.cpp | 20
1 files changed, 20 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.117
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.118
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.117 Tue Mar 20 03:08:30 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed Mar 21 11:44:14 2007
@@ -891,6 +891,26 @@
unsigned LR = getRARegister();
FI-setUsesLR(MF.isPhysRegUsed(LR));
MF.changePhyRegUsed(LR, false);
+
+
+ // Save R31 if necessary
+ int FPSI = FI-getFramePointerSaveIndex();
+ bool IsPPC64 = Subtarget.isPPC64();
+ bool IsELF_ABI = Subtarget.isELF_ABI();
+ const MachineFrameInfo *MFI = MF.getFrameInfo();
+
+ // If the frame pointer save index hasn't been defined yet.
+ if (!FPSI (NoFramePointerElim || MFI-hasVarSizedObjects())
+ IsELF_ABI) {
+// Find out what the fix offset of the frame pointer save area.
+int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
+ !IsELF_ABI);
+// Allocate the frame index for frame pointer save area.
+FPSI = MF.getFrameInfo()-CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
+// Save the result.
+FI-setFramePointerSaveIndex(FPSI);
+ }
+
}
void PPCRegisterInfo::emitPrologue(MachineFunction MF) const {
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.116 - 1.117
PPCRegisterInfo.h updated: 1.33 - 1.34
---
Log message:
Added MRegisterInfo hook to re-materialize an instruction.
---
Diffs of the changes: (+12 -0)
PPCRegisterInfo.cpp |9 +
PPCRegisterInfo.h |3 +++
2 files changed, 12 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.116
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.117
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.116 Tue Mar 6 04:05:14 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Mar 20 03:08:30 2007
@@ -239,6 +239,15 @@
}
}
+void PPCRegisterInfo::reMaterialize(MachineBasicBlock MBB,
+MachineBasicBlock::iterator I,
+unsigned DestReg,
+const MachineInstr *Orig) const {
+ MachineInstr *MI = Orig-clone();
+ MI-getOperand(0).setReg(DestReg);
+ MBB.insert(I, MI);
+}
+
const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const {
// 32-bit Darwin calling convention.
static const unsigned Darwin32_CalleeSavedRegs[] = {
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.33
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.34
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.33 Tue Mar 6 04:05:14 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Tue Mar 20 03:08:30 2007
@@ -49,6 +49,9 @@
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
+ void reMaterialize(MachineBasicBlock MBB, MachineBasicBlock::iterator MI,
+ unsigned DestReg, const MachineInstr *Orig) const;
+
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
/// copy instructions, turning them into load/store instructions.
virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.115 - 1.116
PPCRegisterInfo.h updated: 1.32 - 1.33
---
Log message:
Minor interface change.
---
Diffs of the changes: (+4 -2)
PPCRegisterInfo.cpp |3 ++-
PPCRegisterInfo.h |3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.115
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.116
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.115 Tue Feb 27 18:19:26 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Mar 6 04:05:14 2007
@@ -874,7 +874,8 @@
MFI-setStackSize(FrameSize);
}
-void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction MF)
+void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction MF,
+ RegScavenger *RS)
const {
// Save and clear the LR state.
PPCFunctionInfo *FI = MF.getInfoPPCFunctionInfo();
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.32
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.33
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.32 Tue Feb 27 18:19:26 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Tue Mar 6 04:05:14 2007
@@ -83,7 +83,8 @@
/// frame size.
void determineFrameLayout(MachineFunction MF) const;
- void processFunctionBeforeCalleeSavedScan(MachineFunction MF) const;
+ void processFunctionBeforeCalleeSavedScan(MachineFunction MF,
+RegScavenger *RS = NULL) const;
void emitPrologue(MachineFunction MF) const;
void emitEpilogue(MachineFunction MF, MachineBasicBlock MBB) const;
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.114 - 1.115
PPCRegisterInfo.h updated: 1.31 - 1.32
---
Log message:
PEI now passes a RegScavenger ptr to eliminateFrameIndex.
---
Diffs of the changes: (+4 -3)
PPCRegisterInfo.cpp |4 ++--
PPCRegisterInfo.h |3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.114
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.115
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.114 Tue Feb 27 05:55:45 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Feb 27 18:19:26 2007
@@ -623,8 +623,8 @@
MBB.erase(II);
}
-void
-PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
+void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+ RegScavenger *RS) const {
// Get the instruction.
MachineInstr MI = *II;
// Get the instruction's basic block.
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.31
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.32
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.31 Tue Feb 27 05:55:45 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Tue Feb 27 18:19:26 2007
@@ -76,7 +76,8 @@
bool usesLR(MachineFunction MF) const;
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
- void eliminateFrameIndex(MachineBasicBlock::iterator II) const;
+ void eliminateFrameIndex(MachineBasicBlock::iterator II,
+ RegScavenger *RS = NULL) const;
/// determineFrameLayout - Determine the size of the frame and maximum call
/// frame size.
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.109 - 1.110
---
Log message:
By default, spills kills the register being stored.
---
Diffs of the changes: (+15 -15)
PPCRegisterInfo.cpp | 30 +++---
1 files changed, 15 insertions(+), 15 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.109
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.110
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.109 Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Feb 22 19:10:03 2007
@@ -104,34 +104,34 @@
const TargetRegisterClass *RC) const {
if (RC == PPC::GPRCRegisterClass) {
if (SrcReg != PPC::LR) {
- addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(SrcReg),
-FrameIdx);
+ addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
+.addReg(SrcReg, false, false, true), FrameIdx);
} else {
// FIXME: this spills LR immediately to memory in one step. To do this,
// we use R11, which we know cannot be used in the prolog/epilog. This
is
// a hack.
BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11);
- addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R11),
-FrameIdx);
+ addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
+.addReg(PPC::R11, false, false, true), FrameIdx);
}
} else if (RC == PPC::G8RCRegisterClass) {
if (SrcReg != PPC::LR8) {
- addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(SrcReg),
-FrameIdx);
+ addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD))
+.addReg(SrcReg, false, false, true), FrameIdx);
} else {
// FIXME: this spills LR immediately to memory in one step. To do this,
// we use R11, which we know cannot be used in the prolog/epilog. This
is
// a hack.
BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11);
- addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(PPC::X11),
-FrameIdx);
+ addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD))
+.addReg(PPC::X11, false, false, true), FrameIdx);
}
} else if (RC == PPC::F8RCRegisterClass) {
-addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD)).addReg(SrcReg),
- FrameIdx);
+addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD))
+ .addReg(SrcReg, false, false, true), FrameIdx);
} else if (RC == PPC::F4RCRegisterClass) {
-addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS)).addReg(SrcReg),
- FrameIdx);
+addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS))
+ .addReg(SrcReg, false, false, true), FrameIdx);
} else if (RC == PPC::CRRCRegisterClass) {
// FIXME: We use R0 here, because it isn't available for RA.
// We need to store the CR in the low 4-bits of the saved value. First,
@@ -147,8 +147,8 @@
.addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
}
-addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R0),
- FrameIdx);
+addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
+ .addReg(PPC::R0, false, false, true), FrameIdx);
} else if (RC == PPC::VRRCRegisterClass) {
// We don't have indexed addressing for vector loads. Emit:
// R11 = ADDI FI#
@@ -158,7 +158,7 @@
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
FrameIdx, 0, 0);
BuildMI(MBB, MI, TII.get(PPC::STVX))
- .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
+ .addReg(SrcReg, false, false, true).addReg(PPC::R0).addReg(PPC::R0);
} else {
assert(0 Unknown regclass!);
abort();
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.107 - 1.108
PPCRegisterInfo.h updated: 1.26 - 1.27
---
Log message:
Re-apply my liveintervalanalysis changes. Now with PR1207:
http://llvm.org/PR1207 fixes.
---
Diffs of the changes: (+32 -9)
PPCRegisterInfo.cpp | 39 ++-
PPCRegisterInfo.h |2 ++
2 files changed, 32 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.107
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.108
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.107 Sun Feb 18 21:20:00 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Feb 19 15:49:54 2007
@@ -34,6 +34,7 @@
#include llvm/Support/CommandLine.h
#include llvm/Support/Debug.h
#include llvm/Support/MathExtras.h
+#include llvm/ADT/BitVector.h
#include llvm/ADT/STLExtras.h
#include cstdlib
using namespace llvm;
@@ -338,6 +339,35 @@
Darwin32_CalleeSavedRegClasses;
}
+// needsFP - Return true if the specified function should have a dedicated
frame
+// pointer register. This is true if the function has variable sized allocas
or
+// if frame pointer elimination is disabled.
+//
+static bool needsFP(const MachineFunction MF) {
+ const MachineFrameInfo *MFI = MF.getFrameInfo();
+ return NoFramePointerElim || MFI-hasVarSizedObjects();
+}
+
+BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction MF) const {
+ BitVector Reserved(getNumRegs());
+ Reserved.set(PPC::R0);
+ Reserved.set(PPC::R1);
+ Reserved.set(PPC::LR);
+ // In Linux, r2 is reserved for the OS.
+ if (!Subtarget.isDarwin())
+Reserved.set(PPC::R2);
+ // On PPC64, r13 is the thread pointer. Never allocate this register.
+ // Note that this is overconservative, as it also prevents allocation of
+ // R31 when the FP is not needed.
+ if (Subtarget.isPPC64()) {
+Reserved.set(PPC::R13);
+Reserved.set(PPC::R31);
+ }
+ if (needsFP(MF))
+Reserved.set(PPC::R31);
+ return Reserved;
+}
+
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
/// copy instructions, turning them into load/store instructions.
MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
@@ -398,15 +428,6 @@
// Stack Frame Processing methods
//===--===//
-// needsFP - Return true if the specified function should have a dedicated
frame
-// pointer register. This is true if the function has variable sized allocas
or
-// if frame pointer elimination is disabled.
-//
-static bool needsFP(const MachineFunction MF) {
- const MachineFrameInfo *MFI = MF.getFrameInfo();
- return NoFramePointerElim || MFI-hasVarSizedObjects();
-}
-
// hasFP - Return true if the specified function actually has a dedicated frame
// pointer register. This is true if the function needs a frame pointer and
has
// a non-zero stack size.
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.26
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.27
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.26 Sun Feb 18 21:20:00 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Mon Feb 19 15:49:54 2007
@@ -58,6 +58,8 @@
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
+ BitVector getReservedRegs(const MachineFunction MF) const;
+
/// targetHandlesStackFrameRounding - Returns true if the target is
/// responsible for rounding up the stack frame (probably at emitPrologue
/// time).
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.106 - 1.107
PPCRegisterInfo.h updated: 1.25 - 1.26
---
Log message:
For PR1207: http://llvm.org/PR1207 :
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.
---
Diffs of the changes: (+9 -32)
PPCRegisterInfo.cpp | 39 +--
PPCRegisterInfo.h |2 --
2 files changed, 9 insertions(+), 32 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.106
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.107
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.106 Sat Feb 17 05:06:00 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Sun Feb 18 21:20:00 2007
@@ -34,7 +34,6 @@
#include llvm/Support/CommandLine.h
#include llvm/Support/Debug.h
#include llvm/Support/MathExtras.h
-#include llvm/ADT/BitVector.h
#include llvm/ADT/STLExtras.h
#include cstdlib
using namespace llvm;
@@ -339,35 +338,6 @@
Darwin32_CalleeSavedRegClasses;
}
-// needsFP - Return true if the specified function should have a dedicated
frame
-// pointer register. This is true if the function has variable sized allocas
or
-// if frame pointer elimination is disabled.
-//
-static bool needsFP(const MachineFunction MF) {
- const MachineFrameInfo *MFI = MF.getFrameInfo();
- return NoFramePointerElim || MFI-hasVarSizedObjects();
-}
-
-BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction MF) const {
- BitVector Reserved(getNumRegs());
- Reserved.set(PPC::R0);
- Reserved.set(PPC::R1);
- Reserved.set(PPC::LR);
- // In Linux, r2 is reserved for the OS.
- if (!Subtarget.isDarwin())
-Reserved.set(PPC::R2);
- // On PPC64, r13 is the thread pointer. Never allocate this register.
- // Note that this is overconservative, as it also prevents allocation of
- // R31 when the FP is not needed.
- if (Subtarget.isPPC64()) {
-Reserved.set(PPC::R13);
-Reserved.set(PPC::R31);
- }
- if (needsFP(MF))
-Reserved.set(PPC::R31);
- return Reserved;
-}
-
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
/// copy instructions, turning them into load/store instructions.
MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
@@ -428,6 +398,15 @@
// Stack Frame Processing methods
//===--===//
+// needsFP - Return true if the specified function should have a dedicated
frame
+// pointer register. This is true if the function has variable sized allocas
or
+// if frame pointer elimination is disabled.
+//
+static bool needsFP(const MachineFunction MF) {
+ const MachineFrameInfo *MFI = MF.getFrameInfo();
+ return NoFramePointerElim || MFI-hasVarSizedObjects();
+}
+
// hasFP - Return true if the specified function actually has a dedicated frame
// pointer register. This is true if the function needs a frame pointer and
has
// a non-zero stack size.
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.25
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.26
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.25 Sat Feb 17 05:06:00 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Sun Feb 18 21:20:00 2007
@@ -58,8 +58,6 @@
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
- BitVector getReservedRegs(const MachineFunction MF) const;
-
/// targetHandlesStackFrameRounding - Returns true if the target is
/// responsible for rounding up the stack frame (probably at emitPrologue
/// time).
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.105 - 1.106
PPCRegisterInfo.h updated: 1.24 - 1.25
---
Log message:
Added getReservedRegs().
---
Diffs of the changes: (+32 -9)
PPCRegisterInfo.cpp | 39 ++-
PPCRegisterInfo.h |2 ++
2 files changed, 32 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.105
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.106
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.105 Thu Feb 1 10:31:34 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Sat Feb 17 05:06:00 2007
@@ -34,6 +34,7 @@
#include llvm/Support/CommandLine.h
#include llvm/Support/Debug.h
#include llvm/Support/MathExtras.h
+#include llvm/ADT/BitVector.h
#include llvm/ADT/STLExtras.h
#include cstdlib
using namespace llvm;
@@ -338,6 +339,35 @@
Darwin32_CalleeSavedRegClasses;
}
+// needsFP - Return true if the specified function should have a dedicated
frame
+// pointer register. This is true if the function has variable sized allocas
or
+// if frame pointer elimination is disabled.
+//
+static bool needsFP(const MachineFunction MF) {
+ const MachineFrameInfo *MFI = MF.getFrameInfo();
+ return NoFramePointerElim || MFI-hasVarSizedObjects();
+}
+
+BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction MF) const {
+ BitVector Reserved(getNumRegs());
+ Reserved.set(PPC::R0);
+ Reserved.set(PPC::R1);
+ Reserved.set(PPC::LR);
+ // In Linux, r2 is reserved for the OS.
+ if (!Subtarget.isDarwin())
+Reserved.set(PPC::R2);
+ // On PPC64, r13 is the thread pointer. Never allocate this register.
+ // Note that this is overconservative, as it also prevents allocation of
+ // R31 when the FP is not needed.
+ if (Subtarget.isPPC64()) {
+Reserved.set(PPC::R13);
+Reserved.set(PPC::R31);
+ }
+ if (needsFP(MF))
+Reserved.set(PPC::R31);
+ return Reserved;
+}
+
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
/// copy instructions, turning them into load/store instructions.
MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
@@ -398,15 +428,6 @@
// Stack Frame Processing methods
//===--===//
-// needsFP - Return true if the specified function should have a dedicated
frame
-// pointer register. This is true if the function has variable sized allocas
or
-// if frame pointer elimination is disabled.
-//
-static bool needsFP(const MachineFunction MF) {
- const MachineFrameInfo *MFI = MF.getFrameInfo();
- return NoFramePointerElim || MFI-hasVarSizedObjects();
-}
-
// hasFP - Return true if the specified function actually has a dedicated frame
// pointer register. This is true if the function needs a frame pointer and
has
// a non-zero stack size.
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.24
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.25
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.24 Thu Jan 25 16:25:04 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Sat Feb 17 05:06:00 2007
@@ -58,6 +58,8 @@
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
+ BitVector getReservedRegs(const MachineFunction MF) const;
+
/// targetHandlesStackFrameRounding - Returns true if the target is
/// responsible for rounding up the stack frame (probably at emitPrologue
/// time).
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCTargetAsmInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.101 - 1.102
PPCTargetAsmInfo.cpp updated: 1.14 - 1.15
---
Log message:
Landing pad-less eh for PPC.
---
Diffs of the changes: (+5 -4)
PPCRegisterInfo.cpp |7 +++
PPCTargetAsmInfo.cpp |2 ++
2 files changed, 5 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.101
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.102
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.101 Fri Jan 26 15:22:28 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Jan 29 12:51:14 2007
@@ -756,8 +756,7 @@
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineModuleInfo *MMI = MFI-getMachineModuleInfo();
- // Prepare for debug frame info.
- bool hasDebugInfo = MMI MMI-hasDebugInfo();
+ // Prepare for frame info.
unsigned FrameLabelId = 0;
// Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
@@ -819,7 +818,7 @@
unsigned TargetAlign = MF.getTarget().getFrameInfo()-getStackAlignment();
unsigned MaxAlign = MFI-getMaxAlignment();
- if (hasDebugInfo) {
+ if (MMI) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = MMI-NextLabelID();
BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId);
@@ -870,7 +869,7 @@
}
}
- if (hasDebugInfo) {
+ if (MMI) {
std::vectorMachineMove Moves = MMI-getFrameMoves();
if (NegFrameSize) {
Index: llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp:1.14
llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp:1.15
--- llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp:1.14 Wed Jan 17 19:15:58 2007
+++ llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cppMon Jan 29 12:51:14 2007
@@ -51,12 +51,14 @@
PrivateGlobalPrefix = L;
ConstantPoolSection = \t.const\t;
JumpTableDataSection = .const;
+ GlobalDirective = \t.globl\t;
CStringSection = \t.cstring;
StaticCtorsSection = .mod_init_func;
StaticDtorsSection = .mod_term_func;
UsedDirective = \t.no_dead_strip\t;
WeakRefDirective = \t.weak_reference\t;
HiddenDirective = \t.private_extern\t;
+ SupportsExceptionHandling = true;
// In non-PIC modes, emit a special label before jump tables so that the
// linker can perform more accurate dead code stripping.
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.102 - 1.103
---
Log message:
Only gather frame info if debug or eh.
---
Diffs of the changes: (+2 -2)
PPCRegisterInfo.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.102
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.103
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.102 Mon Jan 29 12:51:14 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Jan 29 17:20:22 2007
@@ -818,7 +818,7 @@
unsigned TargetAlign = MF.getTarget().getFrameInfo()-getStackAlignment();
unsigned MaxAlign = MFI-getMaxAlignment();
- if (MMI) {
+ if (MMI MMI-needsFrameInfo()) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = MMI-NextLabelID();
BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId);
@@ -869,7 +869,7 @@
}
}
- if (MMI) {
+ if (MMI MMI-needsFrameInfo()) {
std::vectorMachineMove Moves = MMI-getFrameMoves();
if (NegFrameSize) {
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.97 - 1.98
PPCRegisterInfo.h updated: 1.23 - 1.24
---
Log message:
- Tell PEI that PPC will handle stack frame rounding itself.
- Do not round up to max. alignment of stack object if it is stack alignment.
It will have to be handled with dynamic aligning code.
---
Diffs of the changes: (+7 -7)
PPCRegisterInfo.cpp |9 ++---
PPCRegisterInfo.h |5 +
2 files changed, 7 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.97
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.98
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.97Wed Jan 24 12:45:13 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Jan 25 16:25:04 2007
@@ -451,9 +451,6 @@
// Determine the maximum call stack size. maxCallFrameSize may be
// less than the minimum.
unsigned maxCallFrameSize = MFI-getMaxCallFrameSize();
- unsigned getMinCallFrameSize =
-PPCFrameInfo::getMinCallFrameSize(LP64);
- maxCallFrameSize = std::max(maxCallFrameSize, getMinCallFrameSize);
// Get the total frame size.
unsigned FrameSize = MFI-getStackSize();
@@ -712,11 +709,9 @@
// Get the alignments provided by the target, and the maximum alignment
// (if any) of the fixed frame objects.
- unsigned TargetAlign = MF.getTarget().getFrameInfo()-getStackAlignment();
unsigned MaxAlign = MFI-getMaxAlignment();
- unsigned Align = std::max(TargetAlign, MaxAlign);
- assert(isPowerOf2_32(Align) Alignment is not power of 2);
- unsigned AlignMask = Align - 1; //
+ unsigned TargetAlign = MF.getTarget().getFrameInfo()-getStackAlignment();
+ unsigned AlignMask = TargetAlign - 1; //
// If we are a leaf function, and use up to 224 bytes of stack space,
// don't have a frame pointer, calls, or dynamic alloca then we do not need
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.23
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.24
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.23 Wed Jan 24 12:45:13 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Thu Jan 25 16:25:04 2007
@@ -58,6 +58,11 @@
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
+ /// targetHandlesStackFrameRounding - Returns true if the target is
+ /// responsible for rounding up the stack frame (probably at emitPrologue
+ /// time).
+ bool targetHandlesStackFrameRounding() const { return true; }
+
bool hasFP(const MachineFunction MF) const;
void eliminateCallFramePseudoInstr(MachineFunction MF,
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
On 25-Jan-07, at 06:25 PM, Evan Cheng wrote: Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.97 llvm/lib/ Target/PowerPC/PPCRegisterInfo.cpp:1.98 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.97 Wed Jan 24 12:45:13 2007 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Jan 25 16:25:04 2007 @@ -451,9 +451,6 @@ // Determine the maximum call stack size. maxCallFrameSize may be // less than the minimum. unsigned maxCallFrameSize = MFI-getMaxCallFrameSize(); - unsigned getMinCallFrameSize = -PPCFrameInfo::getMinCallFrameSize(LP64); - maxCallFrameSize = std::max(maxCallFrameSize, getMinCallFrameSize); // Get the total frame size. unsigned FrameSize = MFI-getStackSize(); Why did you remove this? -- Jim smime.p7s Description: S/MIME cryptographic signature ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
NVM. I forgot this was redundant. -- Jim On 25-Jan-07, at 06:40 PM, Jim Laskey wrote: On 25-Jan-07, at 06:25 PM, Evan Cheng wrote: Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.97 llvm/lib/ Target/PowerPC/PPCRegisterInfo.cpp:1.98 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.97 Wed Jan 24 12:45:13 2007 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Jan 25 16:25:04 2007 @@ -451,9 +451,6 @@ // Determine the maximum call stack size. maxCallFrameSize may be // less than the minimum. unsigned maxCallFrameSize = MFI-getMaxCallFrameSize(); - unsigned getMinCallFrameSize = -PPCFrameInfo::getMinCallFrameSize(LP64); - maxCallFrameSize = std::max(maxCallFrameSize, getMinCallFrameSize); // Get the total frame size. unsigned FrameSize = MFI-getStackSize(); Why did you remove this? -- Jim ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits smime.p7s Description: S/MIME cryptographic signature ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.96 - 1.97
PPCRegisterInfo.h updated: 1.22 - 1.23
---
Log message:
Repair debug frames as a prelude to eh_frames. Switched to using MachineMoves
by value so that clean up is less confusing (these vectors tend to be small.)
---
Diffs of the changes: (+44 -16)
PPCRegisterInfo.cpp | 58 ++--
PPCRegisterInfo.h |2 -
2 files changed, 44 insertions(+), 16 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.96
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.97
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.96Mon Jan 22 18:55:21 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed Jan 24 12:45:13 2007
@@ -762,6 +762,10 @@
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineDebugInfo *DebugInfo = MFI-getMachineDebugInfo();
+ // Prepare for debug frame info.
+ bool hasInfo = DebugInfo DebugInfo-hasInfo();
+ unsigned FrameLabelId = 0;
+
// Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
// process it.
for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
@@ -821,6 +825,12 @@
unsigned TargetAlign = MF.getTarget().getFrameInfo()-getStackAlignment();
unsigned MaxAlign = MFI-getMaxAlignment();
+ if (hasInfo) {
+// Mark effective beginning of when frame pointer becomes valid.
+FrameLabelId = DebugInfo-NextLabelID();
+BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(FrameLabelId);
+ }
+
// Adjust stack pointer: r1 += NegFrameSize.
// If there is a preferred stack alignment, align R1 now
if (!IsPPC64) {
@@ -866,26 +876,44 @@
}
}
- if (DebugInfo DebugInfo-hasInfo()) {
-std::vectorMachineMove * Moves = DebugInfo-getFrameMoves();
-unsigned LabelID = DebugInfo-NextLabelID();
+ if (hasInfo) {
+std::vectorMachineMove Moves = DebugInfo-getFrameMoves();
-// Mark effective beginning of when frame pointer becomes valid.
-BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(LabelID);
+if (NegFrameSize) {
+ // Show update of SP.
+ MachineLocation SPDst(MachineLocation::VirtualFP);
+ MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
+ Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
+} else {
+ MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
+ Moves.push_back(MachineMove(FrameLabelId, SP, SP));
+}
-// Show update of SP.
-MachineLocation SPDst(MachineLocation::VirtualFP);
-MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
-Moves.push_back(new MachineMove(LabelID, SPDst, SPSrc));
+if (HasFP) {
+ MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
+ MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
+ Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
+}
// Add callee saved registers to move list.
const std::vectorCalleeSavedInfo CSI = MFI-getCalleeSavedInfo();
for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
- MachineLocation CSDst(MachineLocation::VirtualFP,
-MFI-getObjectOffset(CSI[I].getFrameIdx()));
- MachineLocation CSSrc(CSI[I].getReg());
- Moves.push_back(new MachineMove(LabelID, CSDst, CSSrc));
+ int Offset = MFI-getObjectOffset(CSI[I].getFrameIdx());
+ unsigned Reg = CSI[I].getReg();
+ if (Reg == PPC::LR || Reg == PPC::LR8) continue;
+ MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
+ MachineLocation CSSrc(Reg);
+ Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
}
+
+// Mark effective beginning of when frame pointer is ready.
+unsigned ReadyLabelId = DebugInfo-NextLabelID();
+BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(ReadyLabelId);
+
+MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
+ (IsPPC64 ? PPC::X1 : PPC::R1));
+MachineLocation FPSrc(MachineLocation::VirtualFP);
+Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
}
// If there is a frame pointer, copy R1 into R31
@@ -983,12 +1011,12 @@
return hasFP(MF) ? PPC::X31 : PPC::X1;
}
-void PPCRegisterInfo::getInitialFrameState(std::vectorMachineMove * Moves)
+void PPCRegisterInfo::getInitialFrameState(std::vectorMachineMove Moves)
const
{
// Initial state of the frame pointer is R1.
MachineLocation Dst(MachineLocation::VirtualFP);
MachineLocation Src(PPC::R1, 0);
- Moves.push_back(new MachineMove(0, Dst, Src));
+ Moves.push_back(MachineMove(0, Dst, Src));
}
#include PPCGenRegisterInfo.inc
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.22
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.23
---
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.94 - 1.95
PPCRegisterInfo.h updated: 1.20 - 1.21
---
Log message:
Fix naming inconsistency.
---
Diffs of the changes: (+12 -12)
PPCRegisterInfo.cpp | 20 ++--
PPCRegisterInfo.h |4 ++--
2 files changed, 12 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.94
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.95
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.94Thu Dec 7 16:21:48 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Jan 2 15:33:01 2007
@@ -238,9 +238,9 @@
}
}
-const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
+const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const {
// 32-bit Darwin calling convention.
- static const unsigned Darwin32_CalleeSaveRegs[] = {
+ static const unsigned Darwin32_CalleeSavedRegs[] = {
PPC::R13, PPC::R14, PPC::R15,
PPC::R16, PPC::R17, PPC::R18, PPC::R19,
PPC::R20, PPC::R21, PPC::R22, PPC::R23,
@@ -261,7 +261,7 @@
PPC::LR, 0
};
// 64-bit Darwin calling convention.
- static const unsigned Darwin64_CalleeSaveRegs[] = {
+ static const unsigned Darwin64_CalleeSavedRegs[] = {
PPC::X14, PPC::X15,
PPC::X16, PPC::X17, PPC::X18, PPC::X19,
PPC::X20, PPC::X21, PPC::X22, PPC::X23,
@@ -282,14 +282,14 @@
PPC::LR8, 0
};
- return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegs :
- Darwin32_CalleeSaveRegs;
+ return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
+ Darwin32_CalleeSavedRegs;
}
const TargetRegisterClass* const*
-PPCRegisterInfo::getCalleeSaveRegClasses() const {
+PPCRegisterInfo::getCalleeSavedRegClasses() const {
// 32-bit Darwin calling convention.
- static const TargetRegisterClass * const Darwin32_CalleeSaveRegClasses[] = {
+ static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = {
PPC::GPRCRegClass,PPC::GPRCRegClass,PPC::GPRCRegClass,
PPC::GPRCRegClass,PPC::GPRCRegClass,PPC::GPRCRegClass,PPC::GPRCRegClass,
PPC::GPRCRegClass,PPC::GPRCRegClass,PPC::GPRCRegClass,PPC::GPRCRegClass,
@@ -312,7 +312,7 @@
};
// 64-bit Darwin calling convention.
- static const TargetRegisterClass * const Darwin64_CalleeSaveRegClasses[] = {
+ static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = {
PPC::G8RCRegClass,PPC::G8RCRegClass,
PPC::G8RCRegClass,PPC::G8RCRegClass,PPC::G8RCRegClass,PPC::G8RCRegClass,
PPC::G8RCRegClass,PPC::G8RCRegClass,PPC::G8RCRegClass,PPC::G8RCRegClass,
@@ -334,8 +334,8 @@
PPC::G8RCRegClass, 0
};
- return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegClasses :
- Darwin32_CalleeSaveRegClasses;
+ return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses :
+ Darwin32_CalleeSavedRegClasses;
}
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.20
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.21
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.20 Wed Dec 6 11:42:06 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Tue Jan 2 15:33:01 2007
@@ -54,9 +54,9 @@
virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
int FrameIndex) const;
- const unsigned *getCalleeSaveRegs() const;
+ const unsigned *getCalleeSavedRegs() const;
- const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
+ const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction MF,
MachineBasicBlock MBB,
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.92 - 1.93 --- Log message: fix CodeGen/PowerPC/2006-12-07-LargeAlloca.ll on ppc64 --- Diffs of the changes: (+1 -0) PPCRegisterInfo.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.92 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.93 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.92Wed Dec 6 11:42:06 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Dec 7 16:15:58 2006 @@ -94,6 +94,7 @@ ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; ImmToIdxMap[PPC::ADDI] = PPC::ADD4; + ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; } void ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.90 - 1.91
---
Log message:
MachineInstr::setOpcode - MachineInstr::setInstrDescriptor
---
Diffs of the changes: (+1 -1)
PPCRegisterInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.90
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.91
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.90Mon Nov 27 17:37:22 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Nov 30 01:12:03 2006
@@ -576,7 +576,7 @@
assert(ImmToIdxMap.count(OpC)
No indexed form of load or store available!);
unsigned NewOpcode = ImmToIdxMap.find(OpC)-second;
-MI.setOpcode(NewOpcode);
+MI.setInstrDescriptor(TII.get(NewOpcode));
MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false);
MI.getOperand(2).ChangeToRegister(PPC::R0, false);
} else {
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.86 - 1.87
---
Log message:
1. Ignore the -disable-fp-elim when the routine is a leaf.
2. Offsets on 64-bit stores are still in bytes.
---
Diffs of the changes: (+2 -2)
PPCRegisterInfo.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.86
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.87
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.86Thu Nov 16 16:43:37 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Fri Nov 17 10:09:31 2006
@@ -704,7 +704,7 @@
// don't have a frame pointer, calls, or dynamic alloca then we do not need
// to adjust the stack pointer (we fit in the Red Zone).
if (FrameSize = 224 // Fits in red zone.
- !needsFP(MF) // Frame pointer can be eliminated.
+ !MFI-hasVarSizedObjects()// No dynamic alloca.
!MFI-hasCalls() // No calls.
MaxAlign = TargetAlign) { // No special alignment.
// No need for frame
@@ -818,7 +818,7 @@
.addImm(NegFrameSize);
BuildMI(MBB, MBBI, PPC::STDUX, 3)
.addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
-} else if (isInt16(NegFrameSize/4)) {
+} else if (isInt16(NegFrameSize)) {
BuildMI(MBB, MBBI, PPC::STDU, 3, PPC::X1)
.addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1);
} else {
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.87 - 1.88 --- Log message: Assert unhandled case. --- Diffs of the changes: (+2 -0) PPCRegisterInfo.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.87 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.88 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.87Fri Nov 17 10:09:31 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Fri Nov 17 12:49:39 2006 @@ -445,6 +445,8 @@ // Get stack alignments. unsigned TargetAlign = MF.getTarget().getFrameInfo()-getStackAlignment(); unsigned MaxAlign = MFI-getMaxAlignment(); + assert(MaxAlign = TargetAlign + Dynamic alloca with large aligns not supported); // Determine the previous frame's address. If FrameSize can't be // represented as 16 bits or we need special alignment, then we load the ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.82 - 1.83
PPCInstr64Bit.td updated: 1.26 - 1.27
---
Log message:
Fix the PPC regressions last night
---
Diffs of the changes: (+7 -7)
PPCInstr64Bit.td|2 +-
PPCRegisterInfo.cpp | 12 ++--
2 files changed, 7 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.82
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.83
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.82Tue Nov 14 12:44:47 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed Nov 15 11:40:51 2006
@@ -418,11 +418,11 @@
if (Old-getOpcode() == PPC::ADJCALLSTACKDOWN) {
if (!Subtarget.isPPC64()) {
BuildMI(MBB, I, PPC::LWZ, 2, PPC::R0).addImm(0).addReg(PPC::R31);
- BuildMI(MBB, I, PPC::STWU, 3)
+ BuildMI(MBB, I, PPC::STWU, 3, PPC::R1)
.addReg(PPC::R0).addImm(-Amount).addReg(PPC::R1);
} else {
BuildMI(MBB, I, PPC::LD, 2, PPC::X0).addImm(0).addReg(PPC::X31);
- BuildMI(MBB, I, PPC::STDU, 3)
+ BuildMI(MBB, I, PPC::STDU, 3, PPC::X1)
.addReg(PPC::X0).addImm(-Amount/4).addReg(PPC::X1);
}
} else {
@@ -684,8 +684,8 @@
BuildMI(MBB, MBBI, PPC::STWUX, 3)
.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
} else if (NumBytes = 32768) {
- BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes)
-.addReg(PPC::R1);
+ BuildMI(MBB, MBBI, PPC::STWU, 3,
+ PPC::R1).addReg(PPC::R1).addImm(NegNumbytes).addReg(PPC::R1);
} else {
BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes 16);
BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
@@ -704,8 +704,8 @@
BuildMI(MBB, MBBI, PPC::STDUX, 3)
.addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
} else if (NumBytes = 32768*4) {
- BuildMI(MBB, MBBI, PPC::STDU, 3).addReg(PPC::X1).addImm(NegNumbytes/4)
- .addReg(PPC::X1);
+ BuildMI(MBB, MBBI, PPC::STDU, 3, PPC::X1)
+ .addReg(PPC::X1).addImm(NegNumbytes/4).addReg(PPC::X1);
} else {
BuildMI(MBB, MBBI, PPC::LIS8, 1, PPC::X0).addImm(NegNumbytes 16);
BuildMI(MBB, MBBI, PPC::ORI8, 2, PPC::X0).addReg(PPC::X0)
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.26
llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.27
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.26 Tue Nov 14 12:44:47 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdWed Nov 15 11:40:51 2006
@@ -364,7 +364,7 @@
[(store G8RC:$rS, xaddr:$dst)], isPPC64,
PPC970_DGroup_Cracked;
-def STDU : DSForm_162, 1, (ops G8RC:$rS, memrix:$dst),
+def STDU : DSForm_162, 1, (ops G8RC:$ea_res, G8RC:$rS, memrix:$dst),
stdu $rS, $dst, LdStSTD,
[], isPPC64;
def STDUX : XForm_831, 181, (ops G8RC:$rS, memrr:$dst),
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.79 - 1.80
---
Log message:
Make sure stack link is set in 64-bit.
---
Diffs of the changes: (+9 -3)
PPCRegisterInfo.cpp | 12 +---
1 files changed, 9 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.79
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.80
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.79Sat Nov 11 13:05:28 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Sat Nov 11 16:22:07 2006
@@ -396,9 +396,15 @@
// Replace the pseudo instruction with a new instruction...
if (Old-getOpcode() == PPC::ADJCALLSTACKDOWN) {
-BuildMI(MBB, I, PPC::LWZ, 2, PPC::R0).addImm(0).addReg(PPC::R31);
-BuildMI(MBB, I, PPC::STWU, 3)
-
.addReg(PPC::R0).addImm(-Amount).addReg(PPC::R1);
+if (!Subtarget.isPPC64()) {
+ BuildMI(MBB, I, PPC::LWZ, 2, PPC::R0).addImm(0).addReg(PPC::R31);
+ BuildMI(MBB, I, PPC::STWU, 3)
+ .addReg(PPC::R0).addImm(-Amount).addReg(PPC::R1);
+} else {
+ BuildMI(MBB, I, PPC::LD, 2, PPC::X0).addImm(0).addReg(PPC::X31);
+ BuildMI(MBB, I, PPC::STDU, 3)
+ .addReg(PPC::X0).addImm(-Amount/4).addReg(PPC::X1);
+}
} else {
assert(Old-getOpcode() == PPC::ADJCALLSTACKUP);
BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(Amount);
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.72 - 1.73
---
Log message:
The PPC64 JIT needs register numbers to encode instructions.
---
Diffs of the changes: (+36 -35)
PPCRegisterInfo.cpp | 71 ++--
1 files changed, 36 insertions(+), 35 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.72
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.73
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.72Mon Jul 10 19:48:23 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Jul 11 15:53:55 2006
@@ -40,42 +40,43 @@
/// getRegisterNumbering - Given the enum value for some register, e.g.
/// PPC::F14, return the number that it corresponds to (e.g. 14).
unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
+ using namespace PPC;
switch (RegEnum) {
-case PPC::R0 : case PPC::F0 : case PPC::V0 : case PPC::CR0: return 0;
-case PPC::R1 : case PPC::F1 : case PPC::V1 : case PPC::CR1: return 1;
-case PPC::R2 : case PPC::F2 : case PPC::V2 : case PPC::CR2: return 2;
-case PPC::R3 : case PPC::F3 : case PPC::V3 : case PPC::CR3: return 3;
-case PPC::R4 : case PPC::F4 : case PPC::V4 : case PPC::CR4: return 4;
-case PPC::R5 : case PPC::F5 : case PPC::V5 : case PPC::CR5: return 5;
-case PPC::R6 : case PPC::F6 : case PPC::V6 : case PPC::CR6: return 6;
-case PPC::R7 : case PPC::F7 : case PPC::V7 : case PPC::CR7: return 7;
-case PPC::R8 : case PPC::F8 : case PPC::V8 : return 8;
-case PPC::R9 : case PPC::F9 : case PPC::V9 : return 9;
-case PPC::R10: case PPC::F10: case PPC::V10: return 10;
-case PPC::R11: case PPC::F11: case PPC::V11: return 11;
-case PPC::R12: case PPC::F12: case PPC::V12: return 12;
-case PPC::R13: case PPC::F13: case PPC::V13: return 13;
-case PPC::R14: case PPC::F14: case PPC::V14: return 14;
-case PPC::R15: case PPC::F15: case PPC::V15: return 15;
-case PPC::R16: case PPC::F16: case PPC::V16: return 16;
-case PPC::R17: case PPC::F17: case PPC::V17: return 17;
-case PPC::R18: case PPC::F18: case PPC::V18: return 18;
-case PPC::R19: case PPC::F19: case PPC::V19: return 19;
-case PPC::R20: case PPC::F20: case PPC::V20: return 20;
-case PPC::R21: case PPC::F21: case PPC::V21: return 21;
-case PPC::R22: case PPC::F22: case PPC::V22: return 22;
-case PPC::R23: case PPC::F23: case PPC::V23: return 23;
-case PPC::R24: case PPC::F24: case PPC::V24: return 24;
-case PPC::R25: case PPC::F25: case PPC::V25: return 25;
-case PPC::R26: case PPC::F26: case PPC::V26: return 26;
-case PPC::R27: case PPC::F27: case PPC::V27: return 27;
-case PPC::R28: case PPC::F28: case PPC::V28: return 28;
-case PPC::R29: case PPC::F29: case PPC::V29: return 29;
-case PPC::R30: case PPC::F30: case PPC::V30: return 30;
-case PPC::R31: case PPC::F31: case PPC::V31: return 31;
-default:
- std::cerr Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n;
- abort();
+ case R0 : case X0 : case F0 : case V0 : case CR0: return 0;
+ case R1 : case X1 : case F1 : case V1 : case CR1: return 1;
+ case R2 : case X2 : case F2 : case V2 : case CR2: return 2;
+ case R3 : case X3 : case F3 : case V3 : case CR3: return 3;
+ case R4 : case X4 : case F4 : case V4 : case CR4: return 4;
+ case R5 : case X5 : case F5 : case V5 : case CR5: return 5;
+ case R6 : case X6 : case F6 : case V6 : case CR6: return 6;
+ case R7 : case X7 : case F7 : case V7 : case CR7: return 7;
+ case R8 : case X8 : case F8 : case V8 : return 8;
+ case R9 : case X9 : case F9 : case V9 : return 9;
+ case R10: case X10: case F10: case V10: return 10;
+ case R11: case X11: case F11: case V11: return 11;
+ case R12: case X12: case F12: case V12: return 12;
+ case R13: case X13: case F13: case V13: return 13;
+ case R14: case X14: case F14: case V14: return 14;
+ case R15: case X15: case F15: case V15: return 15;
+ case R16: case X16: case F16: case V16: return 16;
+ case R17: case X17: case F17: case V17: return 17;
+ case R18: case X18: case F18: case V18: return 18;
+ case R19: case X19: case F19: case V19: return 19;
+ case R20: case X20: case F20: case V20: return 20;
+ case R21: case X21: case F21: case V21: return 21;
+ case R22: case X22: case F22: case V22: return 22;
+ case R23: case X23: case F23: case V23: return 23;
+ case R24: case X24: case F24: case V24: return 24;
+ case R25: case X25: case F25: case V25: return 25;
+ case R26: case X26: case F26: case V26: return 26;
+ case R27: case X27: case F27: case V27: return 27;
+ case R28: case X28: case F28: case V28: return 28;
+ case R29: case X29: case F29: case V29: return 29;
+ case R30: case
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.70 - 1.71
---
Log message:
Fix rewriting frame offsets with ixaddr instructions, which implicitly shift
the offset two bits to the left.
---
Diffs of the changes: (+21 -8)
PPCRegisterInfo.cpp | 29 +
1 files changed, 21 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.70
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.71
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.70Tue Jun 20 18:18:58 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Jun 27 13:55:49 2006
@@ -390,9 +390,27 @@
// Take into account whether it's an add or mem instruction
unsigned OffIdx = (i == 2) ? 1 : 2;
+ // Figure out if the offset in the instruction is shifted right two bits.
This
+ // is true for instructions like STD, which the machine implicitly adds two
+ // low zeros to.
+ bool isIXAddr = false;
+ switch (MI.getOpcode()) {
+ case PPC::LWA:
+ case PPC::LD:
+ case PPC::STD:
+ case PPC::STD_32:
+isIXAddr = true;
+break;
+ }
+
+
// Now add the frame object offset to the offset from r1.
- int Offset = MF.getFrameInfo()-getObjectOffset(FrameIndex) +
- MI.getOperand(OffIdx).getImmedValue();
+ int Offset = MF.getFrameInfo()-getObjectOffset(FrameIndex);
+
+ if (!isIXAddr)
+Offset += MI.getOperand(OffIdx).getImmedValue();
+ else
+Offset += MI.getOperand(OffIdx).getImmedValue() 2;
// If we're not using a Frame Pointer that has been set to the value of the
// SP before having the stack size subtracted from it, then add the stack
size
@@ -415,14 +433,9 @@
MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg());
MI.getOperand(2).ChangeToRegister(PPC::R0);
} else {
-switch (MI.getOpcode()) {
-case PPC::LWA:
-case PPC::LD:
-case PPC::STD:
-case PPC::STD_32:
+if (isIXAddr) {
assert((Offset 3) == 0 Invalid frame offset!);
Offset = 2;// The actual encoded value has the low two bits zero.
- break;
}
MI.getOperand(OffIdx).ChangeToImmediate(Offset);
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.67 - 1.68
---
Log message:
Fix spilling and reloading of CR regs to reload the right values. This fixes
Olden/power (and probably others) with -regalloc=local.
---
Diffs of the changes: (+24 -2)
PPCRegisterInfo.cpp | 26 --
1 files changed, 24 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.67
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.68
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.67Wed May 17 19:12:25 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Jun 12 16:50:57 2006
@@ -102,7 +102,19 @@
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11),
FrameIdx);
} else if (RC == PPC::CRRCRegisterClass) {
+// We need to store the CR in the low 4-bits of the saved value. First,
+// issue a MFCR to save all of the CRBits.
BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
+
+// If the saved register wasn't CR0, shift the bits left so that they are
in
+// CR0's slot.
+if (SrcReg != PPC::CR0) {
+ unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
+ // rlwinm r11, r11, ShiftBits, 0, 31.
+ BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R11)
+.addReg(PPC::R11).addImm(ShiftBits).addImm(0).addImm(31);
+}
+
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11),
FrameIdx);
} else if (RC == PPC::GPRCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
@@ -137,6 +149,16 @@
BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
} else if (RC == PPC::CRRCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
+
+// If the reloaded register isn't CR0, shift the bits right so that they
are
+// in the right CR's slot.
+if (DestReg != PPC::CR0) {
+ unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
+ // rlwinm r11, r11, 32-ShiftBits, 0, 31.
+ BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R11)
+.addReg(PPC::R11).addImm(32-ShiftBits).addImm(0).addImm(31);
+}
+
BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
} else if (RC == PPC::GPRCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
@@ -407,8 +429,8 @@
/// VRRegNo - Map from a numbered VR register to its enum value.
///
static const unsigned short VRRegNo[] = {
- PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7
,
- PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14,
PPC::V15,
+ PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7
,
+ PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14,
PPC::V15,
PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22,
PPC::V23,
PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
};
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.68 - 1.69
---
Log message:
Gaar! Don't use r11 for CR save/restore, use R0. R11 can be register
allocated, thus live across the save/reload. This fixes
llc-beta /MultiSource/Applications/spiff/spiff
llc-beta /MultiSource/Benchmarks/sim/sim:
llc-beta /MultiSource/Benchmarks/Ptrdist/bc/bc
llc-beta /MultiSource/Benchmarks/McCat/12-IOtest/iotest:
llc-beta /MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow
llc-beta /MultiSource/Benchmarks/Fhourstones-3.1/fhourstones3.1
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawdaudio/rawdaudio
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio
llc-beta /MultiSource/Benchmarks/mediabench/g721/g721encode/encode
llc-beta /MultiSource/Benchmarks/mediabench/jpeg/jpeg-6a/cjpeg
and probably others, with -regalloc=local.
---
Diffs of the changes: (+11 -9)
PPCRegisterInfo.cpp | 20 +++-
1 files changed, 11 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.68
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.69
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.68Mon Jun 12 16:50:57 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Jun 12 18:59:16 2006
@@ -102,20 +102,21 @@
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11),
FrameIdx);
} else if (RC == PPC::CRRCRegisterClass) {
+// FIXME: We use R0 here, because it isn't available for RA.
// We need to store the CR in the low 4-bits of the saved value. First,
// issue a MFCR to save all of the CRBits.
-BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
+BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0);
// If the saved register wasn't CR0, shift the bits left so that they are
in
// CR0's slot.
if (SrcReg != PPC::CR0) {
unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
- // rlwinm r11, r11, ShiftBits, 0, 31.
- BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R11)
-.addReg(PPC::R11).addImm(ShiftBits).addImm(0).addImm(31);
+ // rlwinm r0, r0, ShiftBits, 0, 31.
+ BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
+.addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
}
-addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11),
FrameIdx);
+addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx);
} else if (RC == PPC::GPRCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
} else if (RC == PPC::G8RCRegisterClass) {
@@ -148,18 +149,19 @@
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
} else if (RC == PPC::CRRCRegisterClass) {
-addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
+// FIXME: We use R0 here, because it isn't available for RA.
+addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx);
// If the reloaded register isn't CR0, shift the bits right so that they
are
// in the right CR's slot.
if (DestReg != PPC::CR0) {
unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
// rlwinm r11, r11, 32-ShiftBits, 0, 31.
- BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R11)
-.addReg(PPC::R11).addImm(32-ShiftBits).addImm(0).addImm(31);
+ BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
+.addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31);
}
-BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
+BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0);
} else if (RC == PPC::GPRCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
} else if (RC == PPC::G8RCRegisterClass) {
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.65 - 1.66
---
Log message:
Fix the PowerPC JIT-only failure on UnitTests/Vector/sumarray-dbl, which is
really a bad codegen bug that LLC happens to get lucky with. I must chat with
Nate for the proper fix.
---
Diffs of the changes: (+2 -2)
PPCRegisterInfo.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.65
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.66
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.65Thu May 4 12:52:23 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed May 10 01:38:32 2006
@@ -506,11 +506,11 @@
// If there is a preferred stack alignment, align R1 now
if (MaxAlign TargetAlign) {
assert(isPowerOf2_32(MaxAlign) MaxAlign 32767 Invalid
alignment!);
-assert(isInt16(MaxAlign-NumBytes) Unhandled stack size and
alignment!);
+assert(isInt16(0-NumBytes) Unhandled stack size and alignment!);
BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
.addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
- .addImm(MaxAlign-NumBytes);
+ .addImm(0-NumBytes);
BuildMI(MBB, MBBI, PPC::STWUX, 3)
.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
} else if (NumBytes = 32768) {
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.62 - 1.63
PPCRegisterInfo.td updated: 1.35 - 1.36
---
Log message:
Revert Nate's CR patch from last night, which caused many regressions (e.g.
fhourstones).
Loading and storing off R0 isn't what we wanted. Also, taking some CR's out of
CRRC seems to cause failures as well. Further investigation is required.
---
Diffs of the changes: (+9 -26)
PPCRegisterInfo.cpp | 14 ++
PPCRegisterInfo.td | 21 +++--
2 files changed, 9 insertions(+), 26 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.62
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.63
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.62Tue May 2 12:37:31 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu May 4 11:56:45 2006
@@ -102,9 +102,8 @@
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11),
FrameIdx);
} else if (RC == PPC::CRRCRegisterClass) {
-// FIXME: We use R0 here, because it isn't available for RA.
-BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0);
-addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx);
+BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
+addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11),
FrameIdx);
} else if (RC == PPC::GPRCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
} else if (RC == PPC::G8RCRegisterClass) {
@@ -119,7 +118,7 @@
// Dest = LVX R0, R11
//
// FIXME: We use R0 here, because it isn't available for RA.
-addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 2, PPC::R0), FrameIdx, 0, 0);
+addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
BuildMI(MBB, MI, PPC::STVX, 3)
.addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
} else {
@@ -137,9 +136,8 @@
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
} else if (RC == PPC::CRRCRegisterClass) {
-// FIXME: We use R0 here, because it isn't available for RA.
-addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx);
-BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0);
+addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
+BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
} else if (RC == PPC::GPRCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
} else if (RC == PPC::G8RCRegisterClass) {
@@ -154,7 +152,7 @@
// Dest = LVX R0, R11
//
// FIXME: We use R0 here, because it isn't available for RA.
-addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 2, PPC::R0), FrameIdx, 0, 0);
+addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
} else {
assert(0 Unknown regclass!);
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.35
llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.36
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.35 Tue May 2 12:37:31 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td Thu May 4 11:56:45 2006
@@ -264,21 +264,6 @@
V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,
V22, V23, V24, V25, V26, V27, V28, V29, V30, V31];
-def CRRC : RegisterClassPPC, [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3,
CR4]
-{
- let MethodProtos = [{
-iterator allocation_order_begin(MachineFunction MF) const;
-iterator allocation_order_end(MachineFunction MF) const;
- }];
- let MethodBodies = [{
-CRRCClass::iterator
-CRRCClass::allocation_order_begin(MachineFunction MF) const {
- return begin();
-}
-CRRCClass::iterator
-CRRCClass::allocation_order_end(MachineFunction MF) const {
- return end()-3;
-}
- }];
-}
-
+def CRRC : RegisterClassPPC, [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2,
+ CR3, CR4];
+
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.61 - 1.62
PPCRegisterInfo.td updated: 1.34 - 1.35
---
Log message:
Since we don't handle callee-save CRs right yet, don't allocate them. Also
don't step on R11 in the middle of a function when saving and restoring CRs
---
Diffs of the changes: (+26 -9)
PPCRegisterInfo.cpp | 14 --
PPCRegisterInfo.td | 21 ++---
2 files changed, 26 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.61
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.62
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.61Mon Apr 17 16:48:13 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue May 2 12:37:31 2006
@@ -102,8 +102,9 @@
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11),
FrameIdx);
} else if (RC == PPC::CRRCRegisterClass) {
-BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
-addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11),
FrameIdx);
+// FIXME: We use R0 here, because it isn't available for RA.
+BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0);
+addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx);
} else if (RC == PPC::GPRCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
} else if (RC == PPC::G8RCRegisterClass) {
@@ -118,7 +119,7 @@
// Dest = LVX R0, R11
//
// FIXME: We use R0 here, because it isn't available for RA.
-addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
+addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 2, PPC::R0), FrameIdx, 0, 0);
BuildMI(MBB, MI, PPC::STVX, 3)
.addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
} else {
@@ -136,8 +137,9 @@
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
} else if (RC == PPC::CRRCRegisterClass) {
-addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
-BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
+// FIXME: We use R0 here, because it isn't available for RA.
+addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx);
+BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0);
} else if (RC == PPC::GPRCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
} else if (RC == PPC::G8RCRegisterClass) {
@@ -152,7 +154,7 @@
// Dest = LVX R0, R11
//
// FIXME: We use R0 here, because it isn't available for RA.
-addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
+addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 2, PPC::R0), FrameIdx, 0, 0);
BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
} else {
assert(0 Unknown regclass!);
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.34
llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.35
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.34 Mon Apr 17 16:19:12 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td Tue May 2 12:37:31 2006
@@ -264,6 +264,21 @@
V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,
V22, V23, V24, V25, V26, V27, V28, V29, V30, V31];
-def CRRC : RegisterClassPPC, [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2,
- CR3, CR4];
-
+def CRRC : RegisterClassPPC, [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3,
CR4]
+{
+ let MethodProtos = [{
+iterator allocation_order_begin(MachineFunction MF) const;
+iterator allocation_order_end(MachineFunction MF) const;
+ }];
+ let MethodBodies = [{
+CRRCClass::iterator
+CRRCClass::allocation_order_begin(MachineFunction MF) const {
+ return begin();
+}
+CRRCClass::iterator
+CRRCClass::allocation_order_end(MachineFunction MF) const {
+ return end()-3;
+}
+ }];
+}
+
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.57 - 1.58
---
Log message:
Use a small table instead of macros to do this conversion.
---
Diffs of the changes: (+13 -10)
PPCRegisterInfo.cpp | 23 +--
1 files changed, 13 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.57
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.58
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.57Tue Apr 11 14:44:43 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Apr 17 15:59:25 2006
@@ -295,21 +295,24 @@
}
}
+/// VRRegNo - Map from a numbered VR register to its enum value.
+///
+static const unsigned short VRRegNo[] = {
+ PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7
,
+ PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14,
PPC::V15,
+ PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22,
PPC::V23,
+ PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
+};
+
// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
// instruction selector. Based on the vector registers that have been used,
// transform this into the appropriate ORI instruction.
static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
unsigned UsedRegMask = 0;
-#define HANDLEREG(N) if (UsedRegs[PPC::V##N]) UsedRegMask |= 1 (31-N)
- HANDLEREG( 0); HANDLEREG( 1); HANDLEREG( 2); HANDLEREG( 3);
- HANDLEREG( 4); HANDLEREG( 5); HANDLEREG( 6); HANDLEREG( 7);
- HANDLEREG( 8); HANDLEREG( 9); HANDLEREG(10); HANDLEREG(11);
- HANDLEREG(12); HANDLEREG(13); HANDLEREG(14); HANDLEREG(15);
- HANDLEREG(16); HANDLEREG(17); HANDLEREG(18); HANDLEREG(19);
- HANDLEREG(20); HANDLEREG(21); HANDLEREG(22); HANDLEREG(23);
- HANDLEREG(24); HANDLEREG(25); HANDLEREG(26); HANDLEREG(27);
- HANDLEREG(28); HANDLEREG(29); HANDLEREG(30); HANDLEREG(31);
-#undef HANDLEREG
+ for (unsigned i = 0; i != 32; ++i)
+if (UsedRegs[VRRegNo[i]])
+ UsedRegMask |= 1 (31-i);
+
unsigned SrcReg = MI-getOperand(1).getReg();
unsigned DstReg = MI-getOperand(0).getReg();
// If no registers are used, turn this into a copy.
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.60 - 1.61
---
Log message:
Don't diddle VRSAVE if no registers need to be added/removed from it. This
allows us to codegen functions as:
_test_rol:
vspltisw v2, -12
vrlw v2, v2, v2
blr
instead of:
_test_rol:
mfvrsave r2, 256
mr r3, r2
mtvrsave r3
vspltisw v2, -12
vrlw v2, v2, v2
mtvrsave r2
blr
Testcase here: CodeGen/PowerPC/vec_vrsave.ll
---
Diffs of the changes: (+53 -4)
PPCRegisterInfo.cpp | 57
1 files changed, 53 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.60
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.61
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.60Mon Apr 17 16:22:06 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Apr 17 16:48:13 2006
@@ -25,6 +25,7 @@
#include llvm/CodeGen/MachineLocation.h
#include llvm/CodeGen/SelectionDAGNodes.h
#include llvm/Target/TargetFrameInfo.h
+#include llvm/Target/TargetInstrInfo.h
#include llvm/Target/TargetMachine.h
#include llvm/Target/TargetOptions.h
#include llvm/Support/CommandLine.h
@@ -346,6 +347,54 @@
PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
};
+/// RemoveVRSaveCode - We have found that this function does not need any code
+/// to manipulate the VRSAVE register, even though it uses vector registers.
+/// This can happen when the only registers used are known to be live in or out
+/// of the function. Remove all of the VRSAVE related code from the function.
+static void RemoveVRSaveCode(MachineInstr *MI) {
+ MachineBasicBlock *Entry = MI-getParent();
+ MachineFunction *MF = Entry-getParent();
+
+ // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
+ MachineBasicBlock::iterator MBBI = MI;
+ ++MBBI;
+ assert(MBBI != Entry-end() MBBI-getOpcode() == PPC::MTVRSAVE);
+ MBBI-eraseFromParent();
+
+ bool RemovedAllMTVRSAVEs = true;
+ // See if we can find and remove the MTVRSAVE instruction from all of the
+ // epilog blocks.
+ const TargetInstrInfo TII = *MF-getTarget().getInstrInfo();
+ for (MachineFunction::iterator I = MF-begin(), E = MF-end(); I != E; ++I) {
+// If last instruction is a return instruction, add an epilogue
+if (!I-empty() TII.isReturn(I-back().getOpcode())) {
+ bool FoundIt = false;
+ for (MBBI = I-end(); MBBI != I-begin(); ) {
+--MBBI;
+if (MBBI-getOpcode() == PPC::MTVRSAVE) {
+ MBBI-eraseFromParent(); // remove it.
+ FoundIt = true;
+ break;
+}
+ }
+ RemovedAllMTVRSAVEs = FoundIt;
+}
+ }
+
+ // If we found and removed all MTVRSAVE instructions, remove the read of
+ // VRSAVE as well.
+ if (RemovedAllMTVRSAVEs) {
+MBBI = MI;
+assert(MBBI != Entry-begin() UPDATE_VRSAVE is first instr in block?);
+--MBBI;
+assert(MBBI-getOpcode() == PPC::MFVRSAVE VRSAVE instrs wandered?);
+MBBI-eraseFromParent();
+ }
+
+ // Finally, nuke the UPDATE_VRSAVE.
+ MI-eraseFromParent();
+}
+
// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
// instruction selector. Based on the vector registers that have been used,
// transform this into the appropriate ORI instruction.
@@ -375,9 +424,9 @@
unsigned DstReg = MI-getOperand(0).getReg();
// If no registers are used, turn this into a copy.
if (UsedRegMask == 0) {
-if (SrcReg != DstReg)
- BuildMI(*MI-getParent(), MI, PPC::OR4, 2, DstReg)
-.addReg(SrcReg).addReg(SrcReg);
+// Remove all VRSAVE code.
+RemoveVRSaveCode(MI);
+return;
} else if ((UsedRegMask 0x) == UsedRegMask) {
BuildMI(*MI-getParent(), MI, PPC::ORI, 2, DstReg)
.addReg(SrcReg).addImm(UsedRegMask);
@@ -392,7 +441,7 @@
}
// Remove the old UPDATE_VRSAVE instruction.
- MI-getParent()-erase(MI);
+ MI-eraseFromParent();
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.54 - 1.55
---
Log message:
Suppress debug label when not debug.
---
Diffs of the changes: (+1 -1)
PPCRegisterInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.54
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.55
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.54Fri Apr 7 11:34:45 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Apr 11 03:11:53 2006
@@ -407,7 +407,7 @@
.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
}
- if (DebugInfo) {
+ if (DebugInfo DebugInfo-hasInfo()) {
std::vectorMachineMove * Moves = DebugInfo-getFrameMoves();
unsigned LabelID = DebugInfo-NextLabelID();
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.55 - 1.56
---
Log message:
Fix PR727: http://llvm.cs.uiuc.edu/PR727 , correctly handling large stack
aligments on ppc
---
Diffs of the changes: (+28 -32)
PPCRegisterInfo.cpp | 60
1 files changed, 28 insertions(+), 32 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.55
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.56
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.55Tue Apr 11 03:11:53 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Apr 11 14:29:21 2006
@@ -202,12 +202,10 @@
const MachineFrameInfo *MFI = MF.getFrameInfo();
unsigned TargetAlign = MF.getTarget().getFrameInfo()-getStackAlignment();
- // If frame pointers are forced, if there are variable sized stack objects,
- // or if there is an object on the stack that requires more alignment than is
- // normally provided, use a frame pointer.
+ // If frame pointers are forced, or if there are variable sized stack
objects,
+ // use a frame pointer.
//
- return NoFramePointerElim || MFI-hasVarSizedObjects() ||
- MFI-getMaxAlignment() TargetAlign;
+ return NoFramePointerElim || MFI-hasVarSizedObjects();
}
void PPCRegisterInfo::
@@ -396,15 +394,26 @@
int NegNumbytes = -NumBytes;
// Adjust stack pointer: r1 -= numbytes.
- if (NumBytes = 32768) {
-BuildMI(MBB, MBBI, PPC::STWU, 3)
- .addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
+ // If there is a preferred stack alignment, align R1 now
+ if (MaxAlign TargetAlign) {
+assert(isPowerOf2_32(MaxAlign) MaxAlign 32767 Invalid
alignment!);
+assert(NumBytes = 32768 Unhandled stack size and alignment combo!);
+BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
+ .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
+BuildMI(MBB, MBBI,
PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0).addSImm(MaxAlign);
+BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R0).addReg(PPC::R0)
+ .addSImm(NegNumbytes);
+BuildMI(MBB, MBBI, PPC::STWUX, 3)
+ .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
+ } else if (NumBytes = 32768) {
+BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addSImm(NegNumbytes)
+ .addReg(PPC::R1);
} else {
BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes 16);
-BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0)
-.addReg(PPC::R0).addImm(NegNumbytes 0x);
-BuildMI(MBB, MBBI, PPC::STWUX, 3)
-.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
+BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
+ .addImm(NegNumbytes 0x);
+BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
+ .addReg(PPC::R0);
}
if (DebugInfo DebugInfo-hasInfo()) {
@@ -419,19 +428,6 @@
BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addSImm(LabelID);
}
- // If there is a preferred stack alignment, align R1 now
- // FIXME: If this ever matters, this could be made more efficient by folding
- // this into the code above, so that we don't issue two store+update
- // instructions.
- if (MaxAlign TargetAlign) {
-assert(isPowerOf2_32(MaxAlign) MaxAlign 32767 Invalid
alignment!);
-BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
- .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
-BuildMI(MBB, MBBI, PPC::SUBFIC,
2,PPC::R0).addReg(PPC::R0).addImm(MaxAlign);
-BuildMI(MBB, MBBI, PPC::STWUX, 3)
- .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
- }
-
// If there is a frame pointer, copy R1 (SP) into R31 (FP)
if (HasFP) {
BuildMI(MBB, MBBI, PPC::STW, 3)
@@ -446,8 +442,12 @@
assert(MBBI-getOpcode() == PPC::BLR
Can only insert epilog into returning blocks);
+ // Get alignment info so we know how to restore r1
+ const MachineFrameInfo *MFI = MF.getFrameInfo();
+ unsigned TargetAlign = MF.getTarget().getFrameInfo()-getStackAlignment();
+
// Get the number of bytes allocated from the FrameInfo.
- unsigned NumBytes = MF.getFrameInfo()-getStackSize();
+ unsigned NumBytes = MFI-getStackSize();
unsigned GPRSize = 4;
if (NumBytes != 0) {
@@ -460,15 +460,11 @@
// The loaded (or persistent) stack pointer value is offseted by the 'stwu'
// on entry to the function. Add this offset back now.
-if (NumBytes 32768) {
+if (NumBytes 32768 TargetAlign = MFI-getMaxAlignment()) {
BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
.addReg(PPC::R1).addSImm(NumBytes);
} else {
- BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NumBytes 16);
- BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0)
- .addReg(PPC::R0).addImm(NumBytes 0x);
- BuildMI(MBB, MBBI, PPC::ADD4, 2, PPC::R1)
-.addReg(PPC::R0).addReg(PPC::R1);
+ BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
}
}
}
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.56 - 1.57
---
Log message:
Fix SingleSource/UnitTests/Vector/sumarray-dbl
---
Diffs of the changes: (+3 -4)
PPCRegisterInfo.cpp |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.56
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.57
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.56Tue Apr 11 14:29:21 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Apr 11 14:44:43 2006
@@ -397,12 +397,11 @@
// If there is a preferred stack alignment, align R1 now
if (MaxAlign TargetAlign) {
assert(isPowerOf2_32(MaxAlign) MaxAlign 32767 Invalid
alignment!);
-assert(NumBytes = 32768 Unhandled stack size and alignment combo!);
+assert(isInt16(MaxAlign-NumBytes) Unhandled stack size and
alignment!);
BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
.addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
-BuildMI(MBB, MBBI,
PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0).addSImm(MaxAlign);
-BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R0).addReg(PPC::R0)
- .addSImm(NegNumbytes);
+BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
+ .addSImm(MaxAlign-NumBytes);
BuildMI(MBB, MBBI, PPC::STWUX, 3)
.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
} else if (NumBytes = 32768) {
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.53 - 1.54
PPCRegisterInfo.h updated: 1.12 - 1.13
---
Log message:
Foundation for call frame information.
---
Diffs of the changes: (+31 -2)
PPCRegisterInfo.cpp | 31 +--
PPCRegisterInfo.h |2 ++
2 files changed, 31 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.53
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.54
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.53Mon Apr 3 17:03:29 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Fri Apr 7 11:34:45 2006
@@ -19,9 +19,11 @@
#include llvm/Type.h
#include llvm/CodeGen/ValueTypes.h
#include llvm/CodeGen/MachineInstrBuilder.h
+#include llvm/CodeGen/MachineDebugInfo.h
#include llvm/CodeGen/MachineFunction.h
#include llvm/CodeGen/MachineFrameInfo.h
#include llvm/CodeGen/MachineLocation.h
+#include llvm/CodeGen/SelectionDAGNodes.h
#include llvm/Target/TargetFrameInfo.h
#include llvm/Target/TargetMachine.h
#include llvm/Target/TargetOptions.h
@@ -339,6 +341,7 @@
MachineBasicBlock MBB = MF.front(); // Prolog goes in entry BB
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
+ MachineDebugInfo *DebugInfo = MFI-getMachineDebugInfo();
// Do we have a frame pointer for this function?
bool HasFP = hasFP(MF);
@@ -390,13 +393,13 @@
// Update frame info to pretend that this is part of the stack...
MFI-setStackSize(NumBytes);
+ int NegNumbytes = -NumBytes;
// Adjust stack pointer: r1 -= numbytes.
if (NumBytes = 32768) {
BuildMI(MBB, MBBI, PPC::STWU, 3)
.addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
} else {
-int NegNumbytes = -NumBytes;
BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes 16);
BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0)
.addReg(PPC::R0).addImm(NegNumbytes 0x);
@@ -404,6 +407,18 @@
.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
}
+ if (DebugInfo) {
+std::vectorMachineMove * Moves = DebugInfo-getFrameMoves();
+unsigned LabelID = DebugInfo-NextLabelID();
+
+// Show update of SP.
+MachineLocation Dst(MachineLocation::VirtualFP);
+MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes);
+Moves.push_back(new MachineMove(LabelID, Dst, Src));
+
+BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addSImm(LabelID);
+ }
+
// If there is a preferred stack alignment, align R1 now
// FIXME: If this ever matters, this could be made more efficient by folding
// this into the code above, so that we don't issue two store+update
@@ -458,8 +473,20 @@
}
}
+unsigned PPCRegisterInfo::getRARegister() const {
+ return PPC::LR;
+}
+
unsigned PPCRegisterInfo::getFrameRegister(MachineFunction MF) const {
- return getDwarfRegNum(hasFP(MF) ? PPC::R31 : PPC::R1);
+ return hasFP(MF) ? PPC::R31 : PPC::R1;
+}
+
+void PPCRegisterInfo::getInitialFrameState(std::vectorMachineMove * Moves)
+ const
{
+ // Initial state is the frame pointer is R1.
+ MachineLocation Dst(MachineLocation::VirtualFP);
+ MachineLocation Src(PPC::R1, 0);
+ Moves.push_back(new MachineMove(0, Dst, Src));
}
#include PPCGenRegisterInfo.inc
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.12
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.13
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.12 Tue Mar 28 07:48:33 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Fri Apr 7 11:34:45 2006
@@ -57,7 +57,9 @@
void emitEpilogue(MachineFunction MF, MachineBasicBlock MBB) const;
// Debug information queries.
+ unsigned getRARegister() const;
unsigned getFrameRegister(MachineFunction MF) const;
+ void getInitialFrameState(std::vectorMachineMove * Moves) const;
};
} // end namespace llvm
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.52 - 1.53
---
Log message:
Force use of a frame-pointer if there is anything on the stack that is aligned
more than the OS keeps the stack aligned.
---
Diffs of the changes: (+18 -7)
PPCRegisterInfo.cpp | 25 ++---
1 files changed, 18 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.52
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.53
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.52Tue Mar 28 07:48:33 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Apr 3 17:03:29 2006
@@ -196,8 +196,16 @@
// pointer register. This is true if the function has variable sized allocas
or
// if frame pointer elimination is disabled.
//
-static bool hasFP(MachineFunction MF) {
- return NoFramePointerElim || MF.getFrameInfo()-hasVarSizedObjects();
+static bool hasFP(const MachineFunction MF) {
+ const MachineFrameInfo *MFI = MF.getFrameInfo();
+ unsigned TargetAlign = MF.getTarget().getFrameInfo()-getStackAlignment();
+
+ // If frame pointers are forced, if there are variable sized stack objects,
+ // or if there is an object on the stack that requires more alignment than is
+ // normally provided, use a frame pointer.
+ //
+ return NoFramePointerElim || MFI-hasVarSizedObjects() ||
+ MFI-getMaxAlignment() TargetAlign;
}
void PPCRegisterInfo::
@@ -331,9 +339,12 @@
MachineBasicBlock MBB = MF.front(); // Prolog goes in entry BB
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
+
+ // Do we have a frame pointer for this function?
+ bool HasFP = hasFP(MF);
- // Scan the first few instructions of the prolog, looking for an
UPDATE_VRSAVE
- // instruction. If we find it, process it.
+ // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
+ // process it.
for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
if (MBBI-getOpcode() == PPC::UPDATE_VRSAVE) {
HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
@@ -364,7 +375,7 @@
// If we are a leaf function, and use up to 224 bytes of stack space,
// and don't have a frame pointer, then we do not need to adjust the stack
// pointer (we fit in the Red Zone).
- if ((NumBytes == 0) || (NumBytes = 224 !hasFP(MF) !MFI-hasCalls()
+ if ((NumBytes == 0) || (NumBytes = 224 !HasFP !MFI-hasCalls()
MaxAlign = TargetAlign)) {
MFI-setStackSize(0);
return;
@@ -374,7 +385,7 @@
// of the stack and round the size to a multiple of the alignment.
unsigned Align = std::max(TargetAlign, MaxAlign);
unsigned GPRSize = 4;
- unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize;
+ unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize;
NumBytes = (NumBytes+Size+Align-1)/Align*Align;
// Update frame info to pretend that this is part of the stack...
@@ -407,7 +418,7 @@
}
// If there is a frame pointer, copy R1 (SP) into R31 (FP)
- if (hasFP(MF)) {
+ if (HasFP) {
BuildMI(MBB, MBBI, PPC::STW, 3)
.addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.51 - 1.52
PPCRegisterInfo.h updated: 1.11 - 1.12
---
Log message:
Expose base register for DwarfWriter. Refactor code accordingly.
---
Diffs of the changes: (+4 -11)
PPCRegisterInfo.cpp | 11 ++-
PPCRegisterInfo.h |4 ++--
2 files changed, 4 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.51
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.52
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.51Mon Mar 27 14:18:45 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Mar 28 07:48:33 2006
@@ -447,15 +447,8 @@
}
}
-void PPCRegisterInfo::getLocation(MachineFunction MF, unsigned Index,
- MachineLocation ML) const {
- MachineFrameInfo *MFI = MF.getFrameInfo();
- bool FP = hasFP(MF);
-
- // FIXME - Needs to handle register variables.
- // FIXME - Faking that llvm number is same as gcc numbering.
- ML.set(getDwarfRegNum(FP ? PPC::R31 : PPC::R1),
- MFI-getObjectOffset(Index) + MFI-getStackSize());
+unsigned PPCRegisterInfo::getFrameRegister(MachineFunction MF) const {
+ return getDwarfRegNum(hasFP(MF) ? PPC::R31 : PPC::R1);
}
#include PPCGenRegisterInfo.inc
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.11
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.12
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.11 Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Tue Mar 28 07:48:33 2006
@@ -56,8 +56,8 @@
void emitPrologue(MachineFunction MF) const;
void emitEpilogue(MachineFunction MF, MachineBasicBlock MBB) const;
- void getLocation(MachineFunction MF, unsigned Index,
- MachineLocation ML) const;
+ // Debug information queries.
+ unsigned getFrameRegister(MachineFunction MF) const;
};
} // end namespace llvm
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.50 - 1.51 --- Log message: Translate llvm target registers to dwarf register numbers properly. --- Diffs of the changes: (+1 -1) PPCRegisterInfo.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.50 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.51 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.50Thu Mar 23 12:12:57 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Mar 27 14:18:45 2006 @@ -454,7 +454,7 @@ // FIXME - Needs to handle register variables. // FIXME - Faking that llvm number is same as gcc numbering. - ML.set((FP ? PPC::R31 : PPC::R1) - PPC::R0, + ML.set(getDwarfRegNum(FP ? PPC::R31 : PPC::R1), MFI-getObjectOffset(Index) + MFI-getStackSize()); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.49 - 1.50
PPCRegisterInfo.h updated: 1.10 - 1.11
---
Log message:
Add support to locate local variables in frames (early version.)
---
Diffs of the changes: (+15 -0)
PPCRegisterInfo.cpp | 12
PPCRegisterInfo.h |3 +++
2 files changed, 15 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.49
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.50
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.49Tue Mar 21 23:30:33 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Mar 23 12:12:57 2006
@@ -21,6 +21,7 @@
#include llvm/CodeGen/MachineInstrBuilder.h
#include llvm/CodeGen/MachineFunction.h
#include llvm/CodeGen/MachineFrameInfo.h
+#include llvm/CodeGen/MachineLocation.h
#include llvm/Target/TargetFrameInfo.h
#include llvm/Target/TargetMachine.h
#include llvm/Target/TargetOptions.h
@@ -446,5 +447,16 @@
}
}
+void PPCRegisterInfo::getLocation(MachineFunction MF, unsigned Index,
+ MachineLocation ML) const {
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+ bool FP = hasFP(MF);
+
+ // FIXME - Needs to handle register variables.
+ // FIXME - Faking that llvm number is same as gcc numbering.
+ ML.set((FP ? PPC::R31 : PPC::R1) - PPC::R0,
+ MFI-getObjectOffset(Index) + MFI-getStackSize());
+}
+
#include PPCGenRegisterInfo.inc
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.10
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.11
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.10 Thu Feb 2 14:12:32 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Thu Mar 23 12:12:57 2006
@@ -55,6 +55,9 @@
void emitPrologue(MachineFunction MF) const;
void emitEpilogue(MachineFunction MF, MachineBasicBlock MBB) const;
+
+ void getLocation(MachineFunction MF, unsigned Index,
+ MachineLocation ML) const;
};
} // end namespace llvm
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.45 - 1.46
---
Log message:
in functions that use a lot of callee saved regs, this can be more than
5 instructions away.
---
Diffs of the changes: (+1 -1)
PPCRegisterInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.45
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.46
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.45Thu Mar 16 14:03:58 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Mar 16 15:31:45 2006
@@ -315,7 +315,7 @@
// Scan the first few instructions of the prolog, looking for an
UPDATE_VRSAVE
// instruction. If we find it, process it.
- for (unsigned i = 0; MBBI != MBB.end() i 5; ++i, ++MBBI) {
+ for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
if (MBBI-getOpcode() == PPC::UPDATE_VRSAVE) {
HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
break;
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.47 - 1.48
---
Log message:
remove dead variable
---
Diffs of the changes: (+0 -2)
PPCRegisterInfo.cpp |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.47
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.48
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.47Thu Mar 16 16:24:02 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Mar 16 17:52:08 2006
@@ -118,8 +118,6 @@
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
- MachineInstr *I;
-
if (RC == PPC::GPRCRegisterClass) {
BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (RC == PPC::G8RCRegisterClass) {
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.41 - 1.42
---
Log message:
Fix an off-by-one error that Nate's eagle eyes caught
---
Diffs of the changes: (+1 -1)
PPCRegisterInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.41
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.42
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.41Wed Jan 11 17:07:57 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed Jan 11 17:16:29 2006
@@ -380,7 +380,7 @@
// The loaded (or persistent) stack pointer value is offseted by the 'stwu'
// on entry to the function. Add this offset back now.
-if (NumBytes = 32768) {
+if (NumBytes 32768) {
BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
.addReg(PPC::R1).addSImm(NumBytes);
} else {
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.36 - 1.37
---
Log message:
Add the necessary support to the ISel to allow targets to codegen the new
alignment information appropriately. Includes code for PowerPC to support
fixed-size allocas with alignment larger than the stack. Support for
arbitrarily aligned dynamic allocas coming soon.
---
Diffs of the changes: (+26 -3)
PPCRegisterInfo.cpp | 29 ++---
1 files changed, 26 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.36
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.37
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.36Tue Oct 18 11:51:22 2005
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Sun Nov 6 03:00:38 2005
@@ -26,6 +26,7 @@
#include llvm/Target/TargetOptions.h
#include llvm/Support/CommandLine.h
#include llvm/Support/Debug.h
+#include llvm/Support/MathExtras.h
#include llvm/ADT/STLExtras.h
#include cstdlib
#include iostream
@@ -294,6 +295,11 @@
// Get the number of bytes to allocate from the FrameInfo
unsigned NumBytes = MFI-getStackSize();
+
+ // Get the alignments provided by the target, and the maximum alignment
+ // (if any) of the fixed frame objects.
+ unsigned TargetAlign = MF.getTarget().getFrameInfo()-getStackAlignment();
+ unsigned MaxAlign = MFI-getMaxAlignment();
// If we have calls, we cannot use the red zone to store callee save
registers
// and we must set up a stack frame, so calculate the necessary size here.
@@ -307,14 +313,15 @@
// If we are a leaf function, and use up to 224 bytes of stack space,
// and don't have a frame pointer, then we do not need to adjust the stack
// pointer (we fit in the Red Zone).
- if ((NumBytes == 0) || (NumBytes = 224 !hasFP(MF) !MFI-hasCalls())) {
+ if ((NumBytes == 0) || (NumBytes = 224 !hasFP(MF) !MFI-hasCalls()
+ MaxAlign = TargetAlign)) {
MFI-setStackSize(0);
return;
}
// Add the size of R1 to NumBytes size for the store of R1 to the bottom
// of the stack and round the size to a multiple of the alignment.
- unsigned Align = MF.getTarget().getFrameInfo()-getStackAlignment();
+ unsigned Align = std::max(TargetAlign, MaxAlign);
unsigned GPRSize = 4;
unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize;
NumBytes = (NumBytes+Size+Align-1)/Align*Align;
@@ -336,7 +343,23 @@
MI = BuildMI(PPC::STWUX,
3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
MBB.insert(MBBI, MI);
}
-
+
+ // If there is a preferred stack alignment, align R1 now
+ // FIXME: If this ever matters, this could be made more efficient by folding
+ // this into the code above, so that we don't issue two store+update
+ // instructions.
+ if (MaxAlign TargetAlign) {
+assert(isPowerOf2_32(MaxAlign) MaxAlign 32767 Invalid
alignment!);
+MI = BuildMI(PPC::RLWINM, 4, PPC::R0).addReg(PPC::R1).addImm(0)
+ .addImm(32-Log2_32(MaxAlign)).addImm(31);
+MBB.insert(MBBI, MI);
+MI = BuildMI(PPC::SUBFIC, 2, PPC::R0).addReg(PPC::R0).addImm(MaxAlign);
+MBB.insert(MBBI, MI);
+MI = BuildMI(PPC::STWUX,
3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
+MBB.insert(MBBI, MI);
+ }
+
+ // If there is a frame pointer, copy R1 (SP) into R31 (FP)
if (hasFP(MF)) {
MI = BuildMI(PPC::STW,
3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
MBB.insert(MBBI, MI);
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
