[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2007-06-22 Thread Dan Gohman 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.122 - 1.123
---
Log message:

Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.


---
Diffs of the changes:  (+6 -2)

 SparcISelDAGToDAG.cpp |8 ++--
 1 files changed, 6 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.122 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.123
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.122   Wed Mar  7 10:25:09 2007
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Fri Jun 22 09:59:07 2007
@@ -112,6 +112,7 @@
 uint64_t Mask,
 uint64_t KnownZero, 
 uint64_t KnownOne,
+const SelectionDAG DAG,
 unsigned Depth = 0) const;
 
 virtual std::vectorSDOperand
@@ -261,6 +262,7 @@
  uint64_t Mask,
  uint64_t KnownZero, 
  uint64_t KnownOne,
+ const SelectionDAG 
DAG,
  unsigned Depth) const 
{
   uint64_t KnownZero2, KnownOne2;
   KnownZero = KnownOne = 0;   // Don't know anything.
@@ -269,8 +271,10 @@
   default: break;
   case SPISD::SELECT_ICC:
   case SPISD::SELECT_FCC:
-ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
-ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
+DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
+  Depth+1);
+DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
+  Depth+1);
 assert((KnownZero  KnownOne) == 0  Bits known to be one AND zero?); 
 assert((KnownZero2  KnownOne2) == 0  Bits known to be one AND zero?); 
 



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2007-03-07 Thread Anton Korobeynikov 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.121 - 1.122
---
Log message:

Refactoring of formal parameter flags. Enable properly use of 
zext/sext/aext stuff.


---
Diffs of the changes:  (+4 -2)

 SparcISelDAGToDAG.cpp |6 --
 1 files changed, 4 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.121 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.122
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.121   Thu Feb 22 08:56:36 2007
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Wed Mar  7 10:25:09 2007
@@ -516,9 +516,11 @@
 case MVT::i16: {
   // Promote the integer to 32-bits.  If the input type is signed, use a
   // sign extend, otherwise use a zero extend.
-  ISD::NodeType ExtendKind = ISD::ZERO_EXTEND;
-  if (Args[i].isSigned)
+  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
+  if (Args[i].isSExt)
 ExtendKind = ISD::SIGN_EXTEND;
+  else if (Args[i].isZExt)
+ExtendKind = ISD::ZERO_EXTEND;
   Val = DAG.getNode(ExtendKind, MVT::i32, Val);
   // FALL THROUGH
 }



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Re: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2007-03-07 Thread Chris Lattner 
 Refactoring of formal parameter flags. Enable properly use of
 zext/sext/aext stuff.

Thanks Anton!

-Chris


 ---
 Diffs of the changes:  (+4 -2)

  SparcISelDAGToDAG.cpp |6 --
  1 files changed, 4 insertions(+), 2 deletions(-)


 Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
 diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.121 llvm/lib/ 
 Target/Sparc/SparcISelDAGToDAG.cpp:1.122
 --- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.121 Thu Feb 22  
 08:56:36 2007
 +++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp   Wed Mar  7 10:25:09  
 2007
 @@ -516,9 +516,11 @@
  case MVT::i16: {
// Promote the integer to 32-bits.  If the input type is  
 signed, use a
// sign extend, otherwise use a zero extend.
 -  ISD::NodeType ExtendKind = ISD::ZERO_EXTEND;
 -  if (Args[i].isSigned)
 +  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
 +  if (Args[i].isSExt)
  ExtendKind = ISD::SIGN_EXTEND;
 +  else if (Args[i].isZExt)
 +ExtendKind = ISD::ZERO_EXTEND;
Val = DAG.getNode(ExtendKind, MVT::i32, Val);
// FALL THROUGH
  }



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2007-02-22 Thread Jim Laskey 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.120 - 1.121
---
Log message:

Simplify lowering and selection of exception ops.

---
Diffs of the changes:  (+0 -3)

 SparcISelDAGToDAG.cpp |3 ---
 1 files changed, 3 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.120 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.121
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.120   Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu Feb 22 08:56:36 2007
@@ -871,9 +871,6 @@
   // Frame  Return address.  Currently unimplemented
   case ISD::RETURNADDR: break;
   case ISD::FRAMEADDR:  break;
-  // Exception address and exception selector.  Currently unimplemented.
-  case ISD::EXCEPTIONADDR: break;
-  case ISD::EHSELECTION:   break;
   }
   return SDOperand();
 }



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp SparcRegisterInfo.cpp SparcRegisterInfo.h

2007-02-21 Thread Jim Laskey 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.119 - 1.120
SparcRegisterInfo.cpp updated: 1.54 - 1.55
SparcRegisterInfo.h updated: 1.20 - 1.21
---
Log message:

Support to provide exception and selector registers.

---
Diffs of the changes:  (+17 -0)

 SparcISelDAGToDAG.cpp |3 +++
 SparcRegisterInfo.cpp |   10 ++
 SparcRegisterInfo.h   |4 
 3 files changed, 17 insertions(+)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.119 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.120
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.119   Mon Jan 29 16:58:52 2007
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Wed Feb 21 16:54:50 2007
@@ -871,6 +871,9 @@
   // Frame  Return address.  Currently unimplemented
   case ISD::RETURNADDR: break;
   case ISD::FRAMEADDR:  break;
+  // Exception address and exception selector.  Currently unimplemented.
+  case ISD::EXCEPTIONADDR: break;
+  case ISD::EHSELECTION:   break;
   }
   return SDOperand();
 }


Index: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.54 
llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.55
--- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.54Mon Feb 19 15:49:54 2007
+++ llvm/lib/Target/Sparc/SparcRegisterInfo.cpp Wed Feb 21 16:54:50 2007
@@ -250,5 +250,15 @@
   return SP::G1;
 }
 
+unsigned SparcRegisterInfo::getEHExceptionRegister() const {
+  assert(0  What is the exception register);
+  return 0;
+}
+
+unsigned SparcRegisterInfo::getEHHandlerRegister() const {
+  assert(0  What is the exception handler register);
+  return 0;
+}
+
 #include SparcGenRegisterInfo.inc
 


Index: llvm/lib/Target/Sparc/SparcRegisterInfo.h
diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.20 
llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.21
--- llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.20  Mon Feb 19 15:49:54 2007
+++ llvm/lib/Target/Sparc/SparcRegisterInfo.h   Wed Feb 21 16:54:50 2007
@@ -70,6 +70,10 @@
   // Debug information queries.
   unsigned getRARegister() const;
   unsigned getFrameRegister(MachineFunction MF) const;
+
+  // Exception handling queries.
+  unsigned getEHExceptionRegister() const;
+  unsigned getEHHandlerRegister() const;
 };
 
 } // end namespace llvm



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2007-01-29 Thread Nate Begeman 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.118 - 1.119
---
Log message:

Finish off bug 680: http://llvm.org/PR680 , allowing targets to custom lower 
frame and return
address nodes.


---
Diffs of the changes:  (+4 -0)

 SparcISelDAGToDAG.cpp |4 
 1 files changed, 4 insertions(+)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.118 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.119
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.118   Fri Jan 26 08:34:51 2007
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Mon Jan 29 16:58:52 2007
@@ -868,7 +868,11 @@
 }
 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
   }
+  // Frame  Return address.  Currently unimplemented
+  case ISD::RETURNADDR: break;
+  case ISD::FRAMEADDR:  break;
   }
+  return SDOperand();
 }
 
 MachineBasicBlock *



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2007-01-26 Thread Jim Laskey 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.117 - 1.118
---
Log message:

Make LABEL a builtin opcode.

---
Diffs of the changes:  (+1 -1)

 SparcISelDAGToDAG.cpp |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.117 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.118
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.117   Sat Dec 30 23:55:36 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Fri Jan 26 08:34:51 2007
@@ -207,7 +207,7 @@
   // We don't have line number support yet.
   setOperationAction(ISD::LOCATION, MVT::Other, Expand);
   setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
-  setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
+  setOperationAction(ISD::LABEL, MVT::Other, Expand);
 
   // RET must be custom lowered, to meet ABI requirements
   setOperationAction(ISD::RET   , MVT::Other, Custom);



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-12-30 Thread Reid Spencer 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.116 - 1.117
---
Log message:

For PR950: http://llvm.org/PR950 :
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
   type of an function parameter was used to determine whether it should
   be sign extended or zero extended before the call. This information is
   now communicated via the function type's parameter attributes. 
3. The interface to LowerCallTo had to be changed in order to accommodate
   the parameter attribute information. Although it would have been
   convenient to pass in the FunctionType itself, there isn't always one
   present in the caller. Consequently, a signedness indication for the
   result type and for each parameter was provided for in the interface
   to this method. All implementations were changed to make the adjustment
   necessary.


---
Diffs of the changes:  (+21 -19)

 SparcISelDAGToDAG.cpp |   40 +---
 1 files changed, 21 insertions(+), 19 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.116 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.117
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.116   Thu Dec  7 16:21:48 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Sat Dec 30 23:55:36 2006
@@ -117,10 +117,9 @@
 virtual std::vectorSDOperand
   LowerArguments(Function F, SelectionDAG DAG);
 virtual std::pairSDOperand, SDOperand
-  LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
-  unsigned CC,
-  bool isTailCall, SDOperand Callee, ArgListTy Args,
-  SelectionDAG DAG);
+  LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 
+  bool isVarArg, unsigned CC, bool isTailCall, SDOperand 
Callee,
+  ArgListTy Args, SelectionDAG DAG);
 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB);
 
@@ -318,8 +317,7 @@
 MF.addLiveIn(*CurArgReg++, VReg);
 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
 if (ObjectVT != MVT::i32) {
-  unsigned AssertOp = I-getType()-isSigned() ? ISD::AssertSext 
-   : ISD::AssertZext;
+  unsigned AssertOp = ISD::AssertSext;
   Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 
 DAG.getValueType(ObjectVT));
   Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
@@ -332,8 +330,7 @@
 if (ObjectVT == MVT::i32) {
   Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
 } else {
-  ISD::LoadExtType LoadOp =
-I-getType()-isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
+  ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
 
   // Sparc is big endian, so add an offset based on the ObjectVT.
   unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
@@ -472,13 +469,13 @@
 
 std::pairSDOperand, SDOperand
 SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
- bool isVarArg, unsigned CC,
+ bool RetTyIsSigned, bool isVarArg, unsigned 
CC,
  bool isTailCall, SDOperand Callee, 
  ArgListTy Args, SelectionDAG DAG) {
   // Count the size of the outgoing arguments.
   unsigned ArgsSize = 0;
   for (unsigned i = 0, e = Args.size(); i != e; ++i) {
-switch (getValueType(Args[i].second)) {
+switch (getValueType(Args[i].Ty)) {
 default: assert(0  Unknown value type!);
 case MVT::i1:
 case MVT::i8:
@@ -508,7 +505,7 @@
   std::vectorSDOperand RegValuesToPass;
   unsigned ArgOffset = 68;
   for (unsigned i = 0, e = Args.size(); i != e; ++i) {
-SDOperand Val = Args[i].first;
+SDOperand Val = Args[i].Node;
 MVT::ValueType ObjectVT = Val.getValueType();
 SDOperand ValToStore(0, 0);
 unsigned ObjSize;
@@ -516,14 +513,15 @@
 default: assert(0  Unhandled argument type!);
 case MVT::i1:
 case MVT::i8:
-case MVT::i16:
+case MVT::i16: {
   // Promote the integer to 32-bits.  If the input type is signed, use a
   // sign extend, otherwise use a zero extend.
-  if (Args[i].second-isSigned())
-Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
-  else
-Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
+  ISD::NodeType ExtendKind = ISD::ZERO_EXTEND;
+  if (Args[i].isSigned)
+ExtendKind = ISD::SIGN_EXTEND;
+  Val = DAG.getNode(ExtendKind, MVT::i32, Val);
   // FALL THROUGH
+}
 case MVT::i32:
   ObjSize = 4;
 
@@ -629,15 +627,19 @@
 default: assert(0  Unknown value type to return!);
 case MVT::i1:
 case MVT::i8:
-

[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-10-30 Thread Evan Cheng 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.112 - 1.113
---
Log message:

All targets expand BR_JT for now.

---
Diffs of the changes:  (+2 -1)

 SparcISelDAGToDAG.cpp |3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.112 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.113
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.112   Fri Oct 13 16:14:26 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Mon Oct 30 02:02:39 2006
@@ -174,7 +174,8 @@
   
   // Sparc doesn't have BRCOND either, it has BR_CC.
   setOperationAction(ISD::BRCOND, MVT::Other, Expand);
-  setOperationAction(ISD::BRIND, MVT::i32, Expand);
+  setOperationAction(ISD::BRIND, MVT::Other, Expand);
+  setOperationAction(ISD::BR_JT, MVT::Other, Expand);
   setOperationAction(ISD::BR_CC, MVT::i32, Custom);
   setOperationAction(ISD::BR_CC, MVT::f32, Custom);
   setOperationAction(ISD::BR_CC, MVT::f64, Custom);



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp SparcInstrInfo.td

2006-10-13 Thread Evan Cheng 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.111 - 1.112
SparcInstrInfo.td updated: 1.130 - 1.131
---
Log message:

Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.

---
Diffs of the changes:  (+12 -13)

 SparcISelDAGToDAG.cpp |   13 ++---
 SparcInstrInfo.td |   12 ++--
 2 files changed, 12 insertions(+), 13 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.111 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.112
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.111   Mon Oct  9 15:57:25 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Fri Oct 13 16:14:26 2006
@@ -436,8 +436,7 @@
   int FrameIdx = MF.getFrameInfo()-CreateFixedObject(4, ArgOffset);
   SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
 
-  OutChains.push_back(DAG.getStore(DAG.getRoot(),
-   Arg, FIPtr, DAG.getSrcValue(0)));
+  OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
   ArgOffset += 4;
 }
   }
@@ -504,7 +503,7 @@
 
   Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, 
getPointerTy()));
   
-  SDOperand StackPtr, NullSV;
+  SDOperand StackPtr;
   std::vectorSDOperand Stores;
   std::vectorSDOperand RegValuesToPass;
   unsigned ArgOffset = 68;
@@ -584,11 +583,10 @@
 if (ValToStore.Val) {
   if (!StackPtr.Val) {
 StackPtr = DAG.getRegister(SP::O6, MVT::i32);
-NullSV = DAG.getSrcValue(NULL);
   }
   SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
   PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
-  Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NullSV));
+  Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
 }
 ArgOffset += ObjSize;
   }
@@ -785,8 +783,9 @@
 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
DAG.getRegister(SP::I6, MVT::i32),
 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
+SrcValueSDNode *SV = castSrcValueSDNode(Op.getOperand(2));
 return DAG.getStore(Op.getOperand(0), Offset, 
-Op.getOperand(1), Op.getOperand(2));
+Op.getOperand(1), SV-getValue(), SV-getOffset());
   }
   case ISD::VAARG: {
 SDNode *Node = Op.Val;
@@ -802,7 +801,7 @@
 getPointerTy()));
 // Store the incremented VAList to the legalized pointer
 InChain = DAG.getStore(VAList.getValue(1), NextPtr,
-   VAListPtr, Node-getOperand(2));
+   VAListPtr, SV-getValue(), SV-getOffset());
 // Load the actual argument out of the pointer VAList, unless this is an
 // f64 load.
 if (VT != MVT::f64) {


Index: llvm/lib/Target/Sparc/SparcInstrInfo.td
diff -u llvm/lib/Target/Sparc/SparcInstrInfo.td:1.130 
llvm/lib/Target/Sparc/SparcInstrInfo.td:1.131
--- llvm/lib/Target/Sparc/SparcInstrInfo.td:1.130   Thu Oct 12 12:57:58 2006
+++ llvm/lib/Target/Sparc/SparcInstrInfo.td Fri Oct 13 16:14:26 2006
@@ -338,19 +338,19 @@
 def STBrr : F3_13, 0b000101,
  (ops MEMrr:$addr, IntRegs:$src),
  stb $src, [$addr],
- [(truncstore IntRegs:$src, ADDRrr:$addr, i8)];
+ [(truncstorei8 IntRegs:$src, ADDRrr:$addr)];
 def STBri : F3_23, 0b000101,
  (ops MEMri:$addr, IntRegs:$src),
  stb $src, [$addr],
- [(truncstore IntRegs:$src, ADDRri:$addr, i8)];
+ [(truncstorei8 IntRegs:$src, ADDRri:$addr)];
 def STHrr : F3_13, 0b000110,
  (ops MEMrr:$addr, IntRegs:$src),
  sth $src, [$addr],
- [(truncstore IntRegs:$src, ADDRrr:$addr, i16)];
+ [(truncstorei16 IntRegs:$src, ADDRrr:$addr)];
 def STHri : F3_23, 0b000110,
  (ops MEMri:$addr, IntRegs:$src),
  sth $src, [$addr],
- [(truncstore IntRegs:$src, ADDRri:$addr, i16)];
+ [(truncstorei16 IntRegs:$src, ADDRri:$addr)];
 def STrr  : F3_13, 0b000100,
  (ops MEMrr:$addr, IntRegs:$src),
  st $src, [$addr],
@@ -772,7 +772,7 @@
 def : Pat(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src);
 
 // truncstore bool - truncstore byte.
-def : Pat(truncstore IntRegs:$src, ADDRrr:$addr, i1), 
+def : Pat(truncstorei1 IntRegs:$src, ADDRrr:$addr),
   (STBrr ADDRrr:$addr, IntRegs:$src);
-def : Pat(truncstore IntRegs:$src, ADDRri:$addr, i1), 
+def : Pat(truncstorei1 IntRegs:$src, ADDRri:$addr), 
   (STBri ADDRri:$addr, IntRegs:$src);



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp SparcInstrInfo.td

2006-10-09 Thread Evan Cheng 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.110 - 1.111
SparcInstrInfo.td updated: 1.127 - 1.128
---
Log message:

Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.


---
Diffs of the changes:  (+26 -26)

 SparcISelDAGToDAG.cpp |   20 ++--
 SparcInstrInfo.td |   32 
 2 files changed, 26 insertions(+), 26 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.110 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.111
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.110   Thu Oct  5 18:00:34 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Mon Oct  9 15:57:25 2006
@@ -330,7 +330,7 @@
 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
 SDOperand Load;
 if (ObjectVT == MVT::i32) {
-  Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+  Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
 } else {
   ISD::LoadExtType LoadOp =
 I-getType()-isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
@@ -340,7 +340,7 @@
   FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
   DAG.getConstant(Offset, MVT::i32));
   Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
-DAG.getSrcValue(0), ObjectVT);
+NULL, 0, ObjectVT);
   Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
 }
 ArgValues.push_back(Load);
@@ -363,7 +363,7 @@
   } else {
 int FrameIdx = MF.getFrameInfo()-CreateFixedObject(4, ArgOffset);
 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, 
DAG.getSrcValue(0));
+SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
 ArgValues.push_back(Load);
   }
   ArgOffset += 4;
@@ -384,8 +384,7 @@
 // because the double wouldn't be aligned!
 int FrameIdx = MF.getFrameInfo()-CreateFixedObject(8, ArgOffset);
 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 
-DAG.getSrcValue(0)));
+ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0));
   } else {
 SDOperand HiVal;
 if (CurArgReg  ArgRegEnd) {  // Lives in an incoming GPR
@@ -395,7 +394,7 @@
 } else {
   int FrameIdx = MF.getFrameInfo()-CreateFixedObject(4, ArgOffset);
   SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-  HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+  HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
 }
 
 SDOperand LoVal;
@@ -406,7 +405,7 @@
 } else {
   int FrameIdx = MF.getFrameInfo()-CreateFixedObject(4, ArgOffset+4);
   SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-  LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+  LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
 }
 
 // Compose the two halves together into an i64 unit.
@@ -794,8 +793,9 @@
 MVT::ValueType VT = Node-getValueType(0);
 SDOperand InChain = Node-getOperand(0);
 SDOperand VAListPtr = Node-getOperand(1);
+SrcValueSDNode *SV = castSrcValueSDNode(Node-getOperand(2));
 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr,
-   Node-getOperand(2));
+   SV-getValue(), SV-getOffset());
 // Increment the pointer, VAList, to the next vaarg
 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, 
 DAG.getConstant(MVT::getSizeInBits(VT)/8, 
@@ -806,10 +806,10 @@
 // Load the actual argument out of the pointer VAList, unless this is an
 // f64 load.
 if (VT != MVT::f64) {
-  return DAG.getLoad(VT, InChain, VAList, DAG.getSrcValue(0));
+  return DAG.getLoad(VT, InChain, VAList, NULL, 0);
 } else {
   // Otherwise, load it as i64, then do a bitconvert.
-  SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, DAG.getSrcValue(0));
+  SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
   std::vectorMVT::ValueType Tys;
   Tys.push_back(MVT::f64);
   Tys.push_back(MVT::Other);


Index: llvm/lib/Target/Sparc/SparcInstrInfo.td
diff -u llvm/lib/Target/Sparc/SparcInstrInfo.td:1.127 
llvm/lib/Target/Sparc/SparcInstrInfo.td:1.128
--- llvm/lib/Target/Sparc/SparcInstrInfo.td:1.127   Fri Sep  1 17:28:02 2006
+++ llvm/lib/Target/Sparc/SparcInstrInfo.td Mon Oct  9 15:57:25 2006
@@ -278,35 +278,35 @@
 def LDSBrr : F3_13, 0b001001,
   (ops IntRegs:$dst, MEMrr:$addr),
   ldsb [$addr], $dst,
-  [(set IntRegs:$dst, (sextload

[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-10-05 Thread Evan Cheng 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.109 - 1.110
---
Log message:

Make use of getStore().

---
Diffs of the changes:  (+7 -8)

 SparcISelDAGToDAG.cpp |   15 +++
 1 files changed, 7 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.109 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.110
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.109   Tue Oct  3 19:55:51 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu Oct  5 18:00:34 2006
@@ -437,8 +437,8 @@
   int FrameIdx = MF.getFrameInfo()-CreateFixedObject(4, ArgOffset);
   SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
 
-  OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
-  Arg, FIPtr, DAG.getSrcValue(0)));
+  OutChains.push_back(DAG.getStore(DAG.getRoot(),
+   Arg, FIPtr, DAG.getSrcValue(0)));
   ArgOffset += 4;
 }
   }
@@ -589,8 +589,7 @@
   }
   SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
   PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
-  Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-   ValToStore, PtrOff, NullSV));
+  Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NullSV));
 }
 ArgOffset += ObjSize;
   }
@@ -787,8 +786,8 @@
 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
DAG.getRegister(SP::I6, MVT::i32),
 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
-return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset, 
-   Op.getOperand(1), Op.getOperand(2));
+return DAG.getStore(Op.getOperand(0), Offset, 
+Op.getOperand(1), Op.getOperand(2));
   }
   case ISD::VAARG: {
 SDNode *Node = Op.Val;
@@ -802,8 +801,8 @@
 DAG.getConstant(MVT::getSizeInBits(VT)/8, 
 getPointerTy()));
 // Store the incremented VAList to the legalized pointer
-InChain = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), NextPtr,
-  VAListPtr, Node-getOperand(2));
+InChain = DAG.getStore(VAList.getValue(1), NextPtr,
+   VAListPtr, Node-getOperand(2));
 // Load the actual argument out of the pointer VAList, unless this is an
 // f64 load.
 if (VT != MVT::f64) {



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-10-03 Thread Evan Cheng 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.108 - 1.109
---
Log message:

Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.


---
Diffs of the changes:  (+4 -4)

 SparcISelDAGToDAG.cpp |8 
 1 files changed, 4 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.108 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.109
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.108   Tue Sep 12 16:03:10 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Tue Oct  3 19:55:51 2006
@@ -137,6 +137,9 @@
   addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
   addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
 
+  // Turn FP extload into load/fextend
+  setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
+  
   // Custom legalize GlobalAddress nodes into LO/HI parts.
   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
   setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
@@ -161,9 +164,6 @@
   setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
   setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
   
-  // Turn FP extload into load/fextend
-  setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
-  
   // Sparc has no select or setcc: expand to SELECT_CC.
   setOperationAction(ISD::SELECT, MVT::i32, Expand);
   setOperationAction(ISD::SELECT, MVT::f32, Expand);
@@ -332,7 +332,7 @@
 if (ObjectVT == MVT::i32) {
   Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
 } else {
-  unsigned LoadOp =
+  ISD::LoadExtType LoadOp =
 I-getType()-isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
 
   // Sparc is big endian, so add an offset based on the ObjectVT.



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-09-12 Thread Evan Cheng 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.107 - 1.108
---
Log message:

Reflects MachineConstantPoolEntry changes.

---
Diffs of the changes:  (+1 -1)

 SparcISelDAGToDAG.cpp |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.107 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.108
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.107   Sat Aug 26 02:59:33 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Tue Sep 12 16:03:10 2006
@@ -704,7 +704,7 @@
 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
   }
   case ISD::ConstantPool: {
-Constant *C = castConstantPoolSDNode(Op)-get();
+Constant *C = castConstantPoolSDNode(Op)-getConstVal();
 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
   
castConstantPoolSDNode(Op)-getAlignment());
 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-08-25 Thread Evan Cheng 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.104 - 1.105
---
Log message:

Match tblgen changes.

---
Diffs of the changes:  (+8 -6)

 SparcISelDAGToDAG.cpp |   14 --
 1 files changed, 8 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.104 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.105
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.104   Wed Aug 16 02:29:40 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Fri Aug 25 20:07:58 2006
@@ -1076,9 +1076,10 @@
   case ISD::SDIV:
   case ISD::UDIV: {
 // FIXME: should use a custom expander to expose the SRA to the dag.
-SDOperand DivLHS, DivRHS;
-AddToQueue(DivLHS, N-getOperand(0));
-AddToQueue(DivRHS, N-getOperand(1));
+SDOperand DivLHS = N-getOperand(0);
+SDOperand DivRHS = N-getOperand(1);
+AddToISelQueue(DivLHS);
+AddToISelQueue(DivRHS);
 
 // Set the Y register to the high-part.
 SDOperand TopPart;
@@ -1099,9 +1100,10 @@
   case ISD::MULHU:
   case ISD::MULHS: {
 // FIXME: Handle mul by immediate.
-SDOperand MulLHS, MulRHS;
-AddToQueue(MulLHS, N-getOperand(0));
-AddToQueue(MulRHS, N-getOperand(1));
+SDOperand MulLHS = N-getOperand(0);
+SDOperand MulRHS = N-getOperand(1);
+AddToISelQueue(MulLHS);
+AddToISelQueue(MulRHS);
 unsigned Opcode = N-getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
 SDNode *Mul = CurDAG-getTargetNode(Opcode, MVT::i32, MVT::Flag,
 MulLHS, MulRHS);



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-08-16 Thread Evan Cheng 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.103 - 1.104
---
Log message:

SelectNodeTo() may return a SDOperand that is different from the input.

---
Diffs of the changes:  (+3 -3)

 SparcISelDAGToDAG.cpp |6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.103 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.104
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.103   Fri Aug 11 04:08:15 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Wed Aug 16 02:29:40 2006
@@ -1093,8 +1093,8 @@
 
 // FIXME: Handle div by immediate.
 unsigned Opcode = N-getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
-Result = CurDAG-SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, 
TopPart);
-return NULL;
+return CurDAG-SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
+TopPart).Val;
   }
   case ISD::MULHU:
   case ISD::MULHS: {
@@ -1106,7 +1106,7 @@
 SDNode *Mul = CurDAG-getTargetNode(Opcode, MVT::i32, MVT::Flag,
 MulLHS, MulRHS);
 // The high part is in the Y register.
-Result = CurDAG-SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
+return CurDAG-SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)).Val;
 return NULL;
   }
   }



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-08-11 Thread Evan Cheng 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.102 - 1.103
---
Log message:

Match tablegen changes.

---
Diffs of the changes:  (+6 -6)

 SparcISelDAGToDAG.cpp |   12 ++--
 1 files changed, 6 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.102 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.103
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.102   Mon Aug  7 21:23:41 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Fri Aug 11 04:08:15 2006
@@ -966,7 +966,7 @@
   Subtarget(TM.getSubtargetSparcSubtarget()) {
   }
 
-  void Select(SDOperand Result, SDOperand Op);
+  SDNode *Select(SDOperand Result, SDOperand Op);
 
   // Complex Pattern Selectors.
   bool SelectADDRrr(SDOperand N, SDOperand R1, SDOperand R2);
@@ -1063,12 +1063,12 @@
   return true;
 }
 
-void SparcDAGToDAGISel::Select(SDOperand Result, SDOperand Op) {
+SDNode *SparcDAGToDAGISel::Select(SDOperand Result, SDOperand Op) {
   SDNode *N = Op.Val;
   if (N-getOpcode() = ISD::BUILTIN_OP_END 
   N-getOpcode()  SPISD::FIRST_NUMBER) {
 Result = Op;
-return;   // Already selected.
+return NULL;   // Already selected.
   }
 
   switch (N-getOpcode()) {
@@ -1094,7 +1094,7 @@
 // FIXME: Handle div by immediate.
 unsigned Opcode = N-getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
 Result = CurDAG-SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, 
TopPart);
-return;
+return NULL;
   }
   case ISD::MULHU:
   case ISD::MULHS: {
@@ -1107,11 +1107,11 @@
 MulLHS, MulRHS);
 // The high part is in the Y register.
 Result = CurDAG-SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
-return;
+return NULL;
   }
   }
   
-  SelectCode(Result, Op);
+  return SelectCode(Result, Op);
 }
 
 



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-08-07 Thread Chris Lattner 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.101 - 1.102
---
Log message:

Start eliminating temporary vectors used to create DAG nodes.  Instead, pass
in the start of an array and a count of operands where applicable.  In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap.  In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.

I updated a lot of code calling getNode that takes a vector, but ran out of
time.  The rest of the code should be updated, and these methods should be
removed.

We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.

It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.



---
Diffs of the changes:  (+14 -24)

 SparcISelDAGToDAG.cpp |   38 ++
 1 files changed, 14 insertions(+), 24 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.101 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.102
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.101   Mon Aug  7 17:24:18 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Mon Aug  7 21:23:41 2006
@@ -444,7 +444,8 @@
   }
   
   if (!OutChains.empty())
-DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
+DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
+OutChains[0], OutChains.size()));
   
   // Finally, inform the code generator which regs we return values in.
   switch (getValueType(F.getReturnType())) {
@@ -596,7 +597,7 @@
   
   // Emit all stores, make sure the occur before any copies into physregs.
   if (!Stores.empty())
-Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
+Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 
Stores[0],Stores.size());
   
   static const unsigned ArgRegs[] = {
 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
@@ -621,12 +622,8 @@
   std::vectorMVT::ValueType NodeTys;
   NodeTys.push_back(MVT::Other);   // Returns a chain
   NodeTys.push_back(MVT::Flag);// Returns a flag for retval copy to use.
-  std::vectorSDOperand Ops;
-  Ops.push_back(Chain);
-  Ops.push_back(Callee);
-  if (InFlag.Val)
-Ops.push_back(InFlag);
-  Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops);
+  SDOperand Ops[] = { Chain, Callee, InFlag };
+  Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
   InFlag = Chain.getValue(1);
   
   MVT::ValueType RetTyVT = getValueType(RetTy);
@@ -743,10 +740,8 @@
   std::vectorMVT::ValueType VTs;
   VTs.push_back(MVT::i32);
   VTs.push_back(MVT::Flag);
-  std::vectorSDOperand Ops;
-  Ops.push_back(LHS);
-  Ops.push_back(RHS);
-  CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
+  SDOperand Ops[2] = { LHS, RHS };
+  CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
   if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
   Opc = SPISD::BRICC;
 } else {
@@ -774,10 +769,8 @@
   std::vectorMVT::ValueType VTs;
   VTs.push_back(LHS.getValueType());   // subcc returns a value
   VTs.push_back(MVT::Flag);
-  std::vectorSDOperand Ops;
-  Ops.push_back(LHS);
-  Ops.push_back(RHS);
-  CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
+  SDOperand Ops[2] = { LHS, RHS };
+  CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
   Opc = SPISD::SELECT_ICC;
   if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
 } else {
@@ -821,11 +814,10 @@
   std::vectorMVT::ValueType Tys;
   Tys.push_back(MVT::f64);
   Tys.push_back(MVT::Other);
-  std::vectorSDOperand Ops;
   // Bit-Convert the value to f64.
-  Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V));
-  Ops.push_back(V.getValue(1));
-  return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
+  SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
+   V.getValue(1) };
+  return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
 }
   }
   case ISD::DYNAMIC_STACKALLOC: {
@@ -844,10 +836,8 @@
 std::vectorMVT::ValueType Tys;
 Tys.push_back(MVT::i32);
 Tys.push_back(MVT::Other);
-std::vectorSDOperand Ops;
-Ops.push_back(NewVal);
-Ops.push_back(Chain);
-return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
+SDOperand Ops[2] = { NewVal, Chain };
+return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
   }
   case ISD::RET: {
 SDOperand Copy;



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-07-27 Thread Evan Cheng 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.99 - 1.100
---
Log message:

Remove InFlightSet hack. No longer needed.

---
Diffs of the changes:  (+0 -1)

 SparcISelDAGToDAG.cpp |1 -
 1 files changed, 1 deletion(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.99 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.100
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.99Thu Jun 15 03:18:06 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu Jul 27 19:47:19 2006
@@ -1001,7 +1001,6 @@
   
   // Select target instructions for the DAG.
   DAG.setRoot(SelectRoot(DAG.getRoot()));
-  assert(InFlightSet.empty()  ISel InFlightSet has not been emptied!);
   CodeGenMap.clear();
   HandleMap.clear();
   ReplaceMap.clear();



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-06-15 Thread Evan Cheng 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.98 - 1.99
---
Log message:

Type of extract_element index operand should be iPTR.

---
Diffs of the changes:  (+2 -2)

 SparcISelDAGToDAG.cpp |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.98 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.99
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.98Fri May 26 18:10:12 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu Jun 15 03:18:06 2006
@@ -564,9 +564,9 @@
   }
   
   // Split the value into top and bottom part.  Top part goes in a reg.
-  SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 
+  SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 
  DAG.getConstant(1, MVT::i32));
-  SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
+  SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
  DAG.getConstant(0, MVT::i32));
   RegValuesToPass.push_back(Hi);
   



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-05-24 Thread Evan Cheng 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.94 - 1.95
---
Log message:

Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
non-deterministic behavior.


---
Diffs of the changes:  (+2 -0)

 SparcISelDAGToDAG.cpp |2 ++
 1 files changed, 2 insertions(+)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.94 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.95
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.94Wed May 24 12:04:04 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Wed May 24 15:46:25 2006
@@ -996,6 +996,8 @@
   // Select target instructions for the DAG.
   DAG.setRoot(SelectRoot(DAG.getRoot()));
   CodeGenMap.clear();
+  HandleMap.clear();
+  ReplaceMap.clear();
   DAG.RemoveDeadNodes();
   
   // Emit machine code to BB. 



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-05-24 Thread Evan Cheng 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.95 - 1.96
---
Log message:

Assert if InflightSet is not cleared after instruction selecting a BB.


---
Diffs of the changes:  (+1 -0)

 SparcISelDAGToDAG.cpp |1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.95 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.96
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.95Wed May 24 15:46:25 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Wed May 24 19:24:27 2006
@@ -995,6 +995,7 @@
   
   // Select target instructions for the DAG.
   DAG.setRoot(SelectRoot(DAG.getRoot()));
+  assert(InFlightSet.empty()  ISel InFlightSet has not been emptied!);
   CodeGenMap.clear();
   HandleMap.clear();
   ReplaceMap.clear();



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-05-12 Thread Chris Lattner 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.92 - 1.93
---
Log message:

Remove dead variable.


---
Diffs of the changes:  (+0 -1)

 SparcISelDAGToDAG.cpp |1 -
 1 files changed, 1 deletion(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.92 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.93
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.92Sat Apr 22 13:53:45 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Fri May 12 12:31:21 2006
@@ -469,7 +469,6 @@
  bool isVarArg, unsigned CC,
  bool isTailCall, SDOperand Callee, 
  ArgListTy Args, SelectionDAG DAG) {
-  MachineFunction MF = DAG.getMachineFunction();
   // Count the size of the outgoing arguments.
   unsigned ArgsSize = 0;
   for (unsigned i = 0, e = Args.size(); i != e; ++i) {



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-03-26 Thread Nate Begeman 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.90 - 1.91
---
Log message:

SelectionDAGISel can now natively handle Switch instructions, in the same
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks.  The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.

This functionality is currently only enabled on x86, but should be safe for
every target.  In anticipation of making it the default, the cfg is now 
properly updated in the x86, ppc, and sparc select lowering code.


---
Diffs of the changes:  (+9 -1)

 SparcISelDAGToDAG.cpp |   10 +-
 1 files changed, 9 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.90 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.91
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.90Sat Mar 25 00:47:10 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Sun Mar 26 19:32:24 2006
@@ -916,7 +916,15 @@
   MachineFunction *F = BB-getParent();
   F-getBasicBlockList().insert(It, copy0MBB);
   F-getBasicBlockList().insert(It, sinkMBB);
-  // Update machine-CFG edges
+  // Update machine-CFG edges by first adding all successors of the current
+  // block to the new block which will contain the Phi node for the select.
+  for(MachineBasicBlock::succ_iterator i = BB-succ_begin(), 
+  e = BB-succ_end(); i != e; ++i)
+sinkMBB-addSuccessor(*i);
+  // Next, remove all successors of the current block, and add the true
+  // and fallthrough blocks as its successors.
+  while(!BB-succ_empty())
+BB-removeSuccessor(BB-succ_begin());
   BB-addSuccessor(copy0MBB);
   BB-addSuccessor(sinkMBB);
   



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-03-24 Thread Chris Lattner 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.89 - 1.90
---
Log message:

#include Intrinsics.h into all dag isels


---
Diffs of the changes:  (+1 -0)

 SparcISelDAGToDAG.cpp |1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.89 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.90
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.89Thu Mar 16 19:40:33 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Sat Mar 25 00:47:10 2006
@@ -15,6 +15,7 @@
 #include SparcTargetMachine.h
 #include llvm/DerivedTypes.h
 #include llvm/Function.h
+#include llvm/Intrinsics.h
 #include llvm/CodeGen/MachineFrameInfo.h
 #include llvm/CodeGen/MachineFunction.h
 #include llvm/CodeGen/MachineInstrBuilder.h



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-02-16 Thread Nate Begeman 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.85 - 1.86
---
Log message:

Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.


---
Diffs of the changes:  (+26 -13)

 SparcISelDAGToDAG.cpp |   39 ++-
 1 files changed, 26 insertions(+), 13 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.85 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.86
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.85Wed Feb 15 00:41:34 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu Feb 16 15:11:51 2006
@@ -98,11 +98,14 @@
 SparcTargetLowering(TargetMachine TM);
 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG DAG);
 
-/// isMaskedValueZeroForTargetNode - Return true if 'Op  Mask' is known to
-/// be zero. Op is expected to be a target specific node. Used by DAG
-/// combiner.
-virtual bool isMaskedValueZeroForTargetNode(const SDOperand Op,
-uint64_t Mask) const;
+/// computeMaskedBitsForTargetNode - Determine which of the bits specified 
+/// in Mask are known to be either zero or one and return them in the 
+/// KnownZero/KnownOne bitsets.
+virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
+uint64_t Mask,
+uint64_t KnownZero, 
+uint64_t KnownOne,
+unsigned Depth = 0) const;
 
 virtual std::vectorSDOperand
   LowerArguments(Function F, SelectionDAG DAG);
@@ -246,20 +249,30 @@
 /// isMaskedValueZeroForTargetNode - Return true if 'Op  Mask' is known to
 /// be zero. Op is expected to be a target specific node. Used by DAG
 /// combiner.
-bool SparcTargetLowering::
-isMaskedValueZeroForTargetNode(const SDOperand Op, uint64_t Mask) const {
+void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
+ uint64_t Mask,
+ uint64_t KnownZero, 
+ uint64_t KnownOne,
+ unsigned Depth) const 
{
+  uint64_t KnownZero2, KnownOne2;
+  KnownZero = KnownOne = 0;   // Don't know anything.
+  
   switch (Op.getOpcode()) {
-  default: return false; 
+  default: break;
   case SPISD::SELECT_ICC:
   case SPISD::SELECT_FCC:
-assert(MVT::isInteger(Op.getValueType())  Not an integer select!);
-// These operations are masked zero if both the left and the right are 
zero.
-return MaskedValueIsZero(Op.getOperand(0), Mask) 
-   MaskedValueIsZero(Op.getOperand(1), Mask);
+ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
+ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
+assert((KnownZero  KnownOne) == 0  Bits known to be one AND zero?); 
+assert((KnownZero2  KnownOne2) == 0  Bits known to be one AND zero?); 
+
+// Only known if known in both the LHS and RHS.
+KnownOne = KnownOne2;
+KnownZero = KnownZero2;
+break;
   }
 }
 
-
 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
 /// either one or two GPRs, including FP values.  TODO: we should pass FP 
values
 /// in FP registers for fastcc functions.



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp SparcInstrInfo.td

2006-02-16 Thread Nate Begeman 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.86 - 1.87
SparcInstrInfo.td updated: 1.121 - 1.122
---
Log message:

kill ADD_PARTS  SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for 
significant simplifications in the targets.


---
Diffs of the changes:  (+18 -41)

 SparcISelDAGToDAG.cpp |   35 ---
 SparcInstrInfo.td |   24 ++--
 2 files changed, 18 insertions(+), 41 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.86 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.87
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.86Thu Feb 16 15:11:51 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu Feb 16 23:43:56 2006
@@ -1075,41 +1075,6 @@
   
   switch (N-getOpcode()) {
   default: break;
-  case ISD::ADD_PARTS: {
-SDOperand LHSL, LHSH, RHSL, RHSH;
-Select(LHSL, N-getOperand(0));
-Select(LHSH, N-getOperand(1));
-Select(RHSL, N-getOperand(2));
-Select(RHSH, N-getOperand(3));
-// FIXME, handle immediate RHS.
-SDOperand Low =
-  SDOperand(CurDAG-getTargetNode(SP::ADDCCrr, MVT::i32, MVT::Flag,
-  LHSL, RHSL), 0);
-SDOperand Hi =
-  SDOperand(CurDAG-getTargetNode(SP::ADDXrr, MVT::i32, LHSH, RHSH, 
-  Low.getValue(1)), 0);
-CodeGenMap[SDOperand(N, 0)] = Low;
-CodeGenMap[SDOperand(N, 1)] = Hi;
-Result = Op.ResNo ? Hi : Low;
-return;
-  }
-  case ISD::SUB_PARTS: {
-SDOperand LHSL, LHSH, RHSL, RHSH;
-Select(LHSL, N-getOperand(0));
-Select(LHSH, N-getOperand(1));
-Select(RHSL, N-getOperand(2));
-Select(RHSH, N-getOperand(3));
-SDOperand Low =
-  SDOperand(CurDAG-getTargetNode(SP::SUBCCrr, MVT::i32, MVT::Flag,
-  LHSL, RHSL), 0);
-SDOperand Hi =
-  SDOperand(CurDAG-getTargetNode(SP::SUBXrr, MVT::i32, LHSH, RHSH, 
-  Low.getValue(1)), 0);
-CodeGenMap[SDOperand(N, 0)] = Low;
-CodeGenMap[SDOperand(N, 1)] = Hi;
-Result = Op.ResNo ? Hi : Low;
-return;
-  }
   case ISD::SDIV:
   case ISD::UDIV: {
 // FIXME: should use a custom expander to expose the SRA to the dag.


Index: llvm/lib/Target/Sparc/SparcInstrInfo.td
diff -u llvm/lib/Target/Sparc/SparcInstrInfo.td:1.121 
llvm/lib/Target/Sparc/SparcInstrInfo.td:1.122
--- llvm/lib/Target/Sparc/SparcInstrInfo.td:1.121   Fri Feb 10 01:35:42 2006
+++ llvm/lib/Target/Sparc/SparcInstrInfo.td Thu Feb 16 23:43:56 2006
@@ -453,16 +453,20 @@

 def ADDCCrr : F3_12, 0b01, 
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-   addcc $b, $c, $dst, [];
+   addcc $b, $c, $dst,
+   [(set IntRegs:$dst, (addc IntRegs:$b, IntRegs:$c))];
 def ADDCCri : F3_22, 0b01,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
-   addcc $b, $c, $dst, [];
+   addcc $b, $c, $dst, 
+   [(set IntRegs:$dst, (addc IntRegs:$b, simm13:$c))];
 def ADDXrr  : F3_12, 0b001000, 
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-   addx $b, $c, $dst, [];
+   addx $b, $c, $dst,
+   [(set IntRegs:$dst, (adde IntRegs:$b, IntRegs:$c))];
 def ADDXri  : F3_22, 0b001000,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
-   addx $b, $c, $dst, [];
+   addx $b, $c, $dst,
+   [(set IntRegs:$dst, (adde IntRegs:$b, simm13:$c))];
 
 // Section B.15 - Subtract Instructions, p. 110
 def SUBrr   : F3_12, 0b000100, 
@@ -475,10 +479,12 @@
[(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))];
 def SUBXrr  : F3_12, 0b001100, 
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-   subx $b, $c, $dst, [];
+   subx $b, $c, $dst,
+   [(set IntRegs:$dst, (sube IntRegs:$b, IntRegs:$c))];
 def SUBXri  : F3_22, 0b001100,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
-   subx $b, $c, $dst, [];
+   subx $b, $c, $dst,
+   [(set IntRegs:$dst, (sube IntRegs:$b, simm13:$c))];
 def SUBCCrr : F3_12, 0b010100, 
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
subcc $b, $c, $dst,
@@ -866,6 +872,12 @@
 def : Pat(i32 imm:$val),
   (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val));
 
+// subc
+def : Pat(subc IntRegs:$b, IntRegs:$c),
+  (SUBCCrr IntRegs:$b, IntRegs:$c);
+def : Pat(subc IntRegs:$b, simm13:$val),
+  (SUBCCri IntRegs:$b, imm:$val);
+
 // Global addresses, constant pool entries
 def : Pat(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in);
 def : Pat(SPlo tglobaladdr:$in), (ORri G0,

[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-02-14 Thread Chris Lattner 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.84 - 1.85
---
Log message:

Fix SingleSource/Regression/C/2004-08-12-InlinerAndAllocas.c on Sparc.

The ABI specifies that there is a register save area at the bottom of the
stack, which means the actual used pointer needs to be an offset from 
the subtracted value.


---
Diffs of the changes:  (+22 -1)

 SparcISelDAGToDAG.cpp |   23 ++-
 1 files changed, 22 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.84 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.85
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.84Mon Feb 13 03:00:43 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Wed Feb 15 00:41:34 2006
@@ -211,7 +211,7 @@
   setOperationAction(ISD::VAEND , MVT::Other, Expand);
   setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 
   setOperationAction(ISD::STACKRESTORE  , MVT::Other, Expand);
-  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Expand);
+  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
 
   setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
   setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
@@ -807,6 +807,27 @@
   return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
 }
   }
+  case ISD::DYNAMIC_STACKALLOC: {
+SDOperand Chain = Op.getOperand(0);  // Legalize the chain.
+SDOperand Size  = Op.getOperand(1);  // Legalize the size.
+
+unsigned SPReg = SP::O6;
+SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
+SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size);// Value
+Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP);  // Output 
chain
+
+// The resultant pointer is actually 16 words from the bottom of the stack,
+// to provide a register spill area.
+SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
+   DAG.getConstant(96, MVT::i32));
+std::vectorMVT::ValueType Tys;
+Tys.push_back(MVT::i32);
+Tys.push_back(MVT::Other);
+std::vectorSDOperand Ops;
+Ops.push_back(NewVal);
+Ops.push_back(Chain);
+return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
+  }
   case ISD::RET: {
 SDOperand Copy;
 



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-02-13 Thread Chris Lattner 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.83 - 1.84
---
Log message:

Switch targets over to using SelectionDAG::getCALLSEQ_START to create
CALLSEQ_START nodes.


---
Diffs of the changes:  (+1 -2)

 SparcISelDAGToDAG.cpp |3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.83 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.84
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.83Fri Feb 10 01:35:42 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Mon Feb 13 03:00:43 2006
@@ -481,8 +481,7 @@
   // Keep stack frames 8-byte aligned.
   ArgsSize = (ArgsSize+7)  ~7;
 
-  Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
-  DAG.getConstant(ArgsSize, getPointerTy()));
+  Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, 
getPointerTy()));
   
   SDOperand StackPtr, NullSV;
   std::vectorSDOperand Stores;



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-02-08 Thread Evan Cheng 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.79 - 1.80
---
Log message:

Change Select() from 
SDOperand Select(SDOperand N);
to
void Select(SDOperand Result, SDOperand N);


---
Diffs of the changes:  (+49 -32)

 SparcISelDAGToDAG.cpp |   81 ++
 1 files changed, 49 insertions(+), 32 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.79 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.80
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.79Sun Feb  5 02:35:50 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Wed Feb  8 18:37:58 2006
@@ -934,7 +934,7 @@
   Subtarget(TM.getSubtargetSparcSubtarget()) {
   }
 
-  SDOperand Select(SDOperand Op);
+  void Select(SDOperand Result, SDOperand Op);
 
   // Complex Pattern Selectors.
   bool SelectADDRrr(SDOperand N, SDOperand R1, SDOperand R2);
@@ -1025,33 +1025,44 @@
   return true;
 }
 
-SDOperand SparcDAGToDAGISel::Select(SDOperand Op) {
+void SparcDAGToDAGISel::Select(SDOperand Result, SDOperand Op) {
   SDNode *N = Op.Val;
   if (N-getOpcode() = ISD::BUILTIN_OP_END 
-  N-getOpcode()  SPISD::FIRST_NUMBER)
-return Op;   // Already selected.
+  N-getOpcode()  SPISD::FIRST_NUMBER) {
+Result = Op;
+return;   // Already selected.
+  }
+
  // If this has already been converted, use it.
   std::mapSDOperand, SDOperand::iterator CGMI = CodeGenMap.find(Op);
-  if (CGMI != CodeGenMap.end()) return CGMI-second;
+  if (CGMI != CodeGenMap.end()) {
+Result = CGMI-second;
+return;
+  }
   
   switch (N-getOpcode()) {
   default: break;
   case ISD::FrameIndex: {
 int FI = castFrameIndexSDNode(N)-getIndex();
-if (N-hasOneUse())
-  return CurDAG-SelectNodeTo(N, SP::ADDri, MVT::i32,
-  CurDAG-getTargetFrameIndex(FI, MVT::i32),
-  CurDAG-getTargetConstant(0, MVT::i32));
-return CodeGenMap[Op] = 
+if (N-hasOneUse()) {
+  Result = CurDAG-SelectNodeTo(N, SP::ADDri, MVT::i32,
+CurDAG-getTargetFrameIndex(FI, MVT::i32),
+CurDAG-getTargetConstant(0, MVT::i32));
+  return;
+}
+
+Result = CodeGenMap[Op] = 
   CurDAG-getTargetNode(SP::ADDri, MVT::i32,
 CurDAG-getTargetFrameIndex(FI, MVT::i32),
 CurDAG-getTargetConstant(0, MVT::i32));
+return;
   }
   case ISD::ADD_PARTS: {
-SDOperand LHSL = Select(N-getOperand(0));
-SDOperand LHSH = Select(N-getOperand(1));
-SDOperand RHSL = Select(N-getOperand(2));
-SDOperand RHSH = Select(N-getOperand(3));
+SDOperand LHSL, LHSH, RHSL, RHSH;
+Select(LHSL, N-getOperand(0));
+Select(LHSH, N-getOperand(1));
+Select(RHSL, N-getOperand(2));
+Select(RHSH, N-getOperand(3));
 // FIXME, handle immediate RHS.
 SDOperand Low = CurDAG-getTargetNode(SP::ADDCCrr, MVT::i32, MVT::Flag,
   LHSL, RHSL);
@@ -1059,27 +1070,30 @@
   Low.getValue(1));
 CodeGenMap[SDOperand(N, 0)] = Low;
 CodeGenMap[SDOperand(N, 1)] = Hi;
-return Op.ResNo ? Hi : Low;
+Result = Op.ResNo ? Hi : Low;
+return;
   }
   case ISD::SUB_PARTS: {
-SDOperand LHSL = Select(N-getOperand(0));
-SDOperand LHSH = Select(N-getOperand(1));
-SDOperand RHSL = Select(N-getOperand(2));
-SDOperand RHSH = Select(N-getOperand(3));
-// FIXME, handle immediate RHS.
+SDOperand LHSL, LHSH, RHSL, RHSH;
+Select(LHSL, N-getOperand(0));
+Select(LHSH, N-getOperand(1));
+Select(RHSL, N-getOperand(2));
+Select(RHSH, N-getOperand(3));
 SDOperand Low = CurDAG-getTargetNode(SP::SUBCCrr, MVT::i32, MVT::Flag,
   LHSL, RHSL);
 SDOperand Hi  = CurDAG-getTargetNode(SP::SUBXrr, MVT::i32, LHSH, RHSH, 
   Low.getValue(1));
 CodeGenMap[SDOperand(N, 0)] = Low;
 CodeGenMap[SDOperand(N, 1)] = Hi;
-return Op.ResNo ? Hi : Low;
+Result = Op.ResNo ? Hi : Low;
+return;
   }
   case ISD::SDIV:
   case ISD::UDIV: {
 // FIXME: should use a custom expander to expose the SRA to the dag.
-SDOperand DivLHS = Select(N-getOperand(0));
-SDOperand DivRHS = Select(N-getOperand(1));
+SDOperand DivLHS, DivRHS;
+Select(DivLHS, N-getOperand(0));
+Select(DivRHS, N-getOperand(1));
 
 // Set the Y register to the high-part.
 SDOperand TopPart;
@@ -1094,18 +1108,21 @@
 
 // FIXME: Handle div by immediate.
 unsigned Opcode = N-getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
-return CurDAG-SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
+Result = CurDAG-SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, 
TopPart);
+return;
   }
   case ISD::MULHU:
   case ISD::MULHS: {
 //

[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-02-08 Thread Chris Lattner 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.80 - 1.81
---
Log message:

Adjust to MachineConstantPool interface change: instead of keeping a 
value/alignment pair for each constant, keep a value/offset pair.


---
Diffs of the changes:  (+1 -1)

 SparcISelDAGToDAG.cpp |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.80 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.81
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.80Wed Feb  8 18:37:58 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Wed Feb  8 22:46:04 2006
@@ -968,7 +968,7 @@
 }
 
 bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand Base,
-   SDOperand Offset) {
+ SDOperand Offset) {
   if (FrameIndexSDNode *FIN = dyn_castFrameIndexSDNode(Addr)) {
 Base = CurDAG-getTargetFrameIndex(FIN-getIndex(), MVT::i32);
 Offset = CurDAG-getTargetConstant(0, MVT::i32);



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-02-08 Thread Evan Cheng 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.81 - 1.82
---
Log message:

Match getTargetNode() changes (now return SDNode* instead of SDOperand).


---
Diffs of the changes:  (+29 -24)

 SparcISelDAGToDAG.cpp |   53 +++---
 1 files changed, 29 insertions(+), 24 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.81 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.82
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.81Wed Feb  8 22:46:04 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu Feb  9 01:17:49 2006
@@ -1052,9 +1052,9 @@
 }
 
 Result = CodeGenMap[Op] = 
-  CurDAG-getTargetNode(SP::ADDri, MVT::i32,
-CurDAG-getTargetFrameIndex(FI, MVT::i32),
-CurDAG-getTargetConstant(0, MVT::i32));
+  SDOperand(CurDAG-getTargetNode(SP::ADDri, MVT::i32,
+  CurDAG-getTargetFrameIndex(FI, 
MVT::i32),
+CurDAG-getTargetConstant(0, MVT::i32)), 
0);
 return;
   }
   case ISD::ADD_PARTS: {
@@ -1064,10 +1064,12 @@
 Select(RHSL, N-getOperand(2));
 Select(RHSH, N-getOperand(3));
 // FIXME, handle immediate RHS.
-SDOperand Low = CurDAG-getTargetNode(SP::ADDCCrr, MVT::i32, MVT::Flag,
-  LHSL, RHSL);
-SDOperand Hi  = CurDAG-getTargetNode(SP::ADDXrr, MVT::i32, LHSH, RHSH, 
-  Low.getValue(1));
+SDOperand Low =
+  SDOperand(CurDAG-getTargetNode(SP::ADDCCrr, MVT::i32, MVT::Flag,
+  LHSL, RHSL), 0);
+SDOperand Hi =
+  SDOperand(CurDAG-getTargetNode(SP::ADDXrr, MVT::i32, LHSH, RHSH, 
+  Low.getValue(1)), 0);
 CodeGenMap[SDOperand(N, 0)] = Low;
 CodeGenMap[SDOperand(N, 1)] = Hi;
 Result = Op.ResNo ? Hi : Low;
@@ -1079,10 +1081,12 @@
 Select(LHSH, N-getOperand(1));
 Select(RHSL, N-getOperand(2));
 Select(RHSH, N-getOperand(3));
-SDOperand Low = CurDAG-getTargetNode(SP::SUBCCrr, MVT::i32, MVT::Flag,
-  LHSL, RHSL);
-SDOperand Hi  = CurDAG-getTargetNode(SP::SUBXrr, MVT::i32, LHSH, RHSH, 
-  Low.getValue(1));
+SDOperand Low =
+  SDOperand(CurDAG-getTargetNode(SP::SUBCCrr, MVT::i32, MVT::Flag,
+  LHSL, RHSL), 0);
+SDOperand Hi =
+  SDOperand(CurDAG-getTargetNode(SP::SUBXrr, MVT::i32, LHSH, RHSH, 
+  Low.getValue(1)), 0);
 CodeGenMap[SDOperand(N, 0)] = Low;
 CodeGenMap[SDOperand(N, 1)] = Hi;
 Result = Op.ResNo ? Hi : Low;
@@ -1098,13 +1102,13 @@
 // Set the Y register to the high-part.
 SDOperand TopPart;
 if (N-getOpcode() == ISD::SDIV) {
-  TopPart = CurDAG-getTargetNode(SP::SRAri, MVT::i32, DivLHS,
-  CurDAG-getTargetConstant(31, MVT::i32));
+  TopPart = SDOperand(CurDAG-getTargetNode(SP::SRAri, MVT::i32, DivLHS,
+   CurDAG-getTargetConstant(31, MVT::i32)), 
0);
 } else {
   TopPart = CurDAG-getRegister(SP::G0, MVT::i32);
 }
-TopPart = CurDAG-getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
-CurDAG-getRegister(SP::G0, MVT::i32));
+TopPart = SDOperand(CurDAG-getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
+ CurDAG-getRegister(SP::G0, MVT::i32)), 
0);
 
 // FIXME: Handle div by immediate.
 unsigned Opcode = N-getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
@@ -1118,10 +1122,10 @@
 Select(MulLHS, N-getOperand(0));
 Select(MulRHS, N-getOperand(1));
 unsigned Opcode = N-getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
-SDOperand Mul = CurDAG-getTargetNode(Opcode, MVT::i32, MVT::Flag,
+SDNode *Mul = CurDAG-getTargetNode(Opcode, MVT::i32, MVT::Flag,
   MulLHS, MulRHS);
 // The high part is in the Y register.
-Result = CurDAG-SelectNodeTo(N, SP::RDY, MVT::i32, Mul.getValue(1));
+Result = CurDAG-SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
 return;
   }
   case SPISD::CALL:
@@ -1136,17 +1140,18 @@
 SDOperand Chain = N-getOperand(0);
 SDOperand Tmp0 = N1;
 Select(Chain, Chain);
+SDNode *ResNode;
 if (N-getNumOperands() == 3) {
   Select(InFlag, N-getOperand(2));
-  Result = CurDAG-getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0, 
- Chain, InFlag);
+  ResNode = CurDAG-getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0, 
+  Chain, InFlag);
 } else {
-  Result = CurDAG-getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0, 
- Chain);
+

[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

2006-02-04 Thread Evan Cheng 


Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.77 - 1.78
---
Log message:

Use SelectRoot() as the entry to any tblgen based isel.


---
Diffs of the changes:  (+2 -1)

 SparcISelDAGToDAG.cpp |3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.77 
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.78
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.77Sat Feb  4 23:50:24 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Sun Feb  5 00:51:51 2006
@@ -24,6 +24,7 @@
 #include llvm/Target/TargetLowering.h
 #include llvm/Support/Debug.h
 #include iostream
+#include set
 using namespace llvm;
 
 
//===--===//
@@ -958,7 +959,7 @@
   DEBUG(BB-dump());
   
   // Select target instructions for the DAG.
-  DAG.setRoot(Select(DAG.getRoot()));
+  DAG.setRoot(SelectRoot(DAG.getRoot()));
   CodeGenMap.clear();
   DAG.RemoveDeadNodes();
   



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