[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.5 -> 1.6 --- Log message: Add undef --- Diffs of the changes: (+3 -1) TargetSelectionDAG.td |4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.5 llvm/lib/Target/TargetSelectionDAG.td:1.6 --- llvm/lib/Target/TargetSelectionDAG.td:1.5 Thu Oct 20 18:30:37 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Tue Oct 25 16:03:14 2005 @@ -68,7 +68,8 @@ // Builtin profiles. def SDTImm: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. -def SDTVT : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt' +def SDTVT : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. +def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> ]>; @@ -123,6 +124,7 @@ def imm: SDNode<"ISD::Constant" , SDTImm , [], "ConstantSDNode">; def vt : SDNode<"ISD::VALUETYPE" , SDTVT , [], "VTSDNode">; +def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; def add: SDNode<"ISD::ADD" , SDTIntBinOp , [SDNPCommutative, SDNPAssociative]>; def sub: SDNode<"ISD::SUB" , SDTIntBinOp>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.6 -> 1.7 --- Log message: Add nodes for CondCodeSDNode and setcc, and add a bunch of pattern fragments to make it easy to use them. This lets you write patterns like: (set PRRC:$rd, (setne GPRC:$rS, imm:$SH)) and stuff. --- Diffs of the changes: (+64 -0) TargetSelectionDAG.td | 64 ++ 1 files changed, 64 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.6 llvm/lib/Target/TargetSelectionDAG.td:1.7 --- llvm/lib/Target/TargetSelectionDAG.td:1.6 Tue Oct 25 16:03:14 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Wed Oct 26 12:00:25 2005 @@ -99,6 +99,10 @@ SDTCisVTSmallerThanOp<2, 1> ]>; +def SDTSetCC : SDTypeProfile<1, 3, [ // setcc + SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> +]>; + //===--===// // Selection DAG Node Properties. // @@ -124,6 +128,7 @@ def imm: SDNode<"ISD::Constant" , SDTImm , [], "ConstantSDNode">; def vt : SDNode<"ISD::VALUETYPE" , SDTVT , [], "VTSDNode">; +def cond : SDNode<"ISD::CONDCODE" , SDTVT , [], "CondCodeSDNode">; def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; def add: SDNode<"ISD::ADD" , SDTIntBinOp , [SDNPCommutative, SDNPAssociative]>; @@ -167,6 +172,22 @@ def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; def fextend: SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; +def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; + +//===--===// +// Selection DAG Condition Codes + +class CondCode; // ISD::CondCode enums +def SETOEQ : CondCode; def SETOGT : CondCode; +def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; +def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; +def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; +def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; + +def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; +def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; + + //===--===// // Selection DAG Node Transformation Functions. // @@ -219,6 +240,49 @@ def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>; def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; + +// setcc convenience fragments. +def setoeq : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETOEQ)>; +def setogt : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETOGT)>; +def setoge : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETOGE)>; +def setolt : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETOLT)>; +def setole : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETOLE)>; +def setone : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETONE)>; +def seto : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETO)>; +def setuo : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETUO)>; +def setueq : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETUEQ)>; +def setugt : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETUGT)>; +def setuge : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETUGE)>; +def setult : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETULT)>; +def setule : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETULE)>; +def setune : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETUNE)>; +def seteq : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETEQ)>; +def setgt : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETGT)>; +def setge : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETGE)>; +def setlt : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETLT)>; +def setle : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETLE)>; +def setne : PatFrag<(ops node:$lhs, node:$rhs), + (setcc node:$lhs, node:$rhs, SETNE)>; + //===--===// // Selection DAG Pattern Support. // ___
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.7 -> 1.8 --- Log message: add support for int->FP and FP->int ops, and add ia64 patterns for these --- Diffs of the changes: (+11 -0) TargetSelectionDAG.td | 11 +++ 1 files changed, 11 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.7 llvm/lib/Target/TargetSelectionDAG.td:1.8 --- llvm/lib/Target/TargetSelectionDAG.td:1.7 Wed Oct 26 12:00:25 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Mon Oct 31 21:07:25 2005 @@ -94,6 +94,12 @@ def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> ]>; +def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp + SDTCisFP<0>, SDTCisInt<1> +]>; +def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int + SDTCisInt<0>, SDTCisFP<1> +]>; def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, SDTCisVTSmallerThanOp<2, 1> @@ -172,6 +178,11 @@ def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; def fextend: SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; +def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; +def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; +def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; +def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; + def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; //===--===// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.8 -> 1.9 --- Log message: add support for SELECT to TargetSelectionDAG.td, add support for selecting ints to IA64, and a few other ia64 bits and pieces --- Diffs of the changes: (+5 -0) TargetSelectionDAG.td |5 + 1 files changed, 5 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.8 llvm/lib/Target/TargetSelectionDAG.td:1.9 --- llvm/lib/Target/TargetSelectionDAG.td:1.8 Mon Oct 31 21:07:25 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Tue Nov 1 20:37:18 2005 @@ -109,6 +109,10 @@ SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> ]>; +def SDTSelect : SDTypeProfile<1, 3, [ // select + SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> +]>; + //===--===// // Selection DAG Node Properties. // @@ -184,6 +188,7 @@ def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; +def select : SDNode<"ISD::SELECT" , SDTSelect>; //===--===// // Selection DAG Condition Codes ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.9 -> 1.10 --- Log message: Add globaladdress and targetglobaladdress nodes for dag patterns --- Diffs of the changes: (+4 -0) TargetSelectionDAG.td |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.9 llvm/lib/Target/TargetSelectionDAG.td:1.10 --- llvm/lib/Target/TargetSelectionDAG.td:1.9 Tue Nov 1 20:37:18 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Thu Nov 17 01:20:15 2005 @@ -140,6 +140,10 @@ def vt : SDNode<"ISD::VALUETYPE" , SDTVT , [], "VTSDNode">; def cond : SDNode<"ISD::CONDCODE" , SDTVT , [], "CondCodeSDNode">; def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; +def globaladdr : SDNode<"ISD::GlobalAddress", SDTImm, [], +"GlobalAddressSDNode">; +def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTImm, [], +"GlobalAddressSDNode">; def add: SDNode<"ISD::ADD" , SDTIntBinOp , [SDNPCommutative, SDNPAssociative]>; def sub: SDNode<"ISD::SUB" , SDTIntBinOp>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.11 -> 1.12 --- Log message: On some targets (e.g. X86), shift amounts are not the same as the value being shifted. Don't assume they are. --- Diffs of the changes: (+6 -3) TargetSelectionDAG.td |9 ++--- 1 files changed, 6 insertions(+), 3 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.11 llvm/lib/Target/TargetSelectionDAG.td:1.12 --- llvm/lib/Target/TargetSelectionDAG.td:1.11 Sun Dec 4 02:13:17 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Sun Dec 4 20:37:26 2005 @@ -73,6 +73,9 @@ def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> ]>; +def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl + SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> +]>; def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> ]>; @@ -172,9 +175,9 @@ def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; -def srl: SDNode<"ISD::SRL" , SDTIntBinOp>; -def sra: SDNode<"ISD::SRA" , SDTIntBinOp>; -def shl: SDNode<"ISD::SHL" , SDTIntBinOp>; +def srl: SDNode<"ISD::SRL" , SDTIntShiftOp>; +def sra: SDNode<"ISD::SRA" , SDTIntShiftOp>; +def shl: SDNode<"ISD::SHL" , SDTIntShiftOp>; def and: SDNode<"ISD::AND" , SDTIntBinOp, [SDNPCommutative, SDNPAssociative]>; def or : SDNode<"ISD::OR", SDTIntBinOp, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.12 -> 1.13
---
Log message:
Added support for ComplexPattern.
---
Diffs of the changes: (+21 -0)
TargetSelectionDAG.td | 21 +
1 files changed, 21 insertions(+)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.12
llvm/lib/Target/TargetSelectionDAG.td:1.13
--- llvm/lib/Target/TargetSelectionDAG.td:1.12 Sun Dec 4 20:37:26 2005
+++ llvm/lib/Target/TargetSelectionDAG.td Wed Dec 7 22:28:48 2005
@@ -131,6 +131,10 @@
SDTCisInt<0>, SDTCisInt<1>
]>;
+def SDTLoad : SDTypeProfile<1, 1, [ // load
+ SDTCisInt<1>
+]>;
+
//===--===//
// Selection DAG Node Properties.
//
@@ -220,6 +224,8 @@
def writeport : SDNode<"ISD::WRITEPORT" , SDTWritePort, [SDNPHasChain]>;
+def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
+
//===--===//
// Selection DAG Condition Codes
@@ -349,3 +355,18 @@
// not needing a full list.
class Pat : Pattern;
+//===--===//
+// Complex pattern definitions.
+//
+// Complex patterns, e.g. X86 addressing mode, requires pattern matching code
+// in C++. NumOperands is the number of operands returned by the select
function;
+// SelectFunc is the name of the function used to pattern match the max.
pattern;
+// RootNodes are the list of possible root nodes of the sub-dags to match.
+// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr",
[add]>;
+//
+class ComplexPattern roots =
[]> {
+ ValueType Ty = ty;
+ int NumOperands = numops;
+ string SelectFunc = fn;
+ list RootNodes = roots;
+}
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.13 -> 1.14
---
Log message:
Add SDTCisPtrTy and use it for loads, to indicate that the operand of a load
must be a pointer. This removes a type check out of the code generated by
tblgen for load matching.
---
Diffs of the changes: (+5 -3)
TargetSelectionDAG.td |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.13
llvm/lib/Target/TargetSelectionDAG.td:1.14
--- llvm/lib/Target/TargetSelectionDAG.td:1.13 Wed Dec 7 22:28:48 2005
+++ llvm/lib/Target/TargetSelectionDAG.td Fri Dec 9 16:58:42 2005
@@ -24,15 +24,17 @@
}
// SDTCisVT - The specified operand has exactly this VT.
-class SDTCisVT : SDTypeConstraint {
+class SDTCisVT : SDTypeConstraint {
ValueType VT = vt;
}
+class SDTCisPtrTy : SDTypeConstraint;
+
// SDTCisInt - The specified operand is has integer type.
class SDTCisInt : SDTypeConstraint;
// SDTCisFP - The specified operand is has floating point type.
-class SDTCisFP : SDTypeConstraint;
+class SDTCisFP : SDTypeConstraint;
// SDTCisSameAs - The two specified operands have identical types.
class SDTCisSameAs : SDTypeConstraint {
@@ -132,7 +134,7 @@
]>;
def SDTLoad : SDTypeProfile<1, 1, [ // load
- SDTCisInt<1>
+ SDTCisPtrTy<1>
]>;
//===--===//
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.14 -> 1.15 --- Log message: * Added X86 store patterns. * Added X86 dec patterns. --- Diffs of the changes: (+5 -0) TargetSelectionDAG.td |5 + 1 files changed, 5 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.14 llvm/lib/Target/TargetSelectionDAG.td:1.15 --- llvm/lib/Target/TargetSelectionDAG.td:1.14 Fri Dec 9 16:58:42 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Fri Dec 9 18:48:20 2005 @@ -137,6 +137,10 @@ SDTCisPtrTy<1> ]>; +def SDTStore : SDTypeProfile<0, 2, [ // store + SDTCisInt<1> +]>; + //===--===// // Selection DAG Node Properties. // @@ -227,6 +231,7 @@ def writeport : SDNode<"ISD::WRITEPORT" , SDTWritePort, [SDNPHasChain]>; def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>; +def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>; //===--===// // Selection DAG Condition Codes ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.15 -> 1.16 --- Log message: Use SDTCisPtrTy type property for store address. --- Diffs of the changes: (+2 -2) TargetSelectionDAG.td |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.15 llvm/lib/Target/TargetSelectionDAG.td:1.16 --- llvm/lib/Target/TargetSelectionDAG.td:1.15 Fri Dec 9 18:48:20 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Fri Dec 9 19:59:36 2005 @@ -138,7 +138,7 @@ ]>; def SDTStore : SDTypeProfile<0, 2, [ // store - SDTCisInt<1> + SDTCisPtrTy<1> ]>; //===--===// @@ -230,7 +230,7 @@ def writeport : SDNode<"ISD::WRITEPORT" , SDTWritePort, [SDNPHasChain]>; -def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>; +def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>; def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>; //===--===// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.16 -> 1.17 --- Log message: Add support for TargetConstantPool nodes to the dag isel emitter, and use them in the PPC backend, to simplify some logic out of Select and SelectAddr. --- Diffs of the changes: (+2 -0) TargetSelectionDAG.td |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.16 llvm/lib/Target/TargetSelectionDAG.td:1.17 --- llvm/lib/Target/TargetSelectionDAG.td:1.16 Fri Dec 9 19:59:36 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Fri Dec 9 20:36:00 2005 @@ -174,6 +174,8 @@ "GlobalAddressSDNode">; def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTImm, [], "GlobalAddressSDNode">; +def tconstpool : SDNode<"ISD::TargetConstantPool", SDTImm, [], +"ConstantPoolSDNode">; def add: SDNode<"ISD::ADD" , SDTIntBinOp , [SDNPCommutative, SDNPAssociative]>; def sub: SDNode<"ISD::SUB" , SDTIntBinOp>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.17 -> 1.18 --- Log message: Realize the constant pool & global addrs must always be ptr type --- Diffs of the changes: (+6 -5) TargetSelectionDAG.td | 11 ++- 1 files changed, 6 insertions(+), 5 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.17 llvm/lib/Target/TargetSelectionDAG.td:1.18 --- llvm/lib/Target/TargetSelectionDAG.td:1.17 Fri Dec 9 20:36:00 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Sun Dec 11 01:45:04 2005 @@ -69,7 +69,8 @@ } // Builtin profiles. -def SDTImm: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. +def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. +def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. @@ -165,16 +166,16 @@ def set; def node; -def imm: SDNode<"ISD::Constant" , SDTImm , [], "ConstantSDNode">; +def imm: SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; -def globaladdr : SDNode<"ISD::GlobalAddress", SDTImm, [], +def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], "GlobalAddressSDNode">; -def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTImm, [], +def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], "GlobalAddressSDNode">; -def tconstpool : SDNode<"ISD::TargetConstantPool", SDTImm, [], +def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], "ConstantPoolSDNode">; def add: SDNode<"ISD::ADD" , SDTIntBinOp , [SDNPCommutative, SDNPAssociative]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.18 -> 1.19 --- Log message: add selectcc --- Diffs of the changes: (+6 -0) TargetSelectionDAG.td |6 ++ 1 files changed, 6 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.18 llvm/lib/Target/TargetSelectionDAG.td:1.19 --- llvm/lib/Target/TargetSelectionDAG.td:1.18 Sun Dec 11 01:45:04 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Sun Dec 11 02:35:54 2005 @@ -119,6 +119,11 @@ SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> ]>; +def SDTSelectCC : SDTypeProvile<1, 5, [ // select_cc + SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, + SDTCisVT<5, OtherVT> +]>; + def SDTBr : SDTypeProfile<0, 1, [ // br SDTCisVT<0, OtherVT> ]>; @@ -226,6 +231,7 @@ def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; def select : SDNode<"ISD::SELECT" , SDTSelect>; +def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; def brcond : SDNode<"ISD::BRCOND" , SDTBrCond, [SDNPHasChain]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.19 -> 1.20 --- Log message: Fix typo :( --- Diffs of the changes: (+1 -1) TargetSelectionDAG.td |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.19 llvm/lib/Target/TargetSelectionDAG.td:1.20 --- llvm/lib/Target/TargetSelectionDAG.td:1.19 Sun Dec 11 02:35:54 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Sun Dec 11 12:43:13 2005 @@ -119,7 +119,7 @@ SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> ]>; -def SDTSelectCC : SDTypeProvile<1, 5, [ // select_cc +def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, SDTCisVT<5, OtherVT> ]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.20 -> 1.21 --- Log message: Prepare support for AltiVec multiply, divide, and sqrt. --- Diffs of the changes: (+3 -0) TargetSelectionDAG.td |3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.20 llvm/lib/Target/TargetSelectionDAG.td:1.21 --- llvm/lib/Target/TargetSelectionDAG.td:1.20 Sun Dec 11 12:43:13 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Tue Dec 13 16:55:21 2005 @@ -82,6 +82,9 @@ def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> ]>; +def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. + SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> +]>; def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz SDTCisSameAs<0, 1>, SDTCisInt<0> ]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.21 -> 1.22 --- Log message: Added sextld + zextld DAG nodes. --- Diffs of the changes: (+17 -0) TargetSelectionDAG.td | 17 + 1 files changed, 17 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.21 llvm/lib/Target/TargetSelectionDAG.td:1.22 --- llvm/lib/Target/TargetSelectionDAG.td:1.21 Tue Dec 13 16:55:21 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Tue Dec 13 20:21:01 2005 @@ -150,6 +150,12 @@ SDTCisPtrTy<1> ]>; +def SDTIntExtLoad : SDTypeProfile<1, 3, [ // sextload, zextload + SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, + SDTCisVTSmallerThanOp<3, 0> +]>; + + //===--===// // Selection DAG Node Properties. // @@ -173,6 +179,7 @@ def set; def node; +def srcvalue; def imm: SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; @@ -245,6 +252,11 @@ def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>; def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>; +// Do not use sextld and zextld directly. Use sextload and zextload (see +// below) which pass in a dummy srcvalue node which tblgen will skip over. +def sextld : SDNode<"ISD::SEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>; +def zextld : SDNode<"ISD::ZEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>; + //===--===// // Selection DAG Condition Codes @@ -311,6 +323,11 @@ def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>; def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; +// extending load fragments. +def sextload : PatFrag<(ops node:$ptr, node:$vt), +(sextld node:$ptr, srcvalue:$dummy, node:$vt)>; +def zextload : PatFrag<(ops node:$ptr, node:$vt), +(zextld node:$ptr, srcvalue:$dummy, node:$vt)>; // setcc convenience fragments. def setoeq : PatFrag<(ops node:$lhs, node:$rhs), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.22 -> 1.23 --- Log message: Fixed extload type profile. The 4th operand is a ValueType node with type OtherVT, it cannot be compare to type of 1st operand which is an integer type. --- Diffs of the changes: (+1 -2) TargetSelectionDAG.td |3 +-- 1 files changed, 1 insertion(+), 2 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.22 llvm/lib/Target/TargetSelectionDAG.td:1.23 --- llvm/lib/Target/TargetSelectionDAG.td:1.22 Tue Dec 13 20:21:01 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Wed Dec 14 13:40:54 2005 @@ -151,8 +151,7 @@ ]>; def SDTIntExtLoad : SDTypeProfile<1, 3, [ // sextload, zextload - SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, - SDTCisVTSmallerThanOp<3, 0> + SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> ]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.24 -> 1.25 --- Log message: Added constpool, frameindex, and externalsym nodes. --- Diffs of the changes: (+9 -3) TargetSelectionDAG.td | 12 +--- 1 files changed, 9 insertions(+), 3 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.24 llvm/lib/Target/TargetSelectionDAG.td:1.25 --- llvm/lib/Target/TargetSelectionDAG.td:1.24 Wed Dec 14 16:02:59 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Thu Dec 15 02:29:48 2005 @@ -185,12 +185,18 @@ def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; -def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], +def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], "GlobalAddressSDNode">; -def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], +def tglobaladdr: SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], "GlobalAddressSDNode">; -def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], +def constpool : SDNode<"ISD::ConstantPool",SDTPtrLeaf, [], "ConstantPoolSDNode">; +def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], +"ConstantPoolSDNode">; +def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], +"FrameIndexSDNode">; +def externalsym: SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], +"ExternalSymbolSDNode">; def add: SDNode<"ISD::ADD" , SDTIntBinOp , [SDNPCommutative, SDNPAssociative]>; def sub: SDNode<"ISD::SUB" , SDTIntBinOp>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.25 -> 1.26 --- Log message: * Promote all 1 bit entities to 8 bit. * Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit zextload. --- Diffs of the changes: (+4 -1) TargetSelectionDAG.td |5 - 1 files changed, 4 insertions(+), 1 deletion(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.25 llvm/lib/Target/TargetSelectionDAG.td:1.26 --- llvm/lib/Target/TargetSelectionDAG.td:1.25 Thu Dec 15 02:29:48 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Thu Dec 15 13:49:22 2005 @@ -150,7 +150,7 @@ SDTCisPtrTy<1> ]>; -def SDTIntExtLoad : SDTypeProfile<1, 3, [ // sextload, zextload +def SDTIntExtLoad : SDTypeProfile<1, 3, [ // sextload, zextload, extload SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> ]>; @@ -261,6 +261,7 @@ // below) which pass in a dummy srcvalue node which tblgen will skip over. def sextld : SDNode<"ISD::SEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>; def zextld : SDNode<"ISD::ZEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>; +def extld : SDNode<"ISD::EXTLOAD", SDTIntExtLoad, [SDNPHasChain]>; //===--===// // Selection DAG Condition Codes @@ -333,6 +334,8 @@ (sextld node:$ptr, srcvalue:$dummy, node:$vt)>; def zextload : PatFrag<(ops node:$ptr, node:$vt), (zextld node:$ptr, srcvalue:$dummy, node:$vt)>; +def extload : PatFrag<(ops node:$ptr, node:$vt), +(extld node:$ptr, srcvalue:$dummy, node:$vt)>; // setcc convenience fragments. def setoeq : PatFrag<(ops node:$lhs, node:$rhs), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.26 -> 1.27 --- Log message: Added source file/line correspondence for dwarf (PowerPC only at this point.) --- Diffs of the changes: (+10 -0) TargetSelectionDAG.td | 10 ++ 1 files changed, 10 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.26 llvm/lib/Target/TargetSelectionDAG.td:1.27 --- llvm/lib/Target/TargetSelectionDAG.td:1.26 Thu Dec 15 13:49:22 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Fri Dec 16 16:45:29 2005 @@ -415,3 +415,13 @@ string SelectFunc = fn; list RootNodes = roots; } + +//===--===// +// Dwarf support. +// +def SDT_dwarf_loc : SDTypeProfile<0, 3, +[SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>; +def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>; + + + ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.27 -> 1.28 --- Log message: add truncstore --- Diffs of the changes: (+9 -3) TargetSelectionDAG.td | 12 +--- 1 files changed, 9 insertions(+), 3 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.27 llvm/lib/Target/TargetSelectionDAG.td:1.28 --- llvm/lib/Target/TargetSelectionDAG.td:1.27 Fri Dec 16 16:45:29 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Sat Dec 17 14:42:29 2005 @@ -135,8 +135,7 @@ SDTCisInt<0>, SDTCisVT<1, OtherVT> ]>; -def SDTRet : SDTypeProfile<0, 0, [ // ret -]>; +def SDTRet : SDTypeProfile<0, 0, []>; // ret def SDTWritePort : SDTypeProfile<0, 2, [ // writeport SDTCisInt<0>, SDTCisInt<1> @@ -153,6 +152,9 @@ def SDTIntExtLoad : SDTypeProfile<1, 3, [ // sextload, zextload, extload SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> ]>; +def SDTTruncStore : SDTypeProfile<0, 4, [ // truncstore + SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> +]>; //===--===// @@ -262,6 +264,7 @@ def sextld : SDNode<"ISD::SEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>; def zextld : SDNode<"ISD::ZEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>; def extld : SDNode<"ISD::EXTLOAD", SDTIntExtLoad, [SDNPHasChain]>; +def truncst: SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>; //===--===// // Selection DAG Condition Codes @@ -329,13 +332,16 @@ def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>; def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; -// extending load fragments. +// extending load & truncstore fragments. def sextload : PatFrag<(ops node:$ptr, node:$vt), (sextld node:$ptr, srcvalue:$dummy, node:$vt)>; def zextload : PatFrag<(ops node:$ptr, node:$vt), (zextld node:$ptr, srcvalue:$dummy, node:$vt)>; def extload : PatFrag<(ops node:$ptr, node:$vt), (extld node:$ptr, srcvalue:$dummy, node:$vt)>; +def truncstore: PatFrag<(ops node:$val, node:$ptr, node:$vt), +(truncst node:$val, node:$ptr, srcvalue:$dummy, +node:$vt)>; // setcc convenience fragments. def setoeq : PatFrag<(ops node:$lhs, node:$rhs), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.28 -> 1.29 --- Log message: Since extload can also be used by FP, split STDIntExtLoad into two parts, one for use with extload, one for use with sextload and zextload, which are integer only. --- Diffs of the changes: (+5 -2) TargetSelectionDAG.td |7 +-- 1 files changed, 5 insertions(+), 2 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.28 llvm/lib/Target/TargetSelectionDAG.td:1.29 --- llvm/lib/Target/TargetSelectionDAG.td:1.28 Sat Dec 17 14:42:29 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Sat Dec 17 20:48:48 2005 @@ -149,7 +149,10 @@ SDTCisPtrTy<1> ]>; -def SDTIntExtLoad : SDTypeProfile<1, 3, [ // sextload, zextload, extload +def SDTExtLoad : SDTypeProfile<1, 3, [ // extload + SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> +]>; +def SDTIntExtLoad : SDTypeProfile<1, 3, [ // sextload, zextload SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> ]>; def SDTTruncStore : SDTypeProfile<0, 4, [ // truncstore @@ -263,7 +266,7 @@ // below) which pass in a dummy srcvalue node which tblgen will skip over. def sextld : SDNode<"ISD::SEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>; def zextld : SDNode<"ISD::ZEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>; -def extld : SDNode<"ISD::EXTLOAD", SDTIntExtLoad, [SDNPHasChain]>; +def extld : SDNode<"ISD::EXTLOAD", SDTExtLoad,[SDNPHasChain]>; def truncst: SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>; //===--===// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.29 -> 1.30 --- Log message: add a node, for completeness --- Diffs of the changes: (+2 -0) TargetSelectionDAG.td |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.29 llvm/lib/Target/TargetSelectionDAG.td:1.30 --- llvm/lib/Target/TargetSelectionDAG.td:1.29 Sat Dec 17 20:48:48 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Sun Dec 18 01:05:21 2005 @@ -200,6 +200,8 @@ "ConstantPoolSDNode">; def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], "FrameIndexSDNode">; +def tframeindex: SDNode<"ISD::TargetFrameIndex",SDTPtrLeaf, [], +"FrameIndexSDNode">; def externalsym: SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], "ExternalSymbolSDNode">; def add: SDNode<"ISD::ADD" , SDTIntBinOp , ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.30 -> 1.31 --- Log message: X86 conditional branch support. --- Diffs of the changes: (+0 -5) TargetSelectionDAG.td |5 - 1 files changed, 5 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.30 llvm/lib/Target/TargetSelectionDAG.td:1.31 --- llvm/lib/Target/TargetSelectionDAG.td:1.30 Sun Dec 18 01:05:21 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Mon Dec 19 17:12:38 2005 @@ -131,10 +131,6 @@ SDTCisVT<0, OtherVT> ]>; -def SDTBrCond : SDTypeProfile<0, 2, [ // brcond - SDTCisInt<0>, SDTCisVT<1, OtherVT> -]>; - def SDTRet : SDTypeProfile<0, 0, []>; // ret def SDTWritePort : SDTypeProfile<0, 2, [ // writeport @@ -256,7 +252,6 @@ def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; -def brcond : SDNode<"ISD::BRCOND" , SDTBrCond, [SDNPHasChain]>; def ret: SDNode<"ISD::RET", SDTRet,[SDNPHasChain]>; def writeport : SDNode<"ISD::WRITEPORT" , SDTWritePort, [SDNPHasChain]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.31 -> 1.32 --- Log message: Added X86 readport patterns. --- Diffs of the changes: (+5 -0) TargetSelectionDAG.td |5 + 1 files changed, 5 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.31 llvm/lib/Target/TargetSelectionDAG.td:1.32 --- llvm/lib/Target/TargetSelectionDAG.td:1.31 Mon Dec 19 17:12:38 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Tue Dec 20 01:38:38 2005 @@ -133,6 +133,10 @@ def SDTRet : SDTypeProfile<0, 0, []>; // ret +def SDTReadPort : SDTypeProfile<1, 1, [ // readport + SDTCisInt<0>, SDTCisInt<1> +]>; + def SDTWritePort : SDTypeProfile<0, 2, [ // writeport SDTCisInt<0>, SDTCisInt<1> ]>; @@ -254,6 +258,7 @@ def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; def ret: SDNode<"ISD::RET", SDTRet,[SDNPHasChain]>; +def readport : SDNode<"ISD::READPORT" , SDTReadPort, [SDNPHasChain]>; def writeport : SDNode<"ISD::WRITEPORT" , SDTWritePort, [SDNPHasChain]>; def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.32 -> 1.33 --- Log message: add some nodes, forgot to commit this last night :( --- Diffs of the changes: (+2 -0) TargetSelectionDAG.td |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.32 llvm/lib/Target/TargetSelectionDAG.td:1.33 --- llvm/lib/Target/TargetSelectionDAG.td:1.32 Tue Dec 20 01:38:38 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Wed Dec 21 10:22:46 2005 @@ -242,6 +242,8 @@ def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; +def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; +def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; def fextend: SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.33 -> 1.34 --- Log message: Added special flag node FLAG. --- Diffs of the changes: (+1 -0) TargetSelectionDAG.td |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.33 llvm/lib/Target/TargetSelectionDAG.td:1.34 --- llvm/lib/Target/TargetSelectionDAG.td:1.33 Wed Dec 21 10:22:46 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Wed Dec 21 20:25:14 2005 @@ -184,6 +184,7 @@ def set; def node; def srcvalue; +def FLAG; def imm: SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.34 -> 1.35 --- Log message: Operand 1 of TRUNCSTORE can be any of integer and floating point types. --- Diffs of the changes: (+1 -1) TargetSelectionDAG.td |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.34 llvm/lib/Target/TargetSelectionDAG.td:1.35 --- llvm/lib/Target/TargetSelectionDAG.td:1.34 Wed Dec 21 20:25:14 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Fri Dec 23 01:30:30 2005 @@ -156,7 +156,7 @@ SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> ]>; def SDTTruncStore : SDTypeProfile<0, 4, [ // truncstore - SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> + SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> ]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.36 -> 1.37 --- Log message: support targetexternalsym --- Diffs of the changes: (+16 -13) TargetSelectionDAG.td | 29 - 1 files changed, 16 insertions(+), 13 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.36 llvm/lib/Target/TargetSelectionDAG.td:1.37 --- llvm/lib/Target/TargetSelectionDAG.td:1.36 Fri Dec 23 16:14:32 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Sat Dec 24 17:36:59 2005 @@ -190,20 +190,23 @@ def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; -def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], +def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], "GlobalAddressSDNode">; -def tglobaladdr: SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], -"GlobalAddressSDNode">; -def constpool : SDNode<"ISD::ConstantPool",SDTPtrLeaf, [], -"ConstantPoolSDNode">; -def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], -"ConstantPoolSDNode">; -def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], -"FrameIndexSDNode">; -def tframeindex: SDNode<"ISD::TargetFrameIndex",SDTPtrLeaf, [], -"FrameIndexSDNode">; -def externalsym: SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], -"ExternalSymbolSDNode">; +def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], + "GlobalAddressSDNode">; +def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], + "ConstantPoolSDNode">; +def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], + "ConstantPoolSDNode">; +def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], + "FrameIndexSDNode">; +def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], + "FrameIndexSDNode">; +def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], + "ExternalSymbolSDNode">; +def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], + "ExternalSymbolSDNode">; + def add: SDNode<"ISD::ADD" , SDTIntBinOp , [SDNPCommutative, SDNPAssociative]>; def sub: SDNode<"ISD::SUB" , SDTIntBinOp>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.37 -> 1.38 --- Log message: Add support for brcond --- Diffs of the changes: (+5 -0) TargetSelectionDAG.td |5 + 1 files changed, 5 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.37 llvm/lib/Target/TargetSelectionDAG.td:1.38 --- llvm/lib/Target/TargetSelectionDAG.td:1.37 Sat Dec 24 17:36:59 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Sun Jan 1 16:16:43 2006 @@ -131,6 +131,10 @@ SDTCisVT<0, OtherVT> ]>; +def SDTBrcond : SDTypeProfile<0, 2, [ // brcond + SDTCisInt<0>, SDTCisVT<1, OtherVT> +]>; + def SDTRet : SDTypeProfile<0, 0, []>; // ret def SDTReadPort : SDTypeProfile<1, 1, [ // readport @@ -260,6 +264,7 @@ def select : SDNode<"ISD::SELECT" , SDTSelect>; def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; +def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; def ret: SDNode<"ISD::RET", SDTRet,[SDNPHasChain]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.38 -> 1.39 --- Log message: Add unique id to debug location for debug label use (work in progress.) --- Diffs of the changes: (+2 -2) TargetSelectionDAG.td |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.38 llvm/lib/Target/TargetSelectionDAG.td:1.39 --- llvm/lib/Target/TargetSelectionDAG.td:1.38 Sun Jan 1 16:16:43 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Wed Jan 4 09:04:11 2006 @@ -440,8 +440,8 @@ //===--===// // Dwarf support. // -def SDT_dwarf_loc : SDTypeProfile<0, 3, -[SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>; +def SDT_dwarf_loc : SDTypeProfile<0, 4, + [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>, SDTCisInt<3>]>; def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.39 -> 1.40 --- Log message: Added initial support for DEBUG_LABEL allowing debug specific labels to be inserted in the code. --- Diffs of the changes: (+6 -3) TargetSelectionDAG.td |9 ++--- 1 files changed, 6 insertions(+), 3 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.39 llvm/lib/Target/TargetSelectionDAG.td:1.40 --- llvm/lib/Target/TargetSelectionDAG.td:1.39 Wed Jan 4 09:04:11 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Wed Jan 4 19:25:28 2006 @@ -440,9 +440,12 @@ //===--===// // Dwarf support. // -def SDT_dwarf_loc : SDTypeProfile<0, 4, - [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>, SDTCisInt<3>]>; -def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>; +def SDT_dwarf_loc : SDTypeProfile<0, 3, + [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>; +def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>; + +def SDT_dwarf_label : SDTypeProfile<0, 1, [SDTCisInt<0>]>; +def dwarf_label : SDNode<"ISD::DEBUG_LABEL", SDT_dwarf_label,[SDNPHasChain]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.40 -> 1.41 --- Log message: Added fpimm node for ConstantFP. --- Diffs of the changes: (+2 -0) TargetSelectionDAG.td |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.40 llvm/lib/Target/TargetSelectionDAG.td:1.41 --- llvm/lib/Target/TargetSelectionDAG.td:1.40 Wed Jan 4 19:25:28 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Wed Jan 4 20:07:49 2006 @@ -70,6 +70,7 @@ // Builtin profiles. def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. +def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. @@ -190,6 +191,7 @@ def srcvalue; def imm: SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; +def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.42 -> 1.43 --- Log message: Add bswap, rotl, and rotr nodes Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl Targets should add rotl/rotr patterns if they have them --- Diffs of the changes: (+2 -0) TargetSelectionDAG.td |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.42 llvm/lib/Target/TargetSelectionDAG.td:1.43 --- llvm/lib/Target/TargetSelectionDAG.td:1.42 Mon Jan 9 12:28:21 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Wed Jan 11 15:21:00 2006 @@ -230,6 +230,8 @@ def srl: SDNode<"ISD::SRL" , SDTIntShiftOp>; def sra: SDNode<"ISD::SRA" , SDTIntShiftOp>; def shl: SDNode<"ISD::SHL" , SDTIntShiftOp>; +def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; +def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; def and: SDNode<"ISD::AND" , SDTIntBinOp, [SDNPCommutative, SDNPAssociative]>; def or : SDNode<"ISD::OR", SDTIntBinOp, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.43 -> 1.44 --- Log message: bswap implementation --- Diffs of the changes: (+1 -0) TargetSelectionDAG.td |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.43 llvm/lib/Target/TargetSelectionDAG.td:1.44 --- llvm/lib/Target/TargetSelectionDAG.td:1.43 Wed Jan 11 15:21:00 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Fri Jan 13 21:14:10 2006 @@ -240,6 +240,7 @@ [SDNPCommutative, SDNPAssociative]>; def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; +def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.44 -> 1.45 --- Log message: Targets all now request ConstantFP to be legalized into TargetConstantFP. 'fpimm' in .td files is now TargetConstantFP. --- Diffs of the changes: (+2 -1) TargetSelectionDAG.td |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.44 llvm/lib/Target/TargetSelectionDAG.td:1.45 --- llvm/lib/Target/TargetSelectionDAG.td:1.44 Fri Jan 13 21:14:10 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Sun Jan 29 00:26:07 2006 @@ -194,7 +194,8 @@ def srcvalue; def imm: SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; -def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; +def fpimm : SDNode<"ISD::TargetConstantFP", + SDTFPLeaf, [], "ConstantFPSDNode">; def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.45 -> 1.46
---
Log message:
Add a missing and useful pat frag
---
Diffs of the changes: (+9 -2)
TargetSelectionDAG.td | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.45
llvm/lib/Target/TargetSelectionDAG.td:1.46
--- llvm/lib/Target/TargetSelectionDAG.td:1.45 Sun Jan 29 00:26:07 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Thu Feb 16 18:51:06 2006
@@ -164,7 +164,6 @@
SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
]>;
-
//===--===//
// Selection DAG Node Properties.
//
@@ -239,6 +238,14 @@
[SDNPCommutative, SDNPAssociative]>;
def xor: SDNode<"ISD::XOR" , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
+def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
+[SDNPCommutative, SDNPOutFlag]>;
+def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
+[SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
+def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
+[SDNPOutFlag]>;
+def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
+[SDNPOutFlag, SDNPInFlag]>;
def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
@@ -347,7 +354,7 @@
// Leaf fragments.
def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
-
+def immZero: PatLeaf<(imm), [{ return N->isNullValue(); }]>;
def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT());
}]>;
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.46 -> 1.47 --- Log message: Whoops, didn't mean to check this in yet. --- Diffs of the changes: (+0 -8) TargetSelectionDAG.td |8 1 files changed, 8 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.46 llvm/lib/Target/TargetSelectionDAG.td:1.47 --- llvm/lib/Target/TargetSelectionDAG.td:1.46 Thu Feb 16 18:51:06 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Thu Feb 16 18:56:19 2006 @@ -238,14 +238,6 @@ [SDNPCommutative, SDNPAssociative]>; def xor: SDNode<"ISD::XOR" , SDTIntBinOp, [SDNPCommutative, SDNPAssociative]>; -def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, -[SDNPCommutative, SDNPOutFlag]>; -def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, -[SDNPCommutative, SDNPOutFlag, SDNPInFlag]>; -def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, -[SDNPOutFlag]>; -def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, -[SDNPOutFlag, SDNPInFlag]>; def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.47 -> 1.48
---
Log message:
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
---
Diffs of the changes: (+8 -1)
TargetSelectionDAG.td |9 -
1 files changed, 8 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.47
llvm/lib/Target/TargetSelectionDAG.td:1.48
--- llvm/lib/Target/TargetSelectionDAG.td:1.47 Thu Feb 16 18:56:19 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Thu Feb 16 23:43:56 2006
@@ -238,6 +238,14 @@
[SDNPCommutative, SDNPAssociative]>;
def xor: SDNode<"ISD::XOR" , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
+def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
+[SDNPCommutative, SDNPOutFlag]>;
+def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
+[SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
+def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
+[SDNPOutFlag]>;
+def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
+[SDNPOutFlag, SDNPInFlag]>;
def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
@@ -346,7 +354,6 @@
// Leaf fragments.
def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
-def immZero: PatLeaf<(imm), [{ return N->isNullValue(); }]>;
def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT());
}]>;
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.48 -> 1.49 --- Log message: remove the read/write port/io intrinsics. --- Diffs of the changes: (+0 -11) TargetSelectionDAG.td | 11 --- 1 files changed, 11 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.48 llvm/lib/Target/TargetSelectionDAG.td:1.49 --- llvm/lib/Target/TargetSelectionDAG.td:1.48 Thu Feb 16 23:43:56 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Thu Mar 2 18:19:44 2006 @@ -138,14 +138,6 @@ def SDTRet : SDTypeProfile<0, 0, []>; // ret -def SDTReadPort : SDTypeProfile<1, 1, [ // readport - SDTCisInt<0>, SDTCisInt<1> -]>; - -def SDTWritePort : SDTypeProfile<0, 2, [ // writeport - SDTCisInt<0>, SDTCisInt<1> -]>; - def SDTLoad : SDTypeProfile<1, 1, [ // load SDTCisPtrTy<1> ]>; @@ -284,9 +276,6 @@ def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; def ret: SDNode<"ISD::RET", SDTRet,[SDNPHasChain]>; -def readport : SDNode<"ISD::READPORT" , SDTReadPort, [SDNPHasChain]>; -def writeport : SDNode<"ISD::WRITEPORT" , SDTWritePort, [SDNPHasChain]>; - def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>; def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.49 -> 1.50 --- Log message: fcopysign support --- Diffs of the changes: (+1 -0) TargetSelectionDAG.td |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.49 llvm/lib/Target/TargetSelectionDAG.td:1.50 --- llvm/lib/Target/TargetSelectionDAG.td:1.49 Thu Mar 2 18:19:44 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Thu Mar 9 08:57:36 2006 @@ -262,6 +262,7 @@ def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; def fextend: SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; +def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPBinOp>; def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.50 -> 1.51 --- Log message: relax fcopysign --- Diffs of the changes: (+4 -1) TargetSelectionDAG.td |5 - 1 files changed, 4 insertions(+), 1 deletion(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.50 llvm/lib/Target/TargetSelectionDAG.td:1.51 --- llvm/lib/Target/TargetSelectionDAG.td:1.50 Thu Mar 9 08:57:36 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Thu Mar 9 11:47:22 2006 @@ -83,6 +83,9 @@ def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> ]>; +def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. + SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> +]>; def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> ]>; @@ -262,7 +265,7 @@ def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; def fextend: SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; -def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPBinOp>; +def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.51 -> 1.52 --- Log message: add support for the bitconvert node --- Diffs of the changes: (+3 -0) TargetSelectionDAG.td |3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.51 llvm/lib/Target/TargetSelectionDAG.td:1.52 --- llvm/lib/Target/TargetSelectionDAG.td:1.51 Thu Mar 9 11:47:22 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Wed Mar 15 19:29:53 2006 @@ -74,6 +74,8 @@ def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. +def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert + def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> ]>; @@ -251,6 +253,7 @@ def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; +def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>; def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.52 -> 1.53
---
Log message:
add vector_shuffle
---
Diffs of the changes: (+16 -0)
TargetSelectionDAG.td | 16
1 files changed, 16 insertions(+)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.52
llvm/lib/Target/TargetSelectionDAG.td:1.53
--- llvm/lib/Target/TargetSelectionDAG.td:1.52 Wed Mar 15 19:29:53 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Sun Mar 19 23:40:45 2006
@@ -51,6 +51,15 @@
int BigOperandNum = BigOp;
}
+/// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
+/// packed vector types, and that ThisOp is the result of
+/// MVT::getIntVectorWithNumElements with the number of elements that ThisOp
+/// has.
+class SDTCisIntVectorOfSameSize
+ : SDTypeConstraint {
+ int OtherOpNum = OtherOp;
+}
+
//===--===//
// Selection DAG Type Profile definitions.
//
@@ -161,6 +170,10 @@
SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
]>;
+def SDTVecShuffle : SDTypeProfile<1, 3, [
+ SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
+]>;
+
//===--===//
// Selection DAG Node Properties.
//
@@ -293,6 +306,9 @@
def extld : SDNode<"ISD::EXTLOAD", SDTExtLoad,[SDNPHasChain]>;
def truncst: SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>;
+def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
+
+
//===--===//
// Selection DAG Condition Codes
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.53 -> 1.54 --- Log message: Add a build_vector node --- Diffs of the changes: (+1 -1) TargetSelectionDAG.td |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.53 llvm/lib/Target/TargetSelectionDAG.td:1.54 --- llvm/lib/Target/TargetSelectionDAG.td:1.53 Sun Mar 19 23:40:45 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Mon Mar 20 00:18:01 2006 @@ -307,7 +307,7 @@ def truncst: SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>; def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; - +def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>; //===--===// // Selection DAG Condition Codes ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.54 -> 1.55 --- Log message: x86 ISD::SCALAR_TO_VECTOR support. --- Diffs of the changes: (+2 -0) TargetSelectionDAG.td |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.54 llvm/lib/Target/TargetSelectionDAG.td:1.55 --- llvm/lib/Target/TargetSelectionDAG.td:1.54 Mon Mar 20 00:18:01 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Mon Mar 20 18:33:35 2006 @@ -308,6 +308,8 @@ def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>; +def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, + []>; //===--===// // Selection DAG Condition Codes ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.55 -> 1.56 --- Log message: expose intrinsic info to the targets. --- Diffs of the changes: (+3 -0) TargetSelectionDAG.td |3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.55 llvm/lib/Target/TargetSelectionDAG.td:1.56 --- llvm/lib/Target/TargetSelectionDAG.td:1.55 Mon Mar 20 18:33:35 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Fri Mar 24 12:44:11 2006 @@ -12,6 +12,9 @@ // //===--===// +// Include all information about LLVM intrinsics. +include "llvm/Intrinsics.td" + //===--===// // Selection DAG Type Constraint definitions. // ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.57 -> 1.58 --- Log message: Add new intrinsic node definitions for tblgen use --- Diffs of the changes: (+12 -0) TargetSelectionDAG.td | 12 1 files changed, 12 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.57 llvm/lib/Target/TargetSelectionDAG.td:1.58 --- llvm/lib/Target/TargetSelectionDAG.td:1.57 Fri Mar 24 12:52:35 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Fri Mar 24 20:29:35 2006 @@ -311,6 +311,18 @@ def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, []>; +// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use +// these internally. Don't reference these directly. +def intrinsic_void : SDNode<"ISD::INTRINSIC", +SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, +[SDNPHasChain]>; +def intrinsic_w_chain : SDNode<"ISD::INTRINSIC", + SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, + [SDNPHasChain]>; +def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC", +SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; + + //===--===// // Selection DAG Condition Codes ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.58 -> 1.59
---
Log message:
add a vnot helper node for matching 'not' on vectors
---
Diffs of the changes: (+6 -2)
TargetSelectionDAG.td |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.58
llvm/lib/Target/TargetSelectionDAG.td:1.59
--- llvm/lib/Target/TargetSelectionDAG.td:1.58 Fri Mar 24 20:29:35 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Sat Mar 25 17:00:08 2006
@@ -379,13 +379,17 @@
// Leaf fragments.
-def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT());
}]>;
-// Other helper fragments.
+def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
+def immAllOnesV: PatLeaf<(build_vector), [{
+ return ISD::isBuildVectorAllOnesInteger(N);
+}]>;
+// Other helper fragments.
def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
+def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
// extending load & truncstore fragments.
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.59 -> 1.60
---
Log message:
Add immAllZerosV helper
---
Diffs of the changes: (+3 -0)
TargetSelectionDAG.td |3 +++
1 files changed, 3 insertions(+)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.59
llvm/lib/Target/TargetSelectionDAG.td:1.60
--- llvm/lib/Target/TargetSelectionDAG.td:1.59 Sat Mar 25 17:00:08 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Sun Mar 26 03:51:39 2006
@@ -386,6 +386,9 @@
def immAllOnesV: PatLeaf<(build_vector), [{
return ISD::isBuildVectorAllOnesInteger(N);
}]>;
+def immAllZerosV: PatLeaf<(build_vector), [{
+ return ISD::isBuildVectorAllZeros(N);
+}]>;
// Other helper fragments.
def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.60 -> 1.61
---
Log message:
Changed isBuildVectorAllOnesInteger to isBuildVectorAllOnes.
---
Diffs of the changes: (+1 -1)
TargetSelectionDAG.td |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.60
llvm/lib/Target/TargetSelectionDAG.td:1.61
--- llvm/lib/Target/TargetSelectionDAG.td:1.60 Sun Mar 26 03:51:39 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Mon Mar 27 00:59:32 2006
@@ -384,7 +384,7 @@
def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
def immAllOnesV: PatLeaf<(build_vector), [{
- return ISD::isBuildVectorAllOnesInteger(N);
+ return ISD::isBuildVectorAllOnes(N);
}]>;
def immAllZerosV: PatLeaf<(build_vector), [{
return ISD::isBuildVectorAllZeros(N);
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.61 -> 1.62 --- Log message: Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums. --- Diffs of the changes: (+3 -3) TargetSelectionDAG.td |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.61 llvm/lib/Target/TargetSelectionDAG.td:1.62 --- llvm/lib/Target/TargetSelectionDAG.td:1.61 Mon Mar 27 00:59:32 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Mon Mar 27 18:40:33 2006 @@ -313,13 +313,13 @@ // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use // these internally. Don't reference these directly. -def intrinsic_void : SDNode<"ISD::INTRINSIC", +def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, [SDNPHasChain]>; -def intrinsic_w_chain : SDNode<"ISD::INTRINSIC", +def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, [SDNPHasChain]>; -def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC", +def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.62 -> 1.63 --- Log message: Add vector_extract and vector_insert nodes. --- Diffs of the changes: (+4 -0) TargetSelectionDAG.td |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.62 llvm/lib/Target/TargetSelectionDAG.td:1.63 --- llvm/lib/Target/TargetSelectionDAG.td:1.62 Mon Mar 27 18:40:33 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Fri Mar 31 13:21:16 2006 @@ -310,6 +310,10 @@ def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>; def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, []>; +def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", +SDTypeProfile<1, 2, []>, []>; +def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", +SDTypeProfile<1, 3, []>, []>; // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use // these internally. Don't reference these directly. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.63 -> 1.64
---
Log message:
Add a new vnot_conv predicate for matching vnot's where the allones vector is
bitconverted from some other type.
---
Diffs of the changes: (+6 -0)
TargetSelectionDAG.td |6 ++
1 files changed, 6 insertions(+)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.63
llvm/lib/Target/TargetSelectionDAG.td:1.64
--- llvm/lib/Target/TargetSelectionDAG.td:1.63 Fri Mar 31 13:21:16 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Sat Apr 15 18:39:14 2006
@@ -394,9 +394,15 @@
return ISD::isBuildVectorAllZeros(N);
}]>;
+def immAllOnesV_bc: PatLeaf<(bitconvert), [{
+ return ISD::isBuildVectorAllOnes(N);
+}]>;
+
+
// Other helper fragments.
def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
+def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
// extending load & truncstore fragments.
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.73 -> 1.74
---
Log message:
Change load PatFrag to ignore indexed load.
---
Diffs of the changes: (+62 -31)
TargetSelectionDAG.td | 93 +-
1 files changed, 62 insertions(+), 31 deletions(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.73
llvm/lib/Target/TargetSelectionDAG.td:1.74
--- llvm/lib/Target/TargetSelectionDAG.td:1.73 Fri Oct 13 16:14:26 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Thu Oct 26 16:55:50 2006
@@ -399,79 +399,110 @@
def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
+// load fragments.
def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
- return ISD::isNON_EXTLoad(N);
+ if (LoadSDNode *LD = dyn_cast(N))
+return LD->getExtensionType() == ISD::NON_EXTLOAD &&
+ LD->getAddressingMode() == ISD::UNINDEXED;
+ return false;
}]>;
// extending load fragments.
def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
- if (ISD::isEXTLoad(N))
-return cast(N)->getLoadedVT() == MVT::i1;
+ if (LoadSDNode *LD = dyn_cast(N))
+return LD->getExtensionType() == ISD::EXTLOAD &&
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i1;
return false;
}]>;
def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
- if (ISD::isEXTLoad(N))
-return cast(N)->getLoadedVT() == MVT::i8;
+ if (LoadSDNode *LD = dyn_cast(N))
+return LD->getExtensionType() == ISD::EXTLOAD &&
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i8;
return false;
}]>;
def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
- if (ISD::isEXTLoad(N))
-return cast(N)->getLoadedVT() == MVT::i16;
+ if (LoadSDNode *LD = dyn_cast(N))
+return LD->getExtensionType() == ISD::EXTLOAD &&
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i16;
return false;
}]>;
def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
- if (ISD::isEXTLoad(N))
-return cast(N)->getLoadedVT() == MVT::i32;
+ if (LoadSDNode *LD = dyn_cast(N))
+return LD->getExtensionType() == ISD::EXTLOAD &&
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i32;
return false;
}]>;
def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
- if (ISD::isEXTLoad(N))
-return cast(N)->getLoadedVT() == MVT::f32;
+ if (LoadSDNode *LD = dyn_cast(N))
+return LD->getExtensionType() == ISD::EXTLOAD &&
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::f32;
return false;
}]>;
-def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
- if (ISD::isSEXTLoad(N))
-return cast(N)->getLoadedVT() == MVT::i1;
+def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (LoadSDNode *LD = dyn_cast(N))
+return LD->getExtensionType() == ISD::SEXTLOAD &&
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i1;
return false;
}]>;
-def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
- if (ISD::isSEXTLoad(N))
-return cast(N)->getLoadedVT() == MVT::i8;
+def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (LoadSDNode *LD = dyn_cast(N))
+return LD->getExtensionType() == ISD::SEXTLOAD &&
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i8;
return false;
}]>;
def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
- if (ISD::isSEXTLoad(N))
-return cast(N)->getLoadedVT() == MVT::i16;
+ if (LoadSDNode *LD = dyn_cast(N))
+return LD->getExtensionType() == ISD::SEXTLOAD &&
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i16;
return false;
}]>;
def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
- if (ISD::isSEXTLoad(N))
-return cast(N)->getLoadedVT() == MVT::i32;
+ if (LoadSDNode *LD = dyn_cast(N))
+return LD->getExtensionType() == ISD::SEXTLOAD &&
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i32;
return false;
}]>;
-def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
- if (ISD::isZEXTLoad(N))
-return cast(N)->getLoadedVT() == MVT::i1;
+def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (LoadSDNode *LD = dyn_cast(N))
+return LD->getExtensionType() == ISD::ZEXTLOAD &&
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i1;
return false;
}]>;
-def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
- if (ISD::isZEXTLoad(N))
-return cast(N)->getLoadedVT() == MVT::i8;
+def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (LoadSDNode *LD = dyn_cast(N))
+return LD->getExtensionType() == ISD::ZEXTLOAD &&
+ LD->getAddressingMode() == ISD::UNI
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.74 -> 1.75
---
Log message:
Added indexed store node and patfrag's.
---
Diffs of the changes: (+131 -11)
TargetSelectionDAG.td | 142 ++
1 files changed, 131 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.74
llvm/lib/Target/TargetSelectionDAG.td:1.75
--- llvm/lib/Target/TargetSelectionDAG.td:1.74 Thu Oct 26 16:55:50 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Wed Nov 8 17:02:11 2006
@@ -164,6 +164,10 @@
SDTCisPtrTy<1>
]>;
+def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
+ SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
+]>;
+
def SDTVecShuffle : SDTypeProfile<1, 3, [
SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
]>;
@@ -299,6 +303,7 @@
// and truncst (see below).
def ld : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
def st : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
+def ist: SDNode<"ISD::STORE" , SDTIStore, [SDNPHasChain]>;
def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
@@ -505,38 +510,153 @@
// store fragments.
def store : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
- return ISD::isNON_TRUNCStore(N);
+ if (StoreSDNode *ST = dyn_cast(N))
+return !ST->isTruncatingStore();
+ return false;
}]>;
// truncstore fragments.
def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
- if (ISD::isTRUNCStore(N))
-return cast(N)->getStoredVT() == MVT::i1;
+ if (StoreSDNode *ST = dyn_cast(N))
+return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1;
return false;
}]>;
def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
- if (ISD::isTRUNCStore(N))
-return cast(N)->getStoredVT() == MVT::i8;
+ if (StoreSDNode *ST = dyn_cast(N))
+return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8;
return false;
}]>;
def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
- if (ISD::isTRUNCStore(N))
-return cast(N)->getStoredVT() == MVT::i16;
+ if (StoreSDNode *ST = dyn_cast(N))
+return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16;
return false;
}]>;
def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
- if (ISD::isTRUNCStore(N))
-return cast(N)->getStoredVT() == MVT::i32;
+ if (StoreSDNode *ST = dyn_cast(N))
+return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32;
return false;
}]>;
def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
- if (ISD::isTRUNCStore(N))
-return cast(N)->getStoredVT() == MVT::f32;
+ if (StoreSDNode *ST = dyn_cast(N))
+return ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32;
+ return false;
+}]>;
+
+// indexed store fragments.
+def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
+(ist node:$val, node:$base, node:$offset), [{
+ if (StoreSDNode *ST = dyn_cast(N)) {
+ISD::MemOpAddrMode AM = ST->getAddressingMode();
+return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
+ !ST->isTruncatingStore();
+ }
+ return false;
+}]>;
+
+def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
+(ist node:$val, node:$base, node:$offset), [{
+ if (StoreSDNode *ST = dyn_cast(N)) {
+ISD::MemOpAddrMode AM = ST->getAddressingMode();
+return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
+ ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1;
+ }
+ return false;
+}]>;
+def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
+(ist node:$val, node:$base, node:$offset), [{
+ if (StoreSDNode *ST = dyn_cast(N)) {
+ISD::MemOpAddrMode AM = ST->getAddressingMode();
+return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
+ ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8;
+ }
+ return false;
+}]>;
+def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
+ (ist node:$val, node:$base, node:$offset), [{
+ if (StoreSDNode *ST = dyn_cast(N)) {
+ISD::MemOpAddrMode AM = ST->getAddressingMode();
+return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
+ ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16;
+ }
+ return false;
+}]>;
+def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
+ (ist node:$val, node:$base, node:$offset), [{
+ if (StoreSDNode *ST = dyn_cast(N)) {
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.75 -> 1.76
---
Log message:
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
---
Diffs of the changes: (+12 -12)
TargetSelectionDAG.td | 24
1 files changed, 12 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.75
llvm/lib/Target/TargetSelectionDAG.td:1.76
--- llvm/lib/Target/TargetSelectionDAG.td:1.75 Wed Nov 8 17:02:11 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Thu Nov 9 12:44:21 2006
@@ -551,7 +551,7 @@
def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
(ist node:$val, node:$base, node:$offset), [{
if (StoreSDNode *ST = dyn_cast(N)) {
-ISD::MemOpAddrMode AM = ST->getAddressingMode();
+ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
!ST->isTruncatingStore();
}
@@ -561,7 +561,7 @@
def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
(ist node:$val, node:$base, node:$offset), [{
if (StoreSDNode *ST = dyn_cast(N)) {
-ISD::MemOpAddrMode AM = ST->getAddressingMode();
+ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1;
}
@@ -570,7 +570,7 @@
def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
(ist node:$val, node:$base, node:$offset), [{
if (StoreSDNode *ST = dyn_cast(N)) {
-ISD::MemOpAddrMode AM = ST->getAddressingMode();
+ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8;
}
@@ -579,7 +579,7 @@
def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
(ist node:$val, node:$base, node:$offset), [{
if (StoreSDNode *ST = dyn_cast(N)) {
-ISD::MemOpAddrMode AM = ST->getAddressingMode();
+ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16;
}
@@ -588,7 +588,7 @@
def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(ist node:$val, node:$base, node:$offset), [{
if (StoreSDNode *ST = dyn_cast(N)) {
-ISD::MemOpAddrMode AM = ST->getAddressingMode();
+ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32;
}
@@ -597,7 +597,7 @@
def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(ist node:$val, node:$base, node:$offset), [{
if (StoreSDNode *ST = dyn_cast(N)) {
-ISD::MemOpAddrMode AM = ST->getAddressingMode();
+ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32;
}
@@ -607,7 +607,7 @@
def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
(ist node:$val, node:$ptr, node:$offset), [{
if (StoreSDNode *ST = dyn_cast(N)) {
-ISD::MemOpAddrMode AM = ST->getAddressingMode();
+ISD::MemIndexedMode AM = ST->getAddressingMode();
return !ST->isTruncatingStore() &&
(AM == ISD::POST_INC || AM == ISD::POST_DEC);
}
@@ -617,7 +617,7 @@
def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
(ist node:$val, node:$base, node:$offset), [{
if (StoreSDNode *ST = dyn_cast(N)) {
-ISD::MemOpAddrMode AM = ST->getAddressingMode();
+ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1;
}
@@ -626,7 +626,7 @@
def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
(ist node:$val, node:$base, node:$offset), [{
if (StoreSDNode *ST = dyn_cast(N)) {
-ISD::MemOpAddrMode AM = ST->getAddressingMode();
+ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8;
}
@@ -635,7 +635,7 @@
def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
(ist node:$val, node:$base, node:$offset), [{
if (StoreSDNode *ST = dyn_cast(N)) {
-ISD::MemOpAddrMode AM = ST->getAddressingMode();
+ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
ST->isTruncatingStore() && ST->getStoredVT() ==
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.76 -> 1.77
---
Log message:
Fix predicates for unindexed stores so they don't accidentally match indexed
stores.
---
Diffs of the changes: (+39 -33)
TargetSelectionDAG.td | 72 +++---
1 files changed, 39 insertions(+), 33 deletions(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.76
llvm/lib/Target/TargetSelectionDAG.td:1.77
--- llvm/lib/Target/TargetSelectionDAG.td:1.76 Thu Nov 9 12:44:21 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Tue Nov 14 13:13:39 2006
@@ -408,7 +408,7 @@
def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::NON_EXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED;
+ LD->getAddressingMode() == ISD::UNINDEXED;
return false;
}]>;
@@ -416,94 +416,94 @@
def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::EXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i1;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i1;
return false;
}]>;
def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::EXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i8;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i8;
return false;
}]>;
def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::EXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i16;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i16;
return false;
}]>;
def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::EXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i32;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i32;
return false;
}]>;
def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::EXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::f32;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::f32;
return false;
}]>;
def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::SEXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i1;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i1;
return false;
}]>;
def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::SEXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i8;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i8;
return false;
}]>;
def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::SEXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i16;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i16;
return false;
}]>;
def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::SEXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i32;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i32;
return false;
}]>;
def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::ZEXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i1;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i1;
return false;
}]>;
def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast(N))
return LD->getExtensionType() == ISD::ZEXTLOAD &&
- LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i8;
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::i8;
return false;
}]
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.66 -> 1.67 --- Log message: JumpTable support! What this represents is working asm and jit support for x86 and ppc for 100% dense switch statements when relocations are non-PIC. This support will be extended and enhanced in the coming days to support PIC, and less dense forms of jump tables. --- Diffs of the changes: (+9 -0) TargetSelectionDAG.td |9 + 1 files changed, 9 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.66 llvm/lib/Target/TargetSelectionDAG.td:1.67 --- llvm/lib/Target/TargetSelectionDAG.td:1.66 Wed Apr 19 15:38:28 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Sat Apr 22 13:53:45 2006 @@ -150,6 +150,10 @@ SDTCisInt<0>, SDTCisVT<1, OtherVT> ]>; +def SDTBrind : SDTypeProfile<0, 1, [ // brind + SDTCisPtrTy<0> +]>; + def SDTRet : SDTypeProfile<0, 0, []>; // ret def SDTLoad : SDTypeProfile<1, 1, [ // load @@ -217,6 +221,10 @@ "ConstantPoolSDNode">; def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], "ConstantPoolSDNode">; +def jumptable : SDNode<"ISD::JumpTable",SDTPtrLeaf, [], + "JumpTableSDNode">; +def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], + "JumpTableSDNode">; def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], "FrameIndexSDNode">; def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], @@ -293,6 +301,7 @@ def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; +def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; def ret: SDNode<"ISD::RET", SDTRet,[SDNPHasChain]>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.67 -> 1.68 --- Log message: Vector extract / insert index operand should have ptr type. --- Diffs of the changes: (+2 -2) TargetSelectionDAG.td |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.67 llvm/lib/Target/TargetSelectionDAG.td:1.68 --- llvm/lib/Target/TargetSelectionDAG.td:1.67 Sat Apr 22 13:53:45 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Thu Jun 15 03:19:05 2006 @@ -320,9 +320,9 @@ def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, []>; def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", -SDTypeProfile<1, 2, []>, []>; +SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", -SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>]>, []>; +SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use // these internally. Don't reference these directly. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.68 -> 1.69 --- Log message: Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an extra operand to LOADX to specify the exact value extension type. --- Diffs of the changes: (+10 -12) TargetSelectionDAG.td | 22 ++ 1 files changed, 10 insertions(+), 12 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.68 llvm/lib/Target/TargetSelectionDAG.td:1.69 --- llvm/lib/Target/TargetSelectionDAG.td:1.68 Thu Jun 15 03:19:05 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Tue Oct 3 19:53:53 2006 @@ -164,10 +164,10 @@ SDTCisPtrTy<1> ]>; -def SDTExtLoad : SDTypeProfile<1, 3, [ // extload - SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> +def SDTLoadX : SDTypeProfile<1, 4, [ // loadX + SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisVT<4, i32> ]>; -def SDTIntExtLoad : SDTypeProfile<1, 3, [ // sextload, zextload +def SDTIntExtLoad : SDTypeProfile<1, 3, [ // extload, sextload, zextload SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> ]>; def SDTTruncStore : SDTypeProfile<0, 4, [ // truncstore @@ -308,11 +308,9 @@ def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>; def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>; -// Do not use sextld and zextld directly. Use sextload and zextload (see -// below) which pass in a dummy srcvalue node which tblgen will skip over. -def sextld : SDNode<"ISD::SEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>; -def zextld : SDNode<"ISD::ZEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>; -def extld : SDNode<"ISD::EXTLOAD", SDTExtLoad,[SDNPHasChain]>; +// Do not use loadx directly. Use extload, sextload and zextload (see below) +// which pass in a dummy srcvalue node which tblgen will skip over. +def loadx : SDNode<"ISD::LOADX" , SDTLoadX, [SDNPHasChain]>; def truncst: SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>; def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; @@ -415,12 +413,12 @@ def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; // extending load & truncstore fragments. +def extload : PatFrag<(ops node:$ptr, node:$vt), +(loadx node:$ptr, srcvalue:$dummy, node:$vt, 0)>; def sextload : PatFrag<(ops node:$ptr, node:$vt), -(sextld node:$ptr, srcvalue:$dummy, node:$vt)>; +(loadx node:$ptr, srcvalue:$dummy, node:$vt, 1)>; def zextload : PatFrag<(ops node:$ptr, node:$vt), -(zextld node:$ptr, srcvalue:$dummy, node:$vt)>; -def extload : PatFrag<(ops node:$ptr, node:$vt), -(extld node:$ptr, srcvalue:$dummy, node:$vt)>; +(loadx node:$ptr, srcvalue:$dummy, node:$vt, 2)>; def truncstore: PatFrag<(ops node:$val, node:$ptr, node:$vt), (truncst node:$val, node:$ptr, srcvalue:$dummy, node:$vt)>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.69 -> 1.70
---
Log message:
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
---
Diffs of the changes: (+74 -16)
TargetSelectionDAG.td | 90 +-
1 files changed, 74 insertions(+), 16 deletions(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.69
llvm/lib/Target/TargetSelectionDAG.td:1.70
--- llvm/lib/Target/TargetSelectionDAG.td:1.69 Tue Oct 3 19:53:53 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Mon Oct 9 15:57:24 2006
@@ -164,12 +164,6 @@
SDTCisPtrTy<1>
]>;
-def SDTLoadX : SDTypeProfile<1, 4, [ // loadX
- SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisVT<4, i32>
-]>;
-def SDTIntExtLoad : SDTypeProfile<1, 3, [ // extload, sextload, zextload
- SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
-]>;
def SDTTruncStore : SDTypeProfile<0, 4, [ // truncstore
SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
]>;
@@ -305,12 +299,10 @@
def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
def ret: SDNode<"ISD::RET", SDTRet,[SDNPHasChain]>;
-def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
+// Do not use ld directly. Use load, extload, sextload, zextload (see below).
+def ld : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
-// Do not use loadx directly. Use extload, sextload and zextload (see below)
-// which pass in a dummy srcvalue node which tblgen will skip over.
-def loadx : SDNode<"ISD::LOADX" , SDTLoadX, [SDNPHasChain]>;
def truncst: SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>;
def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
@@ -412,13 +404,79 @@
def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
+def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ return ISD::isNON_EXTLoad(N);
+}]>;
+
// extending load & truncstore fragments.
-def extload : PatFrag<(ops node:$ptr, node:$vt),
-(loadx node:$ptr, srcvalue:$dummy, node:$vt, 0)>;
-def sextload : PatFrag<(ops node:$ptr, node:$vt),
-(loadx node:$ptr, srcvalue:$dummy, node:$vt, 1)>;
-def zextload : PatFrag<(ops node:$ptr, node:$vt),
-(loadx node:$ptr, srcvalue:$dummy, node:$vt, 2)>;
+def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i1;
+ return false;
+}]>;
+def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i8;
+ return false;
+}]>;
+def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i16;
+ return false;
+}]>;
+def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i32;
+ return false;
+}]>;
+def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::f32;
+ return false;
+}]>;
+
+def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isSEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i1;
+ return false;
+}]>;
+def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isSEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i8;
+ return false;
+}]>;
+def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isSEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i16;
+ return false;
+}]>;
+def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isSEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i32;
+ return false;
+}]>;
+
+def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isZEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i1;
+ return false;
+}]>;
+def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isZEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i8;
+ return false;
+}]>;
+def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isZEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i16;
+ return false;
+}]>;
+def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (ISD::isZEXTLoad(N))
+return cast(N)->getLoadVT() == MVT::i32;
+ return false;
+}]>;
+
def truncstore: PatFrag<(ops node:$val, node:$ptr, node:$vt),
(truncst node:$val, node:$ptr, srcvalue:$dummy,
node:$vt)>;
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.70 -> 1.71
---
Log message:
Naming consistency.
---
Diffs of the changes: (+13 -13)
TargetSelectionDAG.td | 26 +-
1 files changed, 13 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.70
llvm/lib/Target/TargetSelectionDAG.td:1.71
--- llvm/lib/Target/TargetSelectionDAG.td:1.70 Mon Oct 9 15:57:24 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Wed Oct 11 02:10:22 2006
@@ -411,69 +411,69 @@
// extending load & truncstore fragments.
def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isEXTLoad(N))
-return cast(N)->getLoadVT() == MVT::i1;
+return cast(N)->getLoadedVT() == MVT::i1;
return false;
}]>;
def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isEXTLoad(N))
-return cast(N)->getLoadVT() == MVT::i8;
+return cast(N)->getLoadedVT() == MVT::i8;
return false;
}]>;
def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isEXTLoad(N))
-return cast(N)->getLoadVT() == MVT::i16;
+return cast(N)->getLoadedVT() == MVT::i16;
return false;
}]>;
def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isEXTLoad(N))
-return cast(N)->getLoadVT() == MVT::i32;
+return cast(N)->getLoadedVT() == MVT::i32;
return false;
}]>;
def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isEXTLoad(N))
-return cast(N)->getLoadVT() == MVT::f32;
+return cast(N)->getLoadedVT() == MVT::f32;
return false;
}]>;
def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isSEXTLoad(N))
-return cast(N)->getLoadVT() == MVT::i1;
+return cast(N)->getLoadedVT() == MVT::i1;
return false;
}]>;
def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isSEXTLoad(N))
-return cast(N)->getLoadVT() == MVT::i8;
+return cast(N)->getLoadedVT() == MVT::i8;
return false;
}]>;
def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isSEXTLoad(N))
-return cast(N)->getLoadVT() == MVT::i16;
+return cast(N)->getLoadedVT() == MVT::i16;
return false;
}]>;
def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isSEXTLoad(N))
-return cast(N)->getLoadVT() == MVT::i32;
+return cast(N)->getLoadedVT() == MVT::i32;
return false;
}]>;
def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isZEXTLoad(N))
-return cast(N)->getLoadVT() == MVT::i1;
+return cast(N)->getLoadedVT() == MVT::i1;
return false;
}]>;
def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isZEXTLoad(N))
-return cast(N)->getLoadVT() == MVT::i8;
+return cast(N)->getLoadedVT() == MVT::i8;
return false;
}]>;
def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isZEXTLoad(N))
-return cast(N)->getLoadVT() == MVT::i16;
+return cast(N)->getLoadedVT() == MVT::i16;
return false;
}]>;
def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isZEXTLoad(N))
-return cast(N)->getLoadVT() == MVT::i32;
+return cast(N)->getLoadedVT() == MVT::i32;
return false;
}]>;
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.71 -> 1.72
---
Log message:
Add properties to ComplexPattern.
---
Diffs of the changes: (+3 -1)
TargetSelectionDAG.td |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.71
llvm/lib/Target/TargetSelectionDAG.td:1.72
--- llvm/lib/Target/TargetSelectionDAG.td:1.71 Wed Oct 11 02:10:22 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Wed Oct 11 16:03:11 2006
@@ -554,11 +554,13 @@
// RootNodes are the list of possible root nodes of the sub-dags to match.
// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr",
[add]>;
//
-class ComplexPattern roots =
[]> {
+class ComplexPattern roots = [], list props = []>
{
ValueType Ty = ty;
int NumOperands = numops;
string SelectFunc = fn;
list RootNodes = roots;
+ list Properties = props;
}
//===--===//
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.72 -> 1.73
---
Log message:
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
---
Diffs of the changes: (+40 -12)
TargetSelectionDAG.td | 52 ++
1 files changed, 40 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.72
llvm/lib/Target/TargetSelectionDAG.td:1.73
--- llvm/lib/Target/TargetSelectionDAG.td:1.72 Wed Oct 11 16:03:11 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Fri Oct 13 16:14:26 2006
@@ -164,10 +164,6 @@
SDTCisPtrTy<1>
]>;
-def SDTTruncStore : SDTypeProfile<0, 4, [ // truncstore
- SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
-]>;
-
def SDTVecShuffle : SDTypeProfile<1, 3, [
SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
]>;
@@ -299,11 +295,10 @@
def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
def ret: SDNode<"ISD::RET", SDTRet,[SDNPHasChain]>;
-// Do not use ld directly. Use load, extload, sextload, zextload (see below).
+// Do not use ld, st directly. Use load, extload, sextload, zextload, store,
+// and truncst (see below).
def ld : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
-def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
-
-def truncst: SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>;
+def st : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
@@ -408,7 +403,7 @@
return ISD::isNON_EXTLoad(N);
}]>;
-// extending load & truncstore fragments.
+// extending load fragments.
def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isEXTLoad(N))
return cast(N)->getLoadedVT() == MVT::i1;
@@ -477,9 +472,42 @@
return false;
}]>;
-def truncstore: PatFrag<(ops node:$val, node:$ptr, node:$vt),
-(truncst node:$val, node:$ptr, srcvalue:$dummy,
-node:$vt)>;
+def store : PatFrag<(ops node:$val, node:$ptr),
+(st node:$val, node:$ptr), [{
+ return ISD::isNON_TRUNCStore(N);
+}]>;
+
+// truncstore fragments.
+def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
+ (st node:$val, node:$ptr), [{
+ if (ISD::isTRUNCStore(N))
+return cast(N)->getStoredVT() == MVT::i1;
+ return false;
+}]>;
+def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
+ (st node:$val, node:$ptr), [{
+ if (ISD::isTRUNCStore(N))
+return cast(N)->getStoredVT() == MVT::i8;
+ return false;
+}]>;
+def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
+(st node:$val, node:$ptr), [{
+ if (ISD::isTRUNCStore(N))
+return cast(N)->getStoredVT() == MVT::i16;
+ return false;
+}]>;
+def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
+(st node:$val, node:$ptr), [{
+ if (ISD::isTRUNCStore(N))
+return cast(N)->getStoredVT() == MVT::i32;
+ return false;
+}]>;
+def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
+(st node:$val, node:$ptr), [{
+ if (ISD::isTRUNCStore(N))
+return cast(N)->getStoredVT() == MVT::f32;
+ return false;
+}]>;
// setcc convenience fragments.
def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
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