Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td X86RegisterInfo.cpp
Implemented correct stack probing on mingw/cygwin for dynamic
alloca's.
Also, fixed static case in presence of eax livin. This fixes PR331:
http://llvm.org/PR331
Cool :)
+SDOperand X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
+ SelectionDAG
DAG) {
Please add a comment above this that explains why this lowering is
needed. Also, please assert that the subtarget isCygMing() on entry,
to make it obvious to the reader that this is cygwin-specific
lowering code.
Thanks Anton!
-Chris
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.85 - 1.86
X86ISelLowering.h updated: 1.26 - 1.27
X86InstrInfo.td updated: 1.236 - 1.237
---
Log message:
kill ADD_PARTS SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
---
Diffs of the changes: (+28 -77)
X86ISelLowering.cpp | 30
X86ISelLowering.h | 10
X86InstrInfo.td | 65 ++--
3 files changed, 28 insertions(+), 77 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.85
llvm/lib/Target/X86/X86ISelLowering.cpp:1.86
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.85Thu Feb 16 18:03:04 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Feb 16 23:43:56 2006
@@ -160,8 +160,6 @@
// Darwin ABI issue.
setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
// 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
- setOperationAction(ISD::ADD_PARTS , MVT::i32 , Custom);
- setOperationAction(ISD::SUB_PARTS , MVT::i32 , Custom);
setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
@@ -1270,30 +1268,6 @@
SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG DAG) {
switch (Op.getOpcode()) {
default: assert(0 Should not custom lower this!);
- case ISD::ADD_PARTS:
- case ISD::SUB_PARTS: {
-assert(Op.getNumOperands() == 4 Op.getValueType() == MVT::i32
- Not an i64 add/sub!);
-bool isAdd = Op.getOpcode() == ISD::ADD_PARTS;
-std::vectorMVT::ValueType Tys;
-Tys.push_back(MVT::i32);
-Tys.push_back(MVT::Flag);
-std::vectorSDOperand Ops;
-Ops.push_back(Op.getOperand(0));
-Ops.push_back(Op.getOperand(2));
-SDOperand Lo = DAG.getNode(isAdd ? X86ISD::ADD_FLAG : X86ISD::SUB_FLAG,
- Tys, Ops);
-SDOperand Hi = DAG.getNode(isAdd ? X86ISD::ADC : X86ISD::SBB, MVT::i32,
- Op.getOperand(1), Op.getOperand(3),
- Lo.getValue(1));
-Tys.clear();
-Tys.push_back(MVT::i32);
-Tys.push_back(MVT::i32);
-Ops.clear();
-Ops.push_back(Lo);
-Ops.push_back(Hi);
-return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
- }
case ISD::SHL_PARTS:
case ISD::SRA_PARTS:
case ISD::SRL_PARTS: {
@@ -1910,10 +1884,6 @@
const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {
default: return NULL;
- case X86ISD::ADD_FLAG: return X86ISD::ADD_FLAG;
- case X86ISD::SUB_FLAG: return X86ISD::SUB_FLAG;
- case X86ISD::ADC:return X86ISD::ADC;
- case X86ISD::SBB:return X86ISD::SBB;
case X86ISD::SHLD: return X86ISD::SHLD;
case X86ISD::SHRD: return X86ISD::SHRD;
case X86ISD::FAND: return X86ISD::FAND;
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.26
llvm/lib/Target/X86/X86ISelLowering.h:1.27
--- llvm/lib/Target/X86/X86ISelLowering.h:1.26 Thu Feb 16 15:11:51 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h Thu Feb 16 23:43:56 2006
@@ -26,16 +26,6 @@
// Start the numbering where the builtin ops leave off.
FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
- /// ADD_FLAG, SUB_FLAG - Same as ISD::ADD and ISD::SUB except it also
- /// produces a flag result.
- ADD_FLAG,
- SUB_FLAG,
-
- /// ADC, SBB - Add with carry and subtraction with borrow. These
- /// correspond to X86::ADCxx and X86::SBBxx instructions.
- ADC,
- SBB,
-
/// SHLD, SHRD - Double shift instructions. These correspond to
/// X86::SHLDxx and X86::SHRDxx instructions.
SHLD,
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.236
llvm/lib/Target/X86/X86InstrInfo.td:1.237
--- llvm/lib/Target/X86/X86InstrInfo.td:1.236 Thu Feb 16 17:59:30 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Thu Feb 16 23:43:56 2006
@@ -56,15 +56,6 @@
def SDTX86RdTsc : SDTypeProfile0, 0, [];
-def X86addflag : SDNodeX86ISD::ADD_FLAG, SDTIntBinOp ,
-[SDNPCommutative, SDNPAssociative, SDNPOutFlag];
-def X86subflag : SDNodeX86ISD::SUB_FLAG, SDTIntBinOp,
-[SDNPOutFlag];
-def X86adc : SDNodeX86ISD::ADC , SDTIntBinOp ,
-[SDNPCommutative, SDNPAssociative, SDNPInFlag];
-def X86sbb : SDNodeX86ISD::SBB , SDTIntBinOp,
-[SDNPInFlag];
-
def X86shld: SDNodeX86ISD::SHLD, SDTIntShiftDOp;
def X86shrd: SDNodeX86ISD::SHRD, SDTIntShiftDOp;
@@ -1873,28 +1864,28 @@
let isCommutable =
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.66 - 1.67
X86ISelLowering.h updated: 1.20 - 1.21
X86InstrInfo.td updated: 1.222 - 1.223
---
Log message:
Always use FP stack instructions to perform i64 to f64 as well as f64 to i64
conversions. SSE does not have instructions to handle these tasks.
---
Diffs of the changes: (+64 -17)
X86ISelLowering.cpp | 72 +---
X86ISelLowering.h |2 -
X86InstrInfo.td |7 +++--
3 files changed, 64 insertions(+), 17 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.66
llvm/lib/Target/X86/X86ISelLowering.cpp:1.67
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.66Sun Jan 29 22:09:04 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Jan 30 02:02:57 2006
@@ -68,11 +68,12 @@
setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
+ // We can handle SINT_TO_FP and FP_TO_SINT from/to i64 even though i64
+ // isn't legal.
+ setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
+ setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
+
if (!X86ScalarSSE) {
-// We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64
-// isn't legal.
-setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
-setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
}
@@ -526,12 +527,11 @@
Chain = RetVal.getValue(1);
InFlag = RetVal.getValue(2);
if (X86ScalarSSE) {
- // FIXME:Currently the FST is flagged to the FP_GET_RESULT. This
- // shouldn't be necessary except for RFP cannot be live across
+ // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
+ // shouldn't be necessary except that RFP cannot be live across
// multiple blocks. When stackifier is fixed, they can be uncoupled.
- unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
MachineFunction MF = DAG.getMachineFunction();
- int SSFI = MF.getFrameInfo()-CreateStackObject(Size, Size);
+ int SSFI = MF.getFrameInfo()-CreateStackObject(8, 8);
SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
Tys.clear();
Tys.push_back(MVT::Other);
@@ -1027,12 +1027,11 @@
Chain = RetVal.getValue(1);
InFlag = RetVal.getValue(2);
if (X86ScalarSSE) {
- // FIXME:Currently the FST is flagged to the FP_GET_RESULT. This
- // shouldn't be necessary except for RFP cannot be live across
+ // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
+ // shouldn't be necessary except that RFP cannot be live across
// multiple blocks. When stackifier is fixed, they can be uncoupled.
- unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
MachineFunction MF = DAG.getMachineFunction();
- int SSFI = MF.getFrameInfo()-CreateStackObject(Size, Size);
+ int SSFI = MF.getFrameInfo()-CreateStackObject(8, 8);
SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
Tys.clear();
Tys.push_back(MVT::Other);
@@ -1461,12 +1460,38 @@
// Build the FILD
std::vectorMVT::ValueType Tys;
Tys.push_back(MVT::f64);
+Tys.push_back(MVT::Other);
Tys.push_back(MVT::Flag);
std::vectorSDOperand Ops;
Ops.push_back(Chain);
Ops.push_back(StackSlot);
Ops.push_back(DAG.getValueType(SrcVT));
Result = DAG.getNode(X86ISD::FILD, Tys, Ops);
+
+if (X86ScalarSSE) {
+ assert(Op.getValueType() == MVT::f64 Invalid SINT_TO_FP to lower!);
+ Chain = Result.getValue(1);
+ SDOperand InFlag = Result.getValue(2);
+
+ // FIXME: Currently the FST is flagged to the FILD. This
+ // shouldn't be necessary except that RFP cannot be live across
+ // multiple blocks. When stackifier is fixed, they can be uncoupled.
+ MachineFunction MF = DAG.getMachineFunction();
+ int SSFI = MF.getFrameInfo()-CreateStackObject(8, 8);
+ SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
+ std::vectorMVT::ValueType Tys;
+ Tys.push_back(MVT::Other);
+ std::vectorSDOperand Ops;
+ Ops.push_back(Chain);
+ Ops.push_back(Result);
+ Ops.push_back(StackSlot);
+ Ops.push_back(DAG.getValueType(MVT::f64));
+ Ops.push_back(InFlag);
+ Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
+ Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
+ DAG.getSrcValue(NULL));
+}
+
return Result;
}
case ISD::FP_TO_SINT: {
@@ -1488,10 +1513,29 @@
case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
}
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.26 - 1.27
X86ISelLowering.h updated: 1.12 - 1.13
X86InstrInfo.td updated: 1.194 - 1.195
---
Log message:
SSE cmov support.
---
Diffs of the changes: (+121 -17)
X86ISelLowering.cpp | 109
X86ISelLowering.h |3 +
X86InstrInfo.td | 26 +++-
3 files changed, 121 insertions(+), 17 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.26
llvm/lib/Target/X86/X86ISelLowering.cpp:1.27
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.26Tue Jan 10 14:26:56 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Jan 10 18:33:36 2006
@@ -17,8 +17,9 @@
#include X86TargetMachine.h
#include llvm/CallingConv.h
#include llvm/Function.h
-#include llvm/CodeGen/MachineFunction.h
#include llvm/CodeGen/MachineFrameInfo.h
+#include llvm/CodeGen/MachineFunction.h
+#include llvm/CodeGen/MachineInstrBuilder.h
#include llvm/CodeGen/SelectionDAG.h
#include llvm/CodeGen/SSARegMap.h
#include llvm/Target/TargetOptions.h
@@ -1140,14 +1141,34 @@
return std::make_pair(Result, Chain);
}
-//===--===//
-// X86 Custom Lowering Hooks
-//===--===//
+/// getCondBrOpcodeForX86CC - Returns the X86 conditional branch opcode
+/// which corresponds to the condition code.
+static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) {
+ switch (X86CC) {
+ default: assert(0 Unknown X86 conditional code!);
+ case X86ISD::COND_A: return X86::JA;
+ case X86ISD::COND_AE: return X86::JAE;
+ case X86ISD::COND_B: return X86::JB;
+ case X86ISD::COND_BE: return X86::JBE;
+ case X86ISD::COND_E: return X86::JE;
+ case X86ISD::COND_G: return X86::JG;
+ case X86ISD::COND_GE: return X86::JGE;
+ case X86ISD::COND_L: return X86::JL;
+ case X86ISD::COND_LE: return X86::JLE;
+ case X86ISD::COND_NE: return X86::JNE;
+ case X86ISD::COND_NO: return X86::JNO;
+ case X86ISD::COND_NP: return X86::JNP;
+ case X86ISD::COND_NS: return X86::JNS;
+ case X86ISD::COND_O: return X86::JO;
+ case X86ISD::COND_P: return X86::JP;
+ case X86ISD::COND_S: return X86::JS;
+ }
+}
-/// SetCCToX86CondCode - do a one to one translation of a ISD::CondCode to
-/// X86 specific CondCode. It returns a X86ISD::COND_INVALID if it cannot
+/// getX86CC - do a one to one translation of a ISD::CondCode to the X86
+/// specific condition code. It returns a X86ISD::COND_INVALID if it cannot
/// do a direct translation.
-static unsigned CCToX86CondCode(SDOperand CC, bool isFP) {
+static unsigned getX86CC(SDOperand CC, bool isFP) {
ISD::CondCode SetCCOpcode = castCondCodeSDNode(CC)-get();
unsigned X86CC = X86ISD::COND_INVALID;
if (!isFP) {
@@ -1192,11 +1213,10 @@
return X86CC;
}
-/// SupportedByFPCMOV - is there a floating point cmov for the specific
-/// X86 condition code.
-/// Current x86 isa includes the following FP cmov instructions:
+/// hasFPCMov - is there a floating point cmov for the specific X86 condition
+/// code. Current x86 isa includes the following FP cmov instructions:
/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
-static bool SupportedByFPCMOV(unsigned X86CC) {
+static bool hasFPCMov(unsigned X86CC) {
switch (X86CC) {
default:
return false;
@@ -1212,6 +1232,64 @@
}
}
+MachineBasicBlock *
+X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
+ MachineBasicBlock *BB) {
+ assert((MI-getOpcode() == X86::CMOV_FR32 ||
+ MI-getOpcode() == X86::CMOV_FR64)
+ Unexpected instr type to insert);
+
+ // To insert a SELECT_CC instruction, we actually have to insert the
diamond
+ // control-flow pattern. The incoming instruction knows the destination vreg
+ // to set, the condition code register to branch on, the true/false values to
+ // select between, and a branch opcode to use.
+ const BasicBlock *LLVM_BB = BB-getBasicBlock();
+ ilistMachineBasicBlock::iterator It = BB;
+ ++It;
+
+ // thisMBB:
+ // ...
+ // TrueVal = ...
+ // cmpTY ccX, r1, r2
+ // bCC copy1MBB
+ // fallthrough -- copy0MBB
+ MachineBasicBlock *thisMBB = BB;
+ MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
+ MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
+ unsigned Opc = getCondBrOpcodeForX86CC(MI-getOperand(3).getImmedValue());
+ BuildMI(BB, Opc, 1).addMBB(sinkMBB);
+ MachineFunction *F = BB-getParent();
+ F-getBasicBlockList().insert(It, copy0MBB);
+ F-getBasicBlockList().insert(It, sinkMBB);
+ // Update machine-CFG edges
+ BB-addSuccessor(copy0MBB);
+ BB-addSuccessor(sinkMBB);
+
+ // copy0MBB:
+ // %FalseValue = ...
+ // # fallthrough to sinkMBB
+ BB = copy0MBB;
+
+ // Update machine-CFG edges
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.22 - 1.23
X86ISelLowering.h updated: 1.11 - 1.12
X86InstrInfo.td updated: 1.190 - 1.191
X86RegisterInfo.cpp updated: 1.116 - 1.117
---
Log message:
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS.
---
Diffs of the changes: (+313 -103)
X86ISelLowering.cpp | 126 ++--
X86ISelLowering.h | 21 +++-
X86InstrInfo.td | 267 ++--
X86RegisterInfo.cpp |2
4 files changed, 313 insertions(+), 103 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.22
llvm/lib/Target/X86/X86ISelLowering.cpp:1.23
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.22Thu Jan 5 18:43:03 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Jan 9 12:33:28 2006
@@ -133,6 +133,12 @@
setOperationAction(ISD::RET, MVT::Other, Custom);
// Darwin ABI issue.
setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
+// 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
+setOperationAction(ISD::ADD_PARTS , MVT::i32 , Custom);
+setOperationAction(ISD::SUB_PARTS , MVT::i32 , Custom);
+setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
+setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
+setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
}
// We don't have line number support yet.
@@ -243,13 +249,13 @@
case MVT::f32:
case MVT::f64:
if (!X86ScalarSSE) {
+if (OpVT == MVT::f32)
+ Op = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op);
std::vectorMVT::ValueType Tys;
Tys.push_back(MVT::Other);
Tys.push_back(MVT::Flag);
std::vectorSDOperand Ops;
Ops.push_back(Chain);
-if (OpVT == MVT::f32)
- Op = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op);
Ops.push_back(Op);
Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
} else {
@@ -476,7 +482,6 @@
std::vectorMVT::ValueType NodeTys;
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag);// Returns a flag for retval copy to use.
-
std::vectorSDOperand Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
@@ -991,7 +996,6 @@
std::vectorMVT::ValueType NodeTys;
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag);// Returns a flag for retval copy to use.
-
std::vectorSDOperand Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
@@ -1193,6 +1197,99 @@
SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG DAG) {
switch (Op.getOpcode()) {
default: assert(0 Should not custom lower this!);
+ case ISD::ADD_PARTS:
+ case ISD::SUB_PARTS: {
+assert(Op.getNumOperands() == 4 Op.getValueType() == MVT::i32
+ Not an i64 add/sub!);
+bool isAdd = Op.getOpcode() == ISD::ADD_PARTS;
+std::vectorMVT::ValueType Tys;
+Tys.push_back(MVT::i32);
+Tys.push_back(MVT::Flag);
+std::vectorSDOperand Ops;
+Ops.push_back(Op.getOperand(0));
+Ops.push_back(Op.getOperand(2));
+SDOperand Lo = DAG.getNode(isAdd ? X86ISD::ADD_FLAG : X86ISD::SUB_FLAG,
+ Tys, Ops);
+SDOperand Hi = DAG.getNode(isAdd ? X86ISD::ADC : X86ISD::SBB, MVT::i32,
+ Op.getOperand(1), Op.getOperand(3),
+ Lo.getValue(1));
+Tys.clear();
+Tys.push_back(MVT::i32);
+Tys.push_back(MVT::i32);
+Ops.clear();
+Ops.push_back(Lo);
+Ops.push_back(Hi);
+return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
+ }
+ case ISD::SHL_PARTS:
+ case ISD::SRA_PARTS:
+ case ISD::SRL_PARTS: {
+assert(Op.getNumOperands() == 3 Op.getValueType() == MVT::i32
+ Not an i64 shift!);
+bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
+SDOperand ShOpLo = Op.getOperand(0);
+SDOperand ShOpHi = Op.getOperand(1);
+SDOperand ShAmt = Op.getOperand(2);
+SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi,
+ DAG.getConstant(32, MVT::i32))
+ : DAG.getConstant(0, MVT::i32);
+
+SDOperand Tmp2, Tmp3;
+if (Op.getOpcode() == ISD::SHL_PARTS) {
+ Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
+ Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
+} else {
+ Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
+ Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SHL, MVT::i32, ShOpHi, ShAmt);
+}
+
+SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag,
+ ShAmt, DAG.getConstant(32, MVT::i8));
+
+SDOperand Hi, Lo;
+SDOperand CC = DAG.getConstant(X86ISD::COND_E, MVT::i8);
+
+std::vectorMVT::ValueType Tys;
+Tys.push_back(MVT::i32);
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.12 - 1.13
X86ISelLowering.h updated: 1.6 - 1.7
X86InstrInfo.td updated: 1.179 - 1.180
---
Log message:
* Added support for X86 RET with an additional operand to specify number of
bytes to pop off stack.
* Added support for X86 SETCC.
---
Diffs of the changes: (+122 -64)
X86ISelLowering.cpp | 27 -
X86ISelLowering.h | 17 +-
X86InstrInfo.td | 142 +++-
3 files changed, 122 insertions(+), 64 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.12
llvm/lib/Target/X86/X86ISelLowering.cpp:1.13
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.12Tue Dec 20 20:39:21 2005
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Dec 21 14:21:51 2005
@@ -119,6 +119,9 @@
if (X86DAGIsel) {
setOperationAction(ISD::SELECT , MVT::i16 , Custom);
setOperationAction(ISD::SELECT , MVT::i32 , Custom);
+setOperationAction(ISD::SETCC , MVT::i8 , Custom);
+setOperationAction(ISD::SETCC , MVT::i16 , Custom);
+setOperationAction(ISD::SETCC , MVT::i32 , Custom);
}
// We don't have line number support yet.
@@ -256,7 +259,10 @@
}
break;
}
- return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
+
+ return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
+ Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
+ Copy.getValue(1));
}
//===--===//
@@ -999,10 +1005,20 @@
Tys.push_back(MVT::Other);
return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
}
+ case ISD::SETCC: {
+assert(Op.getValueType() == MVT::i8 SetCC type must be 8-bit integer);
+SDOperand CC = Op.getOperand(2);
+SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
+ Op.getOperand(0), Op.getOperand(1));
+return DAG.getNode(X86ISD::SETCC, MVT::i8, CC, Cond);
+ }
case ISD::SELECT: {
SDOperand Cond = Op.getOperand(0);
SDOperand CC;
-if (Cond.getOpcode() == ISD::SETCC) {
+if (Cond.getOpcode() == X86ISD::SETCC) {
+ CC = Cond.getOperand(0);
+ Cond = Cond.getOperand(1);
+} else if (Cond.getOpcode() == ISD::SETCC) {
CC = Cond.getOperand(2);
Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
Cond.getOperand(0), Cond.getOperand(1));
@@ -1014,12 +1030,14 @@
Op.getOperand(1), Op.getOperand(2), CC, Cond);
}
case ISD::BRCOND: {
-SDOperand Chain = Op.getOperand(0);
SDOperand Cond = Op.getOperand(1);
SDOperand Dest = Op.getOperand(2);
SDOperand CC;
// TODO: handle Cond == OR / AND / XOR
-if (Cond.getOpcode() == ISD::SETCC) {
+if (Cond.getOpcode() == X86ISD::SETCC) {
+ CC = Cond.getOperand(0);
+ Cond = Cond.getOperand(1);
+} else if (Cond.getOpcode() == ISD::SETCC) {
CC = Cond.getOperand(2);
Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
Cond.getOperand(0), Cond.getOperand(1));
@@ -1061,6 +1079,7 @@
case X86ISD::RDTSC_DAG: return X86ISD::RDTSC_DAG;
case X86ISD::CMP:return X86ISD::CMP;
case X86ISD::TEST: return X86ISD::TEST;
+ case X86ISD::SETCC: return X86ISD::SETCC;
case X86ISD::CMOV: return X86ISD::CMOV;
case X86ISD::BRCOND: return X86ISD::BRCOND;
case X86ISD::RET_FLAG: return X86ISD::RET_FLAG;
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.6
llvm/lib/Target/X86/X86ISelLowering.h:1.7
--- llvm/lib/Target/X86/X86ISelLowering.h:1.6 Tue Dec 20 20:39:21 2005
+++ llvm/lib/Target/X86/X86ISelLowering.h Wed Dec 21 14:21:51 2005
@@ -81,13 +81,24 @@
/// X86 compare and logical compare instructions.
CMP, TEST,
- /// X86 conditional moves.
+ /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
+ /// operand produced by a CMP instruction.
+ SETCC,
+
+ /// X86 conditional moves. Operand 1 and operand 2 are the two values
+ /// to select from (operand 1 is a R/W operand). Operand 3 is the
condition
+ /// code, and operand 4 is the flag operand produced by a CMP or TEST
+ /// instruction.
CMOV,
- /// X86 conditional branches.
+ /// X86 conditional branches. Operand 1 is the chain operand, operand 2
+ /// is the block to branch if condition is true, operand 3 is the
+ /// condition code, and operand 4 is the flag operand produced by a CMP
+ /// or TEST instruction.
BRCOND,
- // Return with a flag operand.
+ /// Return with a flag operand. Operand 1 is the number of bytes of stack
+ /// to pop, operand 2 is the chain and operand 3 is a flag
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.9 - 1.10
X86ISelLowering.h updated: 1.3 - 1.4
X86InstrInfo.td updated: 1.172 - 1.173
---
Log message:
X86 conditional branch support.
---
Diffs of the changes: (+53 -14)
X86ISelLowering.cpp | 21 -
X86ISelLowering.h |3 +++
X86InstrInfo.td | 43 ++-
3 files changed, 53 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.9
llvm/lib/Target/X86/X86ISelLowering.cpp:1.10
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.9 Sat Dec 17 01:18:44 2005
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Dec 19 17:12:38 2005
@@ -31,7 +31,6 @@
X86TargetLowering::X86TargetLowering(TargetMachine TM)
: TargetLowering(TM) {
-
// Set up the TargetLowering object.
// X86 is weird, it always uses i8 for shift amounts and setcc results.
@@ -81,6 +80,9 @@
setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
+ if (X86DAGIsel) {
+setOperationAction(ISD::BRCOND , MVT::Other, Custom);
+ }
setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
@@ -949,5 +951,22 @@
return DAG.getNode(X86ISD::CMOV, Op.getValueType(),
Op.getOperand(1), Op.getOperand(2), CC, Cond);
}
+ case ISD::BRCOND: {
+SDOperand Chain = Op.getOperand(0);
+SDOperand Cond = Op.getOperand(1);
+SDOperand Dest = Op.getOperand(2);
+SDOperand CC;
+// TODO: handle Cond == OR / AND / XOR
+if (Cond.getOpcode() == ISD::SETCC) {
+ CC = Cond.getOperand(2);
+ Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
+ Cond.getOperand(0), Cond.getOperand(1));
+} else {
+ CC = DAG.getCondCode(ISD::SETNE);
+ Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
+}
+return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
+ Op.getOperand(0), Op.getOperand(2), CC, Cond);
+ }
}
}
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.3
llvm/lib/Target/X86/X86ISelLowering.h:1.4
--- llvm/lib/Target/X86/X86ISelLowering.h:1.3 Fri Dec 16 19:21:05 2005
+++ llvm/lib/Target/X86/X86ISelLowering.h Mon Dec 19 17:12:38 2005
@@ -72,6 +72,9 @@
/// X86 conditional moves.
CMOV,
+
+ /// X86 conditional branches.
+ BRCOND,
};
}
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.172
llvm/lib/Target/X86/X86InstrInfo.td:1.173
--- llvm/lib/Target/X86/X86InstrInfo.td:1.172 Sat Dec 17 13:47:05 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td Mon Dec 19 17:12:38 2005
@@ -24,10 +24,15 @@
[SDTCisSameAs0, 1, SDTCisSameAs1, 2,
SDTCisVT3, OtherVT, SDTCisVT4, FlagVT];
-def X86cmp : SDNodeX86ISD::CMP , SDTX86CmpTest, [];
-def X86test : SDNodeX86ISD::TEST, SDTX86CmpTest, [];
+def SDTX86BrCond : SDTypeProfile0, 3,
+ [SDTCisVT0, OtherVT,
+ SDTCisVT1, OtherVT, SDTCisVT2, FlagVT];
-def X86cmov : SDNodeX86ISD::CMOV, SDTX86Cmov,[];
+def X86cmp: SDNodeX86ISD::CMP , SDTX86CmpTest, [];
+def X86test : SDNodeX86ISD::TEST, SDTX86CmpTest, [];
+
+def X86cmov : SDNodeX86ISD::CMOV, SDTX86Cmov,[];
+def X86Brcond : SDNodeX86ISD::BRCOND, SDTX86BrCond, [SDNPHasChain];
//===--===//
// X86 Operand Definitions.
@@ -268,21 +273,33 @@
let isBarrier = 1 in
def JMP : IBr0xE9, (ops brtarget:$dst), jmp $dst, [(br bb:$dst)];
+
+def JE : IBr0x84, (ops brtarget:$dst), je $dst,
+ [(X86Brcond bb:$dst, SETEQ, STATUS)], Imp[STATUS],[], TB;
+def JNE : IBr0x85, (ops brtarget:$dst), jne $dst,
+ [(X86Brcond bb:$dst, SETNE, STATUS)], Imp[STATUS],[], TB;
+def JL : IBr0x8C, (ops brtarget:$dst), jl $dst,
+ [(X86Brcond bb:$dst, SETLT, STATUS)], Imp[STATUS],[], TB;
+def JLE : IBr0x8E, (ops brtarget:$dst), jle $dst,
+ [(X86Brcond bb:$dst, SETLE, STATUS)], Imp[STATUS],[], TB;
+def JG : IBr0x8F, (ops brtarget:$dst), jg $dst,
+ [(X86Brcond bb:$dst, SETGT, STATUS)], Imp[STATUS],[], TB;
+def JGE : IBr0x8D, (ops brtarget:$dst), jge $dst,
+ [(X86Brcond bb:$dst, SETGE, STATUS)], Imp[STATUS],[], TB;
+
def JB : IBr0x82, (ops brtarget:$dst), jb $dst,
- [], TB;
-def JAE : IBr0x83, (ops brtarget:$dst), jae $dst, [], TB;
-def JE : IBr0x84, (ops brtarget:$dst), je $dst, [], TB;
-def JNE : IBr0x85, (ops brtarget:$dst), jne $dst, [], TB;
-def JBE : IBr0x86, (ops brtarget:$dst), jbe $dst, [], TB;
-def JA : IBr0x87,
