[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.286 -> 1.287
X86RegisterInfo.cpp updated: 1.170 -> 1.171
---
Log message:
Delete dead code; fix 80 col violations.
---
Diffs of the changes: (+4 -14)
X86InstrInfo.td | 15 ---
X86RegisterInfo.cpp |3 ---
2 files changed, 4 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.286
llvm/lib/Target/X86/X86InstrInfo.td:1.287
--- llvm/lib/Target/X86/X86InstrInfo.td:1.286 Sun Sep 10 21:19:56 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Fri Sep 22 16:43:59 2006
@@ -456,22 +456,15 @@
// Tail call stuff.
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
- def TAILJMPd : IBr<0xE9, (ops i32imm:$dst), "jmp ${dst:call} # TAIL CALL",
[]>;
+ def TAILJMPd : IBr<0xE9, (ops i32imm:$dst), "jmp ${dst:call} # TAIL CALL",
+ []>;
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
- def TAILJMPr : I<0xFF, MRM4r, (ops GR32:$dst), "jmp {*}$dst # TAIL CALL",
[]>;
+ def TAILJMPr : I<0xFF, MRM4r, (ops GR32:$dst), "jmp {*}$dst # TAIL CALL",
+ []>;
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst),
"jmp {*}$dst # TAIL CALL", []>;
-// ADJSTACKPTRri - This is a standard ADD32ri instruction, identical in every
-// way, except that it is marked as being a terminator. This causes the epilog
-// inserter to insert reloads of callee saved registers BEFORE this. We need
-// this until we have a more accurate way of tracking where the stack pointer
is
-// within a function.
-let isTerminator = 1, isTwoAddress = 1 in
- def ADJSTACKPTRri : Ii32<0x81, MRM0r, (ops GR32:$dst, GR32:$src1,
i32imm:$src2),
- "add{l} {$src2, $dst|$dst, $src2}", []>;
-
//===--===//
// Miscellaneous Instructions...
//
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.170
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.171
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.170 Sun Sep 17 15:25:45 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Fri Sep 22 16:43:59 2006
@@ -1093,9 +1093,6 @@
PI->getOperand(0).getReg() == StackPtr) {
NumBytes -= PI->getOperand(2).getImmedValue();
MBB.erase(PI);
-} else if (PI->getOpcode() == X86::ADJSTACKPTRri) {
- NumBytes += PI->getOperand(1).getImmedValue();
- MBB.erase(PI);
}
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.277 -> 1.278
X86RegisterInfo.cpp updated: 1.158 -> 1.159
---
Log message:
Add shift and rotate by 1 instructions / patterns.
---
Diffs of the changes: (+128 -0)
X86InstrInfo.td | 113
X86RegisterInfo.cpp | 15 ++
2 files changed, 128 insertions(+)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.277
llvm/lib/Target/X86/X86InstrInfo.td:1.278
--- llvm/lib/Target/X86/X86InstrInfo.td:1.277 Tue Jun 27 15:34:14 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Wed Jun 28 19:36:51 2006
@@ -1394,6 +1394,14 @@
[(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
}
+// Shift left by one. Not used because (add x, x) is slightly cheaper.
+def SHL8r1 : I<0xD0, MRM4r, (ops GR8 :$dst, GR8 :$src1),
+ "shl{b} {$dst|$dst}", []>;
+def SHL16r1 : I<0xD1, MRM4r, (ops GR16:$dst, GR16:$src1),
+ "shl{w} {$dst|$dst}", []>, OpSize;
+def SHL32r1 : I<0xD1, MRM4r, (ops GR32:$dst, GR32:$src1),
+ "shl{l} {$dst|$dst}", []>;
+
let isTwoAddress = 0 in {
def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst),
"shl{b} {%cl, $dst|$dst, %CL}",
@@ -1417,6 +1425,18 @@
def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
"shl{l} {$src, $dst|$dst, $src}",
[(store (shl (loadi32 addr:$dst), (i8 imm:$src)),
addr:$dst)]>;
+
+ // Shift by 1
+ def SHL8m1 : I<0xD0, MRM4m, (ops i8mem :$dst),
+ "shl{b} $dst",
+ [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
+ def SHL16m1 : I<0xD1, MRM4m, (ops i16mem:$dst),
+ "shl{w} $dst",
+ [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
+ OpSize;
+ def SHL32m1 : I<0xD1, MRM4m, (ops i32mem:$dst),
+ "shl{l} $dst",
+ [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
}
def SHR8rCL : I<0xD2, MRM5r, (ops GR8 :$dst, GR8 :$src),
@@ -1439,6 +1459,17 @@
"shr{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
+// Shift by 1
+def SHR8r1 : I<0xD0, MRM5r, (ops GR8:$dst, GR8:$src1),
+ "shr{b} $dst",
+ [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
+def SHR16r1 : I<0xD1, MRM5r, (ops GR16:$dst, GR16:$src1),
+ "shr{w} $dst",
+ [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
+def SHR32r1 : I<0xD1, MRM5r, (ops GR32:$dst, GR32:$src1),
+ "shr{l} $dst",
+ [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
+
let isTwoAddress = 0 in {
def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst),
"shr{b} {%cl, $dst|$dst, %CL}",
@@ -1462,6 +1493,17 @@
def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src),
"shr{l} {$src, $dst|$dst, $src}",
[(store (srl (loadi32 addr:$dst), (i8 imm:$src)),
addr:$dst)]>;
+
+ // Shift by 1
+ def SHR8m1 : I<0xD0, MRM5m, (ops i8mem :$dst),
+ "shr{b} $dst",
+ [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
+ def SHR16m1 : I<0xD1, MRM5m, (ops i16mem:$dst),
+ "shr{w} $dst",
+ [(store (srl (loadi16 addr:$dst), (i8 1)),
addr:$dst)]>,OpSize;
+ def SHR32m1 : I<0xD1, MRM5m, (ops i32mem:$dst),
+ "shr{l} $dst",
+ [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
}
def SAR8rCL : I<0xD2, MRM7r, (ops GR8 :$dst, GR8 :$src),
@@ -1484,6 +1526,18 @@
def SAR32ri : Ii8<0xC1, MRM7r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
"sar{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
+
+// Shift by 1
+def SAR8r1 : I<0xD0, MRM7r, (ops GR8 :$dst, GR8 :$src1),
+ "sar{b} $dst",
+ [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
+def SAR16r1 : I<0xD1, MRM7r, (ops GR16:$dst, GR16:$src1),
+ "sar{w} $dst",
+ [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
+def SAR32r1 : I<0xD1, MRM7r, (ops GR32:$dst, GR32:$src1),
+ "sar{l} $dst",
+ [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
+
let isTwoAddress = 0 in {
def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst),
"sar{b} {%cl, $dst|$dst, %CL}",
@@ -1507,6 +1561,18 @@
def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src),
"sar{l} {$src, $dst|$dst, $src}",
[(store (sra (loadi32 addr:$dst), (i8 imm:$src)),
addr:$dst)]>;
+
+ // Shift by 1
+ def SAR8m1 : I<0xD0, MRM7m, (ops i8mem :$dst),
+ "sar{b} $dst",
+ [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
+ def SAR16m1 : I<0xD1, MRM7
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td X86RegisterInfo.cpp X86RegisterInfo.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.239 -> 1.240
X86RegisterInfo.cpp updated: 1.124 -> 1.125
X86RegisterInfo.td updated: 1.28 -> 1.29
---
Log message:
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
---
Diffs of the changes: (+37 -20)
X86InstrInfo.td | 16
X86RegisterInfo.cpp | 12 ++--
X86RegisterInfo.td | 29 +++--
3 files changed, 37 insertions(+), 20 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.239
llvm/lib/Target/X86/X86InstrInfo.td:1.240
--- llvm/lib/Target/X86/X86InstrInfo.td:1.239 Fri Feb 17 20:36:28 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Mon Feb 20 16:34:53 2006
@@ -3026,32 +3026,32 @@
// XMM Packed Floating point support (requires SSE / SSE2)
//===--===//
-def MOVAPSrr : I<0x28, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
+def MOVAPSrr : I<0x28, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
"movaps {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE1]>, TB;
-def MOVAPDrr : I<0x28, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
+def MOVAPDrr : I<0x28, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
"movapd {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE2]>, TB, OpSize;
-def MOVAPSrm : I<0x28, MRMSrcMem, (ops V4F4:$dst, f128mem:$src),
+def MOVAPSrm : I<0x28, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
"movaps {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE1]>, TB;
-def MOVAPSmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V4F4:$src),
+def MOVAPSmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V4F32:$src),
"movaps {$src, $dst|$dst, $src}",[]>,
Requires<[HasSSE1]>, TB;
-def MOVAPDrm : I<0x28, MRMSrcMem, (ops V2F8:$dst, f128mem:$src),
+def MOVAPDrm : I<0x28, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
"movapd {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE1]>, TB, OpSize;
-def MOVAPDmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V2F8:$src),
+def MOVAPDmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V2F64:$src),
"movapd {$src, $dst|$dst, $src}",[]>,
Requires<[HasSSE2]>, TB, OpSize;
// Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
// Upper bits are disregarded.
-def FsMOVAPSrr : I<0x28, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
+def FsMOVAPSrr : I<0x28, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
"movaps {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE1]>, TB;
-def FsMOVAPDrr : I<0x28, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
+def FsMOVAPDrr : I<0x28, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
"movapd {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE2]>, TB, OpSize;
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.124
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.125
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.124 Thu Feb 16 16:45:17 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Mon Feb 20 16:34:53 2006
@@ -61,9 +61,9 @@
Opc = X86::MOVSSmr;
} else if (RC == &X86::FR64RegClass) {
Opc = X86::MOVSDmr;
- } else if (RC == &X86::V4F4RegClass) {
+ } else if (RC == &X86::V4F32RegClass) {
Opc = X86::MOVAPSmr;
- } else if (RC == &X86::V2F8RegClass) {
+ } else if (RC == &X86::V2F64RegClass) {
Opc = X86::MOVAPDmr;
} else {
assert(0 && "Unknown regclass");
@@ -89,9 +89,9 @@
Opc = X86::MOVSSrm;
} else if (RC == &X86::FR64RegClass) {
Opc = X86::MOVSDrm;
- } else if (RC == &X86::V4F4RegClass) {
+ } else if (RC == &X86::V4F32RegClass) {
Opc = X86::MOVAPSrm;
- } else if (RC == &X86::V2F8RegClass) {
+ } else if (RC == &X86::V2F64RegClass) {
Opc = X86::MOVAPDrm;
} else {
assert(0 && "Unknown regclass");
@@ -113,9 +113,9 @@
Opc = X86::MOV16rr;
} else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
Opc = X86::FpMOV;
- } else if (RC == &X86::FR32RegClass || RC == &X86::V4F4RegClass) {
+ } else if (RC == &X86::FR32RegClass || RC == &X86::V4F32RegClass) {
Opc = X86::FsMOVAPSrr;
- } else if (RC == &X86::FR64RegClass || RC == &X86::V2F8RegClass) {
+ } else if (RC == &X86::FR64RegClass || RC == &X86::V2F64RegClass) {
Opc = X86::FsMOVAPDrr;
} else {
assert(0 && "Unknown regclass");
Index: llvm/lib/Target/X86/X86RegisterInfo.td
diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.28
llvm/lib/Target/X86/X86RegisterInfo.td:1.29
--- llvm/lib/Target/X86/X86RegisterInfo.td:1.28 Wed Jan 25 18:29:36 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.td Mon Feb 20 16:34:53 2006
@@ -40,6 +40,12 @@
def DL : RegisterGroup<"DL", [DX,EDX]>; def BL :
RegisterGroup<"BL",[BX,EBX]>;
de
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.184 -> 1.185
X86RegisterInfo.cpp updated: 1.113 -> 1.114
---
Log message:
* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
* Added a pseudo instruction (for each target) that represent "return void".
This is a workaround for lack of optional flag operand (return void is not
lowered so it does not have a flag operand.)
---
Diffs of the changes: (+19 -18)
X86InstrInfo.td | 36 ++--
X86RegisterInfo.cpp |1 +
2 files changed, 19 insertions(+), 18 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.184
llvm/lib/Target/X86/X86InstrInfo.td:1.185
--- llvm/lib/Target/X86/X86InstrInfo.td:1.184 Fri Dec 23 01:31:11 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td Fri Dec 23 16:14:32 2005
@@ -32,13 +32,12 @@
[SDTCisVT<0, i8>, SDTCisVT<1, OtherVT>,
SDTCisVT<2, FlagVT>]>;
-def SDTX86RetFlag : SDTypeProfile<0, 2, [SDTCisVT<0, i16>,
- SDTCisVT<1, FlagVT>]>;
+def SDTX86RetFlag : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
SDTCisPtrTy<1>, SDTCisVT<2,
OtherVT>]>;
-def SDTX86FpSet : SDTypeProfile<1, 1, [SDTCisVT<0, FlagVT>, SDTCisFP<1>]>;
+def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest, []>;
def X86test: SDNode<"X86ISD::TEST", SDTX86CmpTest, []>;
@@ -47,7 +46,7 @@
def X86Brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, [SDNPHasChain]>;
def X86SetCC : SDNode<"X86ISD::SETCC",SDTX86SetCC,[]>;
-def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86RetFlag, [SDNPHasChain]>;
+def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86RetFlag, [SDNPHasChain]>;
def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, [SDNPHasChain]>;
@@ -290,13 +289,17 @@
//
// Return instructions.
-let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in
- def RET : I<0xC3, RawFrm, (ops), "ret", [(ret)]>;
-let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in
- def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>;
+let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in {
+ // FIXME: temporary workaround for return without an incoming flag.
+ def RETVOID : I<0xC3, RawFrm, (ops), "ret", [(ret)]>;
+ let hasInFlag = 1 in {
+def RET : I<0xC3, RawFrm, (ops), "ret", []>;
+def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>;
+ }
+}
-def : Pat<(X86retflag 0, FLAG),(RET)>;
-def : Pat<(X86retflag imm:$amt, FLAG), (RETI imm:$amt)>;
+def : Pat<(X86retflag 0),(RET)>;
+def : Pat<(X86retflag imm:$amt), (RETI imm:$amt)>;
// All branches are RawFrm, Void, Branch, and Terminators
let isBranch = 1, isTerminator = 1 in
@@ -2312,17 +2315,14 @@
}
// Random Pseudo Instructions.
-def FpGETRESULT : FpPseudoI<(ops RFP:$dst), SpecialFP, // FPR = ST(0)
- []>;
-def FpSETRESULT : FpPseudoI<(ops RFP:$src), SpecialFP,
- [(set FLAG, (X86fpset RFP:$src))]>,
- Imp<[], [ST0]>; // ST(0) = FPR
+def FpGETRESULT : FpPseudoI<(ops RFP:$dst), SpecialFP, []>; // FPR = ST(0)
+let hasOutFlag = 1 in
+ def FpSETRESULT : FpPseudoI<(ops RFP:$src), SpecialFP,
+[(X86fpset RFP:$src)]>, Imp<[], [ST0]>; // ST(0) = FPR
-def FpMOV : FpI<(ops RFP:$dst, RFP:$src), SpecialFP,
- []>; // f1 = fmov f2
+def FpMOV : FpI<(ops RFP:$dst, RFP:$src), SpecialFP, []>; // f1 = fmov f2
// Arithmetic
-
// Add, Sub, Mul, Div.
def FpADD : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
[(set RFP:$dst, (fadd RFP:$src1, RFP:$src2))]>;
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.113
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.114
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.113 Wed Dec 21 01:47:04 2005
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Fri Dec 23 16:14:32 2005
@@ -568,6 +568,7 @@
switch (MBBI->getOpcode()) {
case X86::RET:
case X86::RETI:
+ case X86::RETVOID: // FIXME: See X86InstrInfo.td
case X86::TAILJMPd:
case X86::TAILJMPr:
case X86::TAILJMPm: break; // These are ok
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